700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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ICS8430-111
700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
Dual differential 3.3V LVPECL output Selectable 14MHz 27MHz differential CLK, nCLK TEST_CLK input CLK, nCLK accepts differential input signal: LVPECL, LVHSTL, LVDS, SSTL, HCSL TEST_CLK accepts following input types: LVCMOS, LVTTL Output frequency range 700MHz range: 200MHz 700MHz Parallel serial interface programming counter output dividers Cycle-to-cycle jitter: 25ps (maximum) 3.3V supply voltage 70°C ambient operating temperature Industrial termperature information available upon request
GENERAL DESCRIPTION
ICS8430-111 general purpose, dual outICS high frequency synthesizer member HiPerClockSthe HiPerClockSfamily High Performance Clock Solutions from ICS. CLK, nCLK pair accept most standard differential input levels. single ended TEST_CLK input accepts LVCMOS LVTTL input levels translates them 3.3V LVPECL levels. operates frequency range 200MHz 700MHz. With output configured divide frequency output frequency steps small 2MHz achieved using 16MHz differential single ended reference clock. Output frequencies 700MHz programmed using serial parallel interfaces configuration logic. jitter frequency range ICS8430-111 makes ideal clock generator most clock tree applications.
BLOCK DIAGRAM
VCO_SEL CLK_SEL TEST_CLK nCLK
ASSIGNMENT
VCO_SEL nP_LOAD nCLK
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
TEST_CLK CLK_SEL VCCA S_LOAD S_DATA S_CLOCK
ICS8430-111
PHASE DETECTOR S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N2 CONFIGURATION INTERFACE LOGIC FOUT0 nFOUT0 FOUT1 nFOUT1
TEST
32-Lead LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
parallel input mode. relationship between frequency, input frequency divider defined follows: fVCO value required values through shown Table Programmable Frequency Function Table. Valid values which will achieve lock 16MHz reference defined 350. frequency defined follows: fOUT fVCO Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into divider output divider when S_LOAD transitions from LOW-to-HIGH. divide output divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly divider output divider each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST Output S_Data, Shift Register Input Output divider CMOS Fout
FUNCTIONAL DESCRIPTION
ICS8430-111 features fully integrated therefore requires external components setting loop bandwidth. differential clock input used input on-chip oscillator. output oscillator divided prior phase detector. A16MHz clock input provides 1MHz reference frequency. operates over range 700MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS8430-111 support input modes program divider output divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode nP_LOAD input initially LOW. data inputs through through passed directly divider output divider. LOW-to-HIGH transition nP_LOAD input, data latched divider remains loaded until next transition nP_LOAD until serial event occurs. result, bits hardwired divider output divider specific default state that will automatically occur during power-up. TEST output when operating
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
PARALLEL LOADING
M0:M8, N0:N1 nP_LOAD
S_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
*NOTE:
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NULL timing slot must observed.
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Input Power Output Power Output Power Output Description
TABLE DESCRIPTIONS
Number Name TEST FOUT1, nFOUT1 VCCO FOUT0, nFOUT0
Pulldown divider inputs. Data latched LOW-to-HIGH transition nP_LOAD input. LVCMOS/LVTTL interface levels. Pullup Pulldown Determines output divider value defined Table Function Table. LVCMOS/LVTTL interface levels. Pullup Negative supply pins. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS/LVTTL interface levels. Core supply pin. Differential output synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, internal dividers reset causing true outputs FOUTx inver Input Pulldown outputs nFOUTx high. When logic LOW, internal dividers outputs enabled. Asser tion does affect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register S_CLOCK Input Pulldown rising edge S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled rising edge S_DATA Input Pulldown S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition data from shift register into dividers. S_LOAD Input Pulldown LVCMOS/LVTTL interface levels. Power Analog supply pin. VCCA Selects between differential clock test inputs reference source. Selects CLK, nCLK inputs when HIGH. Selects TEST_CLK Input Pullup CLK_SEL when LOW. LVCMOS/LVTTL interface levels. Pulldown Test clock input. LVCMOS/LVTTL interface levels. TEST_CLK Input Input Pulldown Non-inver ting differential clock input. nCLK Input Pullup Inver ting differential clock input. Parallel load input. Determines when data present M8:M0 nP_LOAD Input Pulldown loaded into divider, when data present N2:N0 sets output divider value. LVCMOS/LVTTL interface levels. Determines whether synthesizer bypass mode. VCO_SEL Input Pullup LVCMOS/LVTTL interface levels. NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE PARALLEL
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK S_DATA Data Data Data Data Reset. Forces outputs LOW. Data inputs passed directly divider output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed divider output divider. divider output divider values latched. Parallel serial input affect shift registers. S_DATA passed directly divider clocked.
nP_LOAD
Data Data
Data Data
S_LOAD
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE (NOTE
Frequency (MHz) Divide
NOTE These divide values resulting frequencies correspond input frequency 16MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
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Input
Divider Value
Output Frequency (MHz) Minimum Maximum 12.5 87.5 43.75 87.5
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V -0.5V VCCO 0.5V 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA VCCO ICCA Parameter Core Supply Analog Voltage Ouput Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage M0-M7, S_CLOCK, S_DATA, S_LOAD, Input High Current TEST_CLK, nP_LOAD CLK_SEL, VCO_SEL M0-M7, S_CLOCK, S_DATA, S_LOAD, Input TEST_CLK, nP_LOAD Current CLK_SEL, VCO_SEL Test Conditions Minimum -0.3 3.465V 3.465V 3.465V, 3.465V, -150 Typical Maximum Units
Output TEST; NOTE High Voltage Output TEST; NOTE Voltage NOTE Outputs terminated with VCCO/2.
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions nCLK nCLK 3.465V 3.465V 3.465V 3.465V -150 0.85 Minimum Typical Maximum Units
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Current Input Current
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR NOTE NOTE single ended applications, maximum input voltage CLK, nCLK 0.3V. NOTE Common mode voltage defined VIH.
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
NOTE Outputs terminated with VCCO 3.3V Output Load Test Circuit figure Parameter Measurement Information section.
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter TEST_CLK; NOTE Input Frequency CLK, nCLK; NOTE Test Conditions Minimum Typical Maximum Units
S_CLOCK NOTE1: differential input reference frequency range, value must operate within 200MHz 700MHz range. Using minimum input frequency 14MHz, valid values 400. Using maximum frequency 27MHz, valid values 208.
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions fOUT 87.5MHz fOUT 87.5MHz Minimum Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol FMAX Parameter Output Frequency Cycle-to-Cycle Jitter NOTE Period Jitter, Output Skew; NOTE Output Rise/Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time S_DATA S_CLOCK S_CLOCK S_LOAD Output Duty Cycle
tjit(cc) tjit(per) tsk(o)
Lock Time tLOCK Parameter Measurement Information section. NOTE 1:This parameter defined accordance with JEDEC Standard NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points.
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA VCCO
SCOPE
nCLK Cross Points
LVPECL
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nFOUTx FOUTx nFOUTy FOUTy
tsk(o)
Clock Outputs
OUTPUT SKEW
OUTPUT RISE/FALL TIME
nFOUTx FOUTx
VREF
tcycle
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
CYCLE-TO-CYCLE JITTER
nFOUTx FOUTx
PERIOD
PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
PERIOD JITTER
100%
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8430-111 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
3.3V .01F .01F
FIGURE POWER SUPPLY FILTERING
TERMINATION
LVPECL OUTPUTS
drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. There simple termination schemes. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
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FIGURE LVPECL OUTPUT TERMINATION
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VCC/2 generated bias resistors This bias circuit should located close possible input pin. ratio
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL nCLK HiPerClockS Input
R5,R6 locate near driver pin.
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH COUPLE
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8430-111. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8430-111 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 120mA 415.8mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 60mW
Total Power_MAX (3.465V, with outputs switching) 415.8mW 60mW 475.8mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.476W 42.1°C/W 90°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
32-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8430-111
700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
0.9V
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50) 0.9V 19.8mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50) 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8430-111 3960
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700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL Reference Document: JEDEC Publication MS-026
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MINIMUM
NOMINAL
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0.60 0.75 0.10 1.40 0.37 0.15 1.45 0.45 0.20
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ICS8430-111
700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8430DY-111 ICS8430DY-111 Package Lead LQFP Lead LQFP Shipping Packaging tray 1000 tape reel Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8430DY-111 ICS8430DY-111T
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8430DY-111
REV. JUNE 2005

700MHZ, JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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