CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION
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ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
ICS843004-02 output LVPECL Synthesizer optimized generate clock HiPerClockSfrequencies variety high performance applications member HiPerClocksfamily high performance clock solutions from ICS. This device select input reference clock from either crystal input single-ended clock signal configured generate number different output frequencies frequency select pins (F_SEL2:0). ICS843004-02 uses ICS' generation phase noise technology achieve lower typical phase jitter. This ensures that will easily meet clocking requirements high-speed communication protocols such Gigabit Ethernet, Gigbit Fibre Channel, SONET. This device also suitable next generation serial technologies like serial SCSI conveniently packaged small 24-pin TSSOP package.
FEATURES
Four 3.3V LVPECL outputs Selectable crystal oscillator interface LVCMOS/LVTTL single-ended input Crystal input range: 14MHz 37.78MHz Range: 560MHz 680MHz Supports following applications: SONET, Ethernet, Serial ATA, SCSI HDTV phase jitter 155.52MHz (12kHz 20MHz): 0.91ps (typical) Offset Noise Power 100Hz -97.1 dBc/Hz 1kHz -121.6 dBc/Hz 10kHz -124.9 dBc/Hz 100kHz -125.1 dBc/Hz Full 3.3V supply mode 70°C ambient operating temperature
FUNCTION TABLE
Inputs F_SEL2 F_SEL1 F_SEL0 Divider Value Divider Value
ASSIGNMENT
nPLL_SEL VCCA F_SEL0 VCCO F_SEL2 nXTAL_SEL TEST_CLK XTAL_IN XTAL_OUT F_SEL1
BLOCK DIAGRAM
nPLL_SEL Pulldown
(default)
ICS843004-02
24-Lead TSSOP 4.40mm 7.8mm 0.92mm package body Package View
XTAL_IN
XTAL_OUT TEST_CLK
Pulldown
Phase Detector
nXTAL_SEL Pulldown
(default)
Pulldown F_SEL0:2
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice. 843004AG-02 REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE DESCRIPTIONS
Number Name nQ1, VCCO Type Output Power Ouput Input Description Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outputs inver outputs Pulldown high. When logic LOW, internal dividers outputs enabled. LVCMOS/LVTTL interface levels. Selects between TEST_CLK input dividers. When Pulldown LOW, selects (PLL Enable). When HIGH, deselects reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. connect. Analog supply pin. Pullup Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Parallel resonant ystal interface. XTAL_OUT output, XTAL_IN input. Negative supply pin. Pulldown LVCMOS/LVTTL clock input. Selects between ystal TEST_CLK inputs Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
nPLL_SEL VCCA F_SEL0, F_SEL2 F_SEL1 XTAL_OUT, XTAL_IN TEST_CLK nXTAL_SEL nQ3,
Input Unused Power Input Power Input Input Power Input Input Output Output
NOTE: Pulldown Pullup refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical Maximum Units
843004AG-02
REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE OUTPUT CONFIGURATION
Inputs F_SEL2 F_SEL1 F_SEL0
FREQUENCY RANGE FUNCTION TABLE
Divider Value Divider Value (MHz) 593.4066 622.08 622.08 622.08 622.08 637.5 562.5 Output Frequency (MHz) 74.25 74.1758245 155.52 77.76 622.08 311.04 159.375 156.25 187.5 Application HDTV HDTV SCSI SONET SONET SONET SONET SATA SATA Fibre Channel Ethernet Ethernet
Reference Clock 24.75 14.8351649 19.44 19.44 19.44 19.44 26.5625 19.53125 31.25
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ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG 4.6V -0.5V 0.5V 50mA 100mA 70°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA VCCO ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage nPLL_SEL, nXTAL_SEL, Input F_SEL0:F_SEL2, Voltage TEST_CLK Input High Current TEST_CLK, F_SEL1 nPLL_SEL, nXTAL_SEL F_SEL0, F_SEL2 Input Current TEST_CLK, F_SEL1 nPLL_SEL, nXTAL_SEL, F_SEL0, F_SEL2 Test Conditions Minimum Typical -0.3 -0.3 3.465V 3.465V 3.465V, 3.465V, -150 Maximum Units
843004AG-02
REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
NOTE Outputs terminated with VCCO
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using 18pf parallel resonant crystal. Test Conditions Minimum Typical Maximum 37.78 Units Fundamental
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol fOUT Parameter Output Frequency Lock Range Output Skew; NOTE Phase Jitter; NOTE Lock Time Output Rise/Fall Time 155.52MHz, 12kHz -20MHz F_SEL0:F_SEL2 Test Conditions Minimum 74.17 562.5 562.5 0.91 Typical Maximum 637.5 Units
tsk(o)
Output Duty Cycle NOTE Defined skew between outputs same supply voltages with equal load conditions. Measured output differential cross points. NOTE Phase jitter dependent input source used. NOTE This parameter defined accordance with JEDEC Standard
843004AG-02
REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCCA, VCCO
SCOPE
LVPECL
sk(o)
-1.3V±0.165V
3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT
Phase Noise Plot
OUTPUT SKEW
Noise Power
Phase Noise Mask
Clock Outputs
Offset Frequency
Jitter Area Under Masked Phase Noise Plot
PHASE JITTER
OUTPUT RISE/FALL TIME
nQ0:nQ3 Q0:Q3
PERIOD
PERIOD
100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843004AG-02
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ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843004-02 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA.
3.3V .01µF VCCA .01µF 10µF
FIGURE POWER SUPPLY FILTERING
RECOMMENDATIONS UNUSED INPUT OUTPUT PINS OUTPUTS: INPUTS:
CRYSTAL INPUT: applications requiring crystal oscillator input, both XTAL_IN XTAL_OUT left floating. Though required, additional protection, resistor tied from XTAL_IN ground. TEST INPUT: applications requiring test clock, left floating. Though required, additional protection, resistor tied from TEST_CLK ground. SELECT PINS: select pins have internal pull-ups pull-downs; additional resistance required added additional protection. resistor used. LVPECL OUTPUT unused LVPECL outputs left floating. recommend that there trace attached. Both sides differential output pair should either left floating terminated.
843004AG-02
REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
ICS843004-02 been characterized with 18pF parallel resonant crystals. capacitor values shown Figure below were determined using 26.5625MHz 18pF parallel resonant crystal were chosen minimize error.
XTAL2 18pF Parallel Crystal XTAL1
ICS843004-02
Figure CRYSTAL INPUt INTERFACE
TERMINATION 3.3V LVPECL OUTPUT
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
843004AG-02
REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
Figure shows example ICS843004-02 application schematic. this example, device operated VCC=3.3V. decoupling capacitor should located close possible power pin. Both input options shown. device either driven using quartz crystal 3.3V
LVCMOS signal. LVPECL output drivers, only termination examples shown this schematic. Additional termination approaches shown LVPECL Termination Application Note.
nPLL_SEL VCCA 3.3V 10uF 0.01u VCCO F_SEL0
Logic Control Input Examples
Logic Input
Logic Input
Install
F_SEL0 VCCA nPLL_SEL VCCO
843004-02
82.5
82.5
Install
F_SEL1 XTAL_OUT XTAL_IN TEST_CLK nXTAL_SEL F_SEL2 VCCO
Logic Input pins
Logic Input pins
VCC=3.3V VCCO=3.3V
(U1-3)
(U1-12)
(U1-22)
F_SEL1
0.1uF 0.1uF 0.1uF 33pF Driv er_LVCMOS nXTAL_SEL F_SEL2 19.44MHz 18pF 27pF VCCO
Optional Y-Termination
FIGURE ICS843004-02 SCHEMATIC EXAMPLE
843004AG-02
REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE
JAVS. FLOW TABLE LEAD TSSOP
Velocity (Meters Second)
65°C/W
62°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
TRANSISTOR COUNT
transistor count ICS843004-02 3467
843004AG-02
REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
LEAD TSSOP
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 0.65 BASIC 0.75 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication MO-153
843004AG-02
REV. JULY 2005
ICS843004-02
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE ORDERING INFORMATION
Part/Order Number ICS843004AG-02 ICS843004AG-02T Marking ICS843004A02 ICS843004A02 Package Lead TSSOP Lead TSSOP Shipping Packaging tube 2500 tape reel Temperature 70°C 70°C
aforementioned trademark, HiPerClockS trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843004AG-02
REV. JULY 2005
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