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MICROSYSTEMS X84041 Micro Port Saver PROM MPSEEPROM


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This X84041 device been acquired MICROSYSTEMS from Xicor, Inc.
MICROSYSTEMS
X84041
Micro Port Saver PROM
MPSEEPROM
FEATURES
Direct Interface Micros -Eliminates port requirements interface glue logic required -Eliminates need parallel serial converters
DESCRIPTION X84041 Micro Port Saver 4096-bit CMOS PROM designed direct interface port limited microcontroller limited microprocessor designs. X84041 provides benefits serial memories, such cost, power, voltage operation, small package size, while featuring higher data transfer rates reduced interface code requirements- without need dedicated serial bus. X84041 organized also suitable 16-bit 32-bit environments, serial nature
3.3Mbps data transfer rate Power CMOS -2.7V 5.5V Operation -Standby Current Less than 50µA -Active Current Less than 45ns Read Access Time 8-Byte Page Write Mode Typical Nonvolatile Write Cycle Time: High Reliability -100,000 Endurance Cycles -Guaranteed Data Retention: Years 8-Lead PDIP, 8-Lead SOIC, 14-Lead TSSOP Packages
interface.
X84041 directly connects processor communicates over single data line using sequence standard read write operations. This eliminates need dedicated port pins, parallel serial converters, complicated ASIC implementations, other glue logic, lowering system cost.
CONFIGURATION
DIP/SOIC X84041
2704 F01.2
BLOCK DIAGRAM
H.V. GENERATION TIMING CONTROL
COMMAND DECODE CONTROL LOGIC EEPROM ARRAY
TSSOP
2704 F02a.1
DECODE DATA REGISTER
2704
X84041
NAMES Data Input/Output Chip Enable Input Output Enable Input Write Enable Input Write Protect Input Supply Voltage Ground Connect
2704
Xicor, Inc. 1994, 1995, 1996 Patents Pending 2704-4.4 6/12/96 T3/C1/D0
Characteristics subject change without notice
X84041
Write Protect (WP) provides hardware protection against inadvertent writes memory. Xicor E2PROMs designed tested applications requiring extended endurance. Inherent data retention greater than years. DESCRIPTIONS Chip Enable (CE) Chip Enable input must enable read/ write operations. When HIGH, chip deselected, high impedance state, unless nonvolatile write operation underway, X84041 standby power mode. Output Enable (OE) Output Enable input must enable output buffer read data from X84041 line. Write Enable (WE) Write Enable input must write either data command sequences X84041. Data In/Data (I/O) Data command sequences serially written serially read from X84041 through pin. Write Protect (WP) When Write Protect input LOW, nonvolatile writes X84041 disabled. When HIGH, functions, including nonvolatile writes, operate normally. nonvolatile write cycle progress, going will have effect cycle already underway, will inhibit additional nonvolatile write cycles. DEVICE OPERATION X84041 serial E2PROM designed interface directly with most microprocessor buses. Standard signals control read write operations, single line used send receive data commands serially. Data Timing Data input line latched rising edge either whichever occurs first. Data output line active whenever both LOW. Care should taken ensure that never both while LOW. Read Sequence read sequence consists sending 16-bit address followed reading data serially. address written issuing separate write cycles LOW, HIGH) part without read cycle between write cycles. address sent serially, most significant first, over line. Note that this sequence fully static, with special timing restrictions, processor free perform other tasks whenever X84041 HIGH. Once address bits sent, byte data read line issuing separate read cycles LOW, HIGH). this point, issuing reset sequence will terminate read sequence, otherwise X84041 will await further reads sequential read mode. Sequential Read byte address automatically incremented next higher address after each byte data read. data stored memory next address read sequentially continuing issue read cycles. When highest address reached ($1FF), address counter rolls over address $000 reading continued indefinitely. Reset Sequence reset sequence resets X84041 sets internal write enable latch. reset sequence sent time performing read/write "0"/read sequence (see Figs. This sequence breaks multiple read write cycle sequences that normally used when reading from writing part. This sequence used time interrupt sequential read page load. soon write cycle complete, part reset (unless nonvolatile write cycle progress). second read cycle this sequence, further read cycles, will read HIGH until valid read sequence issued. reset sequence must issued beginning both read write sequences sure X84041 initiates these operations properly.
X84041
Figure Read Sequence
(IN)
(OUT) RESET LOAD ADDRESS
READ DATA
2704
Write Sequence nonvolatile write sequence consists sending reset sequence, 16-bit address (the first which don't cares), bytes data, then special "start nonvolatile write cycle" command sequence. reset sequence issued first described Reset Sequence section) internal write enable latch. address written serially issuing separate write cycles LOW, HIGH) part without read cycles between writes. address sent serially, most significant first, pin. eight bytes data written issuing either separate write cycles. Again, read cycles allowed between writes. nonvolatile write cycle initiated issuing special read/write "1"/read sequence. first read cycle ends page load, then write followed read starts nonvolatile write cycle. X84041 recognizes 8byte pages beginning addresses XXXXXX000. When sending data part, attempts exceed upper address page will result address counter "wrapping-around" first address page,
where data loading continue. this reason, sending more than consecutive data bits will result overwriting previous data. nonvolatile write cycle will start partial incomplete write sequence issued. internal write enable latch reset when nonvolatile write cycle completed prevent inadvertent writes. Note that this sequence fully static, with special timing restrictions. processor free perform other tasks whenever chip enable (CE) HIGH. Nonvolatile Write Status status nonvolatile write cycle determined time simply reading state X84041. This read when HIGH. During nonvolatile write cycle LOW. When nonvolatile write cycle complete, goes HIGH. reset sequence also issued during nonvolatile write cycle with same result: long nonvolatile write cycle progress, HIGH when nonvolatile write cycle done.
X84041
Figure Write Sequence
(IN)
(OUT) RESET LOAD ADDRESS LOAD DATA
START NONVOLATILE WRITE
2704
Write Protection following circuitry been included prevent inadvertent nonvolatile writes: internal Write Enable latch reset upon power-up. reset sequence must issued internal write enable latch before starting write sequence. special "start nonvolatile write" command sequence required start nonvolatile write cycle. internal Write Enable latch reset automatically nonvolatile write cycle. internal Write Enable latch reset remains reset long LOW, which blocks nonvolatile write cycles.
SYMBOL TABLE
WAVEFORM
INPUTS Must steady change from HIGH change from HIGH Don't Care: Changes Allowed
OUTPUTS Will steady Will change from HIGH Will change from HIGH Changing: State Known Center Line High Impedance
X84041
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias -65°C +135°C Storage Temperature -65°C +150°C Terminal Voltage with Respect Output Current Lead Temperature (Soldering, seconds) 300°C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Supply Voltage X84041 X84041 X84041
Contact factory availability.
RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. -40°C Max. +70°C +85°C
2704 T02.2
Limits ±10% ±10% 2.7V 5.5V
2704 T03.2
D.C. OPERATING CHARACTERISTICS (VCC ±10%) (Over recommended operating conditions, unless otherwise specified.) Limits Symbol ICC1 ICC2 Parameter Supply Current (Read) Supply Current (Write) Standby Current Input Leakage Current Output Leakage Current Input Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage Min. Max. Units Test Conditions VIL, VIH, Open, clocking 2MHz During Nonvolatile Write Cycle Inputs CMOS Levels VCC, Other Inputs ±10% VOUT
2.1mA, ±10% -1mA, ±10%
2704 T04.3
Notes: min. max. reference only tested.
X84041
D.C. OPERATING CHARACTERISTICS (VCC ±10%) (Over recommended operating conditions, unless otherwise specified.) Limits Symbol ICC1 ICC2 ISB1 VlL(1) VIH(1) Parameter Supply Current (Read) Supply Current (Write) Standby Current Input Leakage Current Output Leakage Current Input Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage Min. Max. Units Test Conditions VIL, VIH, Open, clocking 2MHz During Nonvolatile Write Cycle Inputs CMOS Levels VCC, Other Inputs ±10% VOUT
1mA, ±10% -400µA, ±10%
2704 T05.2
Notes: min. max. reference only tested.
CAPACITANCE Symbol CI/O(2) CIN(2)
+25°C, 1MHz, Parameter Input/Output Capacitance Input Capacitance Max. Units Test Conditions VI/O
2704 T06.2
Notes: Periodically sampled, 100% tested.
POWER-UP TIMING Symbol tPUR(3) tPUW(3) Parameter Power-up Read Operation Power-up Write Operation Max. Units
2704
Notes: Time delays required from time stable until specific operation initiated. Periodically sampled, 100% tested.
A.C. CONDITIONS TEST Input Pulse Levels Input Rise Fall Times Input Output Timing Levels
2704 T08.1
X84041
EQUIVALENT A.C. LOAD CIRCUITS
2.06K OUTPUT 3.03K 30pF
2.39K OUTPUT 4.58K 30pF
2704 F05.2
2704 F05a.3
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Read Cycle Limits X84041 Symbol tLOW tHIGH tLZ(4) tHZ(4) tOLZ(4) tOHZ(4) tWES tWEH Parameter Read Cycle Time Access Time Access Time Time HIGH Time Output HIGH Output High Output HIGH Output High Output Hold from HIGH HIGH Setup Time HIGH Hold Time ±10% Min. Max. ±10% Min. Max. Units
2704 T09.3
Notes: Periodically sampled, 100% tested. tOHZ measured from point where goes HIGH (whichever occurs first) time when longer being driven into load.
X84041
Read Cycle
tLOW tHIGH
tWES
tWEH tOHZ
tOLZ
DATA
HIGH
2704
Write Cycle Limits X84041 Symbol tNVWC(5) tWPH tCPH tOES tOEH tDS(6) tDH(6) tWPCS(7) tWPCH(7) tWPWS(7) tWPWH(7) Parameter Nonvolatile Write Cycle Time Write Cycle Time Pulse Width HIGH Recovery Time Write Setup Time Write Hold Time Pulse Width HIGH Recovery Time HIGH Setup Time HIGH Hold Time Data Setup Time Data Hold Time HIGH Before HIGH After HIGH Before HIGH After ±10% Min. Max. ±10% Min. Max. Units
2704 T10.3
Notes: tNVWC time from falling edge (whichever occurs last) second read cycle "start nonvolatile write cycle" sequence until self-timed, internal nonvolatile write cycle completed. Data latched into X84041 rising edge whichever occurs first. Periodically sampled, 100% tested.
X84041
Controlled Write Cycle
tCPH
tOES tOEH
tWPH
tWPCS
tWPCH
DATA
HIGH
2704
Controlled Write Cycle
tCPH
tOES
tOEH tWPH tWPWH
tWPWS
DATA
HIGH
2704
X84041
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) INDEX 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
NOTE: DIMENSIONS INCHES PARENTHESES MILLIMETERS) PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926
X84041
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE
0.150 (3.80) 0.158 (4.00) INDEX
0.228 (5.80) 0.244 (6.20)
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00)
(4X)
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) 0.020 (0.50)
0.050" TYPICAL
0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL PLACES
NOTE: DIMENSIONS INCHES PARENTHESES MILLIMETERS)
3926 F22.1
X84041
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP PACKAGE TYPE
.025 (.65)
.169 (4.3) .252 (6.4) .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane .019 (.50) .029 (.75) Detail (20X) Seating Plane
.031 (.80) .041 (1.05)
Detail
NOTE: DIMENSIONS INCHES PARENTHESES MILLIMETERS)
3926
X84041
ORDERING INFORMATION
X84041 Device
Range Blank 4.5V 5.5V 2.7V 3.3V 2.7V 5.5V
RoHS Compliant Lead Free package Blank Standard package. lead free
Temperature Range Blank Commercial +70°C Industrial -40°C +85°C Package 8-Lead Plastic 8-Lead SOIC 14-Lead TSSOP
LIMITED WARRANTY
Devices sold Xicor, Inc. covered warranty patent indemnification provisions appearing Terms Sale only. Xicor, Inc. makes warranty, express, statutory, implied, description regarding information forth herein regarding freedom described devices from patent infringement. Xicor, Inc. makes warranty merchantability fitness purpose. Xicor, Inc. reserves right discontinue production change specifications prices time without notice. Xicor, Inc. assumes responsibility circuitry other than circuitry embodied Xicor, Inc. product. other circuits, patents, licenses implied.
U.S. PATENTS Xicor products covered more following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents additional patents pending. LIFE RELATED POLICY situations where semiconductor component failure endanger life, system designers using this product should design system with appropriate error detection correction, redundancy back-up features prevent such occurence. Xicor's products authorized critical components life support devices systems. Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.

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