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Frequently Asked Questions about VMEbus Products
following questions frequently asked customers evaluating using Cypress VMEbus Interface products. These answers will serve introduction each topic. Separate application notes cover these topics more complete detail.
Section Questions Regarding Reset
What requirements reset power-up? properly reset power-up, required that falling edge IRESET signal after following criteria have been met: input voltage reached CLK64M clock input operating within required specifications. VMEbus signals within VMEbus specifications. Local input three-state signals driven deasserted value (LD[7:0] LA[7:0] left floating).
IPL0 must asserted earlier than military devices) after IRESET been asserted. This will initiate global reset. minimum pulse width IPL0 section VIC068A User's Guide more details. What best implement power-up reset? Best results have been obtained when power-up reset initiated through software during system boot. That dedicate external register bits tied IRESET IPL0 signals. During system boot-up, have processor write these bits that first asserts IRESET signal, then asserts IPL0 signal, then negates IPL0 signal, finally negates IRESET signal. Since processor must operational before VIC, this implies that RESET output signal used reset processor. Sample SPARCassembler code this type reset found application note "Software Considerations VIC64." must falling edge IRESET when system stable (see question above), network should used reset power-up. local module remotely reset over VMEbus? assertion SYSRESET VMEbus will reset internal circuitry selected internal register fields VIC. This referred system reset because SYSRESET typically used reset modules VMEbus. individual module reset desired (without resetting entire system), ICR7 (Interprocessor Communication Register set. This will assert HALT RESET from VIC, which used reset local devices specific module. However, when this set, external VMEbus masters access VIC, provisions must made issue IRESET from local side. Asserting IRESET (for minimum will cause initiate internal reset. Upon being granted local grant asserted within timer will expire will proceed been granted), will drive HALT RESET intervals until IRESET deasserted. When detects IRESET deasserted timeout period, will deassert HALT RESET, bringing local module reset. Upon assertion IRESET, will change state internal registers. internal registers must reloaded. power-up reset, global reset must used ensure that internal registers their default values). questions Does drive local when IRESET asserted? After IRESET asserted, attempts arbitrate local bus. granted timer expires, will assert HALT RESET, deassert local request, place three-state outputs high-Z, begin 200-ms timeout period. IRESET still asserted after additional 200-ms timeout periods follow until IRESET deasserted.
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Frequently Asked Questions about VMEbus Products
Section Questions Regarding Interrupts
queue multiple interrupts with same value? will queue pending interrupts that different levels. back-to-back interrupts required same level, first interrupt will have handled before second interrupt recognized. legal continue drive lines same level back-to-back local interrupts requested same level, interrupts must requested sequentially. there check level VMEbus interrupts VIC? interrupt generated writing VIRSR (VMEbus Interrupt Request/Status Register), level checked reading VIRSR. Otherwise, only check level allow local processor perform interrupt acknowledge cycle. proper vector will generated, which should allow software determine interrupt level jumping specific interrupt handler. vector also seen with logic analyzer during interrupt acknowledge cycle. What minimum pulse width LIRQ signals? CLK64M clock period. LIRQ lines internally registered VIC. Therefore, local interrupt request lines asserted least 64-MHz clock period, guaranteed sample recognize asserted request lines CLK64M clock edge. When does latch lines? IPL2, IPL1, IPL0 local priority encoded interrupt request signals. They used interrupt local processor. These signals emulate Motorola interrupt mechanism. lines latched assertion FCIACK signal. FCIACK should asserted processor tell that interrupt being acknowledged. Once detects assertion FCIACK, samples LA[3:1] determine whether interrupt acknowledge VIC's pending interrupt. acknowledge intended VIC, will either pass acknowledge VMEbus (for VMEbus initiated interrupts) provide appropriate acknowledge signals local (for local initiated interrupts). lines change after FCIACK signal deasserted. assertion DSACK0 DSACK1 indicates that acknowledge matches interrupt level that currently requesting.
Section III. Questions Regarding Register Operations
registers programmed over VMEbus? registers (other than registers) cannot directly programmed over VMEbus. They accessed, however, having address decoder drive VIC.
Section Questions Regarding Arbitration
must local arbiter operate? other local master) will assert whenever needs access local bus. arbiter must assert specific master allowing access occur. will maintain until longer wants local bus. system designer pick arbitration scheme (assigning priorities each master, insuring that master will "starved" bus, etc.). Arbiters must also monitor DEDLK signal prioritize local grant during deadlock situations. Once been granted local bus, important that signal removed until deasserted. will keep asserted through entire cycle. tied HIGH? Only designer insure that will never local master. requires local mastership when there slave accesses, block transfers, DRAM refreshes performed board. Does support early release BBSY? Yes. Release When Done release mode been selected, will deassert BBSY upon last assertion
Frequently Asked Questions about VMEbus Products
Section Questions Regarding Deadlock
When DEDLK asserted? When signal FCIACK valid slave select occur same time, will assert DEDLK force processor remove FCIACK retry transaction later. will detect deadlock situation when IFCSEL asserted register access) same time valid slave transaction VIC. does system recover from deadlock? deadlock occurs, will assert DEDLK signal combination DEDLK LBERR and/or HALT, which programmed occur deadlocks). DEDLK must arbiter prioritize local grant perform slave access). During deadlock processor will have access master until slave transaction been completed. other local transactions will affected deadlock. deadlocks disallowed? system designer guarantee that master will access local memory VMEbus board, board does have support deadlocks. Otherwise, they cannot disallowed.
Section Questions Regarding Block Transfers
block transfers interrupted aborted? only abort block transfer asserting LBERR. However, when LBERR asserted, status will saved (bits DMASR, etc.). Also assertion LBERR will cause assert VMEbus BERR, which have severe system ramifications. block transfers taking much local bus/VMEbus bandwidth, block size should shortened block should broken using interleaving. Breaking block cleaner solution. What maximum block transfer? VMEbus specification prohibits crossing 256-byte boundaries during block transfers (2K-byte boundaries VME64). allows larger block transfers deasserting incrementing address, reasserting without relinquishing VMEbus whenever boundary crossed. boundary crossing feature enabled setting BTDR, Block Transfer Definition Register (bit VIC64 with 2K-byte boundaries). Without using CY7C964s with VIC, maximum block transfer bytes (28). This because only direct control over lower order address lines (A[7:1]). CY7C964s used conjunction with VIC068, bytes (216) transferred block. VIC64, maximum block size bytes (224). increase block size fact that CY7C964s give complete access address signals block address incremented past 64K-byte byte VIC64 constraints fact that there eight-bit registers VIC068 (BTLR0 BTLR1) three eight-bit registers VIC64 (BTLR0, BTLR1, BTLR2) define control block transfer length. perform block transfers? least significant BTLR0 should cleared. least significant set, block transfer length ignored only burst performed.
Section VII. Questions Regarding Slave Operations
used implement slave-only interface without using microprocessor? This done, external logic must provided load VIC's internal registers. Please Application Note entitled "Using VIC068A Board Without Microprocessor," Cypress Applications Handbook, 1993. Cypress also offers slave-only interface chips, CY7C960 CY7C961. SLSEL0 SLSEL1 programmed respond more than address space each? Each slave select signals only respond address space time.
Section VIII. Questions Regarding Modeling/Schematic Capture
schematic capture libraries available VIC? schematic OrCAD available Cypress (408-934-2954).
Frequently Asked Questions about VMEbus Products
simulation libraries available VIC? Verilog models available VIC068A, VIC64, VAC068A, CY7C964. Verilog behavioral models standard VMEbus transactions available well. They work with Cadence's Verilog package. Contact your local Cypress Field Applications Engineer obtain them.
Section Questions Regarding Electrical Characteristics
What thermal characteristics Cypresses VMEbus products? Package B144 G145 N160 A144 U162 Theta (Degrees C/Watt) 11.0 13.0 17.7 18.2 Theta (Degrees C/Watt) 38.0 24.0 34.3 45.1 26.0 81.3 108.0 80.7 28.4 Description 144-Pin Plastic 144-Pin Ceramic 160-Pin PQFP 144-Pin TQFP 160-Pin CQFP 64-Pin TQFP 14mm 64-Pin TQFP 10mm 64-Pin CQFP 68-Pin Ceramic
What maximum power consumption VIC? consume 0.75W each. rated max. parts typically consume
Section Miscellaneous Questions
there test mode/pin three-state VIC's outputs testing purposes? VIC's inputs outputs treated synchronous signals clocked CLK64M? inputs outputs should treated asynchronous. There internal synchronizers sync external signals CLK64M purpose running VIC's internal state machines synchronously, there guaranteed timing relationships between signals CLK64M. Does have internal clamping diodes? signals clamped help prevent overshoot problems). There clamping diodes GND. What values capacitors recommended decoupling? 0.10 bypass high frequency decoupling. Four each recommended. They should laid close pins possible with wide traces possible) eliminate some inductive effects. What kind throughput expected from VIC? design group able achieve 61.6 Mbytes second using VIC64, Mbytes second using VIC068. Over Mbytes second possible using VIC64. This maximum usually dependent system constraints rather than interface components. What size VIC068? 315x300 mils VIC068A VIC64, 313x300 mils VAC068A, 144x133 mils CY7C964. Using with CY7C964s VAC), there avoid violating 2-inch VMEbus rule? Users should consider this rule guideline. rule nearly impossible meet using standard VMEbus interface chipset. Traces from VIC/CY7C964s/VAC VMEbus connectors should kept short possible.
Frequently Asked Questions about VMEbus Products
many CY7C964s should used with VIC? Each CY7C964 controls bits both address data. VIC068A VIC64 also control bits address data. Users determine many CY7C964s needed complete their interface determining which address data transactions will supported. A32/D32 interface would require three CY7C964s. VIC64/CY7C964 Design Notes from Cypress Semiconductor more information CY7C964 connect VIC. many gates VIC068A/VAC068A? 19,435 VIC068A; 21,250 VIC64; 18,106 VAC06A; 3000 CY6C964. transistor counts follows: 80,000 VIC068A, 85,000 VIC64, 75,000 VAC068A, 12,000 CY7C964. What capacitive loading signal lines? inputs. outputs. bidirectional signals. many words write posted from local VMEbus side? longword write posted from either side. Which signals have metastability protection? Metastability problem with asynchronous, clocked designs. valid level reached input clocked element (flip-flop, etc.) within specified set-up hold window, condition called "metastability" occur. output clocked element unpredictable. driven valid output level even oscillate. Eventually output will settle valid level, settling time also unpredictable. There several ways combat metastability problems. most common techniques involves "double clocking" input. clocked elements placed, series, signal path. Even first clocked element goes metastable, odds good that output will have settled valid state before set-up hold window second element reached. VMEbus strobe inputs metastability-hardened carry with them CLK64M cycles synchronization delay. DSi, DTACK, BERR also metastability-hardened. both asynchronous path metastability-protected path. When performing slave transfers, asynchronous path used. data bus, address bus, AM5-0, LWORD, WRITE, local signals metastability-hardened. there example code available programming VIC? Yes. file named SAMPCODE.EXE available Cypress (408) 943-2954. This self-extracting file.
Cypress Semiconductor Corporation, 1995. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

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