General Release Specification September 1997 Tokyo Design Op
|
|
|
Top Searches for this datasheet
HC68VBIGRS/D REV.3.0
General Release Specification
September 1997
Tokyo Design Operations Tokyo, Japan
MC68HC68VBI
General Release Specification
Motorola reserves right make changes without further notice products herein improve reliability, function design. Motorola does assume liability arising application product circuit described herein; neither does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part.
Motorola, Inc., 1997
MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
List Sections
Section General Description Section Memory Section Phase-Locked Loop (PLL) Section Data Extraction Module Section Multiplexed Expansion Section Serial Peripheral Interface (SPI) Section Electrical Specifications Section Mechanical Specifications Section Ordering Information
MC68HC68VBI Rev. MOTOROLA List Sections
General Release Specification
List Sections
General Release Specification List Sections
MC68HC68VBI Rev. MOTOROLA
General Release Specification-MC68HC68VBI
Table Contents
Section General Description
Contents Introduction Features Functional Overview 1.4.1 Data Extraction Module 1.4.2 Expanded Interface 1.4.3 Serial Peripheral Interface (SPI) Assignment. Internal Structure Functional Description 1.7.1 PAR/SER. 1.7.2 1.7.3 1.7.4 AD0/SCLK 1.7.5 AD1/SDATA 1.7.6 AD2/SWIN 1.7.7 AD3:AD7 1.7.8 SDI/AS. 1.7.9 SDO/RW 1.7.10 SCK/E 1.7.11 SYNC 1.7.12 VData 1.7.13 1.7.14 PLLTD 1.7.15 PLLTA 1.7.16 TEST 1.7.17 RESET 1.7.18 BUSY. 1.7.19 OSC1.
MC68HC68VBI Rev. MOTOROLA Table Contents
General Release Specification
Table Contents
1.7.20 1.7.21 1.7.22 1.7.23 1.7.24 1.7.25 1.7.26 OSC2. VDD1 VSS1. VDD3 VSS3. VDD2 VSS2. Mode Selection Fixed Frequency Oscillator 1.9.1 Ceramic Crystal Resonator 1.9.2 External Clock 1.9.3 Oscillator Frequency (fOSC).
Section Memory
Contents Introduction MC68HC68VBI Memory Control Registers $00-$18 Status/Data Registers $80-$DD.
Section Phase-Locked Loop (PLL)
Contents Introduction Line Number Definitions State Description Sampling Clock Control Register Extraction Divider Sync Control/Status Miscellaneous Register.
Section Data Extraction Module
Contents Introduction General Operation Signal Connection.
General Release Specification Table Contents
MC68HC68VBI Rev. MOTOROLA
Table Contents
Data Slicer Output Signals BUSY Signal 4.6.1 Register Readability During BUSY Quasi-Horizontal Sync Detection Field Detection Data Extraction Input Signal Description 4.9.1 Pedestal Clamp Data Slicer Circuit Diagram 4.9.2 Pedestal Clamp Timing Diagram. 4.10 Extraction Control Register. 4.11 Mode Description Registers 4.12 Teletext Hamming Decoder 4.13 Mode 4.13.1 Framing Code Synchronization 4.13.2 8/30 Magazine Address Group Match 4.13.3 Format Designation Code Match 4.14 Line Control Registers 4.15 Field Sync Line Sync Registers 4.16 Quasi-Sync Line Count Registers. 4.17 Address Register 4.18 Read Data Registers
Section Multiplexed Expansion
Contents Introduction
Section Serial Peripheral Interface (SPI)
Contents Introduction Memory Access
Section Electrical Specifications
MC68HC68VBI Rev. MOTOROLA Table Contents
Contents .101 Introduction .101 Maximum Ratings .102 Operating Temperature Range. .102
General Release Specification
Table Contents
7.10 7.11 Thermal Characteristics .102 Electrical Characteristics. .103 Data Extraction Characteristics .104 Expanded Interface Characteristic .105 Data Slicer Output Characteristics .106 Serial Peripheral Interface Characteristics .107 Phase-Locked Loop Characteristics .107
Section Mechanical Specifications
Contents .109 Introduction .109 28-Pin Plastic Dual In-Line Package (Case 873) .110
Section Ordering Information
Contents .111 Introduction .111 Order Number .111
General Release Specification Table Contents
MC68HC68VBI Rev. MOTOROLA
General Release Specification-MC68HC68VBI
List Figures
Figure 2-10 3-10 3-11 3-12
Title
Page
Block Diagram. LRPL Timing Example. Clock Signal Distribution NTSC First Field NTSC Second Field First Field Second Field. State Diagram Sampling Control Register (SCCTR) Extraction Divider (EPLLD) Sampling Control Register (SCST). Sampling Control Register (MISC) Data Extraction Timing Diagram. External Video Signal Connections Data Slicer Output Signal Block Diagram.
MC68HC68VBI Rev. MOTOROLA List Figures
General Release Specification
MC68HC68VBI Memory MC68HC68VBI Control Registers Description Control Register $00:$0F Control Register $10:$18 MC68HC68VBI Status/Data Registers Description Status/Data Register $80:$8F Status/Data Register $90:$9F Status/Data Register $B0:$BF Status/Data Register $C0:$CF Data/Status Register $D0:$DD.
Example Expanded Serial Communication 32-Pin PinoutFigure MC68HC68VBI Block Diagram. Oscillator Connections
List Figures
Figure 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 Title Page
Data Slicer Output Signal Timing Diagram. BUSY Timing Diagram Normal Sync Condition BUSY Timing Diagram Unlocked Condition BUSY Timing Diagram Unlocked Condition BUSY Timing Diagram Signal Condition Register Readability During BUSY Quasi-H Sync Timing NTSC First Field. NTSC First Field NTSC Second Field First Field Second Field. Data Extraction Input Line Description Data Extraction Slice Level Description Pedestal Clamp Data Slicer. Pedestal Clamp Timing Extraction Control Register (EXCTR) Mode Description Register (MxD0, MxD1, MxD2) Mode Description Register (MxD1) Mode Description Register (MxD2) Clock Synchronization Edge. Digital Pass Filter Block Diagram Mode Teletext Hamming Decode Enable Diagram Operation Framing Code Synchronization Operation 8/30 MRAG Comparison Operation Format Designation Code Comparison Line Control Registers (LCRx/LCRy) Field Sync Line Sync Registers (FSL7). Line Control Register (L8/L9-L22/L23). Address Register (PAR). Read Data Registers (RD0-RD83) Data Entry Flow Diagram
Multiplexed Expansion Write Cycle Timing Multiplexed Expansion Read Cycle Timing Block Diagram Interface Description Timing Diagram
General Release Specification List Figures
MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
List Tables
Table
Title
Page
Output Frequency Examples.47 Sync Slice Levels Data Slice Levels.73 Teletext Hamming Decoder.82 Order Numbers .109
MC68HC68VBI Rev. MOTOROLA List Tables
General Release Specification
MC68HC68VBI Assignments Mode Selection Table.30
List Tables
General Release Specification List Tables
MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
Section General Description
Contents
Introduction Features
Functional Overview 1.4.1 Data Extraction Module 1.4.2 Expanded Interface 1.4.3 Serial Peripheral Interface (SPI) Assignment. Internal Structure
MC68HC68VBI Rev. MOTOROLA General Description
General Release Specification
Functional Description 1.7.1 PAR/SER. 1.7.2 1.7.3 1.7.4 AD0/SCLK 1.7.5 AD1/SDATA 1.7.6 AD2/SWIN 1.7.7 AD3:AD7 1.7.8 SDI/AS. 1.7.9 SDO/RW 1.7.10 SCK/E 1.7.11 SYNC 1.7.12 VData 1.7.13 1.7.14 PLLTD 1.7.15 PLLTA 1.7.16 TEST 1.7.17 RESET 1.7.18 BUSY. 1.7.19 OSC1.
General Description
1.7.20 1.7.21 1.7.22 1.7.23 1.7.24 1.7.25 1.7.26 OSC2. VDD1 VSS1. VDD3 VSS3. VDD2 VSS2. Mode Selection
Fixed Frequency Oscillator 1.9.1 Ceramic Crystal Resonator 1.9.2 External Clock 1.9.3 Oscillator Frequency (fOSC).
Introduction
Motorola MC68HC68VBI low-cost HCMOS video peripheral capable decoding user-definable vertical blanking interval (VBI) data formats from National Television System Committee (NTSC), phase alternating line system (PAL), sequential color memory system (SECAM) video signals. fully duplexed serial peripheral interface (SPI) Motorola 68HC(7)11 multiplexed expansion enables interface with host processor. functional block diagram MC68HC68VBI shown Figure 1-1.
Features
Cost, HCMOS Technology 32-Pin Quad Flat Pack (QFP) Package Input Data Extraction Closed Caption, Extended Data Service Video Identification Moji Tajuu, Japanese Closed Captioning Kanji Video Programming System (VPS)
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
General Description Functional Overview
Program Delivery Control Mode (PDC) Hamming Decoder Packet 8/30 Format Format
Serial Peripheral Interface (SPI) Motorola 68HC(7)11 Multiplexed Expansion Internal Phase-Locked Loop (PLL) Frequency Generator Quasi-Horizontal Sync Detection
Functional Overview
MC68HC68VBI contains three major functional blocks. They are: data extraction module Multiplexed expansion During communication with host device, input clock needed. single 5-volt ±10% power supply required well fixed-frequency resonator input signal. other timing reference voltage signals generated chip.
1.4.1 Data Extraction Module data extraction module extracts data from composite video signal according programming supplied host. Since critical parameters input signal extracted programmable, extraction most data formats possible. data extraction module capable extracting data three modes from line vertical blanking interval. maximum 8-bit bytes extracted stored this module each field. This data passed host through serial expanded interface. data extraction module uses system with three programmable dividers generation suitable sampling clocks. Appropriate divide
MC68HC68VBI Rev. MOTOROLA General Description General Release Specification
General Description
ratios must chosen programmed user generation sampling clocks. clock switch used switch between related clocks without re-stabilizing lower clock frequencies. External composite sync internally separated sync pulses selected using read sync select bit, RSS, MISC register. mode description memory used define characteristics data formats extracted. These registers organized into four groups three registers. Data extracted described Clock delay, number output delay clocks from horizontal sync leading edge until first data mode Number bytes sampled line clock switch Data slice level Clock synchronization rising falling edge Digital enable Resynchronization enable Output enable
clock synchronization edge used initial clock synchronization maintenance clock synchronization. determined MxRF. this clear, clock will resynchronized rising edge data contained video signal, set, falling edge. clock delay register intended allow user start data acquisition appropriate time. Prior expiration count clock delay register, data contained video signal will sampled. When count clock delay register expires, data acquisition module will synchronize sampling clock first selected edge (depending selection MxRF) video signal.
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
General Description Functional Overview
those data types with start bits, clock delay register should expire after last transition signal before rising edge start bit. those data types with run-in clock start bit, clock delay register should expire after last transition signal before rising edge run-in clock. this way, proper clock synchronization data types achieved. run-in clock used software verify proper synchronization. Following expiration clock delay register, sampling clock will re-establish synchronization every selected edge input video signal. several like data bits occur, clock will detect these bits accurately until resynchronizing next edge. When number bytes sampled been entered into internal memory, data acquisition module will terminate data sampling. This allows user determine beginning each line's samples. specialized mode been included allow selection sampled data. When this mode enabled, only those lines with magazine address group matching 8/30 format code will read into internal data registers. line with different magazine address group encountered, only framing code captured. data detected, entered into data registers. Once modes have been described, user read data three described modes using line control registers. Data read from lines through line control registers contain enable bits indicate mode number desired that line.
MC68HC68VBI Rev. MOTOROLA General Description
General Release Specification
General Description
MULTIPLEXED EXPANDED INTERFACE
DATA EXTRACTION MODULE
SERIAL PERIPHERAL INTERFACE
Figure 1-1. Example Expanded Serial Communication 1.4.2 Expanded Interface expanded interface provides high-speed access between Motorola 68HC(7)11 multiplex expansion MCUs control data registers data extraction module. This accomplished using multiplex expansion mode devices such 'HC11E9 'HC11A8. expanded interface designed require minimum interface hardware provide direct access control data registers data extraction module. Using configuration Figure 1-1, registers accessed software exactly same 'HC11's internal memory locations. memory accessed using high order addresses between $40XX $7FXX. default state, HC11E9 other memory this range. Control signals provided coordinate communication with HC11 MCU.
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
General Description Functional Overview
1.4.3 Serial Peripheral Interface (SPI) full-duplex serial peripheral interface (SPI) links host device with control data registers data extraction module. designed access registers once between each vertical blanking interval. recommended that this done some time during display portion video output. Data read from written registers simultaneously. Starting address $80, part data read. Simultaneously, single contiguous group control registers written. After chip select asserted, first bytes clocked into write start write ignore (stop) address. Thereafter, data clocked into registers starting from start address. ignore address, data longer entered into memory. Clocks must applied full byte ignore address enter previous data into register. Control signals provided coordinate communication with host MCU. Starting from first clock used clock start address, data clocked read-only registers from address $80. Even after ignore address been reached, data from read-only registers will clocked out. When last byte reached, will clocked out.
MC68HC68VBI Rev. MOTOROLA General Description
General Release Specification
General Description Assignment
MC68HC68VBI available 32-pin QFP. assignment this package shown Table 1-1. Table 1-1. MC68HC68VBI Assignments
Expanded Mode Name AD0/ SCLK AD1/ SDATA AD2/ SWIN VDD3 SDI/AS SDO/RW SCK/E VSS3 VDD2 SYNC VData VSS2 VSS1 Note Note Note Note Note Note CMOS/TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Note Note Note Open Drain Function SYNC VData Note Note Note Note Note2 Note Serial Mode CMOS/TTL CMOS CMOS CMOS Note Note Note Note Note CMOS Note Note Note Open Drain Function SCLK SDATA SWIN Note SYNC VData
Note
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
General Description Assignment
Table 1-1. MC68HC68VBI Assignments (Continued)
Expanded Mode Name VDD1 VDD3 PLLTA PLLTD TEST PAR/SER RESET BUSY VSS3 OSC1 OSC2 CMOS/TTL CMOS CMOS CMOS CMOS CMOS Open Drain Function Test Test Test Parallel Reset Busy OSC1 OSC2 Note Note Note Serial Mode CMOS/TTL CMOS CMOS CMOS CMOS CMOS Open Drain Function Test Test
Note
Serial Reset Busy OSC1 OSC2
Note
NOTES: Defined separately Power supply ground Connection external capacitor Pulled down weakly; does affect circuit operation serial mode function
MC68HC68VBI Rev. MOTOROLA General Description
General Release Specification
Test
General Description
PAR/SER
RESET
ADO/SCLK AD1/SDATA
PLLTA VDD3 VDD1 VSS1 VSS2 VData SYNC
AD2/SWIN
MC68HC68VBI 32-PIN
PLLTD
OSC2
OSC1
BUSY
SCK/E
VDD2
TEST
VSS3
SDO/RW
SDI/AS
Figure 1-2. 32-Pin Pinout
NOTE:
line over signal name indicates active-low signal. reference voltage, current, frequency specified following sections will refer nominal values. exact values their tolerance limits specified Section Electrical Specifications.
Internal Structure
block diagram MC68HC68VBI shown Figure 1-3.
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
VDD3
VSS3
General Description Internal Structure
BUSY QUASI-H/V SYNC
SYNC VDD2 VSS2 VData RESET PAR/SER TEST OSC1 OSC2 VDD3 VSS3
SYNC DATA DATA SLICER CLAMP VDD1 VSS1 PLLTD PLLTA
SYSTEM INTERNAL
MULTIPLEX EXPANDED
Figure 1-3. MC68HC68VBI Block Diagram
MC68HC68VBI Rev. MOTOROLA General Description General Release Specification
AD2/SWIN
SDO/RW
SCKK/E
AD1/SDTA
AD0/SCLK
SDI/AS
General Description Functional Description
1.7.1 PAR/SER This input-only activates either expanded serial interface with host controller. When this low-voltage level, serial communication interface activated. When this high-voltage level, expanded interface activated.
1.7.2 This input-only chip select both serial expanded interfaces, depending PAR/SER. When serial activated this high-voltage level, serial interface deselected. When low-voltage level, serial interface selected. first following falling edge clocks data. When expanded activated this high-voltage level, expanded interface deselected. When low-voltage level high-voltage level, expanded interface selected. When serial interface activated, input levels used. When expanded interface activated, CMOS input levels used.
1.7.3 This input-only alternate chip select expanded interface. When serial activated, this affect. When expanded activated this high-voltage level low-voltage level, expanded interface selected. disable this pin, connect low-voltage level.
1.7.4 AD0/SCLK When expanded mode activated, this bidirectional address/data expanded interface. When serial mode activated, this data slicer sampling clock output. When
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
General Description Functional Description
reset, this high impedance. When expanded interface deactivated, this weakly pulled down (about
1.7.5 AD1/SDATA When expanded mode activated, this bidirectional address/data expanded interface. When serial mode activated, this data slicer sampled data output. When reset, this high impedance. When expanded interface deactivated, this weakly pulled down (about
1.7.6 AD2/SWIN When expanded mode activated, this bidirectional address/data expanded interface. When serial mode activated, this data slicer window output. When reset, this high impedance. When expanded interface deactivated, this weakly pulled down (about
1.7.7 AD3:AD7 These bidirectional pins make remainder address/data expanded interface. While reset, these pins high impedance. When expanded interface deactivated, these pins weakly pulled down (about
1.7.8 SDI/AS When expanded interface enabled, this input-only, TTL-level (transistor-transistor logic) functions expanded interface address strobe. When serial communication interface enabled, this serial communication data input pin. When serial interface activated, input levels used. When expanded interface activated, CMOS input levels used.
MC68HC68VBI Rev. MOTOROLA General Description
General Release Specification
General Description
1.7.9 SDO/RW When expanded interface enabled, this open drain, input/output determines read from memory write memory. When serial communication interface enabled, this serial communication data output external pullup resistor should attached. While reset, this high impedance.
1.7.10 SCK/E
This input-only, TTL-level dual function clock input both expanded interface serial interface. When serial mode selected, external pullup resistor should connected this control state during idle periods. When serial interface activated, input levels used. When expanded interface activated, CMOS input levels used.
1.7.11 SYNC This input-only accepts synchronization signals from video source. These signals composite video signal digital level composite sync. composite video input, series capacitor should used. composite sync input, direct coupling should used should set.
1.7.12 VData This accepts video input signal determination pedestal level data extraction. Synchronization signals input SYNC pin.
1.7.13 This used connection external passive components used determine characteristics PLL. Typical passive component capacitor might sourced VSS1.
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
General Description Functional Description
1.7.14 PLLTD This input/output digital test extraction module PLL. reserved factory should always connected VSS3.
1.7.15 PLLTA This input/output analog test extraction module PLL. reserved factory should always connected VSS3.
1.7.16 TEST This input-only factory only should always connected VSS3.
1.7.17 RESET This input-only TTL-level resets peripheral known state.
1.7.18 BUSY This open-drain output-only high during lines through When this signal low, safe access extraction data registers. When this signal high, registers busy. signal this referenced sync selected RSS. While reset, this outputs level.
1.7.19 OSC1 This input-only input fixed-frequency oscillator.
1.7.20 OSC2 This output-only output fixed-frequency oscillator.
MC68HC68VBI Rev. MOTOROLA General Description
General Release Specification
General Description
1.7.21 VDD1 This analog power supply PLL1.
1.7.22 VSS1 This analog ground PLL1.
1.7.23 VDD3 This digital power supply logic circuits.
1.7.24 VSS3 This digital ground logic circuits.
1.7.25 VDD2 This digital power supply noise-sensitive analog circuits.
1.7.26 VSS2 This digital ground noise-sensitive analog circuits.
Mode Selection
Modes selected information Table 1-2. Table 1-2. Mode Selection Table
Mode Serial Expanded Test Test PAR/SER Active Active Factory Test Mode Inactive Active High
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
General Description Fixed Frequency Oscillator
Fixed Frequency Oscillator
fixed-frequency oscillator included generation timing signals when stable frequency available. OSC1 OSC2 pins connections 2-pin on-chip oscillator. OSC1 OSC2 pins accept these sets components: crystal ceramic oscillator shown Figure 1-4(a) external clock signal shown Figure 1-4(b)
1.9.1 Ceramic Crystal Resonator circuit Figure shows typical 2-pin oscillator circuit ceramic crystal resonator. crystal manufacturer's recommendations should followed, resonator's parameters determine external component values required provide maximum stability reliable startup. load capacitance values used oscillator circuit design should include stray capacitances. crystal components should mounted close possible pins startup stabilization minimize output distortion.
OSC1
OSC2
OSC1
OSC2
UNCONNECTED EXTERNAL CLOCK
CRYSTAL CONNECTIONS
EXTERNAL CLOCK SOURCE CONNECTION
Figure 1-4. Oscillator Connections
MC68HC68VBI Rev. MOTOROLA General Description
General Release Specification
General Description
1.9.2 External Clock external clock from another CMOS-compatible device connected OSC1 input, with OSC2 input connected, shown Figure 1-4. This configuration possible regardless oscillator connection not.
1.9.3 Oscillator Frequency (fOSC) When (525-line system), frequency 3.57954 (NTSC fOSC) must used. When (625-line system), frequency 4.43362 (PAL fOSC) must used. This oscillator must always connected ensure proper operation. Vertical sync signals detected using fixed-frequency oscillator must longer than times duration fixed-frequency clock period considered vertical sync signals.
General Release Specification
MC68HC68VBI Rev. General Description MOTOROLA
General Release Specification MC68HC68VBI
Section Memory
Contents
Introduction MC68HC68VBI Memory Control Registers $00-$18 Status/Data Registers $80-$DD.
Introduction
Information concerning MC68HC68VBI memory control registers status/data registers found this section.
MC68HC68VBI Rev. MOTOROLA Memory
General Release Specification
Memory MC68HC68VBI Memory
MC68HC68VBI active bytes registers shown Figure 2-1.
$0000 BYTES EXTRACTION REGISTERS $0004 $0005 BYTES LINE CONTROL REGISTERS $000F $0010 BYTES MODE DESCRIPTION REGISTERS $0018 $0019 BYTES UNUSED $007F $0080 BYTES SYNC STATUS REGISTERS $0089 $008A BYTES DATA REGISTERS $00DD $00DE BYTES UNUSED $00F7 $00F8 BYTES RESERVED $00FF
Figure 2-1. MC68HC68VBI Memory
General Release Specification Memory
MC68HC68VBI Rev. MOTOROLA
Memory Control Registers $00-$18
Control Registers $00-$18
Addr Name Miscellaneous Register Extraction Divider Register Sync Status/Control Register Sampling Clock Control Extraction Control Register Line Control Register Line Control 9/10 Register Line Control 11/12 Register Line Control 13/14 Register Line Control 15/16 Register Line Control 17/18 Register Line Control 19/20 Register Line Control 21/22 Register Line Control 23/24 Register Line Control 25/26 Register Line Control 27/28 Register Mode Description Register Mode Description Register Mode Description Register Mode Description Register Mode Description Register Mode Description Register Mode Description Register Mode Description Register Mode Description Register
Figure 2-2. MC68HC68VBI Control Registers Description
MC68HC68VBI Rev. MOTOROLA Memory
General Release Specification
Memory
Addr
Register Name Miscellaneous (MISC) Extraction Divider (EPLLD) Sync Control/Status (SCST) Sampling Clock Control (SCCTR) Extraction Control (EXCTR) Line Control (LCR7/LCR8) Line Control 9/10 (LCR9/LCR10) Line Control 11/12 (LC11/LCR12) Line Control 13/14 (LCR13/LCR14) Line Control 15/16 (LCR15/LCR16) Line Control 17/18 (LCR17/LCR18) Line Control 19/20 (LCR19/LCR20 Line Control 21/22 (LCRR21/LCR22) Line Control 23/24 (LCR23/LCR24) Line Control 25/26 (LCR25/LCR26) Line Control 27/28 (LCR27/LCR28) Read: Write: Read: Write: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
PFLD SSL2
SSL1
RPSAV SSL0 L8M0 L10M0 L12M0 L14M0 L16M0 L18M0 L20M0 L22M0 L24M0 L26M0 L28M0
PCLD
SSL3
Read: SCHK
EN11 EN13 EN15 EN17 EN19 EN21 EN23 EN25 EN27
L7M1 L9M1 L11M1 L13M1 L15M1 L17M1 L19M1 L21M1 L23M1 L25M1 L27M1
L7M0 L9M0 L11M0 L13M0 L15M0 L17M0 L19M0 L21M0 L23M0 L25M0 L27M0
EN10 EN12 EN14 EN16 EN18 EN20 EN22 EN24 EN26 EN28
L8M1 L10M1 L12M1 L14M1 L16M1 L18M1 L20M1 L22M1 L24M1 L26M1 L28M1
Unimplemented
Figure 2-3. Control Register $00:$0F
General Release Specification Memory MC68HC68VBI Rev. MOTOROLA
Memory Control Registers $00-$18
Addr
Register Name Mode Description (M0D0) Mode Description (M0D1) Mode Description (M0D2) Mode Description (M1D0) Mode Description (M1D1) Mode Description (M1D2) Mode Description (M2D0) Mode Description (M2D1) Mode Description (M2D2) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
M0C6 M0S2 M0SL2 M1C6 M1S2 M1SL2 M2C6 M2S2 M2SL2
M0C5 M0B5 M0SL1 M1C5 M1B5 M1SL1 M2C5 M2B5 M2SL1
M0C4 M0B4 M0SL0 M1C4 M1B4 M1SL0 M2C4 M2B4 M2SL0
M0C3 M0B3 M0RF M1C3 M1B3 M1RF M2C3 M2B3 M2RF
M0C2 M0B2 M0LEN M1C2 M1B2 M1LEN M2C2 M2B2 M2LEN
M0C1 M0B1 M0REN M1C1 M1B1 M1REN M2C1 M2B1 M2REN
M0C0 M0B0 M0OEN M1C0 M1B0 M1OEN M2C0 M2B0 M2OEN
M0PDC M0SL3
M1PDC M1SL3
M2PDC M2SL3
Unimplemented
Figure 2-4. Control Register $10:$18
MC68HC68VBI Rev. MOTOROLA Memory
General Release Specification
Memory Status/Data Registers $80-$DD
Addr Name Field Sync/Line Sync Register Line 8/Line Sync Register Line 10/Line Sync Register Line 12/Line Sync Register Linbe 14/Line Sync Register Line 16/Line Sync Register Line 18/Line Sync Register Line 20/Line Sync Register Line 22/Line Sync Register Address Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Addr Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Name
Figure 2-5. MC68HC68VBI Status/Data Registers Description
General Release Specification Memory
MC68HC68VBI Rev. MOTOROLA
Memory Status/Data Registers $80-$DD
Addr Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Regiser Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Regiser
Name
Addr Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register Data Register
Name
Figure 2-5. MC68HC68VBI Status/Data Registers Description (Continued)
MC68HC68VBI Rev. MOTOROLA Memory
General Release Specification
Memory
Addr
Register Name Field Sync/Line (FSL7) Line 8/Line (L8/L9) Line 10/Line (L10/L11) Line 12/Line (L12/L13) Line 14/Line (L14/L15) Line 16/Line (L16/L17) Line 18/Line (L18/L19) Line 20/Line (L20/L21) Line 22/Line (L22/L23) Address (PAR) Read Data (RD0) Read Data (RD1) Read Data (RD2) Read Data (RD3) Read Data (RD4) Read Data (RD5) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
L8C3 L10C3 L12C3 L14C3 L16C3 L18C3 L20C3 L22C3 MULT R0B7 R1B7 R2B7 R3B7 R4B7 R5B7
L8C2 10C2 L12C2 L14C2 L16C2 L18C2 L20C2 L22C2 PAR6 R0B6 R1B6 R2B6 R3B6 R4B6 R5B6
LRPL 8LC1 L10C1 12LC1 L14C1 L16C1 L18C1 L20C1 L22C1 PAR5 R0B5 R1B5 R2B5 R3B5 R4B5 R5B5
SCHK L8C0 L10C0 L12C0 L14C0 L16C0 L18C0 L20C0 L22C0 PAR4 R0B4 R1B4 R2B4 R3B4 R4B4 R5B4
L7C3 L9C3 L11C3 L13C3 L15C3 L17C3 L19C3 L21C3 L23C3 PAR3 R0B3 R1B3 R2B3 R3B3 R4B3 R5B3
L7C2 L9C2 L11C2 L13C2 L15C2 L17C2 L19C2 L21C2 L23C2 PAR2 R0B2 R1B2 R2B2 R3B2 R4B2 R5B2
L7C1 L9C1 L11C1 L13C1 L15C1 L17C1 L19C1 L21C1 L23C1 PAR1 R0B1 R1B1 R2B1 R3B1 R4B1 R5B1
L7C0 L9C0 L11C0 L13C0 L15C0 L17C0 L19C0 LC210 L23C0 PAR0 R0B0 R1B0 R2B0 R3B0 R4B0 R5B0
Unimplemented
Figure 2-6. Status/Data Register $80:$8F
General Release Specification Memory MC68HC68VBI Rev. MOTOROLA
Memory Status/Data Registers $80-$DD
Addr
Register Name Read Data (RD6) Read Data (RD7 Read Data (RD8) Read Data (RD9) Read Data (RD10) Read Data (RD11) Read Data12 (RD12) Read Data (RD13) Read Data (RD14) Read Data (RD15) Read Data (RD16) Read Data (RD17) Read Data (RD18) Read Data (RD19) Read Data (RD20) Read Data (RD21) Read: Write: Read: Write: Read: Write: Read: Write: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read:
R6B7 R7B7 R8B7 R9B7 R10B7 R11B7 R12B7 R13B7 R14B7 R15B7 R16B7 R17B7 R18B7 R19B7 R20B7 R21B7
R6B6 R7B6 R8B6 R9B6 R10B6 R11B6 R12B6 R13B6 R14B6 R15B6 R16B6 R17B6 R18B6 R19B6 R20B6 R21B6
R6B5 R7B5 R8B5 R9B5 R10B5 R11B5 R12B5 R13B5 R14B5 R15B5 R16B5 R17B5 R18B5 R19B5 R20B5 R21B5
R6B4 R7B4 R8B4 R9B4 R10B4 R11B4 R12B4 R13B4 R14B4 R15B4 R16B4 R17B4 R18B4 R19B4 R20B4 R21B4
R6B3 R7B3 R8B3 R9B3 R10B3 R11B3 R12B3 R13B3 R14B3 R15B3 R16B3 R17B3 R18B3 R19B3 R20B3 R21B3
R7B2 R8B2 R9B2 R10B2 R11B2 R12B2 R13B2 R14B2 R15B2 R16B2 R17B2 R18B2 R19B2 R20B2 R21B2
R6B1 R7B1 R8B1 R9B1 R10B1 R11B1 R12B1 R13B1 R14B1 R15B1 R16B1 R17B1 R18B1 R19B1 R20B1 R21B1
R6B0 R7B0 R8B0 R9B0 R10B0 R11B0 R12B0 R13B0 R14B0 R15B0 R16B0 R17B0 R18B0 R19B0 R20B0 R21B0
Unimplemented
Figure 2-7. Status/Data Register $90:$9F
MC68HC68VBI Rev. MOTOROLA Memory General Release Specification
Memory
Addr
Register Name Read Data (RD38) Read Data (RD39) Read Data (RD40) Read Data (RD41) Read Data (RD42) Read Data (RD43) Read Data (RD44) Read Data (RD45) Read Data (RD46) Read Data (RD47) Read Data (RD48) Read Data (RD49) Read Data (RD50) Read Data (RD51) Read Data (RD52) Read Data (RD53) Read: Write: Read Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
R38B7 R39B7 R40B7 R41B7 R42B7 R43B7 R44B7 R45B7 R46B7 R47B7 R48B7 R49B7 R50B7 R51B7 R52B7 R53B7
R38B6 R39B6 R40B6 R41B6 R42B6 R43B6 R44B6 R45B6 R46B6 R47B6 R48B6 R49B6 R50B6 R51B6 R52B6 R53B6
R38B5 R39B5 R40B5 R41B5 R42B5 R43B5 R44B5 R45B5 R46B5 R47B5 R48B5 R49B5 R50B5 R51B5 R2B5 R53B5
R38B4 R39B4 R40B4 R41B4 R42B4 R43B4 R44B4 R45B4 R46B4 R47B4 R48B4 R49B4 R50B4 R51B4 R52B4 R53B4
R38B3 R39B3 R40B3 R41B3 R42B3 R43B3 R44B3 R45B3 R46B3 R47B3 R48B3 R49B3 R50B3 R51B3 R52B3 R53B3
R38B2 R39B2 R40B2 R41B2 R42B2 R43B2 R44B2 R45B2 R46B2 R47B2 R48B2 R49B2 R50B2 R51B2 R52B2 R53B2
R38B1 R39B1 R40B1 R41B1 R42B1 R43B1 R44B1 R45B1 R46B1 R47B1 R48B1 R49B1 R50B1 R51B1 R52B1 R53B1
R38B0 R39B0 R40B0 R41B0 R42B0 R43B0 R44B0 R45B0 R46B0 R47B0 R48B0 R49B0 R50B0 R51B0 R52B0 R53B0
Unimplemented
Figure 2-8. Status/Data Register $B0:$BF
General Release Specification Memory MC68HC68VBI Rev. MOTOROLA
Memory Status/Data Registers $80-$DD
Addr
Register Name Read Data (RD54) Read Data (RD55) Read Data56 (RD56) Read Data (RD57) Read Data (RD58) Read Data (RD59) Read Data (RD60) Read Data (RD61) Read Data (RD62) Read Data (RD63) Read Data (RD64) Read Data (RD65) Read Data (RD66) Read Data (RD67) Read Data (RD68) Read Data (RD69) Read: Write: Read: Write: Read: Write: Read: Write: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read:
R54B7 R55B7 R56B7 R57B7 R58B7 R59B7 R60B7 R61B7 R62B7 R63B7 R64B7 R65B7 R66B7
R54B6 R55B6 R56B6 R57B6 R58B6 R59B6 R60B6 R61B6 R62B6 R63B6 R64B6 R65B6 R66B6 R67B6 R68B6 R69B6
R54B5 R55B5 R56B5 R57B5 R58B5 R59B5 R60B5 R61B5 R62B5 R63B5 R64B5 R65B5 R66B5 R67B5 R68B5 R69B5
R54B4 R55B4 R56B4 R57B4 R58B4 R59B4 R60B4 R1B4 R62B4 R63B4 R64B4 R65B4 R66B4 R67B4 R68B4 R69B4
R54B3 R55B3 R56B3 R57B3 R58B3 R59B3 R60B3 R61B3 R62B3 R63B3 R64B3 R65B3 R66B3 R67B3 R68B3 R69B3
R54B2 R55B2 R56B2 R57B2 R58B2 R59B2 R60B2 R61B2 R62B2 R63B2 R64B2 R65B2 R6B2 R67B2 R68B2 R69B2
R54B1 R55B1 R56B1 R57B1 R58B1 R59B1 R60B1 R61B1 R62B1 R63B1 R64B1 R65B1 R66B1 R67B1 R68B1 R69B1
R54B0 R55B0 R56B0 R57B0 R58B0 R59B0 R60B0 R61B0 R62B0 R63B0 R64B0 R65B0 R66B0 R67B0 R68B0 R69B0
Read: R67B7 Write: Read: R68B7 Write: Read: Write R69B7
Unimplemented
Figure 2-9. Status/Data Register $C0:$CF
MC68HC68VBI Rev. MOTOROLA Memory General Release Specification
Memory
Addr
Register Name Read Data (RD70) Read Data (RD71) Read Data (RD72) Read Data (RD73) Read Data (RD74) Read Data (RD75) Read Data (RD76) Read Data (RD77) Read Data (RD78) Read Data (RD79) Read Data (RD80) Read Data (RD81) Read Data (RD82) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read:
R70B7 R71B7 R72B7 R73B7 R74B7 R75B7 R76B7 R77B7 R78B7 R79B7 R80B7 R81B7 R82B7 R83B7
R70B6 R71B6 R72B6 R73B6 R74B6 R75B6 R76B6 R77B6 R78B6 R79B6 R80B6 R81B6 R82B6 R83B6
R70B5 R71B5 R72B5 R73B5 R74B5 R75B5 R76B5 R77B5 R78B5 R79B5 R80B5 R81B5 R82B5 R83B5
R70B4 R71B4 R72B4 R73B4 R74B4 R75B4 R76B4 R77B4 R78B4 R79B4 R80B4 R81B4 R82B4 R83B4
R70B3 R71B3 R72B3 R73B3 R74B3 R75B3 R76B3 R77B3 R78B3 R79B3 R80B3 R81B3 R82B3 R83B3
R70B2 R71B2 R72B2 R73B2 R74B2 R75B2 R76B2 R77B2 R78B2 R79B2 R80B2 R81B2 R82B2 R83B2
R70B1 R71B1 R72B1 R73B1 R74B1 R75B1 R76B1 R77B1 R78B1 R79B1 R80B1 R81B1 R82B1 R83B1
R70B0 R71B0 R72B0 R73B0 R74B0 R75B0 R76B0 R77B0 R78B0 R79B0 R80B0 R81B0 R82B0 R83B0
Read Data (RD83)
Write:
Unimplemented
Figure 2-10. Data/Status Register $D0:$DD
General Release Specification Memory
MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
Section Phase-Locked Loop (PLL)
Contents
Introduction Line Number Definitions State Description Sampling Clock Control Register Extraction Divider Sync Control/Status Miscellaneous Register.
MC68HC68VBI Rev. MOTOROLA Phase-Locked Loop (PLL)
General Release Specification
Phase-Locked Loop (PLL) Introduction
MC68HC68VBI on-chip generation synchronous clock signals data extraction module. (See Figure 3-1.)
PHASE COMPARATOR
HSync SEPARATOR INPUT SYNC VSync SEPARATOR
INPUT DELAY CLOCK SYNCHRONIZATION CLOCK SAMPLING CLOCK
LINE COUNTER
LINE NUMBER
VERTICAL SYNC OUTPUT
Figure 3-1. Block Diagram
three programmable dividers clock switch which used determine sampling clock synchronization clock frequency. control registers located control registers, determine value dividers. position clock switch determined MxS2 mode description registers. Table summarizes divider values several input data types.
General Release Specification Phase-Locked Loop (PLL)
MC68HC68VBI Rev. MOTOROLA
Phase-Locked Loop (PLL) Introduction
Table 3-1. Output Frequency Examples
Vertical Blanking Interval Data Type Closed Caption Video Lines Moji Tajuu Teletext Divide Ratio 1792 1820 1820 1776 1920 Register Value MxS2 Sampling Frequency 28.43
power consumption desired during periods when being used, power save bit, RPSAV, located miscellaneous register $00, set. This disables PLL. Operation resumed clearing this bit. lock state determined LRPL field sync/line sync register located status/data registers. LRPL only leading edge vertical sync when locked. LRPL guarantees that become unlocked during vertical blanking interval. disturbance shown Figure should occur, LRPL would when read following line although would locked that time. LRPL would again until next leading edge vertical sync that locked.
MC68HC68VBI Rev. MOTOROLA Phase-Locked Loop (PLL)
General Release Specification
Phase-Locked Loop (PLL)
LINE
LOCK STATE LRPL
BUSY
Figure 3-2. LRPL Timing Example input signal selected used sampling clock generation line counting. user select either externally internally separated vertical horizontal sync input PLL. used generation sampling clocks used data extraction module. Sampling clocks built using horizontal input signal selected sync select (RSS) miscellaneous register located control register. Figure 3-3.
SYNC
INPUT SYNC
LINE COUNTER
EXTRACTION MODULE
SYNC SEPARATOR
TIMING SIGNAL GENERATOR
BUSY
Figure 3-3. Clock Signal Distribution
General Release Specification Phase-Locked Loop (PLL)
MC68HC68VBI Rev. MOTOROLA
Phase-Locked Loop (PLL) Line Number Definitions
Line Number Definitions
Figure 3-4, Figure 3-5, Figure 3-6, Figure show line number definitions NTSC signals. references line numbers will defined unless otherwise specified.
EQUALIZATION
VERTICAL SYNC
EQUALIZATION
SYNC
Figure 3-4. NTSC First Field
EQUALIZATION
VERTICAL SYNC
EQUALIZATION
NTSC
SYNC
Figure 3-5. NTSC Second Field
MC68HC68VBI Rev. MOTOROLA Phase-Locked Loop (PLL)
General Release Specification
NTSC
Phase-Locked Loop (PLL)
EQUALIZATION
VERTICAL SYNC
EQUALIZATION
SYNC
Figure 3-6. First Field
EQUALIZATION
VERTICAL SYNC
EQUALIZATION
SYNC
Figure 3-7. Second Field
State Description
will four modes depending input signal conditions. forms window expected location horizontal sync signal. four states are: Unlock relationship between input sync frequency output frequency Lock Input sync frequency output frequency related according C7:C0 Comp Single missing horizontal sync compensated PLL.
General Release Specification Phase-Locked Loop (PLL) MC68HC68VBI Rev. MOTOROLA
Phase-Locked Loop (PLL) State Description
horizontal sync missing prior near line line either field, this mode will insert horizontal sync. consecutive lines missing horizontal sync pulses, will return unlocked state. Hold Compensates phase jumps caused playback head switching commonly found signals produced video cassette players. This mode disables phase comparator, holds frequency PLL, repositions window according vertical sync. output frequency held discontinuity phase horizontal sync pulses occurs immediately prior vertical sync. this time near line 253. this time near line 303.
ENABLE
UNLOCK
EDGE SEVEN CONSECUTIVE WINDOWS
VSync HOLD EDGE WINDOW TIME tPJR LOCK
EDGE WINDOW TIME tPJR COMP EDGE NEXT LINE'S WINDOW
Figure 3-8. State Diagram
MC68HC68VBI Rev. MOTOROLA Phase-Locked Loop (PLL)
General Release Specification
EDGE NEXT WINDOW AFTER ENTERING COMP MODE
Phase-Locked Loop (PLL) Sampling Clock Control Register
Address: $0003 Read: Write: Reset:
Unimplemented
Figure 3-9. Sampling Control Register (SCCTR) Reserved This used always reads A0:A2 counter These bits divide ratio PLL's divider Values from written. less than desired divide ratio should written these bits. zero written, counter will divide B0:B3 counter These bits divide ratio PLL's divider Values from written. less than desired divide ratio should written these bits. zero written, counter will divide
NOTE:
MxS2 then (A+1)(B+1) must greater than MxS2 then (A+1) must greater than ensure proper operation.
General Release Specification Phase-Locked Loop (PLL)
MC68HC68VBI Rev. MOTOROLA
Phase-Locked Loop (PLL) Extraction Divider
Extraction Divider
Address: $0001 Read:
Write: Reset:
Figure 3-10. Extraction Divider (EPLLD) C0:C7 Counter Adjust These bits determine divide ratio PLL's divider 1729 less than desired divide ratio should written this register. value divider will contents counter adjust register plus fixed offset 1728. Divide ratios from 1729 1984 selected.
MC68HC68VBI Rev. MOTOROLA Phase-Locked Loop (PLL)
General Release Specification
Phase-Locked Loop (PLL) Sync Control/Status
Address: $0002 Read: Write: Reset: SCHK PCLD SSL3 SSL2 SSL1 SSL0
Unimplemented
Figure 3-11. Sampling Control Register (SCST) SCHK Sync Check Same SCHK bit. This cleared read read $02. Bits Reserved These bits used always read PCLD Pedestal Clamp Large Driver Disable Pedestal clamp large driver control Pedestal clamp large driver disabled Pedestal clamp large driver enabled SSL3:SSL0 Sync Slice Level These bits determine voltage level which sync information will sliced.
General Release Specification Phase-Locked Loop (PLL)
MC68HC68VBI Rev. MOTOROLA
Phase-Locked Loop (PLL) Miscellaneous Register
Miscellaneous Register
Address: $0000 Read:
PFLD
RPSAV
Write: Reset:
Unimplemented
Figure 3-12. Sampling Control Register (MISC) SYStem This determines which system type peripheral will use. line system line system PFLD Filter Large Driver Disable This determines enable disable filter's large driver will under automatic manual control. Write: filter large driver always enabled filter large driver dibbled automatically Bits Reserved These bits used always read Read Sync Select This determines internal sync separator will enabled not. direct coupled CMOS level negative true composite sync used, sync separator should bypassed. capacitively coupled video sync used, sync separator should enabled. Write: Direct coupled negative true composite sync (disabled) Internally separated sync (enabled)
MC68HC68VBI Rev. MOTOROLA Phase-Locked Loop (PLL)
General Release Specification
Phase-Locked Loop (PLL)
RPSAV Power Save Mode Power save mode entered using this bit. Write: Power save mode Normal operation
General Release Specification Phase-Locked Loop (PLL)
MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
Section Data Extraction Module
Contents
Introduction General Operation Signal Connection. Data Slicer Output Signals
BUSY Signal 4.6.1 Register Readability During BUSY Quasi-Horizontal Sync Detection Field Detection
4.10 4.11 4.12
Extraction Control Register. Mode Description Registers Teletext Hamming Decoder
4.13 Mode 4.13.1 Framing Code Synchronization 4.13.2 8/30 Magazine Address Group Match 4.13.3 Format Designation Code Match 4.14 4.15 4.16 4.17 4.18
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
Line Control Registers Field Sync Line Sync Registers Quasi-Sync Line Count Registers. Address Register Read Data Registers
General Release Specification
Data Extraction Input Signal Description 4.9.1 Pedestal Clamp Data Slicer Circuit Diagram 4.9.2 Pedestal Clamp Timing Diagram.
Data Extraction Module Introduction
data extraction module MC68HC68VBI high-frequency sampling circuit with low-level composite video signals. Input signal parameters programmable, allowing user define input data formats. Sampling clock frequency programmed using phase-locked loop (PLL) system. Data extracted from NTSC (National Television System Committee), (phase alternating line system), sequential color memory system (SECAM) composite video signals. four modes extracted lines through maximum 8-bit bytes extracted stored this module each field. Features data extraction module include: Extraction Closed Caption, Video Identification Program Delivery Control (PDC) Moji Tajuu, Japanese Closed Captioning Kanji Video Programming System (VPS)
User-Defined Data Formats Real-Time Sampling Clock Resynchronization Quasi-Horizontal Sync Detection Field Detection Packet 8/30 Format Format Mode with Format Determined Hamming Decode
General Operation
Since data extraction module relies only user-defined mode description, user confined sampling pre-defined data formats only. Figure illustrates those parameters signal that user defines typical waveform.
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module General Operation
Voltage slicing levels defined data sync portions signal. sync slice level bits, SSL3:SSL0, define voltage slice level used extract sync signals. data slice level bits, MxSL3:MxSL0, define voltage slice level used extract data from signal. data slice level defined reference pedestal level. sync slice level defined reference sync level. clock synchronization edge determined MxRF mode description registers used initial clock synchronization maintenance clock synchronization. This edge should chosen that accurate, unambiguous sampling clock found. clock delay bits, MxC6:MxC0, define number input delay clock cycles from leading edge horizontal until sampling started. Care should taken that this expires when signal proper polarity before first sampled data bit. sampling clock resynchronized each selected edge after clock delay expires. bits used count number bytes that entered into data registers after sampling started. After number bytes indicated bits have been sampled, more data entered into data registers. Once data formats sampled have been defined, user indicate which lines sample given format using line control registers. user should specify mode sampled corresponding mode description group. more than line data read during given field, data will stored contiguously read data registers. That first byte second line data will immediately follow last byte first line data. Data entered into read data registers starting read data progressing higher addresses data sampled. Data sampled least significant first entered into read data registers least significant (LSB) first. sampling terminated middle byte, bits that byte will entered into data register from least significant (LSB) remaining bits will
MC68HC68VBI Rev. MOTOROLA Data Extraction Module General Release Specification
Data Extraction Module MC68HC68VBI Rev. MOTOROLA
General Release Specification UNDEFINED SIGNAL MxC6:MxC0 SSL3: SSL0 DATA REGISTERS
Data Extraction Module
SAMPLING FREQUENCY SL3:SL0
MxB5:MxB0
INCREASING ADDRESS
Figure 4-1. Data Extraction Timing Diagram
Data Extraction Module Signal Connection
Signal Connection
video signal connected extraction module ways: Using internal sync separator Bypassing internal sync separator using CMOS level negative true composite sync signal directly applied SYNC pin. Figure 4-2(a) Figure 4-2(b).
VData COMPOSITE VIDEO
VData
COMPOSITE VIDEO COMPOSITE SYNC SYNC SYNC
CONNECTION USING INTERNAL SYNC SEPARATOR
CONNECTION USING EXTERNAL SYNC SEPARATOR
Figure 4-2. External Video Signal Connections
Data Slicer Output Signals
When serial mode activated, three outputs data slicer available user. Figure shows representation generation these signals.
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module
DATA SLICER
SAMPLED DATA EXT.
DATA REGISTERS
SDATA SAMPLING CLOCK
SCLK
SWIN
Figure 4-3. Data Slicer Output Signal Block Diagram slicer window output, SWIN, will active high sampled data that entered into data registers. Slicer sampling clock, SCLK, sampling clock used data slicer sample video signal VData. clock resynchronization, duty cycle waveform will always present. slicer data output, SDATA, sampled data. This data also will entered into data registers.
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module BUSY Signal
SDATA SCLK
NOTES: SWIN leading edge clock Clock SWIN trailing edge SCLK period SCLK high time SCLK time Data setup time Data hold time Signal falling time Signal rising time
Figure 4-4. Data Slicer Output Signal Timing Diagram Immediately after expiration count clock delay register, leading edge SWIN will occur line designated sampling mode with MxOEN After initial synchronization sampling clock this line, SCLK SDATA will become active. trailing edge SWIN will occur when number bytes expires next horizontal synchronization pulse expires, whichever occurs first.
BUSY Signal
This signal assists user interfacing with host device appropriate time. While busy signal high, attempts read data registers result unknown data. leading edge BUSY will occur during line interval. trailing edge BUSY will occur eight clocks after leading edge line horizontal sync.
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
SWIN
Data Extraction Module
LINE COUNTER
SYNC DETERMINED BUSY NOTE: LRPL
Figure 4-5. BUSY Timing Diagram Normal Sync Condition disturbance occurs during vertical sync interval, BUSY will remain high until vertical sync interval then fall. disturbance occurs after vertical sync interval, BUSY signal, still high, will fall immediately.
LINE COUNTER
SYNC DETERMINED BUSY
UNLOCKABLE SIGNAL
NOTE: LRPL
Figure 4-6. BUSY Timing Diagram Unlocked Condition
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module BUSY Signal
LINE COUNTER
SYNC DETERMINED
UNLOCKABLE SIGNAL
BUSY
NOTE: LRPL
LINE COUNTER
SYNC DETERMINED BUSY
LOCKABLE UNLOCKABLE SIGNAL
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Figure 4-8. BUSY Timing Diagram Signal Condition
Figure 4-7. BUSY Timing Diagram Unlocked Condition
Data Extraction Module
4.6.1 Register Readability During BUSY When BUSY signal high, access registers permitted. Control registers four most significant bits status registers always readable writable. However, remaining registers only readable while BUSY signal low.
CONTROL STATUS/DATA DATA
BUSY
CONTROL
STATUS/DATA
DATA
BUSY
UNREADABLE; READING THIS TIME WILL RESULT UNKNOWN DATA READABLE
Figure 4-9. Register Readability During BUSY
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Quasi-Horizontal Sync Detection
Quasi-Horizontal Sync Detection
Quasi-horizontal sync pulses counted lines through Quasi-horizontal sync pulses falling edges below sync slice level occurring between genuine horizontal sync pulses. Genuine horizontal sync pulses defined active display region. Figure 4-10 NTSC first field example. second field signals, quasi-horizontal sync pulses also counted lines through locked, quasi-horizontal sync pulses cannot detected.
LINE LINE LINE LINE LINE LINE LINE LINE
ACTIVE DISPLAY REGION
Figure 4-10. Quasi-H Sync Timing NTSC First Field
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module Field Detection
most recent field display indicated field bit, FLD.
EQUALIZATION
VERTICAL SYNC
EQUALIZATION
NTSC
SYNC
Figure 4-11. NTSC First Field
EQUALIZATION
VERTICAL SYNC
EQUALIZATION
NTSC
SYNC
Figure 4-12. NTSC Second Field
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Field Detection
EQUALIZATION
VERTICAL SYNC
EQUALIZATION
SYNC
Figure 4-13. First Field
EQUALIZATION
VERTICAL SYNC
EQUALIZATION
SYNC
Figure 4-14. Second Field
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module Data Extraction Input Signal Description
description input signal data extraction module SYNC shown Figure 4-15, Figure 4-16, Table 4-1, Table 4-2. Limits these signal parameters Data Extraction Characteristics.
DATA
NOTES: Data extraction input voltage amplitude Sync pedestal level Pedestal level maximum data Horizontal line frequency
Figure 4-15. Data Extraction Input Line Description
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Data Extraction Input Signal Description
DATA SLICE REFERENCE VOLTAGE
DATA SLICE LEVEL
SYNC SLOPE SYNC SLICE REFERENCE VOLTAGE
SYNC SLICE LEVEL (SSL3:SSL0)
Figure 4-16. Data Extraction Slice Level Description Data sync slice levels must selected user based characteristics input signal. Figure 4-15 Figure 4-16. sync slice level selected using SSL3:SSL0 bits sync control/status register located control registers. sync slice level referenced sync clamp level. There possible error millivolts sync slice reference voltage. Care must taken when selecting sync slice reference voltage ensure that only
MC68HC68VBI Rev. MOTOROLA Data Extraction Module General Release Specification
NOTES: Data Extraction Input Voltage Amplitude Sync Pedestal Level Pedestal Level Maximum Data Data Slicer Reference Voltage Error Sync Slicer Reference Voltage Error Fall Slope Sync Signals Minimum Data Maximum Data Level
(MxSL3:MxSL0)
Data Extraction Module
those signals considered composite sync quasi-sync pulses cross this reference. pedestal level clamped during lines four five each field shown Figure 4-17 Figure 4-18. pedestal voltage change between lines less than 12.5 data slice level need adjusted compensate this change. Table 4-1. Sync Slice Levels
SSL3: SSL0 Sync Slice Reference Voltage VDD2 VSS2 -108 -120 -133 SSL3: SSL0 Sync Slice Reference Voltage VDD2 VSS2
data slice level selected using MxSL3:MxSL0 bits individual mode select registers. data slice level referenced pedestal clamp level. There possible error millivolts data slice reference voltage. Care must taken when selecting data slice reference voltage ensure that during vertical blanking interval lines selected data extraction only those signals considered valid data pulses cross this reference.
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Data Extraction Input Signal Description
Table 4-2. Data Slice Levels
MxSL3: MxSL0 Data Slice Reference Voltage VDD2 VSS2 MxSL3: MxSL0 Sync Slice Reference Voltage VDD2 VSS2
Average sync data slice levels calculated power supply voltage using variable included above tables. VSlice ((VDD2 VSS2) D/200 Where VSlice data sync slice level. These voltages represent average values with tolerance. Actual voltages vary slightly.
4.9.1 Pedestal Clamp Data Slicer Circuit Diagram Figure 4-17 illustrates pedestal clamp data slicer circuit 68HC68VBI. sync slice circuit shown diagram. pedestal clamp level internal fixed reference level available user. data slice level reference voltage determined MxSL3:MxSL0. four transistors that compose large buffer small buffer used accurately determine clamp pedestal voltage level hold capacitor attached VData pin.
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module
PEDESTAL CLAMP VData PEDESTAL CLAMP LEVEL PEDESTAL CLAMP
LARGE BUFFER
SMALL BUFFER
ENABLE ENABLE ENABLE ENABLE
DATA SLICE REFERENCE VOLTAGE
DATA SLICE
DATA SLICER
Figure 4-17. Pedestal Clamp Data Slicer
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Data Extraction Input Signal Description
4.9.2 Pedestal Clamp Timing Diagram pedestal level clamped during lines Figure 4-18 illustrates active clamping time large large transistors. small small similarly active line interval.
PEDESTAL SAMPLING INTERVAL DATA SLICING
LINE
VData
VData ENABLE ENABLE ENABLE ENABLE
LARGE
PEDESTAL SAMPLING 10.6-11.5
PEDESTAL SAMPLING 10.6-11.5
Figure 4-18. Pedestal Clamp Timing
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module 4.10 Extraction Control Register
Address: $0004 Read: Write: Reset:
Unimplemented
Figure 4-19. Extraction Control Register (EXCTR) Extraction Interrupt Flag This detection line extraction module line counter based sync selected RSS. This read only cleared writing bit. Reset clears this bit. Extraction Module BUSY This from line line extraction module line counter based sync selected RSS. Reset clears this bit. Extraction Interrupt Clear
write only always reads Writing this clears EIF. Writing this effect. Clear effect Bits Reserved These bits used always read Extraction Module Enable enables data extraction module. Reset clears this bit. Extraction module enabled Extraction module disabled
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Mode Description Registers
4.11 Mode Description Registers
Read: Write: Reset:
MxC6 MxC5 MxC4 MxC3 MxC2 MxC1 MxC0
Unimplemented
Figure 4-20. Mode Description Register (MxD0, MxD1, MxD2) Reserved This used always reads MxC6:MxC0 Mode Clock Delay These bits determine many counts input delay clock, extraction frequency divided four, will delayed from leading edge horizontal sync pulse before clock synchronization edge detect circuit enabled. This register should less than reset state.
Read:
MxPDC MxS2 MxB5 MxB4 MxB3 MxB2 MxB1 MxB0
Write: Reset:
Figure 4-21. Mode Description Register (MxD1) MxPDC Mode select This selects mode. Write: mode Normal mode
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module
MxS2 Mode Switch This determines setting PLL's clock switch. Write: Sampling clock output divider. Sampling clock output divider. MxB5:MxB0 Mode number Bytes line These bits give number bytes line specified mode. mode (MxPDC this count starts from includes framing code. non-PDC modes (MxPDC this count starts from first byte.
Read:
MxSL3 MxSL2 MxSL1 MxSL0 MxRF MxLEN MxREN MxOEN
Write: Reset:
Figure 4-22. Mode Description Register (MxD2) MxSL3:MxSL0 Mode Slice Level These bits determine voltage level which vertical blanking information data will sliced. MxRF Mode Rising/Falling edge clock synchronization This determines edge which sampling clock synchronized. Write: Clock synchronization edge falling edge video signal. Clock synchronization edge rising edge video signal.
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Mode Description Registers
FALLING CLOCK SYNCHRONIZATION EDGE
SAMPLING EDGE
RESYNCHRONIZATION EDGE
CLOCK SYNCHRONIZATION EDGE
RISING CLOCK SYNCHRONIZATION EDGE
SAMPLING EDGE
RESYNCHRONIZATION EDGE
CLOCK SYNCHRONIZATION EDGE
Figure 4-23. Clock Synchronization Edge MxLEN Mode Digital Pass Filter Enable This enables VData digital pass filter.
digital pass filter been included data slicer signal chain improve performance under noisy conditions. Since this filter will remove signal pulses with duration less than four clocks, suitable very high frequency data care should exercised application. maximum noise duration 4/(fSync Where fSync frequency horizontal sync input SYNC value C0:C7 EPLLD register plus 1728. pulse, negative positive, having duration less than 4/(fSync will considered noise will removed.
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Write: Filter enabled Filter disabled
Data Extraction Module
minimum signal duration 4/(fSync pulses having duration greater than 4/(fSync will considered data bits removed.
FROM
DIGITAL SYNCHRONIZER PASS FILTER EXTRACTION CIRCUIT
VDATA
CLOCK (fSync
Figure 4-24. Digital Pass Filter Block Diagram MxREN Mode Resynchronization Circuit Enable This enables extraction module clock resynchronization circuit. Write: Resynchronization disabled Resynchronization enabled this set, resynchronization circuit will disabled. After expiration count clock delay register resynchronization first rising edge, clock resynchronization will done. this clear, resynchronization will performed every edge specified MxRF illustrated Figure 4-23. MxOEN Mode Data Slicer Output Enable This enables extraction module data slicer outputs SDATA, SCLK, SWIN. Write: Data slicer output signal enabled mode enabled Data slicer output signal disabled mode disabled serial mode, when this set, SDATA, SCLK, SWIN enabled. These signals will become active described Figure 4-4. serial mode, when this clear SDATA,SCLK, SWIN will fixed low. parallel mode, this effect.
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Teletext Hamming Decoder
4.12 Teletext Hamming Decoder
extraction module includes teletext Hamming decoder mode. decoder used single error detection correction bytes through format 8/30 packets bytes through format 8/30 packets. Additionally, multiple errors detected.
INPUT INCREASING TIME
HAMMING DECODER OUTPUT
input byte consists four message bits (M3, four protection bits (P3, P0). single error occurs these bits, error will corrected output byte single error bit, will output byte. multiple errors occur, multiple error bit, will set. multiple errors present, they cannot corrected.
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module
Table 4-3. Teletext Hamming Decoder
Input Byte Output Nibble
4.13 Mode
This mode allows user select data based detection extension data packets type 8/30. Additionally, teletext Hamming decode will performed shown Figure 4-25. This sequence will followed: Those lines selected mode (MxPDC will sampled into circuitry according sampling clock mode description that line. data stream will searched match teletext framing code. When least seven eight bits match framing
General Release Specification Data Extraction Module MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Mode
code, framing code will entered into data registers without error correction. framing code detected before leading edge next line's horizontal sync, byte data entered into data registers process stops. Following Hamming decode, bytes magazine address group, compared 8/30 format code. magazine address group match 8/30 format code, these bytes entered into data registers process stops. match occurs, these bytes entered into data registers process continues. Following Hamming decode, byte designation code, compared format designation code. designation code format mode will assumed bytes through Hamming decoded entered into data registers. designation code other than format only bytes through will Hamming decoded entered into data registers. remaining bytes, counted from framing code until expiration MxB5:MxB0, entered into data register without Hamming decode. Figure 4-26.
MRAG
STOP MRAG 8/30
STATUS DISPLAY
BITS MATCH FRAMING CODE
MRAG MRAG MRAG 8/30 FORMAT
STATUS DISPLAY
HAMMING DECODED FORMAT
STATUS DISPLAY
Figure 4-25. Mode Teletext Hamming Decode Enable Diagram
MC68HC68VBI Rev. MOTOROLA Data Extraction Module General Release Specification
7-12
13-25
26-45
Data Extraction Module
4.13.1 Framing Code Synchronization third byte every data line comprises framing code 11100100. This code used establish byte synchronization even framing code been wrongly received. Figure 4-26 indicates incoming data compared with framing code pattern. shows that test seven corresponding bits will give correct indication framing code presence single error. framing code Hamming decoded. However, single error allowed. After seven eight bits framing code have been located stream, framing code entered into data registers with error correction.
INCREASING TIME
EXAMPLE WITH 8-BIT CLOCK RUN-IN MOVING THROUGH SHIFT REGISTER
FRAMING CODE SHIFT REGISTER
TEST BYTE COMPARISON WITH DATA SHIFT REGISTER
Figure 4-26. Operation Framing Code Synchronization
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Mode
4.13.2 8/30 Magazine Address Group Match forth fifth bytes every data line magazine address group. These codes used determine line 8/30 format not. Figure 4-27 indicates incoming data compared with 8/30 format pattern. shows that bytes first teletext Hamming decoded before comparison performed, allowing single correctable error each byte. this code matched, error assumed further data entered into data registers.
INCREASING TIME HAMMING DECODER
TEST BYTE COMPARISON WITH HAMMING DECODER OUTPUT
Figure 4-27. Operation 8/30 MRAG Comparison 4.13.3 Format Designation Code Match sixth byte 8/30 format data lines designation code. This code used determine line format not. Figure 4-27 indicates incoming data compared with format pattern. shows that bytes first teletext Hamming decoded before comparison performed, allowing single correctable error. this code matched, format will assumed and, read, bytes through will Hamming decoded. this code matched, bytes through will Hamming decoded, remaining bytes will Hamming decoded.
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module
INCREASING TIME
HAMMING DECODER
TEST NIBBLE COMPARISON WITH HAMMING DECODER OUTPUT
Figure 4-28. Operation Format Designation Code Comparison
4.14 Line Control Registers
Read:
LxM1
LxM0
LyM1
LyM0
Write: Reset:
Unimplemented
Figure 4-29. Line Control Registers (LCRx/LCRy) Line output enable bits These bits enable data acquisition indicated line number, LxM1:LxM0 LyM1:LyM0 Line mode bits These bits determine mode number line number indicated,
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Field Sync Line Sync Registers
4.15 Field Sync Line Sync Registers
Address: $0080 Read: Write: Reset:
LRPL
SCHK
L7C3
L7C2
L7C1
L7C0
Unimplemented Unaffected
Figure 4-30. Field Sync Line Sync Registers (FSL7) Reserved These used. Reading this yield FieLD This indicates most recently sampled field display. Read: Field Field LRPL Lock state This indicates locked input signal. description State Description. Read: Locked locked SCHK Sync Check This when clamped input signal SYNC less than voltage reference determined SSL3:SSL0 including comparator offset. This cleared read read $02. L7C3:L7C0 Line Quasi-Sync Count These bits give number quasi-sync pulses counted line most recently sampled field display.
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
Data Extraction Module 4.16 Quasi-Sync Line Count Registers
Read: Write: Reset:
LxC3
LxC2
LxC1
LxC0
LyC3
LyC2
LyC1
LyC0
Unimplemented Unaffected
Figure 4-31. Line Control Register (L8/L9-L22/L23)
LxC3:LxC0 Line Quasi-Sync Count These bits give number quasi-sync pulses counted line most recently sampled field display. LyC3:LyC0 Line Quasi-Sync Count These bits give number quasi-sync pulses counted line most recently sampled field display.
4.17 Address Register
Address: $0089 Read: Write: Reset:
MULT
PAR6
PAR5
PAR4
PAR3
PAR2
PAR1
PAR0
Unimplemented
Figure 4-32. Address Register (PAR)
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
Data Extraction Module Read Data Registers
MULT Multiple Error This indicates multiple errors have occurred teletext Hamming decoded bytes present field. Read: Multiple error multiple error This read-only cleared vertical sync. PAR6:PAR0 Address Match
4.18 Read Data Registers
Read: Write: Reset:
RxB7
RxB6
RxB5
RxB4
RxB3
RxB2
RxB1
RxB0
Unimplemented Unaffected
Figure 4-33. Read Data Registers (RD0-RD83) RxB7:RxB0 Read Data These registers contain data extracted from most recent field. These registers cleared detection vertical sync. They cleared reset.
MC68HC68VBI Rev. MOTOROLA Data Extraction Module
General Release Specification
These bits offset from location location designation code extracted data data registers. These bits cleared vertical sync detection. 8/30 magazine address group occurs, these bits will remain indicate this.
Data Extraction Module
MODE
ENTER DATA REGISTERS
FRAMING CODE DETECTED
ENTER FRAMING CODE DATA REGISTERS
STOP (PAR $00)
MRAG 8/30 MATCH DESIGNATION CODE OFFSET
HAMMING DECODE LINES 7-12 ENTER INTO DATA REGISTERS
DESIGNATION CODE FORMAT MATCH
ENTER LINES 13-25 INTO DATA REGISTERS WITHOUT HAMMING DECODE
HAMMING DECODE LINES 7-25 ENTER INTO DATA REGISTERS
DATA SPECIFIED LINE ENTER DATA UNTIL EXPIRATION MXB5:MXB0
ENTER DATA UNTIL EXPIRATION MXB5:MXB0 WITHOUT HAMMING DECODE
Figure 4-34. Data Entry Flow Diagram
General Release Specification Data Extraction Module
MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
Section Multiplexed Expansion
Contents
Introduction
Introduction
MC68HC68VBI 8-bit, multiplexed, expanded interface exchange information between host internal status/data control registers.
MC68HC68VBI Rev. MOTOROLA Multiplexed Expansion
General Release Specification
Multiplexed Expansion
WRITE CYCLE
A/D7:A/D0
ADDR
DATA
R/W,
NOTES: Expanded mode input clock period Expanded mode input clock time Expanded mode input clock high time Address valid signal rising edge Delay time, rising edge pulse width Address hold time Input data hold time Address setup time Write data valid signal falling edge
Figure 5-1. Multiplexed Expansion Write Cycle Timing
General Release Specification Multiplexed Expansion
MC68HC68VBI Rev. MOTOROLA
Multiplexed Expansion Introduction
READ CYCLE
A/D7:A/D0 R/W,
ADDR
DATA
Figure 5-2. Multiplexed Expansion Read Cycle Timing
MC68HC68VBI Rev. MOTOROLA Multiplexed Expansion
General Release Specification
NOTES: Expanded mode input clock period Expanded mode input clock time Expanded mode input clock high time Address valid signal rising edge Output data hold time Delay time, rising edge pulse width Address hold time rising edge valid data Address setup time
Multiplexed Expansion
General Release Specification Multiplexed Expansion
MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
Section Serial Peripheral Interface (SPI)
Contents
Introduction Memory Access
Introduction
MC68HC68VBI full-duplex serial peripheral interface (SPI) exchange information between host internal status/ data control registers. serial clock (SCK) chip select (CS) provided host MCU. Serial data input (SDI) input only. Serial data output (SDO) open-drain output only. Figure 6-1.
MC68HC68VBI Rev. MOTOROLA Serial Peripheral Interface (SPI)
General Release Specification
Serial Peripheral Interface (SPI)
STATUS/DATA REGISTERS SERIAL PERIPHERAL INTERFACE CONTROL REGISTERS
Figure 6-1. Block Diagram
Memory Access
registers control operation SPI. However, there flexibility both read write operations executed. start stop addresses data written control registers determined first data bytes input SPI. Data always read from address status/data registers, address selected terminating connection. Figure 6-2. Data sent received least significant (LSB) first illustrated Figure 6-3. Before falling edge must held high externally. After chip select asserted, first bytes clocked into write start (STA) write ignore (IGN) address. Thereafter, data clocked into write-only registers starting from address STA. ignore address (IGN), data longer entered into memory. Clocks must applied full byte ignore address enter previous data into register. will enter data sequentially into control registers from start address until address reached. data clocked address
General Release Specification Serial Peripheral Interface (SPI) MC68HC68VBI Rev. MOTOROLA
Serial Peripheral Interface (SPI) Memory Access
data since will entered into control registers. However, this final byte must clocked ensure that previous bytes have been entered into control registers. After dummy data address been clocked information exchange terminated, desired. However, reading status/data registers complete, additional clocks will enter data into control registers after address. Starting from first clock used clock address STA, data clocked read-only registers from address $80. Even after address been reached, data clocked from pin. When address status/data registers reached, data this address will clocked out. clocks applied after this address, data will continue clocked sequentially. Following data $FF, data will clocked out. When serial peripheral interface selected, data acquisition module cannot access internal status/data registers. host processor's responsibility ensure that serial peripheral interface selected during vertical blanking interval.
MC68HC68VBI Rev. MOTOROLA Serial Peripheral Interface (SPI)
General Release Specification
Serial Peripheral Interface (SPI)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
ADDRESS
DATA STA+1
DATA STA+2
DATA STA+3
DATA
ADDRESS
Figure 6-2. Interface Description
General Release Specification Serial Peripheral Interface (SPI)
MC68HC68VBI Rev. MOTOROLA
Serial Peripheral Interface (SPI) Memory Access
BUSY
HI-Z
HI-Z
Figure 6-3. Timing Diagram
MC68HC68VBI Rev. MOTOROLA Serial Peripheral Interface (SPI)
General Release Specification
NOTES: Cycle time Time cycle BUSY chip selet time Wait time required after BUSY chip select Chip select lead time Wait time required after before first clock Chip select time Wait time required after last clock before high Clock high time Time clock high Clock time Time clock Data setup time Time from change data until rising edge Data hold time Time from rising edge until data change Access time Time high impedance state active data Disable time Time from active data high impedance Data valid -Time from falling edge active data Rise time Time from Fall time Time from Input amplitude levels input signal Output amplitude levels output signal
Serial Peripheral Interface (SPI)
General Release Specification Serial Peripheral Interface (SPI)
MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
Section Electrical Specifications
Contents
7.10 7.11 Introduction .101 Maximum Ratings .102 Operating Temperature Range. .102 Thermal Characteristics .102 Electrical Characteristics. .103 Data Extraction Characteristics .104 Expanded Interface Characteristic .105 Data Slicer Output Characteristics .106 Serial Peripheral Interface Characteristics .107
Introduction
This section contains electrical timing specifications.
MC68HC68VBI Rev. MOTOROLA Electrical Specifications
General Release Specification
Phase-Locked Loop Characteristics .107
Electrical Specifications Maximum Ratings
Maximum ratings extreme limits which exposed without permanently damaging contains circuitry protect inputs against damage from high static voltages; however, apply voltages higher than those shown table. Keep VOut within range (VIn VOut) VDD. Connect unused inputs appropriate voltage level, either VDD.
Rating Supply Voltage Input Voltage Current Drain Pin, Excluding Storage Temperature Range
NOTE: Voltages referenced
Symbol Tstg
Value -0.3 +7.0 -0.3 +150
Unit
Operating Temperature Range
Rating Operating Temperature Range MC68HC68VBI (Standard) Symbol Value Unit
Thermal Characteristics
Characteristic Thermal Resistance 32-Pin Quad Flat Pack (QFP) Symbol Value Unit
General Release Specification
MC68HC68VBI Rev. Electrical Specifications MOTOROLA
Electrical Specifications Electrical Characteristics
Electrical Characteristics
Characteristic
Output Voltage ILoad ±10.0 AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7, OSC2 Output High Voltage (ILoad -0.8 AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7, OSC2 Output Voltage (ILoad AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7, OSC2 Input High Voltage RESET, SDI/AS, SCK/E, (Serial Activated) Input Voltage RESET, SDI/AS, SCK/E, (Serial Activated) Output Voltage (ILoad SDO/RW, BUSY
Input High Voltage AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7, OSC1,PAR/SER TEST, SDO/RW, SDI/AS, SCK/E, (Parallel Activated) SDI/AS, SCK/E, (Serial Activated) Input Voltage AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7, OSC1, PAR/SER TEST, SDO/RW, SDI/AS, SCK/E, (Parallel Activated) Supply Current (See NOTES) Power Save (Standard) Hi-Z Leakage Current TEST, PAR/SER, RESET, SDI/AS CK/E, CSA, OSC1, AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7 Capacitance AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7, OSC2, BUSY TEST, PAR/SER, RESET, SDI/AS SCK/E, CSA, OSC1, AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7 Pull-Down Current AD0/SCLK, AD1/SDATA, AD2/SWIN, AD3:AD7 (Serial Mode)
Symbol
VDD-0.1 VDD-0.8
Unit
IDD1 +IDD2 +IDD3
COut
-100
NOTES: ±10%, Typical values midpoint voltage range, only. supply current measurements made with modes enabled PLLs nominal frequenties. Power save supply current measurements made with pins configured inputs, Vdc, -0.2 Vdc.
MC68HC68VBI Rev. MOTOROLA Electrical Specifications
General Release Specification
Electrical Specifications Data Extraction Characteristics
Characteristic Data Extraction Input Voltage Amplitude1 Sync Pedestal Level Pedestal Level Maximum Data Minimum Data Maximum Data Level Horizontal Line Frequency (525-Line System) Symbol 0.25 15,655 15,546 15,734 15,625 1000 15,813 15,703 12.5 Unit mV/ns
Horizontal Line Frequency (625-Line System) Data Slicer Reference Voltage Error Sync Slicer Reference Voltage Error Pedestal Voltage Change (Lines 4-28) Quasi-Horizontal Sync Duration Vertical Sync Duration Fall Slope Sync Signals (HSync, VSync, Equal Pulse)3
NOTES:
±10%, Refer Figure 4-16. Data Extraction Slice Level Description. transition slope (This calculated recommendation value proper operation tested.)
General Release Specification
MC68HC68VBI Rev. Electrical Specifications MOTOROLA
Electrical Specifications Expanded Interface Characteristic
Expanded Interface Characteristic
Characteristic(1) Expanded Mode Input Clock Period Expanded Mode Input Clock Time Expanded Mode Input Clock High Time Address Valid Signal Rising Edge Output Data Hold Time Delay Time, Rising Edge Pulse Width Address Hold Time Rising Edge Valid Data Input Data Hold Time Address Setup Time Write Data Valid Signal Falling Edge
NOTES:
Symbol
Unit
±10%, Refer Figure 5-1. Multiplexed Expansion Write Cycle Timing Figure 5-2. Multiplexed Expansion Read Cycle Timing.
MC68HC68VBI Rev. MOTOROLA Electrical Specifications
General Release Specification
Electrical Specifications Data Slicer Output Characteristics
Characteristic SWIN Leading Edge Clock Clock SWIN Trailing Edge SCLK Period SCLK High Time SCLK Time Symbol Unit
Data Setup Time Data Hold Time Signal Falling Time Signal Rising Time
NOTES: ±10%, This table valid only Moji Tajuu frequency signals with five more samplings data bit. CLoad Refer Figure 4-4. Data Slicer Output Signal Timing Diagram.
General Release Specification
MC68HC68VBI Rev. Electrical Specifications MOTOROLA
Electrical Specifications Serial Peripheral Interface Characteristics
7.10 Serial Peripheral Interface Characteristics
Characteristic Cycle Time Busy Chip Select Time Chip Select Lead Time Chip Select Time Clock High Time Clock Time Data Setup Time Data Hold Time Access Time Disable Time Data Valid Rise Time Fall Time
NOTES: 10%, Refer Figure 6-3. Timing Diagram.
Symbol tcyc tBCS tLead tLAG tDIS
Unit
7.11 Phase-Locked Loop Characteristics
Characteristic Phase Jump Ready Time fOSC 3.57 fOSC 4.43
NOTE: Refer Figure 3-8.
Symbol tPJR
16.0374 19.417
Unit
MC68HC68VBI Rev. MOTOROLA Electrical Specifications
General Release Specification
Electrical Specifications
General Release Specification
MC68HC68VBI Rev. Electrical Specifications MOTOROLA
General Release Specification MC68HC68VBI
Section Mechanical Specifications
Contents
Introduction .107 28-Pin Plastic Dual In-Line Package (Case 873) .108
Introduction
This section describes dimensions dual in-line package (DIP) small outline integrated circuit (SOIC) packages. following figure shows latest package information time this publication. make sure that have latest package specifications, contact following: Local Motorola Sales Office Motorola Back System (MfaxTM) Phone 1-602-244-6609 EMAIL RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/ Worldwide (wwweb) home page http://motorola.com/sps/
Follow Mfax wwweb on-line instructions retrieve current mechanical specifications.
MC68HC68VBI Rev. MOTOROLA Mechanical Specifications
General Release Specification
Mechanical Specifications 28-Pin Plastic Dual In-Line Package (Case 873)
0.05 (0.002)
0.20 (0.008)
0.20 (0.008)
DETAIL
-A-, -B-, 0.20 (0.008)
DETAIL
0.05 (0.002) 0.20 (0.008)
BASE METAL
DETAIL 0.20 (0.008)
SEATING PLANE
DATUM PLANE
0.01 (0.004)
SECTION
VIEW ROTATED CLOCKWISE
DATUM PLANE
DETAIL
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE LOCATED BOTTOM LEAD COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY BOTTOM PARTING LINE. DATUMS -A-, DETERMINED DATUM PLANE -H-. DIMENSIONS DETERMINED SEATING PLANE -C-. DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 (0.010) SIDE. DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE -H-. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT LOCATED LOWER RADIUS FOOT.
MILLIMETERS 6.95 7.10 6.95 7.10 1.40 1.60 0.273 0.373 1.30 1.50 0.273 0.80 0.20 0.119 0.197 0.33 0.57 0.119 0.135 0.40 0.15 0.25 8.85 9.15 0.15 0.25 8.85 9.15 1.00
INCHES 0.274 0.280 0.274 0.280 0.055 0.063 0.010 0.015 0.051 0.059 0.010 0.031 0.008 0.005 0.008 0.013 0.022 0.220 0.005 0.005 0.016 0.006 0.010 0.348 0.360 0.006 0.010 0.348 0.360 0.039
CASE General Release Specification Mechanical Specifications MC68HC68VBI Rev. MOTOROLA
General Release Specification MC68HC68VBI
Section Ordering Information
Contents
Introduction .109 Order Number .109
Introduction
This section contains ordering information MC68HC68VBI.
Order Number
Table shows order number available package type. Table 9-1. Order Number
Package Type 28-Pin Plastic Dual In-Line Package (DIP) Operating Temperature Range Order Number
MC68HC68VBIFB
MC68HC68VBI Rev. MOTOROLA Ordering Information
General Release Specification
Ordering Information
General Release Specification Ordering Information
MC68HC68VBI Rev. MOTOROLA
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution, P.O. 5405, Denver, Colorado 80217, 1-800-441-2447 1-303-675-2140. Customer Focus Center, 1-800-521-6274 JAPAN: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan, 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Ping Industrial Park, Ting Road, N.T., Hong Kong, 852-26629298 MfaxTM, Motorola Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/; TOUCHTONE, 1-602-244-6609; Canada ONLY, 1-800-774-1848 HOME PAGE: http://motorola.com/sps/
Mfax trademark Motorola, Inc. Motorola, Inc., 1997
MC68HC68VBI/D
Other recent searches
TBA820M - TBA820M TBA820M Datasheet
SNC10D - SNC10D SNC10D Datasheet
SD103CWS - SD103CWS SD103CWS Datasheet
SA001Z16B - SA001Z16B SA001Z16B Datasheet
RH128160T-009-F - RH128160T-009-F RH128160T-009-F Datasheet
LT175M-Q21-LIOX3-H1141 - LT175M-Q21-LIOX3-H1141 LT175M-Q21-LIOX3-H1141 Datasheet
ADM13307 - ADM13307 ADM13307 Datasheet
2SC4682 - 2SC4682 2SC4682 Datasheet
1755570000 - 1755570000 1755570000 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
