µPD780204, 780205, 780206, 780208 8-BIT SINGLE-CHIP MICROCONTROLL

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µPD780204, 780205, 780206, 780208 8-BIT SINGLE-CHIP MICROCONTROLL

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INTEGRATED CIRCUIT
µPD780204, 780205, 780206, 780208
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD780204, 780205, 780206, 780208 microcontrollers products µPD780208 subseries 78K/0 series, incorporate many hardware peripherals such FIPcontroller/driver, 8-bit resolution converter, timer, serial interface, interrupt controller. addition these standard mask models, one-time PROM models that operate same voltage range, EPROM models µPD78P0208, various development tools available. functions these microcontrollers described detail following User's Manual. sure read this manual when design system using these microcontrollers.
µPD780208 Subseries User's Manual: U11302E
78K/0 Series User's Manual Instruction: IEU-1372
FEATURES
High-capacity
Item Product Name Program Memory (ROM) bytes bytes bytes bytes 1024 bytes Internal high-speed 1024 bytes Data Memory Package Buffer bytes display Internal expansion bytes provided 100-pin plastic
µPD780204 µPD780205 µPD780206 µPD780208
Wide range instruction execution time from high-speed (0.4 ultra low-speed (122 ports: controller/driver: total display outputs:
8-bit resolution converter: channels Serial interface: channels Timer: channels Power supply voltage:
APPLICATIONS
Minicomponent stereo, cassette deck, tuner, player, VCR.
ORDERING INFORMATION
Part Number Package 100-pin plastic 100-pin plastic 100-pin plastic 100-pin plastic
Remark indicates code number.
information this document subject change without notice. Document U10436EJ2V0DS00 (2nd edition) Date Published February 1997 Printed Japan mark shows major revised point.
1994
µPD780204, 780205, 780206, 780208
78K/0 SERIES PRODUCT DEVELOPMENT following shows 78K/0 Series products development. Subseries name shown inside frames.
Products mass production Products under development subseries products compatible with bus. EMI-noise reduced version PD78078 timer added µPD78054 external interface enhanced ROM-less version µPD78078 Serial PD78078 enhanched function limited Serial PD78054 enhanced EMI-noise reduced EMI-noise reduced version PD78054 UART converter were added PD78014 enchanced converter µPD780024 enchanced Serial µPD78018F added EMI-noise reduced EMI-noise reduced version PD78018F Low-voltage (1.8 operation version µPD78014, with larger selection capacities converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
µPD78075B µPD78075BY µPD78078 µPD78078Y PD78070A µPD78070AY µPD780018Note PD780018YNote PD780058 PD780058YNote PD78058F PD78058FY PD78054 PD78054Y PD780034 PD780034Y PD780024 µPD780024Y PD78014H PD78018F PD78018FY µPD78014 PD78014Y µPD780001 µPD78002 µPD78002Y µPD78083
Inverter control
64-pin 64-pin 78K/0 Series
PD780964 PD780924
drive
converter µPD780924 enhanced On-chip inverter control circuit UART. EMI-noise reduced. µPD78044F were enhanced, Display output total: µPD78044H were enhanced, Display output total: N-ch open drain added µPD78044F, Display output total: Basic subseries driving FIP, Display output total:
100-pin 100-pin 80-pin 80-pin
µPD780208 PD780228 µPD78044H µPD78044F
drive
100-pin 100-pin 100-pin
PD780308 PD78064B µPD78064
µPD780308Y PD78064Y
µPD78064 enhanced ROM, capacity increased EMI-noise reduced version µPD78064 Basic subseries driving LCDs, On-chip UART
IEBussupported 80-pin
PD78098
IEBus controller added PD78054
64-pin
PD78P0914
On-chip output, digital code decoder, Hsync counter
Note
Under planning
µPD780204, 780205, 780206, 780208
following lists main functional differences between subseries products.
Function Subseries Name Control Capacity (time division 3-wire: 1ch) (time division UART: 1ch) (UART: 1ch) Timer 8-bit 16-bit Watch 8-bit 10-bit 8-bit Serial Interface (UART 1ch) MIN. External Value Expansion
µPD78075B µPD78078 µPD78070A µPD780018 µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
(UART: 1ch, time division 3-wire: 1ch)
Note (time division UART: 1ch) (UART (UART: 1ch) (UART: 2ch)
Inverter control drive
µPD780964 µPD780924 µPD780208 µPD780228 µPD78044H µPD78044F
drive
µPD780308 µPD78064B µPD78064
IEBus supported
µPD78098 µPD78P0914
(UART
Note
10-bit timer: channel
µPD780204, 780205, 780206, 780208
FUNCTIONAL OUTLINE
Product Name Item Internal memory High-speed Buffer display Expansion General-purpose registers Instruction cycle provided
µPD780204
bytes
µPD780205
bytes 1024 bytes bytes bytes
µPD780206
bytes
µPD780208
bytes
1024 bytes
bits registers bits registers banks) Variable instruction execution time
w/main system clock w/subsystem clock
µs/0.8 µs/1.6 µs/3.2 µs/6.4 MHz) 32.768 kHz) Multiplecation/division bits bits, bits bits) operation (set, reset, test, Boolean algebra)
Instruction
ports (including those multiplexed with pins)
Total CMOS input CMOS N-ch open-drain P-ch open-drain P-ch open-drain output
lines lines
lines lines
lines lines
controller/driver
Total Segment Digit
lines lines lines
converter
8-bit resolution channels Supply voltage AVDD
Serial interface
3-wire serial I/O/SBI/2-wire serial mode selectable
channel
3-wire serial mode (w/automatic transfer/receive function bytes): channel Timer 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer Timer output Clock output lines (one 14-bit output) 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, (main system clock: MHz) 32.768 (subsystem clock: 32.768 kHz) Buzzer output kHz, kHz, (main system clock: MHz) channel channels channel channel
µPD780204, 780205, 780206, 780208
Product Name Item Vectored interrupt sources Maskable Non-maskable Software Test input Supply voltage Package
µPD780204
Internal: external: Internal: Internal: line
µPD780205
µPD780206
µPD780208
100-pin plastic
µPD780204, 780205, 780206, 780208
CONTENTS
CONFIGURATION (Top View) BLOCK DIAGRAM FUNCTIONS
PORT PINS PINS OTHER THAN PORT PINS CIRCUITS PROCESSING UNUSED PINS
MEMORY SPACE. PERIPHERAL HARDWARE FUNCTIONS
PORTS CLOCK GENERATOR CIRCUIT TIMER/EVENT COUNTER CLOCK OUTPUT CONTROL CIRCUIT BUZZER OUTPUT CONTROL CIRCUIT CONVERTER SERIAL INTERFACE CONTROLLER/DRIVER
INTERRUPT FUNCTION TEST FUNCTION
INTERRUPT FUNCTION TEST FUNCTION
STANDBY FUNCTION RESET FUNCTION INSTRUCTION
ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVE (REFERENCE VALUE) PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD780204, 780205, 780206, 780208
CONFIGURATION (Top View)
100-Pin Plastic
µPD780204GF µPD780205GF µPD780206GF µPD780208GF
Cautions Connect (Internally Connected) pins directly VSS. Connect AVDD pin. Connect AVSS pin.
P12/ANI2 P11/ANI1 P10/ANI0 AVDD AVREF P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 P127/FIP52 P126/FIP51 P125/FIP50 P124/FIP49
P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 RESET P04/XT1 P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P24/BUSY P23/STB P22/SCK1 P21/SO1 P20/SI1 AVSS P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3
FIP0 FIP1 FIP2 FIP3 FIP4 FIP5 FIP6 FIP7 FIP8 FIP9 FIP10 FIP11 FIP12 P80/FIP13 P81/FIP14 P82/FIP15 P83/FIP16 P84/FIP17 P85/FIP18 P86/FIP19
P87/FIP20 VLOAD P90/FIP21 P91/FIP22 P92/FIP23 P93/FIP24 P94/FIP25 P95/FIP26 P96/FIP27 P97/FIP28 P100/FIP29 P101/FIP30 P102/FIP31 P103/FIP32 P104/FIP33 P105/FIP34 P106/FIP35 P107/FIP36 P110/FIP37 P111/FIP38 P112/FIP39 P113/FIP40 P114/FIP41 P115/FIP42 P116/FIP43 P117/FIP44 P120/FIP45 P121/FIP46 P122/FIP47 P123/FIP48
µPD780204, 780205, 780206, 780208
P00-P04 P10-P17 P20-P27 P30-P37 P70-P74 P80-P87 P90-P97 P100-P107 P110-P117 P120-P127 TI0-TI2 TO0-TO2 SB0, SI0, SO0, Port0 Port1 Port2 Port3 Port7 Port8 Port9 Port10 Port11 Port12 Timer Input Timer Output Serial Serial Input Serial Output SCK0, SCK1 Serial Clock BUSY FIP0-FIP52 VLOAD XT1, RESET ANI0-ANI7 AVDD AVSS AVREF Programmable Clock Buzzer Clock Strobe Busy Fluorescent Indicator Panel Negative Power Supply Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Ground Internally Connected
INTP0-INTP3 Interrupt from Peripherals
µPD780204, 780205, 780206, 780208
BLOCK DIAGRAM
P100 P107 P110 P117 P120 P127
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
PORT PORT
8-bit TIMER/ EVENT COUNTER 8-bit TIMER/ EVENT COUNTER WATCHDOG TIMER WATCH TIMER
PORT PORT PORT PORT PORT
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27
SERIAL INTERFACE
78K/0 CORE
PORT PORT
SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24
SERIAL INTERFACE
PORT
ANI0/P10 ANI7/P17 AVDD AVSS AVREF
CONVERTER
CONTROLLER/ DRIVER
FIP0 FIP52 VLOAD
INTP0/TI0/P00 INTP3/P03
INTERRUPT CONTROL RESET XT1/P04
BUZ/P36 PCL/P35
BUZZER OUTPUT CLOCK OUTPUT CONTROL
SYSTEM CONTROL
Remark capacities internal differ depending product.
µPD780204, 780205, 780206, 780208
FUNCTIONS
PORT PINS (1/2)
Input Function Input only specified input output 1Port P04Note Input 5-bit port units. When used input port pin, on-chip pull-up resistor used through software. Input only Input Input INTP2 INTP3 Reset Input Sharde INTP0/TI0 INTP1
Name
Port P10-P17 8-bit port specified input output 1-bit units. When used input port pin, on-chip pull-up resistor used through software. Port 8-bit port specified input output 1-bit units. directly drive LEDs. When used input port pin, on-chip pull-up resistor used through software. pull-down resistor connected 1-bit units mask option. Input Port 8-bit port specified input output 1-bit units. When used input port pin, on-chip pull-up resistor used through software. Input BUSY SI0/SB0 SO0/SB1 SCK0
Note
Input
ANI0-ANI7
SCK1
Notes
When P04/XT1 pins used input port pin, (FRC) porcessor clock control register (PCC) must this time, feedback resistor subsystem clock oscillator circuit.) When P10/ANI0 through P17/ANI7 pins used analog input lines converter, sure place port input mode. this case, on-chip pull-up resistors automaticaly unused.
µPD780204, 780205, 780206, 780208
PORT PINS (2/2)
Name
Port 5-bit N-ch open-drain port
Function
Reset
Shared
P70-P74
specified input output 1-bit units. directly drive LEDs. pull-up resistor connected 1-bit units mask option. Port 8-bit P-ch open-drain high-voltage output port
Input
P80-P87
Output
directly drive LEDs. pull-down resistor connected 1-bit units mask option (whether VLOAD connected specified 4-bit units). Port 8-bit P-ch open-drain high-voltage output port
Output
FIP13-FIP20
P90-P97
Output
directly drive LEDs. pull-down resistor connected 1-bit units mask option (whether VLOAD connected specified 4-bit units). Port 8-bit P-ch open-drain high-voltage output port
Output
FIP21-FIP28
P100-P107
specified input output units. directly drive LEDs. pull-down resistor connected 1-bit units mask option (whether VLOAD connected specified 4-bit units). Port 8-bit P-ch open-drain high-voltage port
Input
FIP29-FIP36
P110-P117
specified input output 1-bit units. directly drive LEDs. pull-down resistor conneced 1-bit units mask option (whether VLOAD connected specified 4-bit units). Port12 8-bit P-ch open-drain high-voltage port.
Input
FIP37-FIP44
P120-P127
specified input output 1-bit units. directly drive LEDs. pul-down resistor connected 1-bit units mask option (whether VLOAD connected specified 4-bit units).
Input
FIP45-FIP52
µPD780204, 780205, 780206, 780208
PINS OTHER THAN PORT PINS (1/2)
Function Valid edge (rising, falling, both rising falling edges) specified. External interrupt request input Falling edge-active external interrupt input Input Output SCK0 SCK1 BUSY Output Output Input Output Input Automatic transfer/receive strobe output line serial interface Automatic transfer/receive busy input line serial interface External count clock input 16-bit timer (TM0) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) 16-bit timer (TM0) output (multiplexed with 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) output Clock output (for trimming main system clock subsystem clock) Buzzer output High-voltage, high-current output controller/driver display output pull down register connected mask option. Input Input Input Input Input Serial clock lines serial interface Input P00/INTP0 Serial data lines serial interface Input P26/SO0 Serial data output lines serial interface Input P25/SI0 Serial data input lines serial interface Reset Shared P00/TI0 Input Input Input P26/SB1 P25/SB0
Name INTP0 INTP1
Input INTP2 INTP3
Output
Input
FIP0-FIP12
Output
Output
FIP13-FIP20 FIP21-FIP28 FIP29-FIP36 FIP37-FIP44 FIP45-FIP52 VLOAD Connects pull-down resistor controller/driver Output High-voltage, high-current output controller/driver display output
Output
P80-P87 P90-P97 P100-P107
Input
P110-P117 P120-P127
µPD780204, 780205, 780206, 780208
PINS OTHER THAN PORT PINS (2/2)
Input Input Input Input Connect crystal main system clock oscillation. Input Connect crystal subsystem clock oscillation. Positive power supply Ground potential Internal connection. Connected directly pin. Input Function converter analog input lines converter reference voltage input line Analog power supply converter. Connected pin. converter ground line. Connected pin. System reset input Reset Input Shared P10-P17
Name ANI0-ANI7 AVREF AVDD AVSS RESET
µPD780204, 780205, 780206, 780208
CIRCUITS PROCESSING UNUSED PINS
Table shows circuit type each processing unused pins. configuration circuit each type, refer Figure 3-1.
Table 3-1. Circuit Type
Name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0-P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P70-P74 FIP0-FIP12 P80/FIP13-P87/FIP20 P90/FIP21-P97/FIP28 P100/FIP29-P107/FIP36 P110/FIP37-P117/FIP44 P120/FIP45-P127/FIP52 RESET AVREF AVDD AVSS VLOAD Connect directly Connect Input Open Connect Connect 15-C Independently connect through resistor 14-A Output Open 13-B 10-A Independently connect through resistor Input Connect Independently connect through resistor Circuit Type Input Recommended Connections When Unused Connect
µPD780204, 780205, 780206, 780208
Figure 3-1. Circuits (1/2)
Type Type
pullup enable data P-ch IN/OUT output disable Schmitt trigger input with hysteresis characteristics
N-ch
P-ch
Type
pullup enable data P-ch
Type
pullup enable data IN/OUT
P-ch
P-ch
P-ch IN/OUT
output disable
N-ch
output disable
N-ch
(Mask Option)
input enable
Type
pullup enable data
Type 10-A
P-ch
pullup enable
P-ch
P-ch IN/OUT data P-ch IN/OUT (Mask Option) open drain output disable
N-ch
output disable input enable
N-ch
µPD780204, 780205, 780206, 780208
Figure 3-1. Circuits (2/2)
Type
pullup enable data P-ch IN/OUT output disable Comparator
P-ch
Type 15-C
P-ch
P-ch IN/OUT
data N-ch
N-ch P-ch N-ch (Mask Option) (Mask Option) (Mask Option) IN/OUT LOAD
N-ch (Threshold voltage) input enable
Type 13-B
Type
feedback cut-off P-ch
data output disable
N-ch
P-ch Medium-voltage input buffer
Type 14-A
P-ch data N-ch (Mask Option) LOAD (Mask Option) P-ch
µPD780204, 780205, 780206, 780208
MEMORY SPACE
Figure shows memory maps µPD780204, 780205, 780206, 780208.
Figure 4-1. Memory
FFFFH Special function register (SFR) bits General-purpose register bits FA2FH Inhibited F800H F7FFH F400H F3FFH Internal high-speed 1024 bits FB00H FAFFH Data memory space Buffer bits FAC0H FABFH FA80H FA7FH FA30H FA2FH nnnnH+1 nnnnH Program memory space 0000H Internal
Note
FF00H FEFFH FEE0H FEDFH
Internal expansion 1024 bits Inhibited
nnnnH+1 nnnnH Program area 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT entry area 0040H 003FH Vector table area 0000H
Note
Inhibited display bits Inhibited
Notes µPD780206 780208 only. internal capacities vary depending product. (Refer table below.)
Product Name
Internal Last Address nnnnH 7FFFH 9FFFH BFFFH EFFFH
µPD780204 µPD780205 µPD780206 µPD780208
µPD780204, 780205, 780206, 780208
PERIPHERAL HARDWARE FUNCTIONS
PORTS CMOS input (P00, P04) CMOS input/output (P01 P03, ports 1-3) N-ch open-drain input/output (port P-ch open-drain output (ports P-ch open-drain input/output (ports Total
ports classified into following kinds:
Table 5-1. Port Function
Name Name P00, Port P01-P03 Input port port. specified input output 1-bit units. When used input port, internal pull-up resistor connected through software. port. specified input output 1-bit units. When used input port, internal pull-up resistor connected through software. port. specified input output 1-bit units. When used input port, internal pull-up resistor connected through software. port. specified input output 1-bit units. When used input port, internal pull-up resistor connected through software. Pull-down resistor connected 1-bit units mask option. directly drive LED. N-ch open-drain port. specified input output 1-bit units. Pull-up resistor connected 1-bit units mask option. directly drive LED. P-ch open-drain high-voltage output port. Pull-down resistor connected 1-bit units mask option (connection VLOAD specified 4-bit units). directly drive LEDs. P-ch open-drain high-voltage output port. Pull-down resistor connected 1-bit units mask option (connection VLOAD specified 4-bit units). directly drive LEDs. P-ch open-drain high-voltage port. specified input output 1-bit units. Pull-down resistor connected 1-bit units mask option (connection VLOAD specified 4-bit units). directly drive LEDs. P-ch open-drain high-voltage port. specified input output 1-bit units. Pull-down resistor connected 1-bit units mask option (connection VLOAD specified 4-bit units). directly drive LEDs. P-ch open-drain high-voltage port. specified input output 1-bit units. Pull-down resistor connected 1-bit units mask option (connection VLOAD specified 4-bit units). directly drive LEDs. Function
Port
P10-P17
Port
P20-P27
Port
P30-P37
Port
P70-P74
Port
P80-P87
Port
P90-P97
Port
P100-P107
Port
P110-P117
Port
P120-P127
µPD780204, 780205, 780206, 780208
CLOCK GENERATOR CIRCUIT
clock generator circuit kinds generator circuits: main system clock subsystem clock. instruction time changed. µs/0.8 µs/1.6 µs/3.2 µs/6.4 (with main system clock: MHz) (with subsystem clock: 32.768 kHz)
Figure 5-1. Clock Generator Circuit Block Diagram
XT1/P04 Subsystem clock generator circuit
Clock output circuit
Selector
Selector
Noise detector circuit
Watch timer
Pre-scaler Main system clock generator circuit Pre-scaler STOP
Clock hardware peripherals
Selector
Standby control circuit INTP0 sampling clock
clock (fCPU)
TIMER/EVENT COUNTER channel channels channel channel
Five channels timer/event counters provided. 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer
Table 5-2. Timer/Event Counter Groups Configurations
16-bit Timer/ Event Counter Group Interval timer External event counter Timer output output Function Pulse width measurement Square wave output Interrupt Request Test input channel channel output output input output 8-bit Timer/ Event Counter channels channels outputs outputs Watch Timer channel input Watchdog Timer channel
µPD780204, 780205, 780206, 780208
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal
16-bit compare register (CR00) pulse output control circuit
INTTM0
Coincidence
Output control circuit
TO0/P30
X/22 X/23 TI0/INTP0/P00 Edge detector circuit
Selector
16-bit timer register(TM0) Selector INTP0
Cleared
16-bit capture register (CR01)
Internal
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal INTTM1
Selector
8-bit compare register (CR10)
8-bit compare register (CR20)
Coincidence
Coincidence
Output control circuit
TO2/P32 INTTM2
Selector
X/22 -fX/210 X/212 TI1/P33
Selector
8-bit timer register (TM1) Cleared
8-bit timer register (TM2) Cleared
Selector
-fX/210 X/212 TI2/P34
Selector
Output control circuit Internal
TO1/P31
µPD780204, 780205, 780206, 780208
Figure 5-4. Watch Timer Block Diagram
Selector
Selector
Selector
5-bit counter
INTWT
Pre-scaler
Selector
INTTM3
Figure 5-5. Watchdog Timer Block Diagram
Selector
Pre-selector
8-bit counter
Control circuit
Selector
INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request
µPD780204, 780205, 780206, 780208
CLOCK OUTPUT CONTROL CIRCUIT
Clocks following frequencies output clock 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 (with main system clock: MHz) 32.768 (with subsystem clock: 32.768 kHz)
Figure 5-6. Clock Output Control Circuit Block Diagram
Selector
Sync circuit
Output control circuit
PCL/P35
BUZZER OUTPUT CONTROL CIRCUIT
Clocks following frequencies output buzzer: kHz/2.4 kHz/4.9 (with main system clock: MHz)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
Selector
Output control circuit
BUZ/P36
µPD780204, 780205, 780206, 780208
CONVERTER 8-bit resolution 8-channel converter provided. This converter started following modes: Hardware start Software start
Figure 5-8. Converter Block Diagram
Series resistor string AVDD ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive approximation registor (SAR) AVSS
Selector
AVREF Sample hold circuit Voltage comparator
selector
INTP3/P03
Falling edge detector circuit
Control circuit
INTAD INTP3
conversion result register (ADCR)
Internal
SERIAL INTERFACE
channels clocked serial interfaces provided. Serial interface channel Serial interface channel
Table 5-3. Serial Interface Groups Functions
Function 3-line serial mode (serial interface) mode 2-line serial mode 3-line serial mode w/automatic transfer/reception function (MSB/LSB first selectable) Serial Interface Channel (MSB/LSB first selectable) (MSB first) (MSB first) Serial Interface Channel (MSB/LSB first selectable)
µPD780204, 780205, 780206, 780208
Figure 5-9. Serial Interface Channel Block Diagram
Internal
Selector
SI0/SB0/P25
Serial shift register (SIO0)
Output latch
SO0/SB1/P26
Selector
release/ command/acknowledge detector circuit Interrupt request signal generator circuit
Busy/acknowledge output circuit
INTCSI0
SCK0/P27
Serial clock counter
Serial clock control circuit
Selector
X/22 -fX/29
Figure 5-10. Serial Interface Channel Block Diagram
Internal
Automatic data transfer/ reception address pointer (ADTP)
Buffer
Automatic data transfer/reception interval specification register (ADTI)
Coincidence SI1/P20 Serial shift register (SIO1)
SO1/P21 5-bit counter STB/P23 Handshake control circuit
BUSY/P24
SCK1/P22
Serial clock counter
Interrupt request signal generator circuit
INTCSI1
Serial clock control circuit
Selector
X/22 X/29
µPD780204, 780205, 780206, 780208
CONTROLLER/DRIVER Automatic output segment signals (DMA operation) digit signals automatically reading display data Display mode register (DSPM0-DSPM2) that control segments digits output timing digit signal freely selecting display mode using display mode register (DSPM0). Port pins used display used output port port pins (however, FIP0-FIP12 display output pins). Display mode register (DSPM1) adjust luminance eight steps. Hardware suitable scan application using segment pins High-voltage output buffer (FIP driver) that directly drive Display output pins connected pull-down resistor mask option.
controller/driver having following features provided:
Figure 5-11. Selecting Display Modes
Selecting number digits
Selecting number segments
Caution
total number digits segments exceeds specified number digits takes precedence.
µPD780204, 780205, 780206, 780208
Figure 5-12. Controller/Driver Block Diagram
Internal
Write mask control circuit
Display data memory
Digit signal generation circuit
Display data selector
Display data latch
Port output latch
High-voltage buffer
FIP0
FIP13/P80
FIP52/P127
µPD780204, 780205, 780206, 780208
INTERRUPT FUNCTION TEST FUNCTION
INTERRUPT FUNCTION
following three types, sources interrupt functions available: Non-maskable Maskable Software Table 6-1. Interrupt Sources
Interrupt Type Nonmaskable Default PriorityNote Interrupt Source Name INTWDT Trigger Overflow watchdog timer (when watchdog timer mode selected) Internal INTWDT INTP0 INTP1 input edge detection INTP2 INTP3 INTCSI0 transfer serial interface channel transfer serial interface channel Reference time interval signal from watch timer Coincidence signal generation 16-bit timer/event counter Coincidence signal generation 8-bit timer/event counter Coincidence signal generation 8-bit timer/event counter conversion converter scan timing from controller/ driver Execution instruction External 000AH 000CH 000EH Overflow watchdog timer (when interval timer mode selected) 0006H 0008H 0004H Internal/ External Vector Table Address Basic Configuration TypeNote
INTCSI1
0010H
Maskable
INTTM3
0012H
INTTM0
Internal
0014H
INTTM1
0016H
Software
INTTM2 INTAD INTKS
0018H 001AH 001CH 003EH
Notes default priority assumed when more maskable interrupts generated same time, highest lowest. Basic configuration types (A)-(E) respectively correspond Figure 6-1.
µPD780204, 780205, 780206, 780208
Figure 6-1. Basic Configuration Interrupt Function (1/2)
Internal non-maskable interrupt
Internal
Interrupt request
Priority control circuit
Vector table address generator circuit Standby release signal
Internal maskable interrupt
Internal
Interrupt request
Priority control circuit
Vector table address generator circuit Standby release signal
External maskable interrupt (INTP0)
Internal
Sampling clock select register (SCS)
External interrupt mode register (INTM0)
Interrupt request
Sampling clock
Edge detector circuit
Priority control circuit
Vector table address generator circuit Standby release signal
µPD780204, 780205, 780206, 780208
Figure 6-1. Basic Configuration Interrupt Function (2/2)
External maskable interrupt (except INTP0)
Internal
External interrupt mode register (INTM0)
Interrupt request
Edge detector circuit
Priority control circuit
Vector table address generator circuit Standby release signal
Software interrupt
Internal
Interrupt request
Priority control circuit
Vector table address generator circuit
Interrupt request flag
Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
µPD780204, 780205, 780206, 780208
TEST FUNCTION
following trigger available test function.
Test Input Source Name INTWT Trigger Overflow watch timer Internal/ External Internal
Figure 6-2. Basic Configuration Test Function
Internal
Test input source (INTWT)
Standby release signal
Test request flag Test mask flag
µPD780204, 780205, 780206, 780208
STANDBY FUNCTION
standby function reduce current dissipation system effected following modes: HALT mode: this mode, operating clock stopped. using this mode combination with normal operation mode, system operated intermittently, that average current dissipation reduced. STOP mode: Oscillation main system clock stopped. operations main system clock stopped, therefore, current dissipation system minimized with only subsystem clock oscillating.
Figure 7-1. Standby Function
Main system clock operation STOP instruction Interrupt request STOP mode (Oscillation main system clock stopped)
CSS=1 CSS=0 HALT instruction
Subsystem clock operationNote HALT instruction
Interrupt request
Interrupt request HALT mode (Clock supply stopped. Oscillation continues) HALT modeNote (Clock supply stopped. Oscillation continues)
Note
stopping main system clock, current dissipation reduced. When operates subsystem clock, stop main system clock setting MCC. STOP instruction cannot used.
Caution
select main system clock again after main system clock been stopped once while subsystem clock use, make sure through program that oscillation stabilization time elapses, then that main system clock selected.
RESET FUNCTION
system reset following modes: External reset RESET Internal reset watchdog timer that detects hang
µPD780204, 780205, 780206, 780208
INSTRUCTION
8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand #byte First Operand ADDC SUBC ADDC SUBC ADDC SUBC DBNZ ADDC SUBC DBNZ ADDC SUBC ADDC SUBC ADDC SUBC rNote saddr !addr16 [DE] [HL]
byte]
$addr16
None
ADDC SUBC
RORC ROLC
saddr
!addr16
PUSH
[DE] [HL]
ROR4 ROL4
byte]
MULU DIVUW
Note Except
µPD780204, 780205, 780206, 780208
16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand #word First Operand ADDW SUBW CMPW MOVW
Note
rpNote
sfrp
saddrp !addr16
None
MOVW XCHW
MOVW
MOVW
MOVW
MOVW
MOVW
INCW DECW PUSH
sfrp saddrp !addr16
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
Note Only when rp=BC,
manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Second Operand A.bit First Operand A.bit MOV1 BTCLR BTCLR BTCLR BTCLR BTCLR SET1 CLR1 sfr.bit saddr.bit PSW.bit [HL].bit $addr16 None
sfr.bit
MOV1
SET1 CLR1
saddr.bit
MOV1
SET1 CLR1
PSW.bit
MOV1
SET1 CLR1
[HL].bit
MOV1
SET1 CLR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
SET1 CLR1 NOT1
µPD780204, 780205, 780206, 780208
Call/Branch instruction CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Second Operand First Operand Basic operation CALL CALLF CALLT BTCLR DBNZ !addr16 !addr11 [addr5] $addr16
Compound operation
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD780204, 780205, 780206, 780208
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol VLOAD Supply voltage AVDD AVREF AVSS Input voltage Output voltage P04, (except analog input pin), P27, P37, XT2, RESET N-ch open drain Conditions Rating -0.3 +7.0 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 Note +0.3 -0.3 +0.3 -0.3 Note +0.3 Unit
P100 P107, P110 P117, P120 P127 P-ch open drain P03, P17, P27, P87, P97, P100 P107, P110 P117, P120 P127, FIP0 FIP12 ANI0 ANI7 Analog input pins
Analog input voltage
AVSS -0.3 AVREF +0.3
P03, P17, P27, Total P03, P17, P27,
P87, P97, P100 P107, P110 P117,
High-level output current
P120 P127, FIP0 FIP12 Total P87, FIP0 FIP12 Peak value Total P97, P100 P107, Peak value P110 117, P120 P127 P03, P17, Peak value P27, P37, -240 -120
Note
-100
Note
Note
Note
Low-level output current
Total
Peak value
Total P03, to17, Total power dissipation Operating ambient temperature Storage temperature Tstg
Note
Peak value
Note
+150
Caution
Product quality suffer absolute maximum rating exceeded even single parameter, even momentarily. other words, absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded.
Remark Unless specified otherwise, dual-function characteristics same port characteristics. Notes With mask option, range internal pull-up resistor +0.3. should calculated follows: [RMS] [Peak value] Duty
µPD780204, 780205, 780206, 780208
Notes Total power dissipation differs depending temperature (see following figure).
Total power dissipation [mW]
Temperature [°C]
calculate total power dissipation following three power dissipation available µPD780204, 780205, 780206, 780208. three power dissipation should less than total power dissipation less ratings recommended). power dissipation: calculate (MAX.) IDD1 (MAX.). Output power dissipation: Normal output display output available. Power dissipation when maximum current flows into each output. Pull-down resistor power dissipation: Power dissipation pull-down resistor incorporated display output mask option. following calculate total power dissipation example next page. Example Assume following conditions: oscillator Supply current (IDD) 21.6 Display output: grids segments (Cut width 1/16) Maximum current grid Maximum current segment scan timing, display output OFF. Display output voltage: grid (voltage drop segments (voltage drop Fluorescent display control voltage (VLOAD) Mask option pull-down resistor
µPD780204, 780205, 780206, 780208
placing above conditions calculation <3>, total dissipation worked out. power dissipation: 21.6 118.8 Output power dissipation: (VDD VOD) Segment (VDD VOD) Total current value each grid Digit width width) number grids Grids 25.8 Grids Total segment current value illuminated dots number grids Dots Grids
Grid
Pull-down resistor power dissipation: (VOD VLOAD)2 Pull-down resistor value (5.5 (-35 V))2 number grids Digit width number grids Grids 50.9 Grids
Grid
Segment
number illuminated dots (VOD VLOAD)2 Pull-down resistor value number grids (5.5 (-35 V))2 dots 166.1 Grids
Total power dissipation 118.8 25.8 50.9 166.1 364.7 this example, total power dissipation exceed rating total power dissipation, there problem power dissipation. However, when total power dissipation exceeds rating total power dissipation, necessary lower power dissipation. reduce power dissipation, reduce number pull-down resistor.
Figure 10-1 Display Example segments-11 digits
Display Data Memory
FA7AH FA79H FA6AH FA69H FA78H FA77H FA76H FA68H FA67H FA66H FA75H FA74H FA73H FA65H FA64H FA63H FA72H FA71H FA70H FA62H FA61H FA60H
µPD780204, 780205, 780206, 780208
µPD780204, 780205, 780206, 780208
MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS
Resonator Recommended Circuit Parameter Oscillator frequency (fX)Note Conditions MIN. TYP. MAX. Unit
Ceramic resonator
Oscillator stabilization timeNote Oscillator frequency (fX)Note Oscillator stabilization timeNote
4.19
Crystal resonator
External clock
input frequency (fX)Note
PD74HCU04
input high-/low-level width (tXH/t
Notes Only oscillator characteristics shown. CHARACTERISTICS instruction execution times. This time required oscillation stabilize after reset, STOP mode release. Cautions When main system clock oscillator used, following should noted concerning wiring area figure enclosed broken line prevent influence wiring capacitance, etc. wiring should kept short possible. other signal lines should crossed. Keep away from lines carrying high fluctuating current. oscillator capacitor grounding point should always same potential VSS. connect ground pattern carrying high current. signal should taken from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
µPD780204, 780205, 780206, 780208
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS
Resonator Recommended Circuit
Parameter Oscillator frequency (fXT)Note
Conditions
MIN. TYP. MAX. Unit
32.768
Crystal resonator
Oscillator stabilization timeNote
External clock
input frequency (fXT)Note
input high-/low-level width (tXTH/tXTL)
Notes Only oscillator characteristics shown. CHARACTERISTICS instruction execution times. This time required oscillation stabilize after reaches MIN. range oscillation voltage. Cautions When subsystem clock oscillator used, following should noted concerning wiring area figure enclosed broken line prevent influence wiring capacitance, etc. wiring should kept short possible. other signal lines should crossed. Keep away from lines carrying high fluctuating current. oscillator capacitor grounding point should always same potential VSS. connect ground pattern carrying high current. signal should taken from oscillator.
subsystem clock oscillator low-amplitude circuit order achieve consumption current, more prone misoperation noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
µPD780204, 780205, 780206, 780208
RECOMMENDED OSCILLATOR CONSTANT µPD780204, 780205 Main System Clock: Ceramic Resonator
Frequency (MHz) Murata Mfg. Co., Ltd. Toyama CSB1000J CSA2.00MG040 CST2.00MG040 CSA4.00MG CST4.00MGW CSA5.00MG CST5.00MGW Corp. CCR1000K2 FCR4.00MC5 CCR4.00MC3 FCR5.00MC5 CCR5.00MC3 Matsushita Electronics Components Co., Ltd. EFOEC5004A4 EFOEN5004A4 EFOS5004B5 Circuit Constant (pF) (pF) Oscillator Voltage Range MIN. 3.00 2.80 2.80 2.70 2.70 2.90 2.90 2.70 2.70 2.70 2.80 2.70 2.70 2.70 2.70 MAX. 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor
Manufacturer
Product Name
Remark
Caution oscillation circuit constants oscillation voltage range indicate conditions stable oscillation. However, they guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency application circuit. this, necessary directly contact manufacturer resonator being used.
µPD780204, 780205, 780206, 780208
µPD780206, 780208 Main System Clock: Ceramic Resonator
Frequency (MHz) Murata Mfg. Co., Ltd. Toyama CSB1000J CSA2.00MG040 CST2.00MG040 CSA4.00MG CST4.00MGW CSA5.00MG CST5.00MGW Corp. CCR1000K2 CCR2.0MC33 CCR4.0MC3 FCR4.0MC5 CCR4.19MC3 FCR4.19MC5 CCR5.0MC3 FCR5.0MC5 Matsushita Electronics Components Co., Ltd. EFOEC2004A5 EFOEC4004A4 EFOEC4194A4 EFOEC5004A4 4.19 4.19 4.19 Circuit Constant (pF) (pF) Oscillator Voltage Range MIN. 2.80 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.70 2.85 2.70 2.70 MAX. 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 5.50 Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor
Manufacturer
Product Name
Remark
Caution oscillation circuit constants oscillation voltage range indicate conditions stable oscillation. However, they guarantee accuracy oscillation frequency. application circuit requires accuracy oscillation frequency, necessary oscillation frequency application circuit. this, necessary directly contact manufacturer resonator being used.
µPD780204, 780205, 780206, 780208
CAPACITANCE
Parameter Input capacitance Output capacitance Input/output capacitance Symbol COUT Conditions Unmeasured pins returned Unmeasured pins returned MIN. TYP. MAX. Unit
Unmeasured pins returned
P03, P17, P27, P100 P107, P110 P117, P120 P127
Remark Unless otherwise specified, characteristics shared same characteristics port pin. POWER SUPPLY VOLTAGE
Parameter CPUNote Display controller/driver mode 16-bit time/event counter (TM0) converter Other hardware Conditions MIN. 2.7Note TYP. MAX. Unit
Notes Except system clock oscillator, display controller/driver, PWM. Operating power supply voltage range differs depending cycle time. CHARACTERISTICS.
µPD780204, 780205, 780206, 780208
CHARACTERISTICS
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 VIH4 VIH5 P21, P03, P20, P22, P27, P33, P34, RESET XT1/P04, N-ch open-drain Conditions MIN. VIH6 P17, P32, VIH7 P100 P107, P110 P117, P120 P127 Low-level input voltage VIL1 VIL2 VIL3 P21, P03, P20, P22, P27, P33, P34, RESET 0.65 VIL4 VIL5 XT1/P04, VIL6 VIL7 High-level output voltage P17, P32, P100 P107, P110 P117, P120 P127 P03, P17, P27, P37, P87, P97, P100 P107, P110 P117, P120 P127, FIP0 FIP12 P37, P03, P17, VOL2 SB0, SB1, SCK0 -100 With open-drain pull-up TYP. MAX. Unit
Low-level output voltage
VOL1
VOL3
Remark Unless otherwise specified, characteristics shared same those port pin.
µPD780204, 780205, 780206, 780208
CHARACTERISTICS
Parameter High-level input leakage current Symbol ILIH1 Conditions P03, P17, P27, P37, P74, RESET XT1/P04, P100 P107, P110 P117, P120 P127 Low-level input leakage current ILIL1 ILIL2 ILIL3 ILIL4 High-level output leakage current Note ILOH1 VOUT P03, P17, P27, P37, RESET XT1/P04 P100 P107, P110 P117, P120 P127 P03, P17, P27, P37, P87, P97, P100 P107, P110 P117, P120 P127, FIP0 FIP12 P74, N-ch open-drain P03, P17, P27, P37, P87, P97, P100 107, P110 P117, P120 P127, FIP0 FIP12 MIN. TYP. MAX. Unit
ILIH2 ILIH3 ILIH4
3Note 3Note -3Note
ILOH2 Low-level output leakage current Note ILOL1
VOUT VOUT
ILOL2
VOUT VLOAD
Display output current Mask option pull-up resistor Software pull-up resistor
P03, P17, P27,
Notes P110 P117 P120 P127 without on-chip pull-down resistor (specifiable mask option), highlevel input leak current (MAX.) flows only during clocks after instruction been executed read ports (P11, P12) port mode registers (PM11, PM12). Outside period clocks following executing read-out instruction, current (MAX.). P110 P117 P120 P127 without on-chip pull-down resistor (specifiable mask option), highlevel input leak current (MAX.) flows only during clocks after instruction been executed read P11, P12, PM11, PM12. Outside period clocks following executing read-out instruction, current (MAX.). without on-chip pull-up resistor (specifiable mask option), low-level input leak current -200 (MAX.) flows only during clocks after instruction been executed read port (P7) port mode register (PM7). Outside period clocks following executing read-out instruction, current (MAX.). This current excludes current which flows on-chip pull-up/pull-down resistor. Remark Unless otherwise specified, characteritics shared same those port pin.
µPD780204, 780205, 780206, 780208
CHARACTERISTICS
Parameter Mask option pull-down resistor Symbol Conditions P87, P97, P100 P107, P110 P117, P120 P127 P37, crystal oscillation operating mode crystal oscillation HALT mode 32.768 crystal oscillation operating modeNote 32.768 crystal oscillation HALT modeNote STOP mode when connecting feedback resistor %Note %Note VLOAD MIN. TYP. 0.05 MAX. 21.6 1950 Unit
Power supply Note current IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
STOP mode when connecting feedback resistor
Notes This current excludes AVREF current, port current, current which flows on-chip pull-down resistor (mask option). When operating high-speed mode (when processor clock control register (PCC) 00H) When operating low-speed mode (when 04H) When main system clock stopped.
µPD780204, 780205, 780206, 780208
CHARACTERISTICS Basic Operation
Parameter Cycle time (minimum instruction execution time) TI1, input frequency TI1, input high, low-level width Interrupt input high, low-level width RESET low-level width
Symbol
Conditions Operated with main system clock Operated with subsystem clock
MIN. 40Note
TYP.
MAX.
Unit
fTIH fTIL fINTH fINTL tRSL
INTP0 INTP1 INTP3
8/fsamNote
Notes Value when external clock input used subsystem clock. When crystal used, value becomes
Selection fsam fx/2N+1, fx/64, fx/128 available bits (SCS0, SCS1) sampling
clock select register (SCS).
(with main system clock operated)
Operation guarantee range
Cycle time
Power supply voltage
µPD780204, 780205, 780206, 780208
Serial Interface Serial interface channel 3-wire serial mode (SCK0: Internal clock output)
Symbol tKCY1 Conditions MIN. 1600 SCK0 high, low-level width setup time SCK0) tKH1 tKL1 tSIK1 tKCY1/2 tKCY1/2 hold time (from SCK0) SCK0 output delay time tKSI1 tKSO1 pFNote TYP. MAX. Unit
Parameter SCK0 cycle time
Note load capacitance SCK0 output line. (ii) 3-wire serial mode (SCK0: External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Conditions MIN. 1600 SCK0 high, low-level width setup time SCK0) tKH2 tKL2 tSIK2 tKCY2/2 tKCY2/2 hold time (from SCK0) SCK0 output delay time SCK0 rise, fall time tKSI2 tKSO2 pFNote TYP. MAX. Unit
Note load capacitance output line.
µPD780204, 780205, 780206, 780208
(iii) mode (SCK0: Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Conditions MIN. 3200 SCK0 high, low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SCK0 SB0, output delay time SCK0SB0, SB0, SB1SCK0 SB0, high-level width SB0, low-level width tSBL tKCY3 tKH3 tKL3 tSIK3 tKCY3/2 tKCY3/2 tKSI3 pFNote tKCY3/2 TYP. MAX. Unit
tKSO3
1000
tKSB tSBK tSBH
tKCY3 tKCY3 tKCY3
Note load resistance load capacitance SCK0, SB0, output line. (iv) mode (SCK0: External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Conditions MIN. 3200 SCK0 high, low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SCK0 SB0, output delay time SCK0SB0, SB0, SB1SCK0 SB0, high-level width SB0, low-level width SCK0 rise, fall time tKSO4 pFNote tKSB tSBK tSBH tKCY4 tKCY4 tKCY4 1000 tKSI4 tKH4 tKL4 tSIK4 1600 tKCY4/2 TYP. MAX. Unit
tSBL
tKCY4
Note load resistance load capacitance output line.
µPD780204, 780205, 780206, 780208
2-wire serial mode (SCK0: Internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY5 tKH5 tKL5 Conditions pFNote MIN. 1600 tKCY5/2 tKCY5/2 tKCY5/2 SB0, setup time SCK0) SB0, hold time (from SCK0) SCK0SB0, output delay time tKSI5 tSIK5 TYP. MAX. Unit
tKSO5
Note load resistance load capacitance SCK0, SB0, output line. (vi) 2-wire serial mode (SCK0: External clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SCK0SB0, output delay time SCK0 rise, fall time tKSO6 pFNote tKSI6 tKCY6/2 Symbol tKCY6 tKH6 tKL6 tSIK6 Conditions MIN. 1600 TYP. MAX. Unit
Note load resistance load capacitance output line.
µPD780204, 780205, 780206, 780208
Serial interface channel 3-wire serial mode (SCK1: Internal clock output)
Symbol tKCY7 Conditions MIN. 1600 SCK1 high, low-level width setup time SCK1) tKH7 tKL7 tSIK7 tKCY7/2 tKCY7/2 hold time (from SCK1) SCK1 output delay time tKSI7 tKSO7 pFNote TYP. MAX. Unit
Parameter SCK1 cycle time
Note load capacitance SCK1 output line. (ii) 3-wire serial mode (SCK1: External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Conditions MIN. 1600 SCK1 high, low-level width setup time SCK1) tKH8 tKL8 tSIK8 tKCY8/2-50 tKCY8/2-100 hold time (from SCK1) SCK1 output delay time SCK1 rise, fall time tKSI8 tKSO8 pFNote TYP. MAX. Unit
Note load capacitance output line.
µPD780204, 780205, 780206, 780208
(iii) 3-wire serial mode with automatic transmit/receive function (SCK1: Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Conditions MIN. 1600 SCK1 high, low-level width setup time SCK1) tKH9 tKL9 tSIK9 tKCY9/2 tKCY9/2 hold time (from SCK1) SCK1 output delay time SCK1 Strobe signal high-level width Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing Busy inactibe SCK1 tSPS tKSI9 tKSO9 pFNote TYP. MAX. Unit
tSBD tSBW
tKCY9/2 tKCY9
tKCY9/2 tKCY9
tBYS
tBYH
2tKCY9
Note load capacitance SCK1 output line. (iv) 3-wire serial mode with automatic transmit/receive function (SCK1: External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Conditions MIN. 1600 SCK1 high, low-level width setup time SCK1) hold time (from SCK1) SCK1 output delay time SCK1 rise, fall time tKH10 tKL10 tSIK10 tKSI10 tKSO10 pFNote TYP. MAX. Unit
tR10 tF10
Note load capacitance output line.
µPD780204, 780205, 780206, 780208
TIMING TEST POINT (EXCLUDING INPUT)
Test Points
CLOCK TIMING
1/fX
Input
VIH4 (MIN.) VIL4 (MAX.)
1/fXT tXTL tXTH
Input
VIH5 (MIN.) VIL5 (MAX.)
TIMING
1/fTI tTIL tTIH
µPD780204, 780205, 780206, 780208
SERIAL TRANSFER TIMING 3-wire serial mode:
MHz,
tKCY1.2,
tKL1.2, tR2, SCK0, SCK1
tKH1.2, tF2,
tSIK1.2, tKSI1.2,
SI0, tKSO1.2,
Input Data
SO0,
Output Data
mode (bus release signal transfer):
tKCY3.4 tKL3.4 SCK0 tKSB tSBL tSBH tSBK tSIK3.4 tKSI3.4 tKH3.4
SB0, tKSO3.4
mode (command signal transfer):
tKCY3.4 tKL3.4 tKH3.4
SCK0 tKSB tSBK tSIK3.4 tKSI3.4
SB0, tKSO3.4
µPD780204, 780205, 780206, 780208
2-wire serial mode:
tKCY5, tKL5, SCK0 tSIK5, tKH5,
tKSO5,
tKSI5,
SB0,
3-wire serial mode with automatic transmit/receive function:
tSIK9, tKSO9,
tKSI9, tKH9,
tF10 SCK1 tR10 tKL9, tKCY9, tSBD tSBW
3-wire serial mode with automatic transmit/receive function (Busy processing):
SCK1
Note
Note
10+n tBYH
Note
tSPS
tBYS BUSY (Active high)
Note
Though does become level actually, here described does timing rule.
µPD780204, 780205, 780206, 780208
CONVERTER CHARACTERISTICS AVDD AVSS
Parameter Resolution Total error
Note Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Conversion time Sampling time
tCONV tSAMP VIAN AVREF RAVREF
19.1 12/fX AVSS
Note
Analog input voltage Reference voltage AVREF resistor
AVREF AVDD
Notes Quantization error (±1/2LSB) included. This parameter indicated ratio full-scale value. conversion time 19.1 more. Sampling time depends conversion time. DATA MEMORY STOP MODE SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR Subsystem clock stopped, Feedback resistor connected Release signal time Oscillation stabilization wait time tSREL tWAIT Release RESET Release interrupt 217/fX Note Conditions MIN. TYP. MAX. Unit
Note
Selection 212/fX, 214/fX 217/fX available bits (OSTS0 OSTS2) oscillation stabilization time select register (OSTS).
Data retention timing (STOP mode release RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
STOP instruction execution
VDDDR
tSREL
RESET
tWAIT
µPD780204, 780205, 780206, 780208
Data retention timing (standby release signal: STOP mode release interrupt signal)
HALT mode STOP mode Data retention mode Operating mode
STOP instruction execution
VDDDR
tSREL
Standby release signal (interrupt request) tWAIT
Interrupt input timing
tINTL tINTH
INTP0 INTP2
tINTL
INTP3
RESET input timing
tRSL
RESET
µPD780204, 780205, 780206, 780208
CHARACTERISTIC CURVE (REFERENCE VALUE)
µPD780204, 780205
(Main system clock: MHz) 10.0
30H, HALT oscillates, oscillates)
32.768
Supply current [mA]
0.05
HALT stops, oscillates) STOP stops, oscillates)
0.01
0.005
0.001 Supply voltage
µPD780204, 780205, 780206, 780208
(VDD
Supply current [mA]
Clock oscillation frequency [MHz]
µPD780204, 780205, 780206, 780208
(Port
Low-level output current [mA]
Low-level output voltage
(Ports
Low-level output current [mA]
Low-level output voltage
µPD780204, 780205, 780206, 780208
(Port
Low-level output current [mA]
Low-level output voltage
µPD780204, 780205, 780206, 780208
(Port Port High-level output current [mA]
High-level output voltage
(Port Port High-level output current [mA]
High-level output voltage
µPD780204, 780205, 780206, 780208
µPD780206, 780208
(Main system clock: MHz) 10.0
30H, HALT oscillates, oscillates)
32.768
Supply current [mA]
0.05
0.01
0.005
0.001 Supply voltage
µPD780204, 780205, 780206, 780208
(VDD
Supply current [mA]
Clock oscillation frequency [MHz]
µPD780204, 780205, 780206, 780208
(Port
Low-level output current [mA]
Low-level output voltage
(Ports
Low-level output current [mA]
Low-level output voltage
µPD780204, 780205, 780206, 780208
(Port
Low-level output current [mA]
Low-level output voltage
µPD780204, 780205, 780206, 780208
(Port Port High-level output current [mA]
High-level output voltage
(Port Port
High-level output current [mA]
High-level output voltage
µPD780204, 780205, 780206, 780208
PACKAGE DRAWING
PLASTIC
detail lead
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition. ITEM
P100GF-65-3BA1-2 MILLIMETERS 23.6 20.0 14.0 17.6 0.30 0.10 0.15 0.65 (T.P.) 0.15+0.10 -0.05 0.10 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
Remark dimensions materials model same mass-produced model.
5°±5°
µPD780204, 780205, 780206, 780208
RECOMMENDED SOLDERING CONDITIONS
conditions listed below shall when soldering µPD780204, 780205, 780206, 780208. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with sales offices case other soldering process used, case soldering done under different conditions. Table 13-1. Soldering Conditions Surface-Mount Type
100-pin plastic 100-pin plastic 100-pin plastic 100-pin plastic
Recommended Condition Symbol IR35-00-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: Duration: sec. max. above), Number times: Thrice max. Package peak temperature: Duration: sec. max. above), Number times: Thrice max. Solder bath temperature: max. Duration: sec. max. Number times: Once Preliminary heat temperature: max. (Package surface temperature) temperature: max., Duration: sec. max. (per device side)
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
Caution Using more than soldering method should avoided (except case partial heating).
µPD780204, 780205, 780206, 780208
APPENDIX DEVELOPMENT TOOLS
following tools available development systems using µPD780204, 780205, 780206, 780208: Language Processing Software RA78K/0Note CC78K/0
Note
Assembler package common 78K/0 series compiler package common 78K/0 series Device file µPD780208 subseries compiler library source file common 78K/0 series
DF780208Note CC78K/0-L
Note
PROM Writing Tools PG-1500 PA-78P0208GF PA-78P0208KL-T PG-1500 ControllerNote Debugging Tools IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780208-R-EM EP-78064GF-R EV-9200GF-100 SM78K0 ID78K0
Note
PROM programmer Programmer adapter connectd PG-1500
Control program PG-1500
In-circuit emulator common 78K/0 series In-circuit emulator common 78K/0 series (for integrated debugger) Break board common 78K/0 series Emulation board evaluating µPD780208 subseries Emulation probe common µPD78064 subseries Socket mounted target system created 100-pin plastic (GF-3BA type) System simulator common 78K/0 series Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device file µPD780208 subseries
Note Note Note
SD78K/0
DF780208
Real-time RX78K/0 MX78K0
Note
Real-time 78K/0 series 78K/0 series
Note
Notes PC-9800 series (MS-DOS based PC/AT
compatible DOSTM/IBM DOSTM/MS-DOS) based
HP9000 series HP9000 series based
(HP-UX based (HP-UX) based, SPARCstation
(Sun based, EWS4800 series (EWS-UX/V)
PC-9800 series (MS-DOS Windows based PC/AT compatible DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OSTM) based Remarks Please refer 78K/0 Series Selection Guide (U11126E) information third party development tools. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 used combination with DF780208.
µPD780204, 780205, 780206, 780208
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note FT9080Note 1/FT9085Note FI78K0Note FD78K0Note Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes PC-9800 series (MS-DOS) based PC/AT compatible DOS/IBM DOS/MS-DOS) based PC/AT compatible DOS/IBM DOS/MS-DOS Windows) based Remark Please refer 78K/0 Series Selection Guide (U11126E) information third party development tools.
µPD780204, 780205, 780206, 780208
APPENDIX RELATED DOCUMENTS
Documents Related Devices
Document Document Name Japanese English U11302E This document U11295E IEU-1372 U10121E
µPD780208 subseries user's manual µPD780204, 780205, 780206, 780208 data sheet µPD78P0208 data sheet µPD780208 subseries special function register list
78K/0 series user's manual instruction 78K/0 series instruction list 78K/0 series instruction 78K/0 series application note Basic (II)
U11302J U10436J U11295J U10997J IEU-849 U10903J U10904J U10121J
Caution
documents listed above subject change without notice. sure latest documents designing your system.
µPD780204, 780205, 780206, 780208
Development Tool Documents (User's Manual)
Document Document Name Japanese Operation RA78K series assembler package Language RA78K0 assembler package Operation Assembly language Structured assembly language RA78K series structured assembler preprocessor Operation CC78K series compiler Language CC78K0 compiler Operation Language CC78K series library source file CC78K/0 compiler application note PG-1500 PROM programmer PG-1500 controller PC-9800 series (MS-DOS) base PG-1500 controller series DOS) base IE-78000-R IE-78000-R-A IE-78000-R-BK IE-780208-R-EM EP-78064 SM78K0 system simulator SM78K series system simulator Reference External parts user-open interface specification Introduction Reference SD78K/0 screen debugger PC/AT DOS) base Introduction Reference ID78K0 integrated debugger based ID78K0 integrated debugger based ID78K0 integrated debugger Windows based Reference Reference Guide Programming know-how EEU-655 U11517J U11518J EEU-777 EEA-618 EEU-651 EEU-704 EEU-5008 EEU-810 U10057J EEU-867 EEU-977 EEU-934 U10181J U10092J EEU-1284 U11517E U11518E EEA-1208 EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 EEU-1501 EEU-1469 U10181E U10092E EEU-815 U11802J U11801J U11789J EEU-1404 U11802E U11801E U11789E EEU-809 English EEU-1399
EEU-817 EEU-656
EEU-1402 EEU-1280
SD78K/0 screen debugger PC-9800 series (MS-DOS) base
EEU-852 U10952J EEU-5024 U11279J U11151J U11539J U11649J
U10539E EEU-1414 U11279E U11539E U11649E
Caution
documents listed above subject change without notice. documents designing your system.
sure latest
µPD780204, 780205, 780206, 780208
Documents Related Embedded Software (User's Manual)
Document Document Name Japanese Fundamental 78K/0 series real-time Installation Technical 78K/0 series MX78K0 Fuzzy knowledge data creation tool 78K/0, 78K/II, 87AD series fuzzy inference development suppport system translator 78K/0 series fuzzy inference development support system fuzzy inference module 78K/0 series fuzzy inference development support system fuzzy inference debugger Fundamental U11537J U11536J U11538J EEU-5010 EEU-829 EEU-862 English EEU-1438 EEU-1444
EEU-858
EEU-1441
EEU-921
EEU-1458
Other Related Documents
Document Document Name Japanese package manual Semiconductor device mounting technology manual Quality grade semiconductor devices semiconductor device reliability/quality control system Static electricity discharge (ESD) test Semiconductor device quality guarantee guide Product guide related microcomputer other manufacturers C10535J C11531J C10983J MEM-539 C11893J U11416J C10943X C10535E C11531E C10983E MEI-1202 English
Caution
documents listed above subject change without notice. sure latest documents designing your system.
µPD780204, 780205, 780206, 780208
[MEMO]
µPD780204, 780205, 780206, 780208
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD780204, 780205, 780206, 780208
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby Sweden Tel: 8-63 Fax: 8-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD780204, 780205,780206, 780208
documents referred this publication include preliminary versions. However, preliminary versions marked such. IEBus trademarks Corporation. MS-DOS Windows trademarks Microsoft Corporation. DOS, PC/AT, trademarks Corporation. HP9000 series 300, HP9000 series 700, HP-UX trademarks Hewlett-Packard. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems Inc. NEWS NEWS-OS trademarks Sony Corporation.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD780204, 780205, 780206, 780208 8-BIT SINGLE-CHIP MICROCONTROLL

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