µPD30550 VR5500 64-/32-BIT MICROPROCESSOR DESCRIPTION
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INTEGRATED CIRCUIT
µPD30550
VR5500
64-/32-BIT MICROPROCESSOR
DESCRIPTION
µPD30550 (VR5500) member Seriesof RISC (Reduced Instruction Computer) microprocessors. high-performance 64-/32-bit microprocessor that employs RISC architecture developed MIPSTM. VR5500 allows selection 64-bit 32-bit width system interface, operate using protocols compatible with VR5000 Series VR5432 Detailed function descriptions provided following user's manual. sure read manual before designing. VR5500 User's Manual (U16044E)
FEATURES
MIPS 64-bit RISC architecture High-speed operation processing Two-way superscalar super pipeline product: product: entries) Address space Physical: Virtual: bits (64-bit selected) bits (32-bit selected) bits 64-bit mode) bits 32-bit mode) On-chip floating-point unit (FPU) Supports sum-of-products instructions On-chip primary cache memory (instruction/data: each) 2-way associative Supports line lock feature MIPS MIPS 64-/32-bit address/data multiplexed width selectable during reset protocol compatibility with existing products retained Maximum operating frequency product: Internal MHz, external product: Internal MHz, external External/internal multiplication factor selectable from increments Conforms MIPS III, instruction sets. Also supports product-sum operation instruction, rotate instruction, register scan instruction, instruction power mode. Supports hardware debug function (N-Wire) Supply voltage Core block: block: (300 product) (400 product) ±5%,
High-speed translation lookaside buffer (TLB)
information contained this document being issued advance production cycle device. parameters device change before final production Corporation, discretion, withdraw device prior production. devices/types available every country. Please check with local representative availability additional information.
Document U15700EJ1V1DS00 (1st edition) Date Published October 2002 CP(K) Printed Japan
mark
shows major revised points.
2002
2001
µPD30550
APPLICATIONS
Set-top boxes RAID High-end embedded devices, etc.
ORDERING INFORMATION
Part Number Package 272-pin plastic (C/D advanced type) 272-pin plastic (C/D advanced type) Maximum Operating Frequency (MHz)
µPD30550F2-300-NN1 µPD30550F2-400-NN1
CONFIGURATION
272-pin plastic (C/D advanced type)
µPD30550F2-300-NN1 µPD30550F2-400-NN1
Bottom View
View
Index mark
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
(1/2)
VDDIO VDDIO Reset# PReq# ValidIn# ValidOut# SysADC7 SysADC3 SysADC1 SysADC4 SysAD62 SysAD30 SysAD28 SysAD59 VDDIO VDDIO VDDIO VDDIO ColdReset# Release# ExtRqst# BusMode SysID2 SysADC6 SysADC0 SysAD61 Name Name SysAD27 VDDIO VDDIO VDDIO VDDIO WrRdy# SysID1 SysADC2 SysAD63 SysAD29 SysAD58 VDDIO VDDIO VDDIO VDDIO VDDIO RdRdy# SysID0 SysADC5 SysAD31 SysAD60 SysAD26 VDDIO VDDIO SysCmd0 DisDValidO# DWBTrans# O3Return# SysAD57 SysAD25 SysAD56 SysAD24 SysCmd1 SysAD55 SysCmd2 SysCmd3 SysCmd4 SysCmd5 SysAD23 SysAD54 SysAD22 SysAD53 SysCmd6 Name SysAD21 SysCmd7 SysCmd8 TIntSel Int0# SysAD52 SysAD20 SysAD51 SysAD19 Int1# Int2# Int3# Int4# Int5# SysAD17 SysAD49 SysAD18 SysAD50 RMode#/BKTGIO# Name
Caution Leave open. Remark indicates active low.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
(2/2)
Name VDDIO NMI# VDDIO BigEndian SysAD15 SysAD47 SysAD16 SysAD48 SysAD46 DivMode0 DivMode1 DivMode2 VDDIO SysAD44 SysAD13 SysAD45 SysAD14 Name SysAD12 NTrcClk NTrcData0 NTrcData1 NTrcData3 SysAD10 SysAD42 SysAD11 SysAD43 NTrcData2 NTrcEnd VSSPA2 VDDIO JTMS SysAD33 SysAD4 SysAD7 SysAD41 VDDIO VDDIO VDDIO Name VDDIO VDDPA2 VDDIO JTDI SysAD1 SysAD35 SysAD38 SysAD9 VDDIO VDDIO VDDIO VDDIO VSSPA1 SysClock JTRST# (VSS) JTCK SysAD32 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 SysAD3 SysAD37 SysAD39 SysAD40 VDDIO VDDIO VDDIO VDDIO VDDPA1 VDDIO JTDO DrvCon SysAD0 SysAD2 SysAD34 SysAD36 SysAD5 SysAD6 SysAD8 VDDIO VDDIO Name
Caution Leave open. Remarks name parentheses indicates name revision product. indicates active low.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
NAMES
BigEndian: BKTGIO#: BusMode: ColdReset#: DisDValidO#: DivMode(2:0): DrvCon: DWBTrans#: ExtRqst#: Int(5:0)#: JTCK: JTDI: JTDO: JTMS: JTRST#: NMI#: NTrcClk: NTrcData(3:0) NTrcEnd: O3Return#: Remark endian Break/trigger input/output mode Cold reset Disable delay ValidOut# Divide mode Driver control Doubleword block transfer External request Internally connected Interrupt JTAG clock JTAG data input JTAG data output JTAG mode select JTAG reset Non-maskable interrupt N-Trace clock N-Trace data output N-Trace Out-of-Order Return mode SysID(2:0): TIntSel: ValidIn#: ValidOut#: VDD: VDDIO: VDDPA1, VDDPA2: VSS: VSSPA1, VSSPA2: WrRdy#: SysClock: SysCmd(8:0): PReq#: RdRdy#: Release#: Reset#: SysAD(63:0): SysADC(7:0): Processor request Read ready Release Reset System address/data System address/data check System clock System command/data identifier System identifier Timer interrupt selection Valid input Valid output Power supply core Power supply Quiet Ground Quiet Write ready
indicates active low.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
INTERNAL BLOCK DIAGRAM
VR5500 Instruction cache
Control signal SysAD (64/32 bits)
RNRF
Test interface ALU0 FPU/ MACU SysClock Clock generator Data cache ALU1
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
CONTENTS
FUNCTIONS.8
List Functions Recommended Connection Unused Pins
ELECTRICAL SPECIFICATIONS.14 PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
FUNCTIONS
Remark indicates active low. List Functions System interface signals
Name SysAD(63:0) System address/data 64-bit communication between processor external agent. lower bits (SysAD(31:0)) used 32-bit mode. SysADC(7:0) System address/data check SysAD parity. Valid only during data cycle. lower bits (SysADC(3:0)) used 32-bit mode. SysCmd(8:0) System command/data 9-bit that transfers command data identifiers between processor external agent SysID(2:0) System protocol These signals transfer request identifiers out-of-order return mode. processor drives valid identifier synchronization with activation ValidOut# signal. external agent must drive valid identifiers synchronization with activation ValidIn# signal. ValidIn# Input Valid signal indicating that external agent driving valid address data onto SysAD bus, valid command data identifier onto SysCmd bus, valid request identifier onto SysID out-of-order return mode. ValidOut# Output Valid signal indicating that processor driving valid address data onto SysAD bus, valid command data identifier onto SysCmd bus, valid request identifier onto SysID out-of-order return mode. RdRdy# Input Read ready signal indicating that external agent ready accept processor read request WrRdy# Input Write ready signal indicating that external agent ready accept processor write request ExtRqst# Input External request signal indicating that external agent requesting right system interface Release# Output Releases interface signal indicating that processor releasing system interface slave state PReq# Output Processor request signal indicating that processor request that pending Function
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Initialization interface signals
Name DivMode(2:0) Input Division mode These signals division ratio PClock SysClock follows: 111: 110: 101: 100: 011: 010: 001: 000: input levels these signals before power-on reset. Make sure that levels these signals change while VR5500 operating. BigEndian Input Endian mode This signal sets byte ordering addressing. endian Little endian input level this signal before power-on reset. Make sure that level this signal does change while VR5500 operating. BusMode Input mode This signal sets width system interface. bits bits input level this signal before power-on reset. Make sure that level this signal does change while VR5500 operating. TIntSel Input Interrupt source select This signal sets interrupt source assigned Cause register. Timer interrupt Int5# input external write request (SysAD5) input level this signal before power-on reset. Make sure that level this signal does change while VR5500 operating. DisDValidO# Input ValidOut# delay enable ValidOut# active even while address cycle stalled ValidOut# active during address issuance cycle only input level this signal before power-on reset. Make sure that level this signal does change while VR5500 operating. DWBTrans# Input Doubleword block transfer enable (valid 32-bit mode only) Disabled Enabled input level this signal before power-on reset. Make sure that level this signal does change while VR5500 operating. Function
(1/2)
Remark
High level, level
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
(2/2)
Name O3Return# Input Out-of-Order Return mode This signal sets protocol system interface. Normal mode Out-of-order return mode input level this signal before power-on reset. Make sure that level this signal does change while VR5500 operating. ColdReset# Input Cold reset This signal completely initializes internal status processor. Deassert synchronization with SysClock. Reset# Input Reset This signal logically initializes internal status processor. Deassert synchronization with SysClock. DrvCon Input Drive control This signal sets impedance external output driver. Normal (recommended) input level this signal before power-on reset. Make sure that level this signal does change while VR5500 operating. Remark Applies revision later products. Fixed revision products. Function
Remark High level, level O3Return#, DWBTrans#, DisDValidO#, BusMode signals used determining protocol system interface. protocol selected follows accordance with setting these signals.
Protocol VR5000 compatible RM523x compatible VR5432 native mode compatible Out-of-order return mode
O3Return#
DWBTrans# Arbitrary
DisDValidO# Arbitrary
BusMode Arbitrary
Remark High level, 0:Low level RM523x product PMC-Sierra, Inc. Interrupt interface signals
Name Int(5:0)# Input Interrupt These general-purpose processor interrupt requests. input states checked Cause register. Whether Int5# acknowledged depends status TIntSel signal during reset. NMI# Input Non-maskable interrupt This non-maskable interrupt request. Function
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Clock interface signals
Name SysClock Input System clock Clock input processor VDDPA1 VDDPA2 VSSPA1 VSSPA2 Power supply internal Ground internal Function
Power supply
Name VDDIO Power supply core Power supply Ground potential Function
Caution VR5500 uses power supply pins. These power supply pins applied sequence. However, power must applied longer while applied other.
Test interface signals
Name NTrcData(3:0) Output Trace data Trace data output NTrcEnd Output Trace signal that indicates trace data packet. NTrcClk Output Trace clock Clock test interface. same clock SysClock output. RMode#/ BKTGIO# Reset mode/break trigger debug reset mode input signal while JTRST# signal (ColdReset# signal revision products) active. serves break trigger signal during normal operation. JTDI Input JTAG data input Serial data input JTAG JTDO Output JTAG data output Serial data output JTAG. Output performed synchronization with fall JTCK. JTMS Input JTAG mode select This signal selects JTAG test mode. JTCK Input JTAG clock input Serial clock input JTAG. maximum frequency MHz. There need synchronized with SysClock. JTRST# Input JTAG reset input signal initializing JTAG test module. Remark Revision later products only. Function
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Recommended Connection Unused Pins System interface pins 32-bit mode VR5500 allows selection SysAD width from bits bits. When 32-bit mode selected, VR5500 operates using only required system interface pins. Therefore, unused pins follows when operating VR5500 32-bit mode.
Name Recommended Connection Unused Pins SysAD(63:32) SysADC(7:4) Leave open Leave open
Normal mode VR5500 process read/write transactions regardless order which requests issued out-of-order return mode. SysID(2:0) signals used identify each request during this processing. these signals, which used normal mode, follows.
Name Recommended Connection Unused Pins SysID(2:0) Leave open
Parity VR5500 allows selection whether data protected using parity. When parity used, parity data output from processor external agent SysADC bus. However, whether parity used selected software, unless program started, VR5500 cannot determine operation SysADC bus. Therefore, care must taken prevent SysADC from being left open high-impedance state. When parity used, recommended connect each SysADC VDDIO resistor with high resistance value.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Test interface pins VR5500 used perform testing debugging with device mounted board. test interface pins used connection with external debug tool during such debugging. Therefore test interface pins follows when debug function used normal operation mode.
Name Recommended Connection Unused Pins JTCK JTDI JTMS JTRST# JTDO NTrcClk NTrcData(3:0) NTrcEnd RMode#/BKTGIO#
Note
Pull Pull Pull Pull down Leave open Leave open Leave open Leave open Pull
Note Revision later products only.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol VDDIO VDDP Input voltage
Note
Conditions
Ratings -0.5 +4.0 -0.5 +2.0 -0.5 +2.0 -0.5 VDDIO -1.5 VDDIO +125
Unit
Pulse less than
Operating case temperature Storage temperature
Tstg
Note upper limit input voltage (VDDIO 0.3) +4.0 Cautions short-circuit more outputs same time. Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. specifications conditions shown following Characteristics Characteristics sections ranges within which product normally operate quality guaranteed. Operating conditions product
Parameter Supply voltage Symbol VDDIO Conditions MIN. 2.375 3.135 VDDP 1.425 1.425 MAX. 2.625 3.465 1.575 1.575 Unit
Caution also used with voltage range product (1.6 this case, internal operation guaranteed. supply current core block this case specified value product (MAX. product
Parameter Supply voltage Symbol VDDIO Conditions MIN. 2.375 3.135 VDDP MAX. 2.625 3.465 Unit
Caution also used with voltage range product (1.425 1.575 this case, internal operation guaranteed. supply current core block this case specified value product (MAX.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Supply Current
Parameter Supply current core block Symbol operation, VDDP 1.575 product, during normal operation, VDDP IDD_sb product, standby mode, VDDP 1.575 product, standby mode, VDDP 0.45 0.35 Conditions product, during normal MIN. MAX. Unit
Remark
supply current block varies depending application used. normally lower.
Characteristics
When VDDIO (300 product: +85°C, VDDIO ±5%, VDDP ±5%) (400 product: +85°C, VDDIO ±5%, VDDP
Parameter Output voltage, high Output voltage, Input voltage, high Input voltage,
Note
Symbol
Conditions VDDIO MIN., VDDIO MIN.,
MIN. VDDIO
MAX.
Unit
-0.5 VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO -5.0 -5.0
Note
Pulse less than Input voltage, high Input voltage,
Note
-1.5 VDDIO -0.5
VIHC VILC Pulse less than
Note
-1.5
Input current leakage, high Input current leakage, Output current leakage, high Output current leakage,
ILIH ILIL ILOH ILOL
VDDIO VDDIO
Notes Does apply SysClock pin. Only applies SysClock pin.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
When VDDIO (300 product: +85°C, VDDIO ±5%, VDDP ±5%) (400 product: +85°C, VDDIO ±5%, VDDP
Parameter Output voltage, high Output voltage, Input voltage, high Input voltage,
Note
Symbol
Conditions VDDIO MIN., VDDIO MIN.,
MIN.
MAX.
Unit
-0.5 VDDIO VDDIO VDDIO VDDIO -5.0 -5.0
Note
Pulse less than Input voltage, high Input voltage,
Note
-1.5 VDDIO -0.5
VIHC VILC Pulse less than
Note
-1.5
Input current leakage, high Input current leakage, Output current leakage, high Output current leakage,
ILIH ILIL ILOH ILOL
VDDIO VDDIO
Notes Does apply SysClock pin. Only applies SysClock pin.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Power-on Sequence
VR5500 uses power supply pins. These power supply pins applied sequence. However, power must applied longer while applied other.
Parameter Power-on delay Symbol Conditions MIN. MAX. Unit
Capacitance 25°C, VDDIO VDDP
Parameter Input capacitance Output capacitance Symbol COUT Unmeasured pins returned Conditions MIN. MAX. Unit
Characteristics
(300 product: +85, VDDIO ±5%, ±5%, VDDP ±5%) (400 product: +85, VDDIO ±5%, ±5%, VDDP Clock parameters (1/2)
Parameter System clock high-level width System clock low-level width Pipeline clock frequency Symbol product product System clock frequency
Note
Conditions
MIN. 66.7 57.2 44.5 36.4 66.7 57.2 44.5 36.4
MAX.
Unit
85.7 66.6 54.5 88.8 72.7
product
DivMode DivMode 2.5:1 DivMode DivMode 3.5:1 DivMode DivMode 4.5:1 DivMode DivMode 5.5:1
product
DivMode DivMode 2.5:1 DivMode DivMode 3.5:1 DivMode DivMode 4.5:1 DivMode DivMode 5.5:1
Note This frequency which operation internal guaranteed.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Clock parameters (2/2)
Parameter System clock cycle Symbol product Conditions DivMode DivMode 2.5:1 DivMode DivMode 3.5:1 DivMode DivMode 4.5:1 DivMode DivMode 5.5:1 product DivMode DivMode 2.5:1 DivMode DivMode 3.5:1 DivMode DivMode 4.5:1 DivMode DivMode 5.5:1 System clock jitter System clock rise time System clock fall time JTAG clock frequency MIN. 11.7 13.3 16.7 18.3 11.3 12.5 13.8 MAX. 12.5 17.5 22.5 27.5 12.5 17.5 22.5 27.5 Unit
Remarks system clock jitter cycle-to-cycle jitter. JTAG clock runs asynchronously system clock. System interface parameters
Parameter Data output hold time
Note
Symbol
Conditions
MIN.
MAX.
Unit
Data output delay time Data input setup time
Note
product product
Note
Data input hold timeNote
Notes Applies Release#, ValidOut#, SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) pins. Applies ColdReset#, Reset#, Int(5:0), NMI#, ExtRqst#, RdRdy#, ValidIn#, SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) pins. Load coefficient
Parameter Load coefficient Symbol Conditions MIN. MAX. Unit ns/25
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Measurement Conditions Measurement points
SysClock
output pins
Load conditions
output pins
Timing Charts Clock timing
SysClock
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Clock jitter
SysClock
System interface edge timing
SysClock SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0) Output Output Input
ValidOut#, Release#, PReq# Output Output
ValidIn#, ExtRqst#, RdRdy#, WrRdy#, Int(5:0)#, NMI# ColdReset#, Reset# Input
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Clock relationships (DivMode 2:1)
Cycle
SysClock (input)
PClock (internal) Note (output) Data Data Data Data
Note (input)
Data
Data
Data
Data
Note SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0)
Power-on sequence
VDDIO
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Reset Timing Power-on reset timing
Note
VDDIO SysClock (input)
Note
ColdReset# (input)
SysClock SysClock
Reset# (input)
Notes
1.425 (300 product), (400 product) 2.375 operation 3.135 operation
Cold reset timing
VDDIO SysClock (input)
SysClock SysClock
ColdReset# (input) Reset# (input)
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Warm reset timing
VDDIO
SysClock (input) SysClock
ColdReset# (input) Reset# (input)
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
PACKAGE DRAWING
272-PIN PLASTIC (CAVITY DOWN ADVANCED TYPE) (29x29)
INDEX AREA
4-C1.4
detail part
ITEM
MILLIMETERS 29.00±0.20 29.00±0.20 1.27 1.75±0.30 0.60±0.10 1.15 0.25MIN.
0.75±0.15
0.30 0.15 0.20 1.80 1.80 P272F2-127-BA1
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
RECOMMENDED SOLDERING CONDITIONS
This product should soldered mounted under following recommended conditions. details recommended soldering conditions, refer Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representative. Table 4-1. Surface mounting Type Soldering Conditions
µPD30550F2-300-NN1: 272-pin plastic (C/D advanced type) µPD30550F2-400-NN1: 272-pin plastic (C/D advanced type)
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-203-3
Infrared reflow
Package peak temperature: 235°C, Time: seconds max. 210°C higher), Count: Three times less, Exposure limit: daysNote (after that, prebake 125°C hours)
Note After opening pack, store 25°C less less allowable storage period.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Reference document Electrical Characteristics Microcomputer (U15170J) Note This document number that Japanese version.
Note
related documents indicated publication include preliminary versions. However, preliminary versions marked such.
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Filiale Italiana Milano, Italy Tel: 02-66 Fax: 02-66 Branch Netherlands Eindhoven, Netherlands Tel: 040-244 Fax: 040-244
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
Branch Sweden Taeby, Sweden Tel: 08-63 Electronics (Europe) GmbH Fax: 08-63 Duesseldorf, Germany United Kingdom Branch Tel: 0211-65 Milton Keynes, Fax: 0211-65 Tel: 01908-691-133 Fax: 01908-670-290 Sucursal Madrid, Spain Tel: 091-504 Fax: 091-504 Succursale France Tel: 01-30-67 Fax: 01-30-67
Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137
Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
J02.4
Preliminary Data Sheet U15700EJ1V1DS
µPD30550
VR5000, VR5000 Series, VR5432, VR5500, Series trademarks Corporation. MIPS registered trademark MIPS Technologies, Inc. United States.
Exporting this product equipment that includes this product require governmental license from U.S.A. some countries because this product utilizes technologies limited export control regulations U.S.A.
information contained this document being issued advance production cycle device. parameters device change before final production Corporation, discretion, withdraw device prior production. devices/types available every country. Please check with local representative availability additional information. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. Descriptions circuits, software, other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software, information design customer's equipment shall done under full responsibility customer. Corporation assumes responsibility losses incurred customer third parties arising from these circuits, software, information. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance.
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