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L64780 DVB-T COFDM Demodulator
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This document contains proprietary information Logic Corporation. information contained herein used disclosed third parties without express written permission officer Logic Corporation. Document DB14-000113-00, First Edition (February 2000) This document describes Logic Corporation's L64780 DVB-T COFDM Demodulator will remain official reference source revisions/releases this product until rescinded update. receive product literature, visit http://www.lsilogic.com. Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. TRADEMARK ACKNOWLEDGMENT Logic logo design registered trademarks Logic Corporation. other brand product names trademarks their respective companies. Copyright 1999, 2000 Logic Corporation. rights reserved.
Preface
This book primary reference technical manual L64780 DVB-T COFDM Demodulator. contains complete functional description well complete physical electrical specifications Logic L64780.
Audience This document assumes familiar with digital video broadcasting, terrestrial television transmission reception, modulation/demodulation, error control coding, digital signal processing, microprocessors, related support devices. people benefit from this book are:
Organization
engineers managers evaluating L64780 receiver digital cable data transmissions. engineers designing L64780 into system.
This document following chapters appendixes:
Chapter Introduction, provides brief overview L64780 lists features benefits. Chapter Architectural Overview, describes architecture L64780 gives functional description main components. Chapter Interfaces, describes interfaces L64780 gives functional description each. Chapter Register Descriptions, provides description registers that determine functionality L64780.
Preface
Chapter Signal Descriptions, provides description signals used generated L64780. Chapter Specifications, describes specifications L64780 electrical mechanical characteristics. Appendix Programming L64780 Using Serial Interface, describes program L64780 using Serial Bus.
Related Publications
ETSI Specification 744. 1997. "Digital broadcasting systems television, sound data services; Framing structure, channel coding modulation digital terrestrial television."
Stott, J.H., 1996. Terrestrial (DVB-T) Specification Implementation Practical Modem. International Broadcasting Convention 1996.
Conventions Used This Manual word assert means drive signal true active. word deassert means drive signal false inactive. Hexadecimal numbers indicated prefix "0x" (for example, 0x32CF). Binary numbers indicated prefix "0b" (for example, 0b0011.0010.1100.1111).
Preface
Contents
Chapter
Introduction Overview Using L64780 Receiver Tuner Block Functions Modes Operation Features Typical Performance Architectural Overview Demodulator Module Functional Description Analog-to-Digital Converter (ADC) Automatic Gain Control (AGC) 2.3.1 Target Value 2.3.2 External Loop Filter 2.3.3 Loop Gain Real-to-Complex Conversion Fast Fourier Transform (FFT) Block Time Synchronization 2.6.1 Timing Loop Gain 2.6.2 TIM_CLK_INIT Register Definition 2.6.3 External Loop Filter Automatic Frequency Control (AFC) 2.7.1 Analog Frequency Synchronization 2.7.2 Digital Frequency Synchronization 2.7.3 Loop Gain 2.7.4 AFC_INIT_FREQ Register Definition 2.7.5 External Loop Filter Decoding Frame Synchronization Mode Control Logic
Chapter
2-10 2-10 2-10 2-11 2-12 2-12 2-13 2-14
Contents
2.10 2.11 2.12 2.13 Chapter
Channel Estimation Equalization Viterbi Metric Assignment Quantization Symbol Deinterleaver Deinterleaver
2-15 2-16 2-17 2-17
Interfaces Output Interface 3.1.1 Output Format Nonhierarchical Mode 3.1.2 Output Format Hierarchical Mode MUXIN Interface 3.2.1 Access Timing DDFS Blocks 3.2.2 Access Block 3.2.3 Access Block 3.2.4 Access Block 3.2.5 Access Block MUXOUT Interface 3.3.1 DDFS Output 3.3.2 Output 3.3.3 Output 3.3.4 Channel Equalizer (CE) Output 3.3.5 Output 3.3.6 Output Microprocessor Interface Register Descriptions Memory Interrupt Registers 4.2.1 Address Line 0x00 4.2.2 Interrupt Mask Register, Address Line 0x01 Registers 4.3.1 Address Line 0x02 4.3.2 Address Line 0x03 4.3.3 Address Line 0x04 Parameter Registers 4.4.1 Address Line 0x05 4.4.2 Address Lines 0x06, 0x07, 0x08 4.4.3 Address Line 0x09
3-10 3-10 3-11 3-11 3-12 3-13 3-14 3-14 3-14 3-15 3-15 3-16 3-16
Chapter
4-11 4-11 4-12 4-14 4-16 4-16 4-19 4-20
Contents
Chapter
4.4.4 Address Line 0x0A 4.4.5 Address Line 0x0B 4.4.6 Address Line 0x0C 4.4.7 Address Line 0x0D 4.4.8 Address Line 0x0E 4.4.9 Address Lines 0x0F, 0x10 4.4.10 Address Line 0x11 4.4.11 Address Line 0x12 4.4.12 Address Line 0x13 4.4.13 Address Line 0x14 Register Address Line 0x15 Performance Monitoring Registers Address Line 0x16 4.6.1 Address Line 0x17 4.6.2 Address Line 0x18 Mode Register Address Line 0x19 3-Wires Register Address Line 0x1A
4-23 4-24 4-25 4-27 4-27 4-28 4-29 4-30 4-31 4-31 4-32 4-34 4-35 4-35 4-36 4-38
Signal Descriptions Overview Microprocessor Interface Main Signals Sigma-Delta Outputs Signals 3-Wires Signals JTAG Signals Test Pins ASIC Pins 5.10 Pins 5.11 Tester Pins Specifications Electrical Specifications Timing 6.2.1 Input Data Interface 6.2.2 Output Data Interface 6.2.3 Reset Timing Signal Specifications
Chapter
Contents
Appendix
Pinouts 6.4.1 List 6.4.2 Layout Mechanical Drawing
6-11 6-11 6-14 6-15
Programming L64780 Using Serial Interface Serial Protocol Overview Programming Slave Address Using Serial A.2.1 Write Cycle Using Serial A.2.2 Read Cycle Using Serial Customer Feedback
Figures Typical Terrestrial-Only Receiver Tuner Example Receiver Architecture Satellite Terrestrial Reception Performance with Additive Write Gaussian Noise (AWGN) DVB-T Carrier Co-channel PAL-I Interference Ratio Failure Maximum Level Single Echo Failure QPSK, Rate 1/2, Guard Interval DTTV Demodulator Architecture Structure 9-Bit AGC_TARGET Register Loop Pass Filter External Low-Pass Loop Filter Loop Pass Filter Scattered Pilot Structure Output Interface Nonhierarchical Serial Modes Nonhierarchical, Serial Mode, Constellation Nonhierarchical, Serial Mode, Constellation Nonhierarchical, Serial Mode, QPSK Constellation Output Interface Nonhierarchical Parallel Modes Nonhierarchical, Parallel Mode, Constellation Nonhierarchical, Parallel Mode, Constellation 2-12 2-15
viii
Contents
3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28
Nonhierarchical, Parallel Mode, QPSK Constellation Output Interface Hierarchical FECs Modes Hierarchical, Decoders, Constellation Hierarchical, Decoders, Constellation Output Interface Hierarchical Mode Hierarchical, Decoder Mode With Selected) Selected only) Hierarchical, Decoder Mode With Selected Only) MUXIN Signals Interface Timing DDFS Input Mapping Input Mapping Input Mapping Input Mapping Input Mappings D[23:0] Mapping Three-Bit Soft Decision D[23:0] Mapping Four-Bit Soft Decision DDFS Output Mapping Output Mapping Output Mappings Output Mappings Output Mappings Output Mapping Graphical View L64780 Register Address Space Graphical View L64780 Register Address Space Graphical View L64780 Register Address Space Interrupt Generation L64780 Logic Symbol Input Data Timing Output Data Timing Reset Timing Package Layout PQFP Mechanical Drawing: Side Views PQFP Mechanical Drawing: Detail Serial Overview General Call Address
3-10 3-10 3-11 3-11 3-12 3-12 3-12 3-14 3-14 3-14 3-15 3-15 3-16 6-14 6-15 6-16
Contents
Tables Approximate Exact Frequencies Real Complex Conversion MUXINBUS Mapping MUXIN Conifguration MUXOUT_select Word Definition Mode Selection Using Input Signal L64780 Registers Internal Memory DDFS Block Modes MUXIN Signal Settings MUXIN Clock Absolute Maximum Ratings Recommended Operating Conditions Characteristics Input Data Timing Parameters Output Data Timing Parameters Reset Timing Parameters Signal Summary List 3-13 3-16 4-21 4-33
Contents
Chapter Introduction
This chapter provides overview Logic L64780 DVB-T COFDM Demodulator. also lists this chip's features benefits, provides illustrated description typical performance. This chapter contains following sections:
Section 1.1, "Overview," page Section 1.2, "Using L64780 Receiver," page Section 1.3, Tuner Block Functions," page Section 1.4, "Modes Operation," page Section 1.5, "Features," page Section 1.6, "Typical Performance," page
Overview
L64780 part digital terrestrial television receiver signals transmitted accordance with Digital Video Telecommunications Standards Institute (DVB-T/ETSI) specification. These signals convey digital information using Coded Orthogonal Frequency Division Multiplexing (COFDM), well concatenated Reed-Solomon convolutional forward error correction (FEC) techniques. This information payload takes form MPEG-2 transport stream that conveys picture, sound, data information. This MPEG-2 transport stream format used also related specifications transmission digital television signals satellite cable.
L64780 DVB-T OFDM Demodulator
concatenated coding used DVB-T/ETSI specification identical that DVB-S specification satellite transmissions. decoder take same form receivers satellite well terrestrial transmissions. Thus, L64780 chip provides necessary demodulation functions except decoding, which done separate chip, such L64724 L64705. L64780 format pinouts simplify connection L64724/L64705. DVB-T/ETSI specification incorporates many modes, providing wide range capacity/performance trade-off options. L64780 demodulates these modes. Terrestrial transmission paths prone multipath, which result "ghosting" analog television pictures. With conventional methods digital transmission, multipath causes inter-symbol interference. This becomes increasingly problematic rate increases. DVB-T/ETSI specification uses special form modulation that uses Coded Orthogonal Frequency Division Multiplexing, which well-suited channels with significant multipath. tolerate signals with long delay high relative amplitude. Consequently, L64780 accommodate natural multipath (from terrain, buildings, etc.) used Single Frequency Network (SFN). SFN, many transmitters operate same frequency with same modulation (used Digital Audio Broadcasting, which also uses COFDM). frequency domain, multipath seen channel frequency selectivity. COFDM applies concatenated coding, then distributes coded data over many carriers (1705 6817 this case, depending mode). receiver, frequency selectivity channel causes some carriers degraded suppressed. However, receiver determine much each carrier affected noise, then pass this information inner-code Viterbi decoder means soft-decision bits. This allows Viterbi decoder decode data more efficiently. second decoder, Reed-Solomon FEC, completes process.
Introduction
Using L64780 Receiver
L64780 provides those parts receiver DVB-T signals that exclusive terrestrial specification COFDM demodulation inner interleaving. This includes synchronization, channel-equalization, derivation channel-state information. combination Logic L64780 L64724 L64705) chips forms core receiver design DVB-T, supporting possible approaches: exclusively DVB-T reception, dual DVB-T/DVB-S reception (see Figure 1.1). Figure Typical Terrestrial-Only Receiver
VCXO fCLK18 MPEG Demux
MPEG
Tuner
L64780
L64724
Decoder L64005
System
L64118 (automatic gain control) (automatic frequency control)
Figure shows basic structure terrestrial-only receiver. (or, possibly, VHF) signal from antenna passes through Tuner module that delivers intermediate frequency (IF) signal L64780 chip means analog-to-digital converter (ADC). L64780 chip performs essential functions COFDM demodulation, excluding final steps error correction. requires sampling-frequency clock oscillator fCLK18 MHz), which provides control voltage lock frequency desired value. L64780 chip delivers soft-decision information L64705 L64724 chip,
Using L64780 Receiver
which then completes error correction, delivering MPEG-2 Transport Stream. Other MPEG-standard Logic chips (for example, L64118 L64005) then used demultiplex MPEG-2 Transport Stream into coded audio, coded video, data components, handle Conditional Access, decode audio video signals presentation display loudspeakers. Figure 1.1, microprocessor embedded L64118. controls RF-channel selection, mode selection L64780 chip, program selection MPEG demultiplexer.
Tuner Block Functions
Figure indicates functions performed within Tuner block. example uses double-conversion approach, which Tuner converts signal first (IF1, where filtering, amplification, gain control done) followed another conversion second (IF2), required input L64780. Figure Tuner Example
Tracking Filter
Filter
Filter
L64780
Introduction
Figure illustrates terrestrial satellite reception combined unit. satellite reception, signal (for example, from GHz) from dish unit into satellite tuner. This tuner: Selects signal from range Converts signal more intermediate frequencies Down-converts signal base band Feeds components into L64724 single-chip DVB-S satellite receiver L64724: Samples baseband signals Demodulates QPSK Processes error correction functions L64724 also implements bypass demodulation functions. Thus, accept soft decisions delivered L64780 feed them directly Viterbi decoder. This architecture implements cost-effective solution mixed satellite terrestrial front-ends. Figure
UHF/VHF
Receiver Architecture Satellite Terrestrial Reception
Terrestrial Tuner L64780
L-band
Satellite Tuner
L64724
MPEG Transport Stream
Tuner Block Functions
Modes Operation
L64780 supports modes DVB-T specification, including:
sizes Nonhierarchical QPSK, QAM, constellations Hierarchical constellations Constellation scale factors Code rates 1/2, 2/3, 3/4, 5/6, Guard intervals 1/4, 1/8, 1/16, 1/32
Features
L64780 features include:
DVB-T compliance Internal external Digital real-to-complex conversion Spectrum inversion size Rapid time synchronization Rapid frequency synchronization Common phase error correction High-order filter frequency interpolation Automatic mode switching Automatic frame detection channel state information protection against multipath interference 4-bit soft decision outputs Analog digital
Introduction
Stand-alone mode (forward inverse) Easy connection L64705 L64724 160-pin PQFP package
Typical Performance
Figure illustrates target performance L64780 compared simulation results ETSI specification nonhierarchical modes Gaussian channel. Differences between target performance simulations accounted follows:
About noisy reference effect channel equalizer 0.1-0.3 noise channel state measurement
possible specific about source remaining small difference (about because have enough information about conditions under which simulations were performed. losses channel equalizer channel state information) compromises made interests speed tracking time-varying channel. Sacrificing tracking ability reduces losses. Figure
(dB) QPSK
Performance with Additive Write Gaussian Noise (AWGN)
Measured Simulated from specification
Typical Performance
Figure illustrates target protection ratio PAL-I into DVB-T. point indicated "carriers coincident about here" shows point where vision carrier PAL-I signal lines directly with carriers ODFM frequency raster. Figure
(dB) -2500 -1500 -500 Normal Frequency Offset (Hz) Rate Rate QPSK Rate 1500 2500 Carriers coincident about here Less Robust
DVB-T Carrier Co-channel PAL-I Interference Ratio Failure
More Robust
Figure illustrates maximum level echo acceptable demodulator. graph shows that selected mode, demodulator works without failure inside guard interval without failure significantly outside Figure Maximum Level Single Echo Failure QPSK, Rate 1/2, Guard Interval
Relative Level
failure echo here. Delay (µs)
Introduction
Chapter Architectural Overview
This chapter describes L64780 architecture provides functional description each components. contains following sections:
Section 2.1, "Demodulator Module Functional Description," page Section 2.2, "Analog-to-Digital Converter (ADC)," page Section 2.3, "Automatic Gain Control (AGC)," page Section 2.4, "Real-to-Complex Conversion," page Section 2.5, "Fast Fourier Transform (FFT) Block," page Section 2.6, "Time Synchronization," page Section 2.7, "Automatic Frequency Control (AFC)," page 2-10 Section 2.8, "TPS Decoding Frame Synchronization," page 2-13 Section 2.9, "Mode Control Logic," page 2-14 Section 2.10, "Channel Estimation Equalization," page 2-15 Section 2.11, "Viterbi Metric Assignment Quantization," page 2-16 Section 2.12, "Symbol Deinterleaver," page 2-17 Section 2.13, "Bit Deinterleaver," page 2-17
L64780 DVB-T OFDM Demodulator
Demodulator Module Functional Description
components L64780 integrated provide complete system solution demodulation terrestrial satellite originated signals. Figure shows components L64780 indicates their interaction. These components described following sections.
Architectural Overview
Figure
DTTV Demodulator Architecture
Control Analog Control
Digital Control Frequency Sync
Detect
Demodulator Module Functional Description
Input
Real Complex
Frequency Shift
Correction
Channel Estimation Equalization
Viterbi Metrics
Quantize
Symbol Deintlv.
Deintlv.
Time Sync
Decoder
Frame Pulse Configuration Information
Output Interface.
Guard Interval Configuration Size Microprocessor Interface
VCXO
Fast Fourier Transform Analog-to-digital converter VCXO Voltage-controlled crystal oscillator Sigma-Delta Channel state information
Analog-to-Digital Converter (ADC)
Features L64780 analog-to-digital converter include:
low-IF center frequency input: 4.57 input bandwidth: sampling clock: 18.29 resolution: 8-bit
L64780 also offers 10-bit parallel port connection external, 10-bit ADC.
Automatic Gain Control (AGC)
Tuner Amplifier amplifies signal. resulting signal value amplifies this signal that variance allows work properly. this, input signal power must 10.95 down maximum input range, normalized 1.0. This means value input L64780 0.283
2.3.1 Target Value
Figure defines nine-bit AGC_TARGET register. Figure Structure 9-Bit AGC_TARGET Register
AGC_TARGET_MSB[5:0]
AGC_TARGET_LSB[5:0]
perform correctly, input level COFDM signal must 10.95 down normalized Input Range. Thus, target value, input signal must 0.283, shown Equation 2.1.
Equation
Architectural Overview
Since recommended value 0.283, recommended value 0.226, resulting AGC_TARGET initial value 0x74 (0b0111.0100). Thus:
AGC_TARGET_LSB (0b100) AGC_TARGET_MSB 0x0E (0b01110)
Also description Section 4.4.4, "Address Line 0x0A," page 4-23.
2.3.2 External Loop Filter
input power control signal drives Sigma Delta modulated output, AGCOUT. AGCOUT signal drive external passive filter that feeds gain control stage, shown Figure 2.3. Figure Loop Pass Filter
AGCOUT CAGC= RAGC=
values low-pass filter must meet following requirement:
Equation RAGC CAGC
Figure recommended values.
Automatic Gain Control (AGC)
2.3.3 Loop Gain
gain loop, must obey following rule:
Equation
where:
slope tuner characteristics dB/V. target value input signal.
With value 0.283 tuner characteristic dB/V, loop gain
Equation
code Logic uses approximation nearest power Logic uses AGC_GAIN[2:0] register, with following correspondence:
Equation
AGC_GAIN
Because number values AGC_GAIN have limited, those Thus,
Equation
AGC_GAIN
example, AGC_GAIN most appropriate value, giving value
Equation
1.52
real-to-complex block takes input samples from output converts them into complex baseband representation input block.
Architectural Overview
Real-to-Complex Conversion
DVB-T signal occupies bandwidth approximately 7.61 MHz; signal symmetrically disposed extent about notional center carrier. radiated, this normally lies range; however, spectrum symmetrical, because upper lower sidebands different double-sideband modulated signal does have symmetrical spectrum). Thus, complex representation needed describe baseband. This spectrum derived using in-phase quadrature-phase demodulators, each would have sampled separately, using ADCs many well-matched components. L64780 chip avoids complexity expensive matching analog components. uses single ADC, derives complexbaseband representation internal digital processing. samples DVB-T signal then real-to-complex block digitally shifts samples complex baseband form, centered zero frequency. fundamental operation this conversion processing that nominal center frequency (fLIF) related sampling frequency, fCLK18, used (see Table 2.1, which shows that fCLK18 fLIF almost exactly). circuitry L64780 ensures that this case. output block complex numbers rate fCLK18/2. frequencies Table apply normal version DVB-T specification with channels spaced MHz. adopt DVB-T specification with channel spacing, scale clock frequency other frequencies within system (including bit-rate capacity factors 6/8, respectively. Table Approximate Exact Frequencies Real Complex Conversion
Symbol sampling frequency Low-IF center frequency fCLK18 fLIF Approx. Frequency, Exact Frequency, 18.28 4.57 128/7 32/7
Real-to-Complex Conversion
Fast Fourier Transform (FFT) Block
block converts from temporal frequency domain representation. following modes operation:
Inverse (2048 points) (8192 points) mode
Time Synchronization
This block finds optimum timing start window, synchronizes frequency clock, fCLK18, received signal options duration symbol duration guard interval given paragraph DVB-T/ETSI Specification. block takes sequence complex numbers from real-tocomplex conversion block and, synchronize clock, produces control signal voltage-controlled oscillator. control voltage VCXO converted into Sigma-Delta Modulated signal output single wire signal. This signal requires external low-pass filtering extract mean value, which represents control voltage oscillator. transmitter repeats segment signal during guard interval. This block detects repeated portion signal. signal processing resists impairment from high levels echoes interference.
2.6.1 Timing Loop Gain
mode, optimal IIRGAIN 0b01, 3.125 This leads values
Equation
1.69 VCXO
mode, optimal IIRGAIN 0b11,
Architectural Overview
This leads values equal
Equation
VCXO
2.6.2 TIM_CLK_INIT Register Definition
TIM_CLK_INIT register defined two's complement 15-bit register that following meaning: VCXO TIM_CLK_INIT
Equation 2.10
where central frequency VCXO.
2.6.3 External Loop Filter
control voltage signal VCXO drives Sigma Delta modulated output, VCXOUT. VCXOUT drive external passive filter that feeds timing clock control stage. Figure 2.4. Figure External Low-Pass Loop Filter
VCXOUT CTIM= RTIM=
cutoff frequency this system giving estimate Loop Bandwidth resulting low-pass filter time constant values low-pass filter must meet following requirement: RTIM CTIM
Time Synchronization
Automatic Frequency Control (AFC)
methods applying correction required achieve frequency synchronization analog digital. method used depends design analog tuner. L64780 allows both options, which described following subsections.
2.7.1 Analog Frequency Synchronization
This block adjusts frequency local oscillator tuner that center frequency equal nominal value fLIF. adjustment must accurate within small fraction carrier spacing, that intercarrier interference kept acceptably level tracking ability channel estimation absorbed correcting error frequency local oscillator. block takes sequence complex numbers from output block produces control signal local oscillator. This control signal delivered single-wire Sigma-Delta signal. initial error frequency local oscillator several times carrier spacing; measurement frequency error relies continual pilot carriers. measurement range 51.7 mode mode. oscillator control signal derived from measured frequency error. value control signal also read initialized through microprocessor interface, which allows previously stored value used when channel selected, making acquisition faster.
2.7.2 Digital Frequency Synchronization
This block uses digital signal processing (DSP) correct tolerance frequency local oscillator tuner. shifts frequency complex baseband signal that center frequency zero. shift needs accurate within small fraction carrier spacing that intercarrier interference kept acceptably level tracking ability channel estimation absorbed correcting error frequency local oscillator.
2-10
Architectural Overview
block takes sequence complex numbers from output block produces numerical control signal. also takes sequence complex numbers from real-to-complex conversion block applies frequency shift numbers according numerical control signal. Then, passes data block. digital frequency synchronization block comprises parts: shift frequency complex baseband signal, measure error center frequency complex baseband signal presented block. Multiplying signal rotating vector shifts frequency complex baseband signal. number-controlled oscillator (NCO) with sine cosine outputs generates rotating vector. frequency range kHz. error frequency local oscillator translates directly into error center frequency complex baseband signal. range measurement 51.7 mode, mode. numerical control signal derived from measured frequency error. microprocessor interface read initialize value control signal. This allows previously stored value used when channel selected, thus making acquisition faster.
2.7.3 Loop Gain
digital mode, optimal sensitivity (KSENS) when AFC_SENSITIVITY field Parameter Registers (see page 4-18) 0b110:
Equation 2.11
SENS 1.56
analog mode, optimal AFC_SENSITIVITY defined
Equation 2.12
74.4 SENS VCXO
Automatic Frequency Control (AFC)
2-11
2.7.4 AFC_INIT_FREQ Register Definition
digital loop mode, AFC_INIT_FREQ register defined two's complement 24-bit register with following usage: AFC_INIT_FREQ
Equation 2.13
where central frequency VCXO. analog loop mode, AFC_INIT_FREQ register defined two's complement 24-bit register L64780 following usage: vcxo AFC_INIT_FREQ
Equation 2.14
where frequency VCXO.
2.7.5 External Loop Filter
control signal frequency loop drives Sigma-Delta modulated output AFCOUT. AFCOUT signal drive external passive filter that feeds timing clock control stage, shown Figure 2.5. Figure Loop Pass Filter
AFCOUT CAFC RAFC
cutoff frequency this circuit giving rough estimate Frequency Loop Bandwidth resulting low-pass filter time constant:
Equation 2.15
2-12
Architectural Overview
values low-pass filter must meet requirement shown Equation 2.16:
Equation 2.16
Decoding Frame Synchronization
This block takes sequence complex numbers from output block recovers Transmission Parameter Signalling (TPS) data defined paragraph DVB-T/ETSI specification. block passes resulting data control logic L64780; thus configures mode operation much demodulator's circuitry. data contains information
modulation system Whether transmission hierarchical What value transmission hierarchical) inner code rate(s) guard interval mode:
guard interval mode interaction cannot used acquisition, assist receiver handling reconfiguration transmission. implication, also indicates phase four-symbol sequence insertion scattered pilots. Decoder extracts data bits from carriers retains most recent bits. decoder detects start frame carries Bose-Chaudhuri-Hocque (BCH) error check block bits, that data containing errors discarded. data list above passed control logic along with flags: indicates start frame; other indicates whether error check detects errors. there were errors, control logic uses data configure demodulator, discarding previous settings. settings read initialized through microprocessor interface, which allows previously stored settings used when channel selected, making acquisition faster.
Decoding Frame Synchronization
2-13
Mode Control Logic
previously stored mode data available, they used when channel selected when signal strength rises after period signal loss. This done means external microprocessor makes acquisition faster. When Mode Control Logic becomes error-free block, mode data from that block replaces previously determined mode data. this context, mode data consists
mode Length guard interval Modulation system Hierarchy information Inner code rate
mode control logic configures demodulator blocks whose operation affected these parameters. Acquisition demodulator outlined following steps: Achieve full synchronization start clock frequency. Make coarse fine automatic frequency control (AFC) corrections, achieve frequency synchronization. Equalize channel frequency response, once Symbol Number zero. Wait frame start block, wait another frame complete block received. There wait more additional frames, necessary, until block received without errors. modulation system, hierarchy information, code rate from data used configure Viterbi metric assignment block, and, means microprocessor interface, external Viterbi decoder(s).
2-14
Architectural Overview
2.10 Channel Estimation Equalization
output from block sequence complex numbers, each describing signal received COFDM carriers. numbers correspond values, chosen from points current constellation, which were used modulate each carrier modulator. However, each carrier received with unknown amplitude phase combined effects
channel through which signal passed (which, general, frequency selective) minor error timing window
purpose channel estimation equalization block correct these effects that complex numbers output would, plotted Argand diagram, correspond points transmitted constellation (for example, QPSK, QAM, QAM) except superimposed noise interference. transmitted DVB-T signal contains "scattered pilots," which distributed among data cells regular pattern (see Figure 2.6). These transmitted with known values: imaginary part always zero, while real part fixed amplitude. sign real part, however, determined carrier number (according pseudorandom function that also used similar determine real part continual pilots). Figure
Kmin=
Scattered Pilot Structure
Kmax= 1704 Kmax= 6816
Symbol Symbol Symbol Symbol Symbol
Channel Estimation Equalization Block compares each received scattered-pilot cell with known transmitted value (derived from
Channel Estimation Equalization
2-15
PRBS generator) obtain snapshot response "channel" (including timing uncertainty) corresponding carrier that time instant. data cells that must corrected between scattered pilots, both frequency time. This allows appropriately generated corrections each data cell using suitable form interpolation applied measured values scattered pilots. well obtaining "in-between" values channel response, interpolator also slightly reduces effects thermal noise scattered-pilot measurements. reduction noise fact that scattered pilots transmitted with power approximately greater than data cells, keeps inevitable loss performance scattered-pilot noise within acceptable bounds.
2.11 Viterbi Metric Assignment Quantization
This block takes sequence complex numbers, each describing signal received COFDM carriers, after equalization. These received versions complex numbers chosen modulator from points current constellation, according coded bits sent. This block forms Viterbi metrics ("soft decisions") each received bits. These metrics quantized passed after reordering deinterleaver stages, associated Viterbi convolutional decoder. "soft" rather than "hard" decisions vital obtaining rugged properties COFDM. associated Viterbi convolutional decoder, which resides separate chip (for example, Logic L64724), capable accepting soft decisions that quantized either three four bits. Three bits required acceptable performance, while four bits improve performance higher-order modulation options DVBT specification, especially with non-uniform constellations. Decoder chips designed primarily QPSK BPSK modulation commonly three bits because advantage using four bits minimal. L64780 chip provides 4-bit soft decisions, also used drive 3-bit decoders.
2-16
Architectural Overview
2.12 Symbol Deinterleaver
From each received constellation point, Viterbi metric assignment block extracts soft decisions. symbol deinterleaver accepts COFDM symbol containing soft decisions reorders them according algorithm defined DVB-T specification. then passes this reordered data deinterleaver. Echoes cause minima ("holes") received spectrum, leading groups carriers which data unreliable. optimum operation Viterbi decoder, these groups unreliable carriers must split symbol deinterleaver fulfills part this function; remainder done deinterleaver. mode, there 1705 COFDM carriers, which 1512 each symbol carry data. Each these carriers yields either (QPSK), QAM), QAM) soft decisions. Each these soft decisions consists four bits information. effect operation symbol deinterleaver write possible 1512 24-bit words into using address sequence, read them using different address sequence. This means there delay COFDM symbol between input output. case, there 6048 (out total 6817) COFDM carriers that convey data; thus, L64780 provides 6048 24-bit RAM.
2.13 Deinterleaver
presence multipath interference, some COFDM carriers convey data less ruggedly than others. Each COFDM carrier supplies either two, four, soft decisions; these would impaired carrier they came from were impaired. optimum operation Viterbi decoder, best groups unreliable soft decisions maximally spaced. purpose deinterleaver split unreliable soft decisions caused single unreliable COFDM carrier. symbol deinterleaver separates groups unreliable COFDM carriers. deinterleaver accepts groups 3-bit 4-bit soft decisions generated from same COFDM carrier from symbol deinterleaver.
Symbol Deinterleaver
2-17
deinterleaver rearranges these groups soft decisions separate soft decisions generated from same carrier. deinterleaver passes these soft decisions output interface L64780 external decoding. There 6-bit deinterleavers, QPSK, COFDM carrier provides soft decisions: from real part, from imaginary part. deinterleaves soft decision extracted from real part; deinterleaves soft decision from imaginary part. this case, used. (both hierarchical nonhierarchical), COFDM carrier provides four soft decisions: from real part, from imaginary part. deinterleaves soft decision extracted from real part; deinterleaves from imaginary part. deinterleaves from real part; deinterleaves from imaginary part. this case, used. (both hierarchical nonhierarchical), COFDM carrier provides soft decisions: three from real part, three from imaginary part. deinterleaves soft decision extracted from real part; deinterleaves from imaginary part. deinterleaves from real part; deinterleaves from imaginary part. deinterleaves from real part; deinterleaves from imaginary part.
2-18
Architectural Overview
Chapter Interfaces
This chapter describes interfaces Logic L64780 DVB-T COFDM Demodulator. consists following sections:
Section 3.1, "Output Interface," page Section 3.2, "MUXIN Interface," page Section 3.3, "MUXOUT Interface," page 3-13 Section 3.4, "Microprocessor Interface," page 3-16
Output Interface
output interface formats soft decisions presentation downstream Viterbi decoder. input this block stream fourbit 3-bit Viterbi soft decisions from inner deinterleaver. output from this block connects Viterbi decoder that external L64780. output from soft decisions format suitable direct connection L64724 L64705. This block operates differently nonhierarchical hierarchical modes, have serial parallel output format. This block's operational modes described following subsections.
3.1.1 Output Format Nonhierarchical Mode
nonhierarchical mode, output format serial parallel.
L64780 DVB-T OFDM Demodulator
3.1.1.1 Serial Output Format serial output mode, output port L64780 configured shown Figure 3.1. Figure Output Interface Nonhierarchical Serial Modes
DVOUT (not used DVOUT_LP (not used*) CLKOUT54
L64780
When used, signal deasserted LOW.
output interface passes 4-bit 3-bit soft decisions Viterbi decoder through signal accompanied assertion DVOUT. outputs from output interface clocked CLKOUT54. With constellation, L64780 extracts soft decisions from every constellation point MHz; example, soft decision presented every clock cycle. Figure 3.2. Figure
CLKOUT54 SD0[3:0] DVOUT SD00 SD01 SD02 SD03 SD04 SD05 SD06 SD07 SD08 SD09 SD010
Nonhierarchical, Serial Mode, Constellation
Every time soft decisions received from deinterleaver, DVOUT signal stays asserted clock cycles. DVOUT signal deasserted only during scattered pilots, unused carriers, guard interval.
Interfaces
constellation, during which four soft decisions extracted every MHz, DVOUT signal stays asserted over four clock cycles. Figure 3.3. Figure
CLKOUT54 SD0[3:0] SD00 SD01 SD02 SD03 SD04 SD05 SD06 SD07
Nonhierarchical, Serial Mode, Constellation
DVOUT
QPSK constellation, only soft decisions extracted every MHz, resulting DVOUT being asserted over clock cycles. Figure 3.4. Figure
CLKOUT54 SD0[3:0] DVOUT SD00 SD01 SD02 SD03
Nonhierarchical, Serial Mode, QPSK Constellation
3.1.1.2 Parallel Output Format this mode, soft decisions output parallel, output interface L64780 configured. Figure 3.5. Figure Output Interface Nonhierarchical Parallel Modes
DVOUT DVOUT_LP (not used*) CLKOUT54 When used, signal deasserted LOW.
L64780
output interface passes soft decisions Viterbi decoder parallel through SD1, accompanied data valid indicator.
Output Interface
Because soft decisions presented parallel QAM, soft decisions presented three consecutive clock cycles over clock cycle period (Figure 3.6). DVOUT signal deasserted during scattered pilots, unused carriers, guard interval. Figure
CLKOUT54 SD0[3:0] SD1[3:0] DVOUT SD00 SD10 SD01 SD11 SD02 SD12 SD03 SD13 SD04 SD05 SD14 SD15
Nonhierarchical, Parallel Mode, Constellation
When constellation used, DVOUT asserted clock cycles clock cycles (Figure 3.7). When QPSK used, asserted only clock cycles (Figure 3.8). Figure
CLKOUT54
Nonhierarchical, Parallel Mode, Constellation
SD0[3:0]
SD1[3:0] DVOUT
SD00 SD10
SD01 SD11
SD02 SD12
SD03 SD13
Figure
CLKOUT54
Nonhierarchical, Parallel Mode, QPSK Constellation
SD0[3:0]
SD1[3:0] DVOUT
SD00 SD10
SD01 SD11
Interfaces
3.1.2 Output Format Hierarchical Mode
following subsections describe decoding High-Priority Low-Priority data streams hierarchical mode. 3.1.2.1 Decoding Streams hierarchical mode, output port L64780 configured (Figure 3.9). High- Low-Priority streams delivered SD1, respectively. DVOUT validates High-Priority data stream; DVOUT_LP validates Low-Priority data stream. Figure Output Interface Hierarchical FECs Modes
(High-Priority Stream) DVOUT (Low-Priority Stream) DVOUT_LP CLKOUT54
L64780
When mode, soft decisions transmitted SD1. DVOUT DVOUT_LP stay asserted clock cycles. Figure 3.10. Figure 3.10 Hierarchical, Decoders, Constellation
CLKOUT54 SD0[3:0] SD1[3:0] DVOUT DVOUT_LP SD00 SD01 SD10 SD11 SD02 SD03 SD12 SD13
Output Interface
When mode, soft decisions transmitted four soft decisions transmitted SD1. DVOUT signal stays asserted during clock cycles over clock cycles DVOUT_LP signal stays asserted four clock cycles. Figure 3.11. Figure 3.11 Hierarchical, Decoders, Constellation
CLKOUT54 SD0[3:0] DVOUT SD1[3:0] DVOUT_LP SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD00 SD01 SD02 SD03
3.1.2.2 Decoding Only Stream this mode, output port L64780 configured (Figure 3.12). DOF_HPLP signal selects between output streams. data stream this output format same nonhierarchical case. Figure 3.12 Output Interface Hierarchical Mode
(HP/LP Stream) DVOUT (not used DVOUT_LP (not used*) CLKOUT54
L64780
When used, signal deasserted LOW.
Interfaces
When soft decisions received from Deinterleaver block selected) (only selected), soft decisions transmitted over SD0. result that DVOUT asserted clock cycles. Figure 3.13. Figure 3.13 Hierarchical, Decoder Mode With Selected) Selected only)
CLKOUT54 SD0[3:0] DVOUT SD00 SD01 SD02 SD03
When soft decisions received from Deinterleaver block, function configured with data stream selected, four consecutive soft decisions must transmitted over SD0. Thus, DVALIDOUT asserted four clock cycles. Figure 3.14. Figure 3.14 Hierarchical, Decoder Mode With Selected Only)
CLKOUT54 SD0[3:0] DVOUT SD00 SD01 SD02 SD03 SD04 SD05 SD06 SD07
Output Interface
MUXIN Interface
MUXIN lets enter data test vectors) into device specific locations, which lets bypass some front functional blocks test internal functional block. Important: This interface used Logic internal testing intended customer production receivers.
MUXIN (MUXINBUS) 27-bit wide bus, multiplexed with bypass (DIGADCIN[9:0]). Table shows mapping. Table MUXINBUS Mapping
MUXINBUS[26:10] MUXIN[16:0]
MUXINBUS[9:0] DIGADCIN[9:0]
Clocking data into chip very simple because L64780 offers clock output (CLKMUXIN) that automatically correct phase frequency. CLKMUXIN automatically selects correct internal clock, depending block selected. Figure 3.15 shows connect external logic that brings data MUXINBUS. Figure 3.15 MUXIN Signals Interface
CLKMUXIN
TEST_VECTOR
MUXINBUS[26:0]
DATA GENERATOR
L64780
Interfaces
MUXINBUS software controlled provides testing possibilities. control word MUXIN_select[2:0], located address 0x15, mapped bits Table defines MUXIN_select[2:0] word. Table MUXIN Conifguration
Definition Normal mode Access Timing DDFS block Access block Access block Access block Input block Reserved Reserved
MUXIN_select[2:0]
MUXIN Interface
3.2.1 Access Timing DDFS Blocks
When selecting access Timing DDFS blocks, CLKMUXIN signal configured clock (more precisely, four times IF). DDFS block digital rotator that performs carrier frequency compensation. signals data two's complement format), start pulse (START), data valid signal (DV). These signals mapped MUXINBUS. Figure 3.16. Figure 3.16 Timing DDFS Input Mapping
Q[9:0] I[9:0]
START
this mode, select whether start pulse comes from MUXINBUS from Timing recovery unit. start pulse delimits every COFDM symbol. This selection done through DDFS_MODE (address 0x9, DDFS_MODE start pulse comes from test (test mode); otherwise, Timing block delivers start pulse. Note that this mode could correspond external downconverter that feeds data directly into Timing DFFS blocks.
3.2.2 Access Block
block performs estimation carrier frequency drift produces analog digital feedback control signal compensate this drift. this mode, CLKMUXIN signal configured clock (more precisely, eight times IF). signals data two's complement format), start pulse (START), data valid (DV) signal, COFDM symbol number (S_NB). These signals mapped MUXINBUS. Figure 3.17. Figure 3.17 Input Mapping
START Q[9:0] I[9:0]
S_NB
3-10
Interfaces
this mode, select whether COFDM symbol number comes from informations (Frame Number) from MUXINBUS (S_NB). This selection done through AFC_MODE (address 0x5, AFC_MODE COFDM symbol number comes from MUXINBUS (S_NB) full MUXIN mode; otherwise, comes from register (partial MUXIN mode).
3.2.3 Access Block
this mode, CLKMUXIN signal configured clock (more precisely, eight times IF). signals data two's complement format) start pulse (START). These signals mapped MUXINBUS. Figure 3.18. Figure 3.18 Input Mapping
START Q[9:0] I[9:0]
this mode, L64780 used stand-alone processor forward mode (FFT_DIR inverse mode (FFT_DIR FFT_DIR register located address 0x11,
3.2.4 Access Block
block performs Channel State Information (CSI) processing, which builds soft decisions Viterbi decoder using priori information from Channel Equalizer (CE). this mode, CLKMUXIN configured clock (more precisely: four times IF). signals data twos complement format), start pulse (START), data valid (DV) signal, COFDM symbol number (S_NB), marker data valid) scattered pilots (DVSP). These signals mapped MUXINBUS. Figure 3.19. Figure 3.19 Input Mapping
DVSP Q[10:0] I[10:0]
START S_NB
MUXIN Interface
3-11
3.2.5 Access Block
block performs Symbol Deinterleaving (SDI) specified ETSI specification. this mode, CLKMUXIN signal configured clock (more precisely, four times IF). signals 24-bit data contain soft decisions, four bits soft decision, start pulse (START), data valid (DV) signal, symbol parity (S_P). symbol number marked even symbol numbers marked These signals mapped MUXINBUS. Figure 3.20. Figure 3.20 Input Mappings
D[23:0]
START
data mapped 3-bit 4-bit soft decision modes, shown Figure 3.21 Figure 3.22, respectively. highest weight position. Note that means reserved. Figure 3.21 D[23:0] Mapping Three-Bit Soft Decision
QSPK
QPSK
Figure 3.22 D[23:0] Mapping Four-Bit Soft Decision
QSPK QPSK
3-12
Interfaces
MUXOUT Interface
MUXOUT lets probe point device while receiving transport stream (TS). Important: This interface used Logic internal test purposes intended customer production receivers.
MUXOUTBUS bits wide. each probed point, data control signals available this (including clock). clock same aspect ratio CLKMUXIN; duty cycle type. Software controls MUXOUTBUS, which provides five test possibilities. control word MUXOUT_select[2:0], located address 0x15 (bits Table define MUXOUT_select word. Table MUXOUT_select Word Definition
Definition DDFS output output output output output Reserved Reserved
MUXIN_select[2:0]
Note that MUXOUT 3-stated asserting MUX_CTRL (bit Mode Register Address Line), address 0x19. active when MUX_CTRL
MUXOUT Interface
3-13
3.3.1 DDFS Output
DDFS output lets probe signals after carrier frequency compensation prior processing. signals data two's complement format), start pulse that delimits COFDM symbols (START), data valid (DV) signal that accompanies valid data, clock. These signals mapped MUXOUTBUS. Figure 3.23. Figure 3.23 DDFS Output Mapping
Q[9:0] I[9:0]
START
3.3.2 Output
output lets probe data prior Common Phase Error (CPE) correction Channel Equalization (CE). signals data two's complement format), start pulse that delimits COFDM symbols (START), data valid (DV) signal that accompanies valid data, clock. These signals mapped MUXOUTBUS. Figure 3.24. Figure 3.24 Output Mapping
Q[9:0] I[9:0]
START
3.3.3 Output
output lets probe data after Common Phase Error (CPE) correction prior Channel Equalization (CE). signals data two's complement format), start pulse that delimits COFDM symbols (START), data valid (DV) signal that accompanies valid data, clock. These signals mapped MUXOUTBUS. Figure 3.25. Figure 3.25 Output Mappings
Q[11:0] I[11:0]
START
3-14
Interfaces
3.3.4 Channel Equalizer (CE) Output
Channel Equalizer (CE) output lets probe data after channel equalization frequency response channel. After channel equalization, display constellation feeding data into DACs. constellation display purposes, DACs require only 8-bit resolution. signals this point data two's complement format, start pulse that delimits COFDM symbols (START), data valid (DV) signal that accompanies valid data, clock. These signals mapped MUXOUTBUS. Figure 3.26. Figure 3.26 Output Mappings
Q[11:0] I[11:0]
START
data available represent either equalized data frequency response channel depending upon CE_SELECT (address 0x11, When CE_SELECT equalized data present MUXOUT bus; otherwise, MUXOUT contains channel response frequency domain.
3.3.5 Output
output provides averaged measure carrier confidence placed hard decision. signals present this point degree confidence (CSI), start pulse that delimits COFDM symbols (START), data valid (DV) signal that accompanies valid data, clock. These signals mapped MUXOUTBUS. Figure 3.27. Figure 3.27 Output Mappings
CSI[10:0]
START
high value indicates level confidence, viceversa. word nonsigned data, which used drive graph representing quality reception channel.
MUXOUT Interface
3-15
3.3.6 Output
output lets probe internal ADC. signals digitized input samples (ADC) clock. These signals, which two's complement format, mapped MUXOUTBUS. Figure 3.28. Figure 3.28 Output Mapping
ADC[7:0]
Microprocessor Interface
microprocessor interface operates Serial Mode. Important: Parallel mode interface provided test purposes. This interface used Logic internal testing intended customer production receivers.
Serial mode interface serial interface operating slave mode. protocol compatible with specifications. more detailed description Serial Bus, Appendix input signal selects either serial parallel mode. Table summarizes different modes. Table
High
Mode Selection Using Input Signal
Mode Parallel Serial Notes Internal only L64780 Serial Interface
When Serial interface mode, used serial data signal, used serial clock signal. D[7:1] used serial slave address. When using serial bus, D[7:1] must hardwired appropriate device slave address.
3-16
Interfaces
Chapter Register Descriptions
This chapter provides overview L64780 register space gives detailed description registers. This chapter consists following sections:
Section 4.1, "Memory Map," page Section 4.2, "Interrupt Registers," page Section 4.3, "TPS Registers," page 4-11 Section 4.4, "Parameter Registers," page 4-16 Section 4.5, "Mux Register Address Line 0x15," page 4-32 Section 4.6, "Performance Monitoring Registers Address Line 0x16," page 4-34 Section 4.7, "Mode Register Address Line 0x19," page 4-36 Section 4.8, "3-Wires Register Address Line 0x1A," page 4-38
L64780 DVB-T OFDM Demodulator
Memory
Table lists L64780 registers provides DTTV demodulator internal memory map. description each these registers groups provided following sections. Table L64780 Registers Internal Memory
Register Width (Bits)
Space
Address 0x00 0x01 0x02 0x03
Register name Interrupt register Interrupt Mask register register register register Parameters register Parameters register Parameters register Parameters register
Type
0x04 0x05 0x06 0x07 0x08
Register Descriptions
Table
L64780 Registers Internal Memory (Cont.)
Register Width (Bits)
Space
Address 0x09 0x0A 0x0B 0x0C 0x0D
Register name Parameters register Parameters register Parameters register Parameters register Parameters register Parameters register Parameters register Parameters register Parameters register Parameters register Parameters register Parameters register register Performance Monitoring register Performance Monitoring register Performance Monitoring register Mode register Wires register
Type
0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
0x18 0x19 0x1A
Figure through Figure give graphical view register address space. Shaded parts these figures denote reserved bits.
Memory
Figure
ddress 0x00
Graphical View L64780 Register Address Space
Interrupt Register
Sync Into Change Change
0x01
Sync Change
Into Change
Interrupt Mask Register
0x02 0x03 0x04 Frame Number
Mode
Guard
Code Rate
Code Rate Type
Registers
Hierarchy Info
0x05
Clipping
Mode
Fine Mode
Stall Polarity
Sensitivity
0x06 0x07 0x08
AFC_INIT_FREQ [LSB] Parameter registers
AFC_INIT_FREQ [CSB]
AFC_INIT_FREQ [MSB]
Register Descriptions
Figure
Address 0x09
Graphical View L64780 Register Address Space
Disable Disable Format Disable Polarity DDFS Disable DDFS Mode Gain Chip
Soft Decision Width
0x0A
Target[LSB]
0x0B
Format
target[MSB] IIRgain
0x0C 0x0D
TIM_LOOP_I
TIM_LOOP_P
Timing Offset Position[LSB]
0x0E 0x0F 0x10
STALL
Polarity
Timing Offset Position[MSB]
Parameter Registers
Timing INIT [LSB]
Timing INIT [MSB]
0x11
Disable
Disable
Disable
TEMPO Type
Select
Direction Format
Gain setting
0x12 0x13 0x14
IIrate
HP_OFFSET LP_OFFSET
Memory
Figure
Address
Graphical View L64780 Register Address Space
Register
0x15
MUXIN Select
MUXOUT Select
0x16 0x17 0x18
Frame Sync
Freq Sync
Start Clock Sync Sync
Sync
Average Channel State Information Indication
Performance Monitoring Registers
Peak Channel State Information Indication
0x19
Odrain Ctrl
Wires3 Ctrl
Ctrl
Ctrl
Soft Reset
Auto Mode Enable
Change Mode
Mode Register
0x1A
WIRES3_IN
WIRES3_OUT
Wires Register
Register Descriptions
Interrupt Registers
DTTV demodulator generates interrupts based events specific functional blocks chip. These events reported Interrupt register. types events might interest external microcontroller:
Events relating severe impairments. external microcontroller must evaluate severity these events take necessary corrective action. Events relating changes operation DTTV demodulator. These occur during normal operation made available external microcontroller monitoring.
Interrupt register address 0x00 provides microprocessor with events DTTV demodulator that cause internal interrupt. This read-only register contains bitmap indicating which events took place. associated with Interrupt Mask register.
4.2.1 Address Line 0x00
0x00
SYNC_CHANGE TPS_INFO_CHANGE
Reserved These bits reserved.
[7:2]
SYNC_CHANGE Synchronization Change Interrupt This indicates more aspects DTTV demodulator synchronization have changed. initial condition SYNC_CHANGE interrupt). this interrupt generated.
Interrupt Registers
Sync change event visible through signal SYNC CHANGE (see Section 4.6, "Performance Monitoring Registers Address Line 0x16") occurs when least following synchronizations changed during demodulation:
Frame_Sync_OK when frame
synchronization reached reset when frame synchronization lost. Frame_Sync_OK visible through Performance Monitoring register.
Freq_Sync_OK when demodulator frequency locked reset when frequency synchronization reached lost. Freq_Sync_OK visible through Performance Monitoring Register
Start_Sync_OK when timing
block properly determined start FFT; reset when this lost. Start_Sync_OK visible through Performance Monitoring Register
Clock_Sync_OK when sampling
frequency properly locked; reset when sync reached. Clock_Sync_OK visible through Performance Monitoring register
TPS_Sync_OK when
frame error free; reset when frame corrupted. TPS_Sync_OK visible through Performance Monitoring Register TPS_INFO_CHANGE Change Interrupt valid structure been received that differs from current mode DTTV demodulator. This interrupt does occur only change frame number. TPS_INFO_CHANGE initially reset interrupt). this interrupt generated. TPS_INFO_CHANGE only when received error-free (BCH-correct) different from last information stored registers. This only reset microprocessor read access. TPS_INFO_CHANGE evaluated every COFDM frame, visible through TPS_INFO_CHANGE signal (see Section 4.3, "TPS Registers").
Register Descriptions
4.2.2 Interrupt Mask Register, Address Line 0x01
microprocessor select between polling interrupt driven approach programming Interrupt Mask register. Only when Interrupt Mask register associated with event Interrupt register interrupt this event enabled; otherwise, polling selected. interrupt-related events reported Interrupt register lead assertion INTn signal (active LOW). receiving interrupt signal, microcontroller expected read Interrupt register identify cause(s) this interrupt. microcontroller thereby resets interrupt events Interrupt register; this remains effect until interrupt (TPS info change Sync change) occurs. disable permanently interrupt mechanism, reset Interrupt Mask register. Figure shows implementation interrupt generation. Figure Interrupt Generation
Eventi
Maski
From other interrupts
Interrupt Registers
Note that read access Address resets Interrupt Register. does mask interrupts that arise time host reads interrupt register; thus, when Host reads interrupt register, each interrupt either reset, again interrupt occurs.
0x01 SYNC_CHANGE_MASK TPS_INFO_CHANGE_ MASK
Reserved These bits reserved.
[7:2]
SYNC_CHANGE _MASK Synchronization Change Interrupt Mask This enables disables generation interrupt more aspects DTTV demodulator synchronization have changed. this interrupt masked; interrupt enabled. initial condition this TPS_INFO_CHANGE_MASK Change Interrupt Mask This enables disables generation interrupt TPS_INFO_CHANGE bit. this interrupt masked; interrupt enabled. initial condition this
4-10
Register Descriptions
Registers
These registers have functions, depending whether they read from, written they read from, they indicate that contents last structure were correctly received. they written they next mode operation DTTV demodulator. mode change does take effect until CHANGE_MODE command issued setting CHANGE_MODE Mode register). meaning bits contained described ETSI specification.
4.3.1 Address Line 0x02
0x02 GUARD
MODE
FFTMODE
Reserved These bits reserved.
[7:4]
COFDM Transmission Mode [3:2] When this register read, these bits provide last value received channel, using signalling information. When register written, these bits store next COFDM transmission mode value that system uses. values are:
FFTMODE[1:0] Definition Mode Mode Unused Unused
initial condition FFTMODE 0b00 (2k).
Registers
4-11
GUARD
Guard Interval [1:0] When this register read, Guard Interval provides last value received channel, using signalling information. When this register written, Guard [1:0] stores next Guard value that system uses. values are:
GUARD[1:0] Definition 1/32 Guard Interval 1/16 Guard Interval Guard Interval Guard Interval
initial condition Guard Interval 0b00 (1/32).
4.3.2 Address Line 0x03
0x03 LP_CODE_RATE HP_CODE_RATE
Reserved These bits reserved.
[7:6]
LP_CODE_RATE Viterbi Low-Priority Code Rate [5:3] When this register read, these bits provide last value received channel, using signalling information.
4-12
Register Descriptions
When this register written, these bits store next Viterbi Code Rate Low-Priority stream value that system uses. values are:
LP_CODE_RATE[2:0] Definition Code Rate Code Rate Code Rate Code Rate Code Rate Reserved Reserved Reserved
initial condition LP_CODE_RATE 0b000 (1/2). HP_CODE_RATE Viterbi High-Priority Code Rate [2:0] When this register read, these bits provide last value received channel, using signalling information. When this register written, these bits store next Viterbi Code Rate High-Priority stream value that system uses. values are:
HP_CODE_RATE[2:0] Definition Code Rate Code Rate Code Rate Code Rate Code Rate Reserved Reserved Reserved
initial condition these bits 0b001 (2/3).
Registers
4-13
4.3.3 Address Line 0x04
0x04 HIERARCHY
FRAME_NB
QAMTYPE
FRAME_NB
Reserved This reserved.
COFDM Frame Number [6:5] When this register read, these bits provide last value received channel, using signalling information. values are:
FRAME_NB[1:0] Definition Frame Frame Frame Frame
initial condition FRAME_NB 0b00 (Frame Internally, there three registers:
first (0x02, active register) contains
current mode DTTV demodulator.
second (the next register, 0x03) written
writing register register map. When "change mode" command issued, next register copied into active register, this becomes current mode demodulator.
third register (the received register, 0x04)
contains copy last valid that received input signal. This register read reading from register register map. AUTO_MODE_ENABLE set, then every time valid received super-frame boundary detected, demodulator copies contents received register into active register (and changes current mode DTTV receiver received changes). received (stored received register) current mode DTTV demodulator (held
4-14
Register Descriptions
active register) differ, TPS_INFO_CHANGE CLK18 clock cycle. When TPS_INFO_CHANGE interrupt enabled this event occurs, DTTV demodulator generates interrupt external microcontroller. rule TPS_INFO_CHANGE applies data bits except frame number. HIERARCHY COFDM Nonuniform Constellation Ratio [4:2] When this register read, these bits provide last value received channel, using signalling information. When this register written, these bits store next Constellation expansion ratio that system uses. values are:
HIERARCHY[2:0] Definition Nonhierarchical Reserved Reserved Reserved Reserved
initial condition HIERARCHY 0b000 (Nonhierarchical).
Registers
4-15
QAMTYPE
Constellation Type [1:0] When this register read, these bits provide last value received channel, using signalling information. When this register written these bits store next Constellation Type value that system uses. values are:
QAMTYPE[1:0] Definition QPSK reserved
initial condition QAMTYPE 0b10 QAM).
Parameter Registers
Parameter registers contain configuration information. registers read, they indicate current parameter value. These Parameter registers only configurable through microprocessor.
4.4.1 Address Line 0x05
0x05
AFC_ AFC_FINE AFC_MODE AFC_STALL AFC_POL AFC_SENSITIVITY CLIPPING _MODE
AFC_CLIPPING Loop Bandwidth Limiter This selects combination method between Fine Algorithm part Coarse Algorithm part. When using Method (AFC_CLIPPING combination done adding values. When Coarse part integer number carrier spacing, Fine part fraction carrier spacing, result exact frequency offset. When using Method (AFC_CLIPPING Fine part only considered when Coarse value
4-16
Register Descriptions
not, value applied Tuner Oscillator (via Sigma-Delta) either This limits bandwidth system. initial condition AFC_CLIPPING which Method AFC_MODE Muxin Mode When MUXIN connected AFC, this determines Symbol Number coming from (Partial MUXIN Mode), Normal functional mode, coming from MUXIN itself (Full MUXIN Mode). this Symbol Number coming from Full MUXIN Mode; this Symbol Number coming from Partial MUXIN Mode. initial condition AFC_MODE Full MUXIN mode. However, this effect default mode AFC_MUXIN (which means that taking Symbol Number from matter what value AFC_MODE is). definition MUXIN register more information. AFC_FINE_MODE Fine Algorithm Mode This determines Fine Algorithm performs weighted mean. Weighted mean mode chosen (this algorithm performs weighted mean signal measurements perform Fine calculation. Unweighted mean mode chosen (this algorithm does perform weighted mean signal measurements perform Fine calculation. initial condition this Weighted Mean mode. AFC_STALL Loop Updating Freeze This determines Loop working frozen. Loop working (0), integrator inside L64780 updates value from time time.
Parameter Registers
4-17
Loop stalled (1), integrator inside L64780 keeps internal value constant, enabling Frequency Offset means software (using AFC_INIT_FREQ). initial condition AFC_STALL normal working mode. AFC_POL Polarity These bits determine polarity external VCO. polarity positive (this output frequency external down-converter must increase with increasing voltage from AFCOUT pin. polarity negative (this output frequency external down-converter must decrease with increasing voltage from AFCOUT pin. initial condition AFC_POL (positive). AFC_SENSITIVITY Loop Gain [2:0] These bits adjust Gain Loop Filter. value according sensitivity input external down-converter. values digital loop mode are:
AFC_SENSITIVITY[2:0] Definition
SENS 1.52 SENS SENS
SENS 1.22 SENS 2.44 SENS 4.88 SENS SENS 1.95
initial condition these bits 0b110, SENS
4-18
Register Descriptions
values Analog loop mode are:
AFC_SENSITIVITY[2:0] Definition
SENS 2.44 SENS 4.88 SENS SENS SENS SENS SENS 1.95
SENS 1.56
initial condition these bits 0b110, SENS 1.56
4.4.2 Address Lines 0x06, 0x07, 0x08
0x06 0x07 0x08 AFC_INIT_FRQ_LSB AFC_INIT_FRQ_CSB AFC_INIT_FRQ_MSB
AFC_INIT_FRQ Initial Frequency Offset [7:0] These three 8-bit registers select Initial Frequency Offset that directed towards Tuner DDFS block.
When these registers read, resultant value
represents actual Frequency Offset (for example, content integrator) recovered system.
When this register written, resultant value reinitializes Integrator value.
Three accesses necessary update these
registers; thus, should first stall Integrator setting AFC_STALL then update values. reactivate integrator resetting AFC_STALL initial condition these registers
Parameter Registers
4-19
4.4.3 Address Line 0x09
0x09 SOFTBIT ADCON
BDI_ SDI_ DISABLE DISABLE
DOF_OUTPUT_ FORMAT
DDFS_ DDFS_ DISABLE MODE
SOFTBIT
Soft Decision Number Bits This determines 3-bit 4-bit soft decision used. initial condition this Disable this Deinterleaver disabled; this Deinterleaver enabled. initial condition this Normal Operational Mode.
BDI_DISABLE
SDI_DISABLE Disable this Symbol Deinterleaver disabled; this Symbol Deinterleaver enabled. initial condition this Normal Operational Mode. DOF_OUTPUT_FORMAT Chip Output Format [4:3] These bits select output format L64780 towards decoder chip. different formats described Section 3.4, "Microprocessor Interface." There three modes:
When Nonhierarchical mode, submodes
provided: Serial Parallel. Serial Mode, data presented only SD0. Parallel Mode, data presented SD1.
When Hierarchical mode with only chip,
either stream Stream presented.
4-20
Register Descriptions
When Hierarchical mode with chips,
streams presented SD1, respectively.
DOF_OUTPUT_ Hierarchical FORMAT[1:0] Definition Serial Mode Parallel Mode stream over SD0, Mode stream over SD0, Mode over SD0, over SD1, Mode
initial condition these bits 0b00. DDFS_DISABLE DDFS Disable This determines DDFS performs Baseband correction (1). initial condition DDFS_DISABLE Normal Operational Mode (0). DDFS_MODE DDFS Start Pulse Selector this DDFS block gets START Pulse (pulse delimiting every COFDM symbol) from Timing Recovery Unit Block; this DDFS block gets START Pulse from MUXIN Block. initial condition value DDFS_MODE DDFS block operate four modes, listed Table 4.2. Table
DDFS Mode
DDFS Block Modes
DDFS Muxin DDFS Disable Functional Mode Normal Test Down-Converter Off-Chip Disable Mode
Parameter Registers
4-21
When Normal mode, L64780 receives real signal intermediate frequency (about MHz), block performs baseband conversion. this mode, DDFS block receives complex baseband signal directly from block takes DDFS_XIN, DDFS_YIN, DDFS_DVIN signals symbol synchronization DDFS_STARTIN signal from Timing synchronization (TIM) block. Down-Converter Off-Chip mode, baseband conversion done tuner, COFDM symbol synchronization signal still provided block. this mode, DDFS block takes DDFS_XOFF, DDFS_YOFF, DDFS_DVOFF signals from offchip interface, whereas symbol synchronization DDFS_STARTIN signal comes from block (see Section 3.2.1, "Access Timing DDFS Blocks," page 3-10, DDFS_XOFF, DDFS_YOFF, DDFS_DVOFF signals mapping into MUXIN bus). When Test mode, DDFS block receives baseband complex data symbol synchronization from off-chip interface. this mode, DDFS_XOFF, DDFS_YOFF, DDFS_DVOFF, DDFS_STARTOFF signals come from off-chip interface. (See Section 3.2.1, "Access Timing DDFS Blocks," page 3-10, DDFS_XOFF, DDFS_YOFF, DDFS_DVOFF DDFS_STARTOFF signals mapping into MUXIN bus.) Disable mode, only DDFS_XIN, DDFS_YIN, DDFS_DVIN, DDFS_STARTIN signals used; frequency shift applied incoming complex data, data processing time latency must preserved. ADCON Selector This determines L64780 uses 8-bit on-chip (1), external 10-bit ADC. initial condition ADCON external 10-bit ADC.
4-22
Register Descriptions
4.4.4 Address Line 0x0A
0x0A AGC_GAIN
AGC_TARGET_LSB
AGC_DISABLE AGC_POL
AGC_TARGET_LSB Target Value (LSB) [7:5] These bits select LSBs Target value Loop (see Section 2.3.1, "AGC Target Value"). initial condition these bits 0b100. AGC_DISABLE Disable This determines disabled (0). initial condition AGC_DISABLE Normal Operational Mode. AGC_POL Loop Polarity This selects polarity external Loop. polarity positive (this gain external down-converter must increase with increasing voltage from AGCOUT pin. polarity negative (this gain external down-converter must decrease with increasing voltage from AGCOUT pin. initial condition AGC_POL negative.
Parameter Registers
4-23
AGC_GAIN
Loop Gain [2:0] These bits adjust Gain Loop Filter. value according sensitivity loop. values are:
AGC_GAIN[2:0] Definition
initial condition these bits 0b011,
4.4.5 Address Line 0x0B
0x0B ADC_FORMAT R2C_SI AGC_TARGET_MSB
ADC_FORMAT Format Output This determines outputs values two's complement binary offset format (0). initial condition ADC_FORMAT binary offset. R2C_SI COFDM Spectrum Inversion During up-conversion following downconversion, COFDM spectrum inverted, depending equipment used. This determines COFDM signal should spectrally inverted (0). initial condition R2C_SI normal operation. This spectrum inversion changes sign sine function (negative positive
4-24
Register Descriptions
AGC_TARGET_MSB Target Value (MSB) [5:0] These bits select MSBs Target value Loop (see Section 2.3.1, "AGC Target Value"). initial condition these bits 0x0E.
4.4.6 Address Line 0x0C
0x0C TIM_LOOP_I TIM_LOOP_P
TIM_IIRGAIN
TIM_LOOP_I Timing Gain Loop [7:5] These bits adjust Timing Gain Loop Filter. value according sensitivity VXCO loop.
TIM_LOOP_I[2:0] Definition
0.125 3.125
1.95 1.22
7.63
initial condition TIM_LOOP_I ob011 (Gain 1.95
Parameter Registers
4-25
TIM_LOOP_P Timing Gain Loop [4:2] These bits adjust Timing Gain Loop Filter. value according sensitivity VXCO loop.
TIM_LOOP_P[2:0] Definition
0.25 0.125 6.25
initial condition TIM_LOOP_P 0b011 1.0. (Gain TIM_IIRGAIN Timing Filter Time Constant [1:0] These bits govern amount Filtering done Timing Loop Filter.
TIM_IIRGAIN[1:0] Definition 6.25 1.56
3.125
initial condition TIM_IIRGAIN 0b01 (Gain 3.125
4-26
Register Descriptions
4.4.7 Address Line 0x0D
0x0D TIM_OFFSET_LSB
TIM_OFFSET_LSB Start Pulse Phase Offset (LSB) [7:0] start pulse signal with periodicity every FFT-MODE+GUARD cycles steady state). TIM_OFFSET bits adjust phase this signal periodic window. initial condition TIM_OFFSET_LSB bits 0x00.
4.4.8 Address Line 0x0E
0x0E TIM_STALL TIM_POL TIM_OFFSET_MSB
TIM_STALL
Loop Updating Freeze This determines Loop working (this stalled (this Loop working, integrator inside L64780 updates value. Loop stalled, integrator inside L64780 keeps internal value constant, letting VCXO Frequency Offset means TIM_CLK_INIT bits. initial condition TIM_STALL normal working mode.
TIM_POL
VCXO Polarity This determines polarity external VCXO:
polarity positive (this output
frequency external VCXO increases with increasing voltage from VCXOUT.
polarity negative (this output
frequency external VCXO decreases with increasing voltage from VCXOUT. initial condition TIM_POL negative polarity.
Parameter Registers
4-27
TIM_OFFSET_MSB Start Pulse Phase Offset (MSB) [5:0] start pulse signal with periodicity every FFT-MODE GUARD cycles steady state). TIM_OFFSET bits adjust phase this signal periodic window. initial condition these bits 0x00.
4.4.9 Address Lines 0x0F, 0x10
0x0F 0x10 TIM_CLK_INIT_LSB TIM_CLK_INIT_MSB
TIM_CLK_INIT Timing Initial VCXO Offset [7:0] These registers, TIM_CLK_INIT_LSB TIM_CLK_INIT_MSB, select initial VCXO frequency offset that directed external VCXO. When this register read, value represents actual VCXO offset (for example, content integrator) recovered system. When this register written, this value reinitializes Integrator value. accesses required update these registers; thus, should first stall Integrator setting TIM_STALL then update values. process unfrozen clearing TIM_STALL back initial condition these bits 0x00 (both registers 0x00).
4-28
Register Descriptions
4.4.10 Address Line 0x11
0x11
CPE_ CE_TEMPO- CE_SEL DISABLE_ FFT_DIR DISABLE DISABLE TYPE
FFT_GAIN
CPE_DISABLE Common Phase Error Disable This determines disabled (0). initial condition this normal operation. CE_DISABLE Disable This determines disabled (0). initial condition this normal operation. CE_DISABLE_ETS Timing Shift Disable Channel Equalizer emulates negative echo ease implementation. this value negative echo generation disabled. this negative echo generation enabled. initial condition this Working Mode. CE_TEMPOTYPE Timing Interpolation Type This selects mode operation Channel Equalizer Timing Interpolation. this mode Zero Order Hold; this mode Linear. initial condition this Linear. CE_SELECT MUXOUT Selector When MUXOUT selected output Channel Equalizer value, either Channel Response Equalized Data output. Note that both cases affect receiver functionality. initial condition this Equalized Data. Direction This determines Forward mode (Timing Frequency Domain, Backward mode (Frequency Timing Domain, L64780 normal operational mode, direction Forward. initial condition FFT_DIR Forward.
FFT_DIR
Parameter Registers
4-29
FFT_GAIN
Clipping Rounding [1:0] This register selects clips rounds case overflow. values are:
FFT_GAIN[1:0] Definition Gain Gain Gain Gain
initial condition these bits 0b10, Gain
4.4.11 Address Line 0x12
0x12 CSI_OUT_ FORMAT
CSI_IIRATE
Reserved These bits reserved.
[7:3]
CSI_OUT_FORMAT Softbits Format This allows generation softbit values either two's complement binary offset (0). initial condition this binary offset. CSI_IIRATE Filter Gain [1:0] These bits Gain Channel State Information Unit. values are:
CSI_IIRATE[1:0] Definition Gain Gain Gain Gain
initial condition CSI_IIRATE 0b01, Gain
4-30
Register Descriptions
4.4.12 Address Line 0x13
0x13 HP_OFFSET
HP_OFFSET
Reserved These bits reserved.
[7:6]
Stream Quantizer Gains [5:0] These bits Quantizer Gain Channel State Information Unit High-Priority stream. initial value HP_OFFSET bits 0x36.
4.4.13 Address Line 0x14
0x14 LP_OFFSET
LP_OFFSET
Reserved These bits reserved.
[7:6]
Stream Quantizer Gains [5:0] These bits Quantizer Gain Channel State Information Unit Low-Priority stream. initial value LP_OFFSET 0x36.
Parameter Registers
4-31
Register Address Line 0x15
This register brings data from specific blocks. MUXIN register directly output from goes Clock generator block.
0x15 MUXIN MUXOUT
MUXIN
Reserved These bits reserved.
[7:6]
MUXIN Selector [5:3] These bits select point system driven through MUXIN input pins CLKMUXIN clock sample data coming into L64780. There possibilities:
MUXIN Definition Normal Mode MUXIN inputs Timing DDFS Block MUXIN inputs Block MUXIN inputs Block MUXIN inputs Block MUXIN inputs Block unused unused Muxin Clock
initial value MUXIN 0b000 MUXIN). Table defines different MUXIN signals Muxin clock.
4-32
Register Descriptions
Table
MUXIN Signal Settings MUXIN Clock
Muxin DDFS Muxin Muxin Muxin Muxin Muxin Muxin Clock CLK18 CLK36 CLK36 CLK18 CLK18
MUXIN
MUXOUT
MUXOUT Selector [2:0] These bits select point system monitored through output block. There possibilities:
MUXOUT[2:0] Definition DDFS Output Presented Output Presented Output Presented Output Presented Output Presented Output Presented unused unused
initial value these bits 0b011, Output.
Register Address Line 0x15
4-33
Performance Monitoring Registers Address Line 0x16
These registers contain aggregate statistical monitoring information available block.
0x16
FRAME_ TPS_ SYNC_ SYNC_
AFC_ TIM_ TIM_CLK_ SYNC_ START_ SYNC_OK SYNC_OK SYNC_OK
Reserved These bits reserved.
[7:6]
FRAME_SYNC_OK COFDM Frame Synchronization frame synchronization DTTV demodulator correct, this (ODFM frame locked). this COFDM frame unlocked. initial condition this locked. TPS_SYNC_OK Synchronization code indicates that valid, this (TPS locked). this unlocked. initial condition this locked. AFC_SYNC_OK Synchronization frequency synchronization DTTV demodulator correct, this (AFC locked); otherwise, (unlocked). initial condition this locked. TIM_CLK_SYNC_OK Timing Synchronization sampling frequency synchronization DTTV demodulator correct, this (VCXO locked); otherwise, unlocked. initial condition this locked.
4-34
Register Descriptions
TIM_START_SYNC_OK Start Pulse Synchronization start window synchronization (start pulse locked) DTTV demodulator correct, this location otherwise, start pulse unlocked. initial condition this locked. SYNC_OK Overall Chip Synchronization aspects DTTV demodulator synchronized, this this least unit locked. initial condition this locked.
4.6.1 Address Line 0x17
0x17 CSI_AVERAGE
CSI_AVERAGE Reliability Average [7:0] This register indicates overall reliability carriers making average (integer number) reliability each carrier.
4.6.2 Address Line 0x18
0x18 CSI_PEAK
CSI_PEAK
Reliability Peak [7:0] This register gives integer number carriers when value filtered Channel State Information exceeds given threshold. more than carriers exceed this value, then returned.
Performance Monitoring Registers Address Line 0x16
4-35
Mode Register Address Line 0x19
This register influences DTTV demodulator operates.
CTRL MUX_ CTRL SOFT_ RESET
0x19
ODRAIN WIRES3 _CTRL _CTRL
AUTO_ CHANGE MODE_ _MODE ENABLE
Reserved This reserved.
ODRAIN_CTRL Output Drain Controller This allows 3-Wire pins Open Drain Mode. When this 3-wire output working open drain When this normal mode. initial condition this Output Drain Mode. WIRES3_CTRL ODRAIN_CTRL bits generate OBC_WIRE3_CTRL[2:0] 3-state control signals, specified following table.
OBC_WIRE3_OUT ODRAIN_CTRL WIRE3_CTRL
WIRES3_CTRL 3-Wire 3-State Controller When this 3-Wires pins 3-stated. When this pins normal mode. initial condition this normal mode.
4-36
Register Descriptions
SD_CTRL
Normal Output 3-State Controller When this Normal pins 3-stated. initial condition this normal mode. MUXOUT 3-State Controller When this MUXOUT pins 3-stated. initial condition this normal mode.
MUX_CTRL
SOFT_RESET Chip Soft Reset Setting this enables hard reset L64780 logic (except registers, which keep their values). This allows proper reset chip default configuration (memories also reset Note that Soft Reset must asserted from external microcontroller; pulse. When this soft reset enabled. When this soft reset possible. AUTO_MODE_ENABLE Auto Updating This determines updating controlled external microcontroller, Active registers automatically updated each time value arrive from Broadcaster. this current mode defined register) demodulator updated whenever valid received. this manual configuration register required. initial condition this Manual Update. CHANGE_MODE Updating Register When mode operation been written into register, writing value into this location causes demodulator change mode. Section 4.3, "TPS Registers," page 4-11 more information.
Mode Register Address Line 0x19
4-37
3-Wires Register Address Line 0x1A
3-wires register emulates 3-Wires protocol controls tuner. also used emulate software interface towards tuner.
0x1A WIRES3_IN WIRES3_OUT
WIRES3_IN
Reserved These bits reserved.
[7:6]
3-Wires Input [5:3] These bits collect information coming from 3-Wires off-chip inputs. initial condition WIRES3_IN 0x0.
WIRES3_OUT 3-Wires Output [2:0] These bits directly presented off-chip control Tuner. initial condition WIRES3_OUT 0x0.
4-38
Register Descriptions
Chapter Signal Descriptions
This chapter describes L64780 signals. These signals grouped function. Within each group, signals described alphabetical order. This chapter consists following sections:
Section 5.1, "Overview," page Section 5.2, "Microprocessor Interface," page Section 5.3, "Main Signals," page Section 5.4, "Sigma-Delta Outputs," page Section 5.5, "MUX Signals," page Section 5.6, "3-Wires Signals," page Section 5.7, "JTAG Signals," page Section 5.8, "Test Pins," page Section 5.9, "ASIC Pins," page Section 5.10, "PLL Pins," page Section 5.11, "Tester Pins," page
Overview
Figure provides logic symbol L64780.
L64780 DVB-T OFDM Demodulator
Figure
L64780 Logic Symbol
Microprocessor Interface Main outputs DVOUT DVOUT_LP STARTOUT CLKOUT54 READ DTACKn INTn
Main inputs RESET DIGIN CLK18 AVIN ADCPD ADCGVSS ADCVSS ADCGVDD ADCVDD ADDVREFP ADCVREFN IBIAS JTAG pins TRESETN Tester pins TEST0 TEST1 ASIC pins TIDDTN PROCQ L64780 DVB-T Receiver
Sigma-Delta outputs AFCOUT AGCOUT VCXOUT MUXOUT MUXIN CLKMUXIN Wires XCTR_OUT XCTR_IN
PLLVSS PLLVDD
PLLAGND PLLLP2 pins
PLLTSTCLK PLLTSTSEL
Signal Descriptions
Microprocessor Interface
This section lists describes microprocessor interface signals. Note that parallel interface mode used Logic internal testing intended customer production receivers. serial mode interface used production systems. A[4:0] Address DTTV receiver five-bit address bus, A[4:0], that used with eight-bit data bus, D[7:0], read/write strobe, Read, address strobe, ASn, chip select strobe, CSn, read write internal registers. address lines select internal registers. Serial Mode, used serial clock, A[4:1] must connected ground. Address Strobe Active address strobe input. Latches address A[4:0] falling edge. Serial interface mode, must connected VDD. Chip Select Active chip select strobe input. During read cycle, must access on-chip data registers. During read access, external controller latch data from DTTV receiver with rising edge CSn. During write access, must prior data being valid from external controller DTTV receiver. Serial Interface mode, must connected VDD. Microprocessor Data This bidirectional used input when data written chip, output when chip read. When L64780 being read written data lines 3-stated. Serial Interface Mode, used serial data, D[7:1] used programmable Serial interface. Data Transaction Acknowledge Active output indicating that transaction been completed. When driven, line open-drain 3-stated.
D[7:0]
DTACKn
Microprocessor Interface
INTn
Interrupt DTTV receiver asserts INTn when internal, unmasked interrupt flag set. INTn remains asserted long interrupt condition persists interrupt flag masked. When driven, line opendrain 3-stated. Microprocessor Operation Mode When this signal LOW, operation Parallel Mode; when HIGH, operation Serial Mode.
READ
Read Strobe When HIGH, read operation selected; when LOW, write operation selected. Serial interface mode, READ must connected VDD.
Main Signals
This section lists describes main signals input L64780 output L64705/L64724. ADCGVDD ADCGVSS ADCPD Guard Internal Must connected VDD. Internal Guard Must connected ground.
Power-Down Mode Internal This active HIGH normal mode must connected ground. Analog Internal Must connected VDD.
ADCVDD ADCVREFN ADCVREFP ADCVSS AVIN
Internal Negative Reference Voltage When used, this must connected ground. Internal Positive Reference Voltage When used, this must connected ground. Analog Internal Must connected ground. Analog Input Internal external ADC, this must connected ground.
Signal Descriptions
CLK18
Clock This input clock coming from external VCXO. Clock This clock output used clock L64705 L64724. Digital Inputs Digital inputs normal mode when 10-bit off-chip used. DIGIN0 represents LSB, while DIGIN9 represents MSB. This latched with CLK18 clock. MUXIN mode, DIGIN[9:0] represents LSBs MUXIN bits, with DIGIN[0] mapped MUXIN0, DIGIN9 MUXIN9. on-chip ADC, this must connected ground. Data Valid 3-State When asserted HIGH, this signal validates SD0[3:0] bus. Data Valid 3-State When asserted HIGH, this signal validates SD1[3:0] bus. Input Bias Current Internal When used, this must connected ground. Reset
Hard reset. This active-HIGH. Section Table 6.6,
CLKOUT54
DIGIN[9:0]
DVOUT
DVOUT_LP
IBIAS RESET
"Reset Timing Parameters," page 6-5, minimum maximum assertion time valid reset. SD0[3:0] 3-State first 4-bit output used output high- low-priority streams. 3-State second 4-bit output used output high- low-priority streams. First Soft Decision Mark 3-State When asserted HIGH, this signal marks first soft decision COFDM symbol presented off-chip.
SD1[3:0]
STARTOUT
Main Signals
Sigma-Delta Outputs
This section lists describes output signals L64705/L64724. AGCOUT VCXOUT Sigma Delta output VCXOUT. AFCOUT Output Sigma Delta output AFCOUT. Open Drain Output Sigma-Delta output AGC. Open Drain Open Drain
Signals
This section lists describes input output signals. This interface used Logic internal testing intended customer production receivers. MUXIN[16:0] Muxin Pull-Down This combined with 10-bit ADCIN[9:0] form 27-input MUXIN bus. When used, this must connected ground. Clock MUXIN Clock This provides clock latch MUXIN bus. 3-State
CLKMUXIN
MUXOUT[26:0] Test This 27-input used testing.
Signal Descriptions
3-Wires Signals
This section lists describes 3-wire signals. XCTR_OUT[2:0] Tuner Control Output 3-State These three output pins mainly used control tuner directly controlled through microprocessor. XCTR_IN[2:0] Tuner Control Input These three input pins collect information from tuner. When used, these pins must connected ground.
JTAG Signals
This section lists describes JTAG signals. JTAG Clock Pull-Up When normal operating mode, this must connected VDD. JTAG Test Data Input Pull-UP When normal operating mode, this must connected VDD. JTAG Test Data Output JTAG Test Data output. 3-State
JTAG Test Mode Select Pull-Up When normal operating mode, this must connected VDD. JTAG Reset Pull-Up When normal operating mode, this must connected VDD.
TRESETN
3-Wires Signals
Test Pins
This section lists describes test signals. TEST0 Test Selection This used test selection. When normal operating mode, this must connected ground. Test Selection This used test selection. When normal operating mode, this must connected ground.
TEST1
ASIC Pins
This section lists describes ASIC signals. This active controls output pins. normal operating mode, must connected VDD. TIDDTN This active HIGH. normal operating mode, must connected ground. PROCQ Dedicated output ASIC characterization.
5.10 Pins
This section lists describes signals. PLLVSS PLLVDD PLLAGND PLLLP2 Ground Internal This signal must connected ground. Internal This signal must connected VDD. Analog Ground Internal This signal must connected ground. Voltage Control This signal must connected external filter.
Signal Descriptions
5.11 Tester Pins
This section lists describes internal tester signals. PLLTSTCLK dedicated internal test purposes. normal operating mode, this must connected ground. PLLTSTSEL dedicated internal test purposes. normal operating mode, this must connected ground.
Tester Pins
5-10
Signal Descriptions
Chapter Specifications
This chapter describes electrical specifications, power requirements, characteristics, timing parameters L6780. consists following sections:
Section 6.1, "Electrical Specifications," page Section 6.2, Timing," page Section 6.3, "Signal Specifications," page Section 6.4, "Pinouts," page 6-11 Section 6.5, "Mechanical Drawing," page 6-15
Electrical Specifications
This section specifies electrical requirements L64780. Table lists absolute maximum ratings L64780.
Table
Parameter
Absolute Maximum Ratings
Symbol TSTG Limits1 -0.3 +3.9 -1.0 -1.0 +125 Unit
Supply Voltage LVTTL Input Voltage Compatible Input Voltage Input Current Storage Temperature Range (Plastic)
ratings this table those beyond which permanent device damage likely occur. These values should used limits normal device operation.
L64780 DVB-T OFDM Demodulator
Table lists recommended operating conditions L64780. Table
Parameter Supply Voltage Operating Ambient Temperature Range
Recommended Operating Conditions
Symbol Limits1 +3.0 +3.6 Unit
normal device operation, adhere limits this table. Sustained operation device conditions exceeding these values, even they within absolute maximum rating limits, result permanent device damage impaired device reliability. Device functionality stated limits guaranteed conditions exceed recommended operating conditions.
Table lists characteristics L64780, which produced with LCBG10p process. This 0.35-micron drawn gate length cellbased process. Characteristics table same device that buffer with listed parameters. Table
Symbol
Characteristics
Parameter Supply Voltage Input Voltage Input High Voltage LVTTL Temp Range Compatible Condition -115 -214 Unit
+0.3
Switching Threshold Schmitt Trigger, Positivegoing Threshold Schmitt Trigger, Negativegoing Threshold Schmitt Trigger, Hysteresis
Input Current Inputs with Pulldown Resistors Inputs with Pullup Resistors
Specifications
Table
Symbol
Characteristics (Cont.)
Parameter Output High Voltage Type Type Type Type Type Type B121 =-12 Condition Unit
Output Voltage Type Type Type Type Type Type B122
3-state Output Leakage Current Output Short Circuit Current3, Output Short Circuit, BT4F
Quiescent Supply Current Dynamic Supply Current Input Capacitance4
Input Bidirectional Buffers 5-volt Compatible
COUT
Output Capacitance5
Output Buffer5 5-volt Compatible
Requires output pads. "Interfacing Signals Using G10®-p Technologies" application note series output buffer values. Type output. Output short circuit current other outputs will scale. Excluding package capacitance. Output using single buffer structure (excluding package).
Electrical Specifications
Timing
following subsections provide timing input data interface output data interface.
6.2.1 Input Data Interface
Figure shows waveform timing input data interface. Figure Input Data Timing
CLK18
DIGADCIN
Table lists timings input data interface L64780. Table
Input Data Timing Parameters
Description Input Setup time CLK18 Input Hold time CLK18 Clock pulse width high Clock cycle time 24.9 55.5 Unit
Parameter tpwh tcycle
Specifications
6.2.2 Output Data Interface
Figure shows waveform timing output data interface. Figure Output Data Timing
CLKOUT54 S0[3:0] S1[3:0] STARTOUT DVOUT DVOUT_LP
CLK18
Table lists timing parameters output data interface L64780. Table Output Data Timing Parameters
Description Output delay from CLKOUT54 falling edge Unit
Parameter
6.2.3 Reset Timing
Figure illustrates reset timing L64780. Table lists describes output data timing parameters. Figure
Reset Timing
RESET
Table
Reset Timing Parameters
Description Reset Pulse Width High Wake-Up time (PLL acquisition time) Unit CLK18 cycles
Parameter tRWH
Timing
Signal Specifications
Table provides summary numbers their associated signals, grouped function.
Table
Signal Summary List
5-Volt Compatible
Major I/Os
Name
Description
Buffer Type
Drive (mA)
Type
Active
CLK18 RESET CLKOUT54
Input clock Main Reset Clock output L64705 L64724
LVTTL Input LVTTL Input LVTTL Output
High
Microprocessor Interface 125-9 109-18 A[4:0] D[7:0] READ DTACKn INTn Address Bus1 Data Bus2 LVTTL Input LVTTL Bidir LVTTL Input LVTTL Input LVTTL Input LVTTL Output LVTTL Output LVTTL Input Pull-Up Pull-Up Pull-Up 3-State Open Drain Pull-Down
Read/Write selection Chip Select Address Strobe Data Acknowledge Interrupt Serial/Parallel Mode
Specifications
Table
Signal Summary List (Cont.)
5-Volt Compatible
Main Input 144-142, 139, 138, 135-133, 131,
Name
Description
Buffer Type
Drive (mA)
Type
Active
DIGIN[9:0]
Digital Input normal mode. Testin input otherwise Power Down Guard Supply Analog supply Positive Reference Voltage Negative Reference Voltage Analog Input when using internal Input bias current Analog supply Guard Supply
LVTTL Input
Pull-Down
ADCPD ADCGVSS ADCVSS ADCVREFP
Analog Input Analog Input Analog Input Analog Input
HIGH
ADCVREFN
Analog Input
AVIN
Analog Input
IBIAS ADCVDD ADCGVDD
Analog Input Analog Input Analog Input
Signal Specifications
Table
Signal Summary List (Cont.)
5-Volt Compatible
Name
Description
Buffer Type
Drive (mA)
Type
Active
Main Output 56-8, 51-3, DVOUT DVOUT_LP STARTOUT SD0[3:0] SD1[3:0] Data Valid Data Valid First Soft Decision Mark LVTTL Output LVTTL Output LVTTL Output LVTTL Output LVTTL Output 3-state 3-state 3-state 3-state 3-state
Output VCXOUT AFCOUT AGCOUT VCXOUT Timing Loop Output Tuner Output LVTTL Output LVTTL Output LVTTL Output Open Drain Open Drain Open Drain
Pins MUXIN[16:0] Input Mux. Combined with DIGADCIN form input bits Clock output Generate MUXIN LVTTL Input Pull-Down
CLKMUXIN
LVTTL Output
Specifications
Table
Signal Summary List (Cont.)
5-Volt Compatible
66-69, 71-74, 76-79, 82-85, 87-90, 92-97,
Name
Description
Buffer Type
Drive (mA)
Type
Active
MUXOUT[26:0]
Output Mux: Mainly test issues
LVTTL Output
3-state
Wires Buffer 37-39 XCTR_OUT[2:0] Pins used control Tuner XCTR_IN[2:0] Pins used retrieve informations from Tuner LVTTL Output LVTTL Input 3-state
JTAG: Test Access Port (TAP) TRESETN JTAG Clock LVTTL Input JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output JTAG Reset LVTTL Input LVTTL Input LVTTL Output LVTTL Input Pull-Up Pull-Up Pull-Up 3-state Pull-Up
Test PLL; Scan Mode; Bist Mode TEST0 TEST1 Test Mode Selection Test Mode Selection LVTTL Input LVTTL Input
Signal Specifications
Table
Signal Summary List (Cont.)
5-Volt Compatible
Name
Description
Buffer Type
Drive (mA)
Type
Active
ASIC Specific Pins Control pins bidirectional 3-state outputs Control power down PLL, oscillator disable pull up/pull down Dedicated output Procmon LVTTL Input
TIDDTN
LVTTL Input
High
PROCQ
LVTTL Output
Internal Pins PLLVSS PLLVDD PLLLP2 ground power control voltage pin, connection external loop filter analog ground Analog Input Analog Input Analog Bidir
PLLAGND
Analog Output
Tester Pins PLLTSTCLK PLLTSTSEL open loop replace output feedback loop LVTTL Input LVTTL Input High
also used also used
Serial Clock. Therefore Schmitt Buffer. Serial Data. Therefore, Bidirectional Schmitt Buffer.
6-10
Specifications
Pinouts
following subsections provide numerical alphabetic listing L64780 pins, well pinout package drawing showing location pins.
6.4.1 List
Table numerically lists L64780 pins their associated signals.
Pinouts
6-11
Table
Signal XCTR_IN0 XCTR_IN1 XCTR_IN2 MUXIN0 MUXIN1 VSS2 MUXIN2 MUXIN3 MUXIN4 MUXIN5 MUXIN6 MUXIN7 MUXIN8 MUXIN9 MUXIN10 MUXIN11 VSS2 RESET MUXIN12 MUXIN13 MUXIN14 MUXIN15 MUXIN16 TRESETN VSS2 CLKOUT54 DTACKn INTn XCTR_OUT0 XCTR_OUT1 XCTR_OUT2 VCXOUT
List Number
Signal VSS2 TEST0 TEST1 CLKMUXIN SD1_3 SD1_2 SD1_1 SD1_0 SD0_3 SD0_2 SD0_1 SD0_0 STARTOUT DVOUT_LP DVOUT MUXOUT26 MUXOUT25 MUXOUT24 MUXOUT23 MUXOUT22 MUXOUT21 MUXOUT20 MUXOUT19 MUXOUT18 MUXOUT17 MUXOUT16 MUXOUT15 MUXOUT14 MUXOUT13 MUXOUT12 MUXOUT11 Signal MUXOUT10 MUXOUT9 MUXOUT8 MUXOUT7 MUXOUT6 MUXOUT5 MUXOUT4 MUXOUT3 MUXOUT2 MUXOUT1 MUXOUT0 CLK18 PLLVDD PLLAGND PLLLP2 PLLVSS VSS2 READ VSS2 AFCOUT VSS2 Signal DIGIN_0 DIGIN_1 DIGIN_2 DIGIN_3 DIGIN_4 DIGIN_5 DIGIN_6 TIDDTN VSS2 DIGIN_7 DIGIN_8 DIGIN_9 PLLTSTCLK PLLTSTSEL PROCQ AGCOUT ADCPD ADCGVSS ADCVSS ADCVREFP ADCVREFN AVIN IBIAS ADCVDD ADCGVDD
Table alphabetically lists L64780 signals their associated pins.
6-12
Specifications
Table
Signal ADCGVDD ADCGVSS ADCPD ADCVDD ADCVREFN ADCVREFP ADCVSS AFCOUT AGCOUT AVIN CLK18 CLKMUXIN CLKOUT54 DIGIN0 DIGIN1 DIGIN2 DIGIN3 DIGIN4 DIGIN5 DIGIN6 DIGIN7 DIGIN8 DIGIN9 DTACKn DVOUT DVOUT_LP IBIAS
List Name
Signal INTn MUXIN0 MUXIN1 MUXIN2 MUXIN3 MUXIN4 MUXIN5 MUXIN6 MUXIN7 MUXIN8 MUXIN9 MUXIN10 MUXIN11 MUXIN12 MUXIN13 MUXIN14 MUXIN15 MUXIN16 MUXOUT0 MUXOUT1 MUXOUT2 MUXOUT3 MUXOUT4 MUXOUT5 MUXOUT6 MUXOUT7 MUXOUT8 MUXOUT9 MUXOUT10 MUXOUT11 MUXOUT12 MUXOUT13 MUXOUT14 MUXOUT15 MUXOUT16 MUXOUT17 MUXOUT18 MUXOUT19 MUXOUT20 MUXOUT21 MUXOUT22 MUXOUT23 Signal MUXOUT24 MUXOUT25 MUXOUT26 PLLAGND PLLLP2 PLLTSTCLK PLLTSTSEL PLLVDD PLLVSS PROCQ READ RESET SD0_0 SD0_1 SD0_2 SD0_3 SD1_2 SD1_0 SD1_1 SD1_3 STARTOUT TEST0 TEST1 TIDDTN TRESETN VCXOUT Signal VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 XCTR_IN0 XCTR_IN1 XCTR_IN2 XCTR_OUT0 XCTR_OUT1 XCTR_OUT2
Pinouts
6-13
6.4.2 Layout
Figure illustrates L64780 package layout. Figure Package Layout
ADCGVDD ADCVDD IBIAS AVIN ADCVREFN ADCVREFP ADCVSS ADCGVSS ADCPD AGCOUT PROCQ PLLTSTSEL PLLTSTCLK DIGIN_9 DIGIN_8 DIGIN_7 VSS2 TIDDTN DIGIN_6 DIGIN_5 DIGIN_4 DIGIN_3 DIGIN_2 DIGIN_1 DIGIN_0 VSS2 AFCOUT XCTR_IN_0 XCTR_IN_1 XCTR_IN_2 MUXIN_0 MUXIN_1 VSS2 MUXIN_2 MUXIN_3 MUXIN_4 MUXIN_5 MUXIN_6 MUXIN_7 MUXIN_8 MUXIN_9 MUXIN_10 MUXIN_11 VSS2 RESET MUXIN_12 MUXIN_13 MUXIN_14 MUXIN_15 MUXIN_16 TRESETN VSS2 CLKOUT54 DTACKn INTn XCTR_OUT_0 XCTR_OUT_1 XCTR_OUT_2
L64780
(PQFPt Package, View) (Body Size (Tip dimension: 31.2 (External Lead Pitch: 0.65 Package Code: UM55)
VSS2 READ VSS2 PLLVSS PLLLP2 PLLAGND PLLVDD CLK18 MUXOUT_0 MUXOUT_1 MUXOUT_2 MUXOUT_3 MUXOUT_4 MUXOUT_5 MUXOUT_6 MUXOUT_7 MUXOUT_8 MUXOUT_9 MUXOUT_10 MUXOUT_11 MUXOUT_12 MUXOUT_13
6-14
VCXOUT VSS2 TEST0 TEST1 CLKMUXIN SD1_3 SD1_2 SD1_1 SD1_0 SD0_3 SD0_2 SD0_1 SD0_0 STARTOUT DVOUT_LP DVOUT MUXOUT_26 MUXOUT_25 MUXOUT_24 MUXOUT_23 MUXOUT_22 MUXOUT_21 MUXOUT_20 MUXOUT_19 MUXOUT_18 MUXOUT_17 MUXOUT_16 MUXOUT_15 MUXOUT_14
Specifications
Mechanical Drawing
Figure shows mechanical drawing L64780 160-pin PQFP. Figure PQFP Mechanical Drawing: Side Views
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code UM55.
Mechanical Drawing
6-15
Figure
PQFP Mechanical Drawing: Detail
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code UM55.
6-16
Specifications
Appendix Programming L64780 Using Serial Interface
This appendix discusses program L64780 internal registers data tables using serial protocol. This appendix intended primarily system programmers developing software drivers using serial bus. consists following sections:
Section A.1, "Serial Protocol Overview," page Section A.2, "Programming Slave Address Using Serial Bus," page
Serial Protocol Overview
multimaster Serial interface one-bit lines: (Serial Clock), (Serial Data). These connected (see Figure A.1). External pullup resistors hold logic when operation. Serial protocol documentation detailed explanation electrical characteristics. D[7:1] used serial slave address. When using serial bus, D[7:1] must hardwired appropriate device slave address. Select serial mode L64780 asserting P_S. Features serial protocol include:
one-bit lines: Serial Data. serial clock (maximum frequency kHz). have external pull-up resistors (the normally HIGH). Master always generates clock, cycle start/stop conditions.
Figure provides overview illustration serial bus. Figure Serial Overview
5.0V 5.0V
Serial Compliant Device
Serial Compliant Device
Programming L64780 Using Serial Interface
Programming Slave Address Using Serial
general call (Master issues start condition followed eight zeroes) used address every device serial bus. device that requires information supplied through this general call must acknowledge cycle. Figure General Call Address
General Call Addr. Start Condition Acknowledge Cycle Don't Care
A.2.1 Write Cycle Using Serial
following steps describe write cycle using serial bus. cycle started Master issuing start condition. 7-bit slave address transmitted. reset transmitted, indicating write cycle. addressed Slave acknowledges reception slave address driving cycle. Master sends 8-bit address. addressed Slave acknowledges reception address driving cycle. Master sends 8-bit data. addressed Slave acknowledges reception data driving cycle. Master terminates cycle issuing stop condition.
Programming Slave Address Using Serial
A.2.2 Read Cycle Using Serial
cycle started with start condition. 7-bit slave address transmitted. reset transmitted, indicating write cycle. addressed Slave acknowledges reception slave address driving cycle. Master sends 8-bit address. addressed Slave acknowledges reception address driving cycle. Master issues another start condition. 7-bit slave address transmitted. transmitted, indicating read cycle. addressed Slave acknowledges reception slave address driving cycle. slave starts transmitting data. Master must acknowledge receipt data driving during cycle. Master terminates cycle issuing stop condition.
Programming L64780 Using Serial Interface
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