HM51W4265C/CL Series Preliminary Rev. Dec. 1994 Hitachi HM51
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ADE-203-309
HM51W4265C/CL Series
Preliminary Rev. Dec. 1994
Hitachi HM51W4265C/CL CMOS dynamic organized 262,144 words bits. HM51W4265C/CL realized higher density, higher performance various functions employing CMOS process technology some CMOS circuit design technologies. HM51W4265C/CL offers Extended Data (EDO) Page Mode high speed access mode. Multiplexed address input permits HM51W4265C/CL packaged standard 400-mil 44-pin plastic TSOP Internal refresh timer enables self refresh operation. 2CAS byte control Battery back operation (L-version) Self-refresh operation
Ordering Information
Type HM51W4265CTT-7 HM51W4265CTT-8 HM51W4265CLTT-7 HM51W4265CLTT-8 Access time Package 44-pin plastic TSOP (TTP-44/40DB)
Features
Single (±0.3 High speed Access time ns/80 (max) power dissipation Active mode mW/342 (max) Standby mode (max) 0.36 (max) (L-version) page mode capability refresh cycles (L-version) variations refresh RAS-only refresh CAS-before-RAS refresh
Note:
This document contains information product under development. Hitachi reserves right change discontinue product without notice.
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