HM514265C Series Preliminary Rev. Dec. 1994 Hitachi HM514265

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HM514265C Series Preliminary Rev. Dec. 1994 Hitachi HM514265

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ADE-203-309
HM514265C Series
Preliminary Rev. Dec. 1994
Hitachi HM514265C CMOS dynamic organized 262,144 words bits. HM514265C realized higher density, higher performance various functions employing CMOS process technology some CMOS circuit design technologies. HM514265C offers Extended Data (EDO) Page Mode high speed access mode. Multiplexed address input permits HM514265C packaged standard 400-mil 40-pin plastic SOJ.
Ordering Information
Type HM514265CJ-6 HM514265CJ-7 HM514265CJ-8 Access time Package 400-mil 40-pin plastic (CP-40DA)
Features
Single (±10%) High speed Access time ns/70 ns/80 (max) power dissipation Active mode mW/770 mW/688 (max) Standby mode (max) page mode capability refresh cycles variations refresh RAS-only refresh CAS-before-RAS refresh 2CAS byte control
Note:
specifications this device subject change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications.
HM514265C Series
Arrangement
HM514265C Series I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 LCAS UCAS
(Top view)
Description
name Function Address input address Column address Refresh address Data-in/data-out address strobe Column address strobe Read/write enable Output enable Power Ground
I/O0 I/O15 UCAS, LCAS
I/O5
I/O7 I/O6 I/O4
I/O5 Buffer I/O4 Buffer I/O6 Buffer I/O7 Buffer
Decoder
Block Diagram
Decoder
Memory Array Memory Array Column Decoder Memory Array Memory Array Column Decoder
Decoder I/O3 I/O3 Buffer
Selector
Selector
Column Decoder Address
I/O2 I/O2 Buffer
Memory Array
Decoder Decoder
Decoder Decoder
Memory Array
I/O1 I/O1 Buffer
Selector
Selector
Column Decoder
A0,A1,A2,A3
Decoder
Memory Array
I/O0 I/O0 Buffer
Memory Array
Peripheral Circuit
Peripheral Circuit
I/O15 I/O15 Buffer
Peripheral Circuit
Decoder
Decoder
Memory Array
I/O14 Buffer
Memory Array
I/O14
Address A4,A5
Selector
Selector
Column Decoder
Column Decoder Memory Array
I/O13 I/O13 Buffer
Memory Array A6,A7,A8
Decoder Decoder
Decoder Decoder
Memory Array Selector
Memory Array Selector Column Decoder
I/O12 I/O12 Buffer Decoder
Column Decoder
Decoder
Memory Array
Memory Array
I/O11 Buffer I/O9 Buffer I/O8 Buffer
I/O10 I/O10 Buffer
I/O11
I/O8
I/O9
LCAS
UCAS
HM514265C Series
HM514265C Series
Operation Mode
HM514265C series following operation modes. Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle
LCAS UCAS Valid Open Undefined Valid Open page mode read cycle page mode early write cycle page mode delayed write cycle page mode read-modify-write cycle Read cycle (Output disabled)
Self refresh cycle page mode read cycle page mode early write cycle page mode delayed write cycle page mode read- modify-write cycle
Inputs Output Open Valid Valid Open Undefined Valid Open Open Operation Standby Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle Self refresh cycle
Notes: High(inactive) Low(active) tWCS Early write cycle tWCS Delayed write cycle Mode determined function UCAS LCAS. (Mode earliest UCAS LCAS active edge reset latest UCAS LCAS inactive edge.) However write OPERATION output control done independently each UCAS, LCAS. LCAS UCAS then CAS-before-RAS refresh cycle selected.
HM514265C Series
Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Symbol Iout Topr Tstg Value -1.0 +7.0 -1.0 +7.0 +125 Unit
Recommended Operating Conditions +70°C)
Parameter Supply voltage Symbol Input high voltage Input voltage Note: -1.0 Unit Note
voltage referred VSS.
HM514265C Series
Characteristics +70°C, 10%,
HM514265C Parameter Operating current Standby current Symbol ICC1 ICC2 Notes RAS, cycling interface RAS, Dout High-Z CMOS interface RAS, Dout High-Z
Unit Test conditions
RAS-only refresh current Standby current CAS-before-RAS refresh current page mode current Input leakage current
ICC3 ICC5 ICC6 ICC4
VIH, Dout enable tHPC Vout Dout disable High Iout Iout
Output leakage current Output high voltage Output voltage
Notes: depends output load condition when device selected. specified output open condition. Address changed twice less while VIL. Address changed once less within page cycle.
Capacitance 25°C, 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI/O Unit Notes
Notes: Capacitance measured with Boonton Meter effective capacitance measuring method. disable Dout.
HM514265C Series
Characteristics +70°C, 10%, (HM514265C-7/8) *14, *15, +70°C, (HM514265C-6) *14, *15,
Test Conditions Input rise fall times Input level Input timing reference levels Output timing reference levels Output load gate (Including scope jig)
Read, Write, Read-Modify-Write Refresh Cycles (Common parameters)
HM514265C Parameter Random read write cycle time precharge time pulse width pulse width address setup time address hold time Column address setup time Column address hold time delay time column address delay time hold time hold time precharge time delay time delay time from setup time from Transition time (rise fall) Refresh period Symbol tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tREF Unit Notes
10000 10000
10000 10000
10000 10000
HM514265C Series
Read Cycle
HM514265C Parameter Access time from Access time from Access time from address Access time from Read command setup time Read command hold time Read command hold time Column address lead time Column address lead time Output buffer turn-off time Output buffer turn-off time delay time delay time delay time pulse width Turn-off Turn-off Output data hold time Output data hold time from Read command hold time from Read command hold time from Read command hold time from column address Symbol tRAC tCAC tOAC tRCS tRCH tRRH tRAL tCAL tOFF1 tOFF2 tCDD tRDD tWDD tOEP tOFR tWEZ tOHR tRCHR tRCHC tRCHA Unit Notes
HM514265C Series
Write Cycle
HM514265C Parameter Write command setup time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tRWL tCWL Unit Notes
Read-Modify-Write Cycle
HM514265C Parameter Read-modify-write cycle time delay time delay time Column address delay time hold time from Symbol tRWC tRWD tCWD tAWD tOEH Unit Notes
Refresh Cycle
HM514265C Parameter setup time (CBR refresh cycle) hold time (CBR refresh cycle) precharge hold time precharge time normal mode Symbol tCSR tCHR tRPC tCPN Unit Notes
HM514265C Series
Page Mode Cycle
HM514265C Parameter page mode cycle time page mode pulse width Access time from precharge hold time from precharge Output data hold time from hold time referred setup time Read command hold time from precharge Symbol tHPC tRASC tACP tRHCP tDOH tCOL tCOP tRCHP Unit Notes
page mode precharge time
100000
100000
100000
Page Mode Read-Modify-Write Cycle
HM514265C Parameter page mode read-modify-write cycle time page mode read-modify-write cycle precharge delay time Symbol tHPCM tCPW Unit Notes
Notes: measurements assume Assumes that tRCD tRCD (max) tRAD tRAD (max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assumes that tRCD tRCD (max) tRAD tRAD (max). Assumes that tRCD tRCD (max) tRAD tRAD (max). tOFF1 (max), tOFF2 (max), tOFR (max) tWEZ (max) define time which output achieves open circuit condition referred output voltage levels. (min) (max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only, tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only, tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA.
HM514265C Series
tWCS, tRWD, tCWD tAWD restrictive operating parameters. They included data sheet electrical characteristics only: tWCS tWCS (min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD tRWD (min), tCWD tCWD (min), tAWD tAWD (min) tCPW tCPW (min), cycle readmodify-write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referred leading edge early write cycle leading edge delayed write read-modify-write cycle. tRASC defines pulse width mode cycles. Access time determined longest among tAA, tCAC tACP. initial pause required after power followed minimum eight initialization cycles (RAS-only refresh cycle CAS-before-RAS refresh cycle). internal refresh counter used, minimum eight CAS-before-RAS refresh cycles required. delayed write read-modify-write cycles, must disable output buffer prior applying data device. Either tRCH tRRH must satisfied read cycle. When both LCAS UCAS same time, 16-bits data written into device. LCAS UCAS cannot staggered within same write/read cycles. pins shall supplied with same voltages. tASC, tCAH, tRCS, tRCH, tWCS, tWCH, tCSR tRPC determined earlier falling edge UCAS LCAS. tCRP, tCHR, tACP tCPW determined later rising edge UCAS LCAS. tCWL, tDH, tCHS should satisfied both UCAS LCAS. tCPN determined time that both UCAS LCAS high. When output buffers enabled once, sustain impedance state until valid data obtained. When output buffer turned within very short time, generally causes large VCC/VSS line noise, which causes degrade min/VIL level. tHPC (min) achieved during series page mode early write cycles page mode read cycles. both write read operation mixed page mode cycle (EDO page mode cycle (1), (2)), minimum value cycle tHPC (tCAS 2tT) becomes greater than specified tHPC (min) value. tOFF1 tOFR determined later rising edge CAS. tDOH defines time which output level satisfies output timing reference levels. Measured with test conditions. tRAS (min) tRWD (min) tRWL (min) read-modify-write cycle. tCAS (min) tCWD (min) tCWL (min) read-modify-write cycle. tCSH (min) achieved when tRCD tCSH (min) tCAS (min).
HM514265C Series
Notes concerning 2CAS control
Each UCAS/LCAS should satisfy timing specifications individually. Different operation mode upper/lower byte allowed; such following.
Delayed write
UCAS
Early write
LCAS
Closely separated upper/lower byte control allowed. However when condition (tCP satisfied, fast page mode performed.
UCAS
LCAS
HM514265C Series
Timing Waveforms*30
Read Cycle
LCAS UCAS
Address
Column RCHR RCHC RCHA OFF1 Dout High-Z OFF2
Dout
Notes:
(min) (max), (min) (max))
Invalid Dout
HM514265C Series
Early Write Cycle
LCAS UCAS
tASC
Address
Column
Dout
High-Z*
(min)
HM514265C Series
Delayed Write Cycle
LCAS UCAS Column
Address
Dout
Invalid Dout*
High-Z
OFF2
Invalid Dout comes out, when level.
HM514265C Series
Read-Modify-Write Cycle
tRWC tRAS
tRCD tCAS tCRP
LCAS UCAS tASR tRAH tRAD tASC tCAH
Address
tRCS
Column
tCWD tAWD
tCWL tRWL
tRWD
tCAC tRAC tDZC High-Z
Dout tOAC
Dout tOFF2 tDZO tODD tOEP tOEH
HM514265C Series
Page Mode Read Cycle (tHPC minimum cycle operation)
RASC RHCP
LCAS UCAS
Address tASC
Column
Column
Column RCHA
RCHP RCHC
High-Z Dout
OFF1 Dout OFF2
Dout
Dout
HM514265C Series
Page Mode Read Cycle (High-Z control
RASC RCHR RCHC RCHA tASR tRAH tCAH tDZC Column tCAL High-Z
Column
tCAS RCHP RHCP tCAS RCHC
Column
LCAS UCAS
Column
tASC
Address
tRDD tCDD
tDZO
tCOL
tCOP tODD
tOAC tCAC tRAC
Dout
tACP tCAC tWEZ tOFF2 tOAC Dout
tACP tACP tCAC tDOH Dout
Dout
tOFF2 tCAC tOAC Dout
tOFR tOHR tOFF2 tOFF1
Dout
HM514265C Series
Page Mode Early Write Cycle (tHPC minimum cycle operation)
RASC
LCAS UCAS
Address
Column
Column
Column
Dout
High-Z
HM514265C Series
Page Mode Read-Modify-Write Cycle
RASC
tRCD LCAS UCAS Column
Address
Column
Column
Dout
High-Z
HM514265C Series
Page Mode Delayed Write Cycle
RASC LCAS UCAS HPCM
Address
Column
Column
Column
High-Z tOAC Dout Dout OFF2 Dout OFF2 High-Z Dout OFF2
High-Z
tOEP
HM514265C Series
Page Mode Cycle
RASC tCPW tAWD tASR tRAH tCAH Column High-Z tODD tASC Column tASC tCAS tCAS RCHP RCHC RCHA Column tRDD tCDD
LCAS UCAS
Address
Column tCAL
tWDD
tOAC tCAC
tDZO tCAC tOFF2
tACP tCAC tOAC
tOFR tWEZ tOFF2 tOFF1 Dout
Dout
Dout
Dout
HM514265C Series
Page Mode Cycle
RASC RCHR tCPW tASR tRAH tCAH Column tODD tDZO tODD Column tCAS tCWL tASC tCAS RCHP RCHC RCHA Column tRDD tCDD
LCAS UCAS
Address
Column tCAL High-Z
tDZO tWDD
tOAC tCAC tRAC tOFF2
tACP tCAC
tACP tOFF2 tCAC tOAC
tOFR tWEZ tOFF2 tOFF1 Dout
Dout
Dout
Dout
HM514265C Series
CAS-Before-RAS Refresh Cycle
LCAS UCAS
Address OFF1
Dout High-Z
HM514265C Series
RAS-Only Refresh Cycle
tRAC
tCRP LCAS UCAS tRPC tCRP
tASR
tRAH
Address
Dout
High-Z
Refresh address (AX0 AX8)

HM514265C Series Preliminary Rev. Dec. 1994 Hitachi HM514265

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