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µPD78011BY, 78012BY, 78013Y, 78014Y 8-BIT SINGLE-CHIP MICROCOMPUT


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INTEGRATED CIRCUIT
µPD78011BY, 78012BY, 78013Y, 78014Y
8-BIT SINGLE-CHIP MICROCOMPUTERS
DESCRIPTION
µPD78011BY, µPD78012BY, µPD78013Y µPD78014Y, µPD78014Y sub-series products 78K/0 series, support control function. These computers incorporate various peripherals such serial interface (including mode), 8-bit resolution converter, timer, interrupt control, etc. one-time PROM EPROM product, µPD78P014Y, capable operating same power supply voltage range mask product available. Development tools also provided. Functions described detail following User's Manual, which should read when carrying design work.
µPD78014, 78014Y Series User's Manual IEU-1343
FEATURES
Serial Interface channels (compatible with mode channel) ROM/RAM capacitance package
Item Product Name Program Memory (ROM) bytes bytes bytes bytes 1024 bytes Data Memory Internal High-Speed bytes Buffer bytes 64-pin Plastic Shrink (750 mil) 64-pin Plastic
Package
µPD78011BY µPD78012BY µPD78013Y µPD78014Y
External memory expansion space: bytes Instruction execution time varied from high-speed (0.4 ultra-low-speed (122 ports: (N-ch open-drain included) 8-bit resolution converter channels Timer: channels Operating voltage range
APPLICATION
Telephone, VCR, audio, camera, home appliances, etc.
information this document subject change without notice. Document IC-3405B IC-8573B) Date Published December 1994 Printed Japan Major changes this revision indicated stars margins.
1994
µPD78011BY, 78012BY, 78013Y, 78014Y
ORDERING INFORMATION
Ordering Code Package 64-pin plastic shrink (750 mil) 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic shrink (750 mil) shrink (750 mil) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard
64-pin plastic 64-pin plastic shrink (750 mil) 64-pin plastic
Remark means code number.
Please refer "Quality grade Semiconductor Devices" (Document number IEI-1209) published Corporation know specification quality grade devices recommended applications.
78K/0 SERIES DEVELOPMENT
Product volume production
µPD78064Y Sub-series µPD78064 Sub-series
µPD78078Y Sub-series µPD78078 Sub-series
100-pin package 8-bit timer/event counter added External expansion function added
Products under development sub-series comprise products with compatibility.
100-pin package controller/driver, UART added 16-bit timer/event counter functions enhanced
µPD78054Y Sub-series µPD78054 Sub-series µPD78014Y Sub-series µPD78014 Sub-series
64-pin package converter 16-bit timer/event counter, with automatic transmission/reception function added Multiply/divide instruction added 80-pin package UART, converter, real-time output port added 16-bit timer/event counter functions enhanced
µPD78098 Sub-series
80-pin package IEBuscontroller added
µPD78044A Sub-series PD78044 Sub-series
80-pin package Automatic transmission/reception function added 6-bit up/down counter added controller/driver function enhanced
µPD78024 Sub-series µPD78002Y Sub-series µPD78002 Sub-series
64-pin package 64-pin package converter 16-bit timer/event counter controller/driver Multiply/divide instructions added
µPD78011BY, 78012BY, 78013Y, 78014Y
OVERVIEW FUNCTION
Product Name Item Internal memory Internal highspeed Buffer
µPD78011BY
bytes bytes
µPD78012BY
bytes
µPD78013Y
bytes 1024 bytes bytes
µPD78014Y
bytes
Memory space General registers Instruction cycle
bytes bits registers bits registers banks) On-chip instruction execution time cycle modification function
When main system µs/0.8 µs/1.6 µs/3.2 µs/6.4 10.0 operation) clock selected When subsystem 32.768 operation) clock selected Instruction 16-bit operation Multiplication/division bits bits,16 bits bits) manipulation (set, reset, test, boolean operation) correction, etc.
ports
Total CMOS input CMOS N-channel open-drain withstand voltage)
converter
8-bit resolution channels Operable over wide power supply voltage range: 3-wire/SBI/2-wire/I2C mode selectable: channel 3-wire mode (on-chip max. bytes automatic data transmit/receive function): channel 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Serial interface
Timer
Timer output Clock output Buzzer output Vectored interrupts Maskable interrupts Non-maskable interrupt Software interrupt
(14-bit output 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 main system clock 10.0 operation), 32.768 subsystem clock 32.768 operation) kHz, kHz, main system clock 10.0 operation) Internal External Internal Internal
Test input
Internal External +85°C 64-pin plastic shrink (750 mil) 64-pin plastic
Operating voltage range Operating temperature range Package
µPD78011BY, 78012BY, 78013Y, 78014Y
CONTENTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTION LIST
PORT PINS NON-PORT PINS CIRCUITS RECOMMENDED CONNECTION UNUSED PINS
MEMORY SPACE CHARACTERISTIC PERIPHERAL HARDWARE FUNCTIONS
PORTS CLOCK GENERATOR TIMER/EVENT COUNTER CLOCK OUTPUT CONTROL CIRCUIT BUZZER OUTPUT CONTROL CIRCUIT CONVERTER SERIAL INTERFACES
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS TEST FUNCTIONS
EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTION RESET FUNCTION
INSTRUCTION ELECTRICAL SPECIFICATIONS.32 CHARACTERISTIC CURVE (REFERENCE VALUES) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTATION
µPD78011BY, 78012BY, 78013Y, 78014Y
CONFIGURATION (TOP VIEW)
64-Pin Plastic Shrink (750 mil)
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13
P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P57/A15 P56/A14
µPD78011BYCW- µPD78013YCW-
µPD78012BYCW- µPD78014YCW-
Cautions
Always connect (Internally Connected) VSS. Always connect AVDD VDD. Always connect AVSS VSS.
µPD78011BY, 78012BY, 78013Y, 78014Y
64-Pin Plastic
P26/SO0/SB1/SDA1
P25/SI0/SB0/SDA0
P27/SCK0/SCL
P24/BUSY
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
P12/ANI2
P21/SO1
P23/STB
P20/SI1
P11/ANI1 P10/ANI0 P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
µPD78011BYGC- -AB8 µPD78012BYGC- -AB8 µPD78013YGC- -AB8 µPD78014YGC- -AB8
P52/A10
P53/A11
P54/A12
P55/A13
P47/AD7
P56/A14
P57/A15
Cautions
Always connect (Internally Connected) VSS. Always connect AVDD VDD. Always connect AVSS VSS.
P65/WR
P50/A8
P51/A9
P64/RD
µPD78011BY, 78012BY, 78013Y, 78014Y
INTP0 INTP3 SB0, SI0, SO0, SCK0, SCK1 SDA0, SDA1 BUSY Port Port Port Port Port WAIT ASTB XT1, RESET ANI0 ANI7 AVDD AVSS AVREF Address/Data Address Read Strobe Write Strobe Wait Address Strobe Crystal (Main System Clock) Crystal (Subsystem Clock) Reset
Port Port Interrupt From Peripherals Timer Input Timer Output Serial Serial Input Serial Output Serial Clock Serial Clock Serial Data Programmable Clock
Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Ground Internally Connected
Buzzer Clock Strobe Busy
TO0/P30 TI0/INTP0/P00 16-bit TIMER/ EVENT COUNTER PROGRAM COUNTER PORT P01-P03 TO1/P31 TI1/P33 8-bit TIMER/ EVENT COUNTER GENERAL REGISTER DECODE CONTROL PORT DATA MEMORY PORT WATCHDOG TIMER P30-P37 P20-P27 PORT P10-P17 TO2/P32 TI2/P34 8-bit TIMER/ EVENT COUNTER PROGRAM MEMORY PORT WATCH TIMER P40-P47 SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 PORT SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SERIAL INTERFACE CLOCK OUTPUT CONTROL CLOCK GENERATOR MAIN P60-P67 SERIAL INTERFACE PORT P50-P57 BUZZER OUTPUT CLOCK DIVIDER STAND CONTROL AD0/P40AD7/P47 A8/P50A15/P57 BUZ/P36 PCL/P35 P04/XT1 EXTERNAL ACCESS RD/P64 WR/P65 WAIT/P66 ASTB/P67 INTERRUPT CONTROL RESET ANI0/P10 -ANI7/P17 AVDD AVSS AVREF INTP0/P00 -INTP3/P03 CONVERTER
BLOCK DIAGRAM
µPD78011BY, 78012BY, 78013Y, 78014Y
Remark Internal capacity varies depending product.
µPD78011BY, 78012BY, 78013Y, 78014Y
FUNCTION LIST
PORT PINS (1/2)
Name P04Note
Input Input/ output Port 5-bit port
Function Input only Input/output specified bit-wise. When used input port, pull-up resistor used software. Input only Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software.Note Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software.
Reset Input Input
DualFunction INTP0/TI0 INTP1 INTP2 INTP3
Input Input/ output
Input Input
ANI0 ANI7
Input/ output
Input
SCK1 BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
Input/ output
Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resisztor used software.
Input
Input/ output
Port 8-bit input/output port. Input/output specified 8-bit unit. When used input port, pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Input
Notes When using P04/XT1 pins input port, on-chip feedback resistor subsystem clock oscillator with (FRC) processor control register When using P10/ANI0 P17/ANI7 pins converter analog input, pull-up resistor automatically unused.
µPD78011BY, 78012BY, 78013Y, 78014Y
PORT PINS (2/2)
Name
Input/ output
Function Port 8-bit input/output port. driven directly. Input/output specified bit-wise. When used input port, pull-up resistor used software.
Reset Input
DualFunction
Input/ output
Port 8-bit input/output port. Input/output specified bit-wise.
N-ch open-drain input/output port. On-chip pull-up resistor specified mask option. driven directly. When used input port, pull-up resistor used software.
Input
WAIT ASTB
Caution Non-use pull-up resistor (specified mask option) increases low-level input leakage current -200 (MAX.) either following cases: When low-level input performed using external device expansion function. 3-clock cycle when port (P6)/port mode register (PM6) read instruction execution performed.
µPD78011BY, 78012BY, 78013Y, 78014Y
NON-PORT PINS (1/2)
Name INTP0 INTP1 INTP2 INTP3 SDA0 SDA1 SCK0 SCK1 BUSY
Input
Function External interrupt input which effective edge (rising edge, falling edge, both rising edge falling edge) specified.
Reset Input
DualFunction P00/TI0
Falling edge detection external interrupt input Input Serial interface serial data input Input
P25/SB0/SDA0
Output
Serial interface serial data output
Input
P26/SB1/SDA1
Input /output
Serial interface serial data input/output
Input
P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0SB0 P26/SO0/SB1
Input /output
Serial interface serial clock input/output
Input
P27/SCL P27/SCK0
Output Input Input
Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input External count clock input 16-bit timer (TM0) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2)
Input Input Input
P00/INTP0
Output
16-bit timer (TM0) output (shared 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) output
Input
Output Output Input /output Output Output
Clock output (for main system clock, subsystem clock trimming) Buzzer output Low-order address/data external memory expansion
Input Input Input
WAIT ASTB
High-order address external memory expansion External memory read operation strobe signal output External memory write operation strobe signal output
Input Input
Input Output
Wait insertion external memory access Strobe output which latches address information output ports access external memory
Input Input
µPD78011BY, 78012BY, 78013Y, 78014Y
NON-PORT PINS (2/2)
Name ANI0 ANI7 AVREF AVDD AVSS RESET
Input Input Input Input Input Positive power supply Ground potential converter analog input
Function
Reset Input
DualFunction
converter reference voltage input converter analog power supply. Connected VDD. converter ground potential. Connected VSS. System reset input Main system clock oscillation crystal connection
Subsystem clock oscillation crystal connection
Input
Internal connection. Connected directly VSS.
µPD78011BY, 78012BY, 78013Y, 78014Y
CIRCUITS RECOMMENDED CONNECTION UNUSED PINS input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Fig. 3-1.
Table Input/Output Circuit Type Each (1/2)
Name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 P17/ANI7
Input/output Circuit Type Input
Recommended Connection when Used Connected Input Output Connected Leave open.
Input/output
Input Input/output
Connected Input Output Input Output Connected Leave open. Connected Leave open.
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7
10-A
Input/output
Input/output
Input Output
Connected Leave open.
Input/output
Input Output Input Output
Connected Leave open. Connected Leave open.
P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB
13-B
Input/output
µPD78011BY, 78012BY, 78013Y, 78014Y
Table Input/Output Circuit Type Each (2/2)
Name RESET AVREF AVDD AVSS
Input/output Circuit Type
Input
Recommended Connection when Used
Leave open. Connected
Connected Connected Connected directly
µPD78011BY, 78012BY, 78013Y, 78014Y
Fig. Input/Output Circuits
Type Type 10-A
pullup enable data P-ch
P-ch
open drain output disable N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type
Type pullup enable data
P-ch P-ch
pullup enable data P-ch
P-ch
output disable N-ch
output disable Comparator
N-ch P-ch
N-ch (Threshold Voltage) input enable Type Mask Option pullup enable data P-ch output disable N-ch P-ch P-ch data output disable N-ch input enable Type 13-B
Middle-High Voltage Input Buffer Type Type feedback cut-off P-ch data P-ch output disable N-ch P-ch
pullup enable
µPD78011BY, 78012BY, 78013Y, 78014Y
MEMORY SPACE
Memory µPD78011BY, µPD78012BY, µPD78013Y µPD78014Y shown Table 4-1. Fig. Memory
FFFFH Special Function Registers (SFR) Bits FF00H FEFFH FEE0H FEDFH General Registers Bits
Internal High-Speed RAMNote
mmmmH mmmmH-1 Prohibited Data Memory Space FAE0H FADFH FAC0H FABFH FA80H FA7FH External Memory Buffer Bits
nnnnH Program Area 1000H 0FFFH CALLF Entry Area Prohibited 0800H 07FFH Program Area
Program Memory Space nnnnH-1 nnnnH
0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area
Internal
ROMNote
0000H
0000H
Remark
Shaded area indicates internal memory.
Note Internal ROM/internal high-speed capacitance depends product (See table below).
Product Name Internal Address nnnnH 1FFFH 3FFFH 5FFFH 7FFFH FB00H Internal High-Speed Initial Address mmmmH FD00H
µPD78011BY µPD78012BY µPD78013Y µPD78014Y
µPD78011BY, 78012BY, 78013Y, 78014Y
CHARACTERISTICS PERIPHERAL HARDWARE FUNCTIONS
PORTS
following ports set: CMOS input (P00, P04) CMOS input/output (P01 P03, port port 5,P64 P67) N-ch open-drain input/output withstand voltage)(P60 P63) Total
Table Functions Ports
Name Port Name P00, Port Port Port Port Input only port port. specifiable bit-wise. When used input port, internal pull-up resistor used software. port. specifiable bit-wise. When used input port, internal pull-up resistor used software. port. specifiable bit-wise. When used input port, internal pull-up resistor used software. port. specifiable bit-wise. When used input port, internal pull-up resistor used software. port. specifiable 8-bit unit. When used input port, internal pull-up resistor used software. Test input flag (KRIF) falling edge detection. port. specifiable bit-wise. When used input port, internal pull-up resistor used software. driven directly. N-ch open-drain port. specifiable bit-wise. Pull-up resistor incorporated mask option. driven directly. port. specifiable bit-wise. When used input port, internal pull-up resistor used software. Function
Port
Port
Caution Non-use pull-up resistor (specified mask option) increases low-level input leakage current -200 (MAX.) either following cases: When low-level input performed using external device expansion function used. 3-clock cycle when port6 (P6)/port mode register (PM6) read instruction execution performed.
µPD78011BY, 78012BY, 78013Y, 78014Y
CLOCK GENERATOR
Clock generator includes main system clock generator subsystem clock generator also change instruction execution time. µs/0.8 µs/1.6 µs/3.2 µs/6.4 (Main system clock: operation 10.0 MHz) (Subsystem clock: operation 32.768 kHz) Fig. Clock Generator Block Diagram
XT1/P04
Subsystem Clock Oscillator
Watch Timer, Clock Output Function Prescaler
Main System Clock Oscillator
Prescaler Selector Standby Control Circuit Wait Control Circuit INTP0 Sampling Clock Clock Peripheral Hardware
STOP
Clock (fCPU)
TIMER/EVENT COUNTER channels timer/event counters incorporated. 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Table Type Function Timer/Event Counter
16-bit Timer/ Event Counter Type Interval timer External event counter Function Timer output output Pulse width measurement Square-wave output Interrupt request channel channel output output input output 8-bit Timer/ Event Counter channels channels outputs outputs
Watch Timer channel
Watchdog Timer channel
µPD78011BY, 78012BY, 78013Y, 78014Y
Fig. 16-bit Timer/Event Counter Block Diagram
Internal
16-Bit Compare Register (CR00) Pulse Output Control Circuit Output Control Circuit
INTTM0
Match fX/2 fX/2 fX/2
TO0/P30
Selector
16-Bit Timer Register (TM0) Clear Selector INTP0 16-Bit Capture Register (CR01)
TI0/INTP0/P00
Edge Detector
Internal
Fig. 8-Bit Timer/Event Counter Block Diagram
Internal
INTTM1 8-Bit Compere Register (CR10)
8-Bit Compare Register (CR20) Selector Match Output Control Circuit TO2/P32 INTTM2
Match
fX/2 -fX/2
fX/2
Selector
8-Bit Timer Register 1(TM1) Clear Selector
TI1/P33
8-Bit Timer Register (TM2) Clear
fX/22-fX/210 fX/212 TI2/P34 Output Control Circuit Internal TO1/P31 Selector Selector
µPD78011BY, 78012BY, 78013Y, 78014Y
Fig. Watch Timer Block Diagram
fX/28
Selec-
Selector Prescaler
5-Bit Conter
Selector INTWT
Selector
INTTM3
Fig. Watchdog Timer Block Diagram
Prescaler INTWDT Maskable Interrupt Request
Selector
8-Bit Counter
Control Circuit
RESET INTWDT Non-Maskable Interrupt Request
µPD78011BY, 78012BY, 78013Y, 78014Y
CLOCK OUTPUT CONTROL CIRCUIT
following frequency clocks output clock output: 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 (Main system clock operation 10.0 MHz) 32.768 (Subsystem clock operation 32.768 kHz)
Fig. Clock Output Control Circuit Block Diagram
fX/2
fX/24 fX/25 fX/26 fX/27 fX/28 Selector Synchronization Circuit Output Control Circuit PCL/P35
BUZZER OUTPUT CONTROL CIRCUIT following frequency clocks output buzzer output: kHz/4.9 kHz/9.8 (Main system clock operation 10.0 MHz)
Figure Buzzer Output Control Circuit Block Diagram
fX/210 fX/211 fX/2
Selector
Output Control Circuit
BUZ/P36
µPD78011BY, 78012BY, 78013Y, 78014Y
CONVERTER 8-bit resolution 8-channel converter incorporated. following start methods conversion operation. Hardware start Software start
Fig. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive Approximation Register (SAR) AVSS Selector Selector Sample Hold Circuit Voltage Comparator AVDD AVREF
INTP3/P03
Falling Edge Detector
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
µPD78011BY, 78012BY, 78013Y, 78014Y
SERIAL INTERFACES channels clocked serial interface incorporated. Serial interface channel Serial interface channel Table Type Function Serial Interface
Function wires serial mode wires serial mode with automatic transmission/ reception function (Serial interface) mode wires serial mode (Inter mode (MSB start) (MSB start) (MSB start) Serial interface channel (MSB/LSB start switchable) Serial interface channel (MSB/LSB start switchable) (MSB/LSB start switchable)
Fig. Serial Interface Channel Block Diagram
Internal
SDA0/SI0/ SB0/P25 SDA1/SO0/ SB1/P26
Selector
Serial Shift Register (SIO0)
Output Latch
Selector
Release/Command/ Acknowledge Detector Interrupt Request Signal Generator
Busy/Acknowledge Output Circuit
SCL/SCK0/P27
Serial Counter
INTCSI0
fX/2 -fX/2
Serial Clock Control Circuit
Selector
µPD78011BY, 78012BY, 78013Y, 78014Y
Fig. 5-10 Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit Address Pointer (ADTP)
Buffer
SI1/P20
Serial Shift Register (SIO1)
SO1/P21
STB/P23
BUSY/P24
Handshake Control Circuit
SCK1/P22
Serial Counter
Interrupt Request Signal Generator
INTCSI1
fX/22-fX/29 Serial Clock Control Circuit Selector
µPD78011BY, 78012BY, 78013Y, 78014Y
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS following types interrupt functions set: Non-maskable interrupt Maskable interrupt Software interrupt Table Interrupt Sources
Interrupt Source Name INTWDT Trigger Watchdog timer overflow (non-maskable interrupt selection) Watchdog timer overflow (interval timer selection) input edge detection External 0006H 0008H 000AH 000CH serial interface channel transfer serial interface channel transfer Reference time interval signal from watch timer 16-bit timer/event counter match signal generation 8-bit timer/event counter match signal generation 8-bit timer/event counter match signal generation converter conversion instruction execution Internal Internal 000EH 0010H 0012H Basic Configuration TypeNote
Interrupt Type Nonmaskable Maskable
Default PriorityNote
Internal/ External Internal
Vector Table Address 0004H
INTWDT
INTP0 INTP1 INTP2 INTP3 INTCSI0 INTCSI1 INTTM3
INTTM0
0014H
INTTM1
0016H
INTTM2
0018H
Software
INTAD
001AH 003EH
Notes Default priority priority when multiple maskable interrupts generated same time. first, last. Basic configuration types correspond following pages.
µPD78011BY, 78012BY, 78013Y, 78014Y
Fig. Interrupt Function Basic Configuration (1/2) Internal non-maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External maskable interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Samplig Clock
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78011BY, 78012BY, 78013Y, 78014Y
Fig. Interrupt Function Basic Configuration (2/2) External maskable interrupt (except INTP0)
Internal
External Interrupt Mode Register (INTM0)
Interrupt Request
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Remarks
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
µPD78011BY, 78012BY, 78013Y, 78014Y
TEST FUNCTIONS
test functions shown Table 6-2. Table Test Source list
Test Source Name INTWT INTPT4 Watch timer overflow Port falling edge detection Trigger Internal External
Internal/External
Fig. Test Function Basic Configuration
Internal
Test Input Signal
Standby Release Signal
Remarks
Test Input Flag Test Mask Flag
µPD78011BY, 78012BY, 78013Y, 78014Y
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion functions connect external devices areas other than internal ROM, SFR. External devices connection uses ports
STANDBY FUNCTION
There following standby functions reduce system power cunsumption. HALT mode this mode, operation clock stopped. average consumption current STOP mode reduced intermittent operation combination with normal operation. this mode, main system clock oscillator stopped. power consumption greatly reduced subsystem clock only stopping whole main system, clock operations. Figure Standby Function
CSS=1 Main System Clock Operation CSS=0 Interrupt Request STOP Instruction Interrupt Request HALT Mode Clock supply stopped oscillation retained HALT Instruction Interrupt Request HALT modeNote Clock supply stopped oscillation retained HALT Instruction Subsystem Clock OperationNote
STOP Mode main system clock oscillation stopped
Note Stopping main system clock enables consumption current reduced. operated subsystem clock, main system clock should stopped set. STOP instruction available. Caution operated subsystem clock when main system clock stopped, reswitching main system should performed after stable oscillation time been obtained program.
RESET FUNCTION
There following reset methods. External reset RESET Internal reset watchdog time runaway time detection
µPD78011BY, 78012BY, 78013Y, 78014Y
INSTRUCTION
8-Bit Instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand #byte First Operand ADDC SUBC ADDC SUBC ADDC SUBC ADDC SUBC ADDC SUBC ADDC SUBC rNote saddr !addr16 [DE] [HL]
byte] ADDC SUBC
$addr16
None
RORC ROLC
saddr ADDC SUBC
DBNZ
DBNZ
!addr16
PUSH
[DE] [HL]
ROR4 ROL4
byte]
MULU DIVUW
Note
Except
µPD78011BY, 78012BY, 78013Y, 78014Y
16-Bit Instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand ADDW SUBW CMPW MOVW MOVW MOVW MOVW* MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW #word rpNote sfrp saddrp !addr16 None
sfrp saddrp !addrp16 Note
INCW, DECW PUSH,
Only case
Manipulation Instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Second Operand First Operand A.bit MOV1 BTCLR BTCLR BTCLR BTCLR BTCLR SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 A.bit sfr.bit saddr.bit PSW.bit [HL].bit $addr16 None
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
Call Instruction/Branch Instructions CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Second Operand First Operand Basic Instruction Compound Instruction !addr16 CALL, !addr11 CALLF [addr5] CALLT $addr16 BNC, BTCLR, DBNZ
Other Instructions ADJBA, ADJBS, BRK, RET, RET1, RETB, SEL, NOP, HALT, STOP
µPD78011BY, 78012BY, 78013Y, 78014Y
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage
SYMBOL AVDD AVREF AVSS
TEST CONDITIONS
RATING -0.3 -0.3 -0.3 -0.3
UNIT
Input voltage
P04, P17, P27, P37, P47, P57, P67, Open-drain
-0.3 -0.3 -0.3
Output voltage Analog input voltage Output current high
P17, P27, total P03, P47, P57, total Analog input
AVSS -0.3 AVREF
Output current
Peak value Effective value Peak value P47, total Effective value IOLNote P03, P56, P57, total Peak value Effective value Peak value Effective value Peak value Effective value
P03, total P17, P27, total Operating temperature Storage temperature
Topt
Tstg
+150
Note Effective value should calculated follows: [Effective value] [Peak value] duty Caution Absolute maximum ratings rated values beyond which some physical damages caused product; parameters table above exceeds rated value even moment, quality product deteriorate. sure product within rated values.
µPD78011BY, 78012BY, 78013Y, 78014Y
CAPACITANCE
PARAMETER Input capacitance capacitance SYMBOL TEST CONDITIONS Unmeasured pins returned P03, P17, P27, P37, P47, P57, toP63 MIN. TYP. MAX. UNIT
Unmeasured pins returned
Remark Unless otherwise specified, characteristics dual-function pins equivalent those port pins. MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS
RESONATOR Ceramic resonator RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fX)Note1 Oscillation stabilization timeNote2 Oscillator frequency (fX)Note1 Oscillation stabilization timeNote2 External clock
TEST CONDITIONS Oscillator voltage range After reaches oscillator voltage range MIN.
MIN.
TYP.
MAX.
UNIT
Crystal resonator
8.38
10.0
input frequency (fX)Note1 input high/low level width (tXH tXL)
µPD74HCU04
42.5
Notes Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wiring area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same ground ground pattern which high current flows.
fetch signal from oscillator. main system clock oscillation circuit operated subsystem clock when main system clock stopped, reswitching main system clock should performed after stable oscillation time been obtained program.
µPD78011BY, 78012BY, 78013Y, 78014Y
SUBSYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS
RESONATOR Crystal resonator
RECOMMENDED CIRCUIT
PARAMETER Oscillator frequency (fXT)Note Oscillation stabilization timeNote input frequency (fXT)Note input high/low level width (tXTH tXTL)
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
32.768
External clock
Notes Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reached minimum oscillation voltage range. Cautions When using subsystem clock oscillator, wiring area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same
ground ground pattern which high current flows. fetch signal from oscillator. subsystem clock oscillation circuit designed amplification circuit provide consumption current, causing misoperation noise more frequently than main system clock. Special care should therefore taken wiring method when subsystem clock used.
µPD78011BY, 78012BY, 78013Y, 78014Y
RECOMMENDED OSCILATION CIRCUIT CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR case µPD78011BY µPD78012BY
MANUFACTURER
PRODUCT NAME
FREQUENCY (MHz)
RECOMMENDED CIRCUIT CONSTANT (pF) (pF) Built-in Built-in Built-in Built-in
OSCILLATOR VOLTAGE RANGE MIN. MAX.
Murata Mfg. Co., Ltd.
CSB1000J
1.00 1.01 1.25 1.26 1.79 1.80 2.44
Built-in
2.45 4.18 Built-in 4.19 6.00 Built-in 6.01 10.0 Built-in 4.19
Kyocera
KBR-4. 19MWS KBR-4. 19MKS KBR-4. 19MSA 4.19 PBRC4. KBR-10. KBR-1000F 1.00 KBR-1000Y 10.0
µPD78011BY, 78012BY, 78013Y, 78014Y
case µPD78013Y µPD78014Y
MANUFACTURER
PRODUCT NAME
FREQUENCY (MHz)
RECOMMENDED CIRCUIT CONSTANT (pF) (pF) Built-in Built-in Built-in Built-in
OSCILLATOR VOLTAGE RANGE MIN. MAX.
Murata Mfg. Co., Ltd.
CSB1000J
1.00 1.01 1.25 1.26 1.79 1.80 2.44
Built-in
2.45 4.18 Built-in 4.19 6.00 Built-in 6.01 10.0 Built-in
Remarks
indicates frequency.
SUBSYSTEM CLOCK: CRYSTAL RESONATOR case µPD78011BY µPD78012BY
RECOMMENDED MANUFACTURER PRODUCT NAME FREQUENCY (kHz) (pF) Daishinku DT-38 (1TA632E00, load capacitance (pF) CIRCUIT CONSTANT
OSCILLATOR VOLTAGE RANGE MIN. MAX.
32.768
case µPD78013Y µPD78014Y
RECOMMENDED MANUFACTURER PRODUCT NAME FREQUENCY (kHz) (pF) Daishinku DT-38 (1TA632E00, load capacitance (pF) CIRCUIT CONSTANT
OSCILLATOR VOLTAGE RANGE MIN. MAX.
32.768
µPD78011BY, 78012BY, 78013Y, 78014Y
CHARACTERISTICS
PARAMETER Input voltage high
SYMBOL VIH1 VIH2 VIH3 VIH4 VIH5
TEST CONDITIONS P17, P21, P23, P32, P37, P47, P57, P03, P20, P22, P27, P33, P34, RESET XT1/P04, Open-drain
MIN. VDD-0.5 VDD-0.5 VDD-0.3
TYP.
MAX.
UNIT
Input voltage
VIL1 VIL2 VIL3 VIL4 VIL5
P17, P21, P23, P32, P37, P47, P57, P03, P20, P22, P27, P33, P34, RESET XT1/P04,
Output voltage high Output voltage
VOH1
-100 P57, open-drain pulled-up
VDD-1.0 VDD-0.5
VOL1
toP03, P17, P27, P37, P47, SB0, SB1, SCK0
VOL2 VOL3 Input leakage current high
ILIH1
toP03, P17, P27, P37, P47, P57, P67, RESET P17, P37, P57, RESET
ILIH2 ILIH3 Input leakage current
XT1/P04, toP03, P27, P47, P67,
ILIL1 ILIL2 ILIL3
XT1/P04,
Note
-200 -3Note
Other than above
Notes When memory expansion mode used memory expansion mode register (MM) with on-chip pull-up resistor mask option. Non-use pull-up resistor (specified mask option) increases low-level input leakage current -200 (MAX.) either following cases: When low-level input performed using external device expansion function used. 3-clock cycle when port (P6)/port mode register (PM6) read instruction execution performed.
µPD78011BY, 78012BY, 78013Y, 78014Y
CHARACTERISTICS
PARAMETER Output leakage current high Output leakage current Mask option pull-up resister Software pull-up resister SYMBOL ILOH1 ILOL VOUT VOUT P03, P17, P27, P37, P47, P57, 8.38 MHz, Crystal oscillation operating mode 8.38 MHz, Crystal oscillation HALT mode 32,768 kHz, Crystal oscilation operating mode 32,768 kHz, Crystal oscilation HALT mode STOP mode When feedback resister connected STOP mode When feedback resister disconnected Note Note 0.05 TEST CONDITIONS MIN. TYP. MAX. 22.5 1650 UNIT
Power supply currentNote
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Notes Operating high-speed mode (when processor clock control register 00H) Operating low-speed mode (when processor clock control register 04H) AVREF current port current excluded. Remark Unless otherwise specified, characteristics dual-function pins equivalent those port pins.
µPD78011BY, 78012BY, 78013Y, 78014Y
CHARACTERISTICS Basic Operation
PARAMETER Cycle time (Min. instruction execution time) SYMBOL TEST CONDITIONS Operating main system clock MIN. 0.96 tTIH tTIL tINTH tINTL INTP0 INTP1 INTP3 RESET level width tRST 8/fsamNote TYP. MAX. UNIT
Operating subsystem clock input frequency input high/ low-level width Interrupt input high/low-level width
Note combination with bits (SCS0) (SCS1) sampling clock select register, selection fsam possible between fx/2N+1, fx/64 fx/128 (when case µPD78011BY, µPD78012BY, µPD78013Y µPD78014Y
main system clock operation)
case µPD78P014Y
main system clock operation)
Guaranteed Operation Range Guaranteed Operation Range
Cycle Time
Supply Voltage
Supply Voltage
Caution guaranteed operation range differs between µPD78011BY, µPD78012BY, µPD78013Y, µPD78014Y µPD78P014Y. Remarks indicates indicates
µPD78011BY, 78012BY, 78013Y, 78014Y
Read/Write Operation
PARAMETER ASTB high-level width Address setup time Address hold time Data input time from address
SYMBOL TEST CONDITIONS tASTH tADS tADH tADD1 tADD2 Load resistor
MIN. 0.5tCY 0.5tCY-30
MAX.
UNIT
(2+2n)tCY-50 (3+2n)tCY-100 (1+2n)tCY-25 (2.5+2n)tCY-100 (1.5+2n)tCY-20 (2.5+2n)tCY-20 0.5tCY 1.5tCY 0.5tCY (0.5+2n)tCY (2.5+2n)tCY 0.5tCY-30 1.5tCY tCY-10 tCY+40 (2+2n)tCY
Data input time from
tRDD1 tRDD2
Read data hold time low-level width
tRDH tRDL1 tRDL2
WAIT input time from
tRDWT1 tRDWT2
WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from delay time from write data
tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST
tRDADH tRDWD tWDWR
0.5tCY-120 0.5tCY-170
tCY+50
0.5tCY 0.5tCY tCY+60 tCY+100 2.5tCY+80 2.5tCY+80
Address hold time from tWRADH
delay time from WAIT delay time from WAIT
tWTRD tWTWR
0.5tCY 0.5tCY
Remarks
TCY/4 indicates number waits. indicates load capacitance P40/AD0 P47/AD7, P50/A8 P57/A15, P64/RD, P65/WR, P66/WAIT, P67/ASTB pins)
µPD78011BY, 78012BY, 78013Y, 78014Y
Serial Interface 3-wire serial mode (SCK. Internal clock output)
PARAMETER cycle time
SYMBOL tKCY1
TEST CONDITIONS
MIN. 3200
TYP.
MAX.
UNIT
high/low-level width setup time SCK) hold time (from SCK) output delay time from
tKH1 tKL1 tSIK1 tKSI1
tKCY1/2-50 tKCY1/2-150 1000
tKSO1
pFNote
Note load capacitance output line.
µPD78011BY, 78012BY, 78013Y, 78014Y
3-wire serial mode (SCK.External clock input) case serial interface channel
PARAMETER cycle time tKCY2 3200 high/low-level width setup time SCK) hold time (from SCK) output delay time from tKH2 tKL2 tSIK2 tKSI2 tKSO2 pFNote 1000 1600 SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
rise/fall time
When external device expansion function used When external When 16-bit timer device expan- output function sion function used used When 16-bit timer output function used
1000
Note load capacitance output line.
case serial interface channel
PARAMETER cycle time tKCY2 3200 high/low-level width setup time SCK) hold time (from SCK) output delay time from tKH2 tKL2 tSIK2 tKSI2 tKSO2 pFNote 1000 rise/fall time When external device expansion function used When external device expansion function used 1600 SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
1000
Note load capacitance output line.
µPD78011BY, 78012BY, 78013Y, 78014Y
mode (SCK.Internal clock output)
PARAMETER cycle time
SYMBOL tKCY3
TEST CONDITIONS
MIN. 3200
TYP.
MAX.
UNIT
high/low-level width SB0, setup time SCK) SB0, hold time (from SCK) SB0, output delay time from SB0, from from SB0, SB0, high-level width SB0, low-level width
tKH3 tKL3 tSIK3
tKCY3/2-50 tKCY3/2-150
tKSI3 tKSO3 tKSB tSBK tSBH pFNote
tKCY3/2
tKCY3 tKCY3 tKCY3
1000
tSBL
tKCY3
Note load resistors load capacitance output line.
µPD78011BY, 78012BY, 78013Y, 78014Y
mode (SCK.External clock input)
PARAMETER cycle time
SYMBOL tKCY4
TEST CONDITIONS
MIN. 3200
TYP.
MAX.
UNIT
high/low-level width SB0, setup time SCK) SB0, hold time (from SCK) SB0, output delay time from SB0, from from SB0, SB0, high-level width SB0, low-level width
tKH4 tKL4 tSIK4
1600
tKSI4
tKCY4/2
tKSO4 pFNote
tKCY4 tKCY4 tKCY4
1000
tKSB tSBK tSBH
tSBL When external device expansion function used When external When 16-bit timer device expan- output function sion function used used When 16-bit timer output function used
tKCY4
rise/fall time
1000
Note load resistors load capacitance output line.
µPD78011BY, 78012BY, 78013Y, 78014Y
2-wire serial mode (SCK. Internal clock output)
PARAMETER cycle time tKCY5 3800 high-level width low-level width SB0, setup time SCK) SB0, hold time (from SCK) SB0, output delay time from tKSI5 tKSO5 pFNote 1000 tKH5 tKL5 tSIK5 pFNote tKCY5/2-50 tKCY5/2-50 SYMBOL TEST CONDITIONS MIN. 1600 TYP. MAX. UNIT
Note load resistors load capacitance SCK0, output line. 2-wire serial mode (SCK. External clock input)
PARAMETER cycle time
SYMBOL tKCY6
TEST CONDITIONS
MIN. 1600 3800
TYP.
MAX.
UNIT
high-level width low-level width SB0, setup time SCK) SB0, hold time (from SCK) SB0, output delay time from rise/fall time
tKH6 tKL6 tSIK6
tKSI6 tKSO6 pFNote
tKCY6/2 1000
When external device expansion function used When external When 16-bit timer device expan- output function sion function used used When 16-bit timer output function used
1000
Note load resistors load capacitance SCK0, output line.
µPD78011BY, 78012BY, 78013Y, 78014Y
interface
PARAMETER input clock frequency Pre-transmission release time Start condition hold time level time high level time Start condition setup time Data hold time Data setup time tSUDAT SYMBOL fSCL TEST CONDITIONS MIN. TYP. MAX. UNIT
tBUF
1000
tHDSTA tLOW tHIGH tSUSTA tHDDAT Data held fall time.
SDA0, SDA1, signal rise time
tR4Note
pFNote When external device expansion function used When external When 16-bit timer device expanoutput function sion function used used When 16-bit timer output function used pFNote
tR4Note
SDA0, SDA1, signal fall time Stop condition setup time
1000
tSUSTO
Notes When internal clock output used serial clock When external clock input used serial clock indicate load resistance load capacitance SCL, SDA0 SDA1 output line, respectively.
µPD78011BY, 78012BY, 78013Y, 78014Y
3-wire serial mode with automatic transmit/receive function (SCK.Internal clock output)
PARAMETER cycle time
SYMBOL tKCY7
TEST CONDITIONS
MIN. 3200
TYP.
MAX.
UNIT
high/low-level width setup time SCK) hold time (from SCK) output delay time from
tKH7 tKL7
tKCY7/2-50 tKCY7/2-150
tSIK7
tKSI7
tKSO7 pFNote
1000
from Strobe signal highlevel width Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) from busy inactive
tSBD
tKCY7
tSBW
tKCY7-30
tKCY7+30
tBYS
tBYH
tSPS
2tKCY7
Note load capacitance output line.
µPD78011BY, 78012BY, 78013Y, 78014Y
3-wire serial mode with automatic transmit/receive function (SCK.External clock input)
PARAMETER cycle time
SYMBOL tKCY8
TEST CONDITIONS
MIN. 3200
TYP.
MAX.
UNIT
high/low-level width setup time SCK) hold time (from SCK) output delay time from
tKH8 tKL8
1600
tSIK8
tKSI8
tKSO8 pFNote
1000
rise/fall time
When external device expansion function used When external device expansion function used
1000
Note load capacitance output line. Converter AVDD AVSS
PARAMETER Resolution Overall errorNote Conversion time Sampling time Analog input voltage Reference voltage AVREF current tCONV tSAMP VIAN AVREF AIREF 19.1 24/fx AVSS AVREF AVDD SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Note Quantization error (±1/2 LSB) included. This expressed proportion full-scale value.
µPD78011BY, 78012BY, 78013Y, 78014Y
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
0.4V
Input
1/fXT
tXTL
tXTH 0.4V
Input
Timing
1/fTI
tTIL TI0-TI2
tTIH
µPD78011BY, 78012BY, 78013Y, 78014Y
Read/Write Operation External fetch wait):
A8-A15 Low-Order Address AD0-AD7 tADS tASTH ASTB
High-Order Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8-A15 Low-Order Address AD0-AD7 tADS tASTH ASTB
High-Order Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
µPD78011BY, 78012BY, 78013Y, 78014Y
External data access wait):
A8-A15 Low-Order Address AD0-AD7 tADS tADH tASTH ASTB
High-Order Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD tRDL2
tRDWD
tWDS tWDWR
tWDH tWRADH
tASTWR tWRL1
External data access (wait insertion):
A8-A15 Low-Order Address AD0-AD7 tADS tADH tASTH ASTB
High-Order Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD tRDL2 tRDWD tASTWR tWRL1 tWRADH tWDS tWDWR tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
µPD78011BY, 78012BY, 78013Y, 78014Y
Serial Transfer Timing 3-wire serial mode:
tKCY
tKL1,
tKH1,
tSIK1, tKSI1,
tKSO1,
Input Data
Output Data
mode (bus release signal transfer):
tKCY3, tKL3, tKH3,
tKSB tSBL tSBH tSBK tSIK3, tKSI3,
SB0, tKSO3,
mode (command signal transfer):
tKCY3, tKL3, tKH3,
tKSB tSBK tSIK3, tKSI3,
SB0, tKSO3,
µPD78011BY, 78012BY, 78013Y, 78014Y
2-wire serial mode:
tKCY5, tKL5, tSIK5, tKSO5, SB0, tKSI5, tKH5,
mode:
tLOW SDA0, SDA1 tBUF tHDSTA tSUSTO tHIGH tHDDAT tSUDAT tSUSTA tHDSTA
3-wire serial mode with automatic transmit/receive function:
tSIK7, tKSO7,
tKSI7, tKH7,
tSBD tKL7, tKCY7, tSBW
µPD78011BY, 78012BY, 78013Y, 78014Y
3-wire serial mode with automatic transmit/receive function (busy processing):
Note
Note tBYS
10+n Note tBYH tSPS
BUSY (Active high)
Note This signal driven here; shown such indicate timing.
µPD78011BY, 78012BY, 78013Y, 78014Y
DATA MEMORY STOP MODE SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
PARAMETER Data retention supply voltage Data retention supply current
SYMBOL VDDDR
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
IDDDR
VDDDR Subsystem clock stop feed-back resister disconnected Release RESET
Release signal time Oscillation stabilization wait time
tSREL
218/fx
Note
tWAIT Release interrupt
Note combination with bits (OSTS0 OSTS2) oscillation stabilization time select register, selection 213/fx 215/fx 218/fx possible. Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retension Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retension Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78011BY, 78012BY, 78013Y, 78014Y
Interrupt Input Timing
tINTL INTP0-INTP2 tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
µPD78011BY, 78012BY, 78013Y, 78014Y
CHARACTERISTIC CURVE (REFERENCE VALUES)
(Main System Clock 8.38 MHz)
(Ta=25°C) 10.0 PCC=00H
PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT Oscillation, Oscillation)
Supply Current [mA]
PCC=B0H 0.05 HALT Stop, Oscillation) STOP Stop, Oscillation)
0.01
0.005
=8.38 =32.768
0.001
Supply Voltage
µPD78011BY, 78012BY, 78013Y, 78014Y
(Main System Clock 4.19 MHz)
(Ta=25°C) 10.0
PCC=00H
PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT Oscillation, Oscillation)
Supply Current [mA]
PCC=B0H 0.05 HALT Stop, Oscillation) STOP Stop, Oscillation)
0.01
0.005
=4.19 =32.768
0.001
Supply Voltage
µPD78011BY, 78012BY, 78013Y, 78014Y
(VDD 25°C)
PCC=00H
Supply Current [mA]
PCC=01H
PCC=02H PCC=03H
PCC=04H HALT Oscillation)
Clock Oscillator Frequency [MHz]
(VDD 25°C)
PCC=00H
Supply Current [mA]
PCC=01H
Clock Oscillator Frequency [MHz]
PCC=02H PCC=03H PCC=04H HALT Oscillation)
µPD78011BY, 78012BY, 78013Y, 78014Y
(Port P67)
25°C)
Output Current [mA]
Output Voltage
(Port
25°C)
Output Current [mA]
Output Voltage
µPD78011BY, 78012BY, 78013Y, 78014Y
(P60 P63)
25°C)
Output Current [mA]
Output Voltage
(Port P67)
Output Current High [mA]
Output Voltage High
µPD78011BY, 78012BY, 78013Y, 78014Y
PACKAGE DRAWINGS
PACKAGE DRAWINGS MASS-PRODUCED PRODUCTS (1/2)
PLASTIC SHRINK (750 mil)
NOTE Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15°
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15° P64C-70-750A,C-1
Caution different from corresponding mass-produced products shape material. PACKAGE DRAWINGS (1/2)
µPD78011BY, 78012BY, 78013Y, 78014Y
PACKAGE DRAWINGS MASS-PRODUCED PRODUCTS (2/2)
PLASTIC
detail lead
P64GC-80-AB8-3 ITEM MILLIMETERS 17.6 14.0 14.0 17.6 0.35 0.10 0.15 (T.P.) 0.15+0.10 -0.05 0.10 2.55 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
Note
Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Caution different from corresponding mass-produced products shape material. PACKAGE DRAWINGS (2/2)."
5°±5°
µPD78011BY, 78012BY, 78013Y, 78014Y
PACKAGE DRAWINGS (1/2) 64PIN CERAMIC SHRINK (SEAM WELD) (750 mil)
0~15°
P64D-70-750A1 Notes Each lead centerline located within 0.25 (0.01 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel. ITEM MILLIMETERS 58.16 MAX. 1.521 MAX. 1.778 (T.P.) 0.46 0.05 MIN. 1.02 MIN. 3.14 5.08 MAX. 19.05 (T.P.) 18.8 0.25 0.05 0.25 INCHES 2.290 MAX. 0.060 MAX. 0.070 (T.P.) 0.018 0.002 0.031 MIN. 0.138 0.012 0.040 MIN. 0.124 0.200 MAX. 0.750 (T.P.) 0.740 0.010 -0.003 0.01
+0.002
µPD78011BY, 78012BY, 78013Y, 78014Y
PACKAGE DRAWINGS (2/2)
CERAMIC (FOR
(Bottom View)
X64B-80A-1 INCHES 0.866 0.016 0.551 0.551 0.866 0.016 0.039 0.039 0.013 0.031 (T.P.) 0.157+0.007 -0.006 0.01 0.119 MAX. 0.022 0.039 0.047
ITEM
MILLIMETERS 22.0 14.0 14.0 22.0 0.32 (T.P.) 0.15 0.25 MAX. 0.55
µPD78011BY, 78012BY, 78013Y, 78014Y
RECOMMENDED SOLDERING CONDITIONS
µPD78011BY, µPD78012BY, µPD78013Y, µPD78014Y should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document "Semiconductor Device Mount Manual" (IE-1207). soldering methods conditions other than those recommended below, contact sales personnel. Table 14-1 Surface Mounting Type Soldering Conditions
Soldering Method Infrared reflow
64-Pin Plastic 64-Pin Plastic
Soldering Conditions Recommended Condition Symbol IR35-00-2
Package peak temperature: 235°C Duration: sec. max. 210°C above) Number times: Twice max. <precautions> second reflow should started after first reflow device temperature returned ordinary state. Flux washing must performed water after first reflow. Package peak temperature: 215°C Duration: sec. max. 200°C above) Number times: Twice max. <precautions> second reflow should started after first reflow device temperature returned ordinary state. Flux washing must performed water after first reflow. Terminal temperature: 300°C max. Duration: sec. max. (per device side)
VP15-00-2
Partial heating method
Caution more than soldering method should avoided (except partial heating method).
µPD78011BY, 78012BY, 78013Y, 78014Y
64-Pin Plastic 64-Pin Plastic
Soldering Conditions Package peak temperature: 235°C Duration: sec. max. 210°C above) Number times: Twice max. <precautions> second reflow should started after first reflow device temperature returned ordinary state. Flux washing must performed water after first reflow. Package peak temperature: 215°C Duration: sec. max. 200°C above) Number times: Twice max. <precautions> second reflow should started after first reflow device temperature returned ordinary state. Flux washing must performed water after first reflow. Solder bath temperature: 260°C max. Duration: sec. max. Number times: Once Preliminary heat temperature: 120°C max. (Package surface temperature) Terminal temperature: 300°C max. Duration: sec. max. (per device side) Recommended Condition Symbol IR35-00-2
Soldering Method Infrared reflow
VP15-00-2
Wave soldering
WS60-00-1
Partial heating method
Caution more than soldering method should avoided (except partial heating method). Table 14-2 Insertion Type Soldering Conditions
64-pin plastic shrink (750mil) 64-pin plastic shrink (750mil) 64-pin plastic shrink (750mil) 64-pin plastic shrink (750mil)
Soldering Conditions Solder bath temperature: 260°C max., Duration: sec. max. Terminal temperature: 300°C max., Duration: sec. max. (for each pin)
Soldering Method Wave soldering (terminal only) Partial heating method
Caution Apply wave soldering terminals only. that solder does contact with chip directly.
µPD78011BY, 78012BY, 78013Y, 78014Y
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78011BY, µPD78012BY, µPD78013Y, µPD78014Y. Language Processors
RA78K/0Notes CC78K/0Notes 78K/0 series common assembler package 78K/0 series common compiler package Device file µPD78014 sub-series 78K/0 series common compiler library source file
DF78014Notes CC78K/0-LNotes
PROM Write Tools
PG-1500 PA-78P014CW PA-78P014GC PG-1500 controllerNotes PROM programmer Programmer adapter connected PG-1500 PG-1500 control program
Debugging Tools
IE-78000-R IE-78000-R-BK IE-78014-R-EM EP-78240CW-R EP-78240GC-R EV-9200GC-64 SD78K/0Notes 78K/0 series common in-circuit emulator 78K/0 series common break board Evaluation emulation board µPD78002 µPD78014 sub-series Emulation probe common with µPD78244 sub-series Socket mounted onto user system board 64-pin plastic IE-78000-R screen debugger 78K/0 series system simulator Device file µPD78014 sub-series
SM78k/0Notes DF78014Notes
Real-Time
RX78K/0Notes 78K/0 series real-time 78K/0 series
MX78K/0Notes 1-3,
Fuzzy Inference Development Support System
FE9000Note FE9200Note FT9080Note FT9085Note FI78K0Notes FD78K0Notes Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes PC-9800 series (MS-DOSTM) based PC/AT(PC DOSTM) based HP9000 series 300and HP9000 series 700TM(HP-UXTM) based, SPARCstation(Sun OSTM) based EWS4800 series(EWS-UX/VTM) based PC-9800 series (MS-DOS WindowsTM) based PC/AT Windows) based Under development Remarks "78K/0 Series Selection Guide (IF-1185)" development tools created third parties. RA78K/0, CC78K/0, SD78K/0, SM78K/0 used with DF78014.
µPD78011BY, 78012BY, 78013Y, 78014Y
APPENDIX RELATED DOCUMENTATION
Device Related Documentation
Document Name User`s Manual 78K/0 Series User's Manual, Instruction Application Note Basic Basic Floating Point Arithmetic Program Document (Japanese) IEU-780 IEU-849 IEA-715 IEA-740 IEA-718 Document (English) IEU-1343 IEU-1372 IEA-1288 IEA-1299 IEA-1289
Development Tool Documentation (User`s Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller IE-78000-R IE-78000-R-BK IE-78014-R-EM SD78K/0 Screen Debugger Basic Reference Document (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-651 EEU-704 EEU-810 EEU-867 EEU-805 EEU-852 EEU-816 Document (English) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEU-1335 EEU-1291 EEU-1398 EEU-1427 EEU-1400 EEU-1414 EEU-1413
Documents Related Built-in Software (User's Manual)
Document Name Tool Creating Fuzzy Knowledge Data 78K/0, 78K/II, 87AD Series Fuzzy Interface Development Support System, Translator Document (Japanese) EEU-829 EEU-862 Document (English) EEU-1438 EEU-1444
Other Documents
Document Name Package Manual Surface Mount Technology Manual Quality Grades Semiconductor Devices Semiconductor Devices Quality Control Guarantee Guide Document (Japanese) IEI-635 IEI-616 IEI-620 MEI-603 Document (English) IEI-1213 IEI-1207 IEI-1209 MEI-1202
Caution contents above documents subject change without notice. latest documents should used design, etc.
µPD78011BY, 78012BY, 78013Y, 78014Y
µPD78011BY, 78012BY, 78013Y, 78014Y
Cautions CMOS Devices
Countermeasures against static electricity MOSs Caution When handling devices, take care that they electrostatically charged. Strong static electricity cause dielectric breakdown gates. When transporting storing devices, conductive trays, magazine cases, shock absorbers, metal cases that uses packaging shipping. sure ground devices during assembling. allow devices stand plastic plates touch pins. Also handle boards which devices mounted same way.
CMOS-specific handling unused input pins Caution Hold CMOS devices fixed input level. Unlike bipolar NMOS devices, CMOS device operated with input, intermediate-level input caused noise. This allows current flow CMOS device, resulting malfunction. pull-up pull-down resistor hold fixed input level. Since unused pins function output pins unexpected times, each unused should separately connected through resistor. handling unused pins documented, follow instructions document.
Statuses devices initialization Caution initial status device unpredictable when power turned Since characteristics device determined amount ions implanted molecules, initial status cannot determined manufacture process. responsibility output statuses pins, input output settings, contents registers power However, assures operation after reset items mode setting they defined. When turn device having reset function, sure reset device first.
Note Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips
registered trademark Corporation. EWS-4800 Series, EWS-UX/V, IEBus trademarks Corporation. MS-DOS Windows trademarks Microsoft Corporation. PC/AT trademarks Corporation. HP9000 Series 300, HP9000 Series 700, HP-UX trademarks HewlettPackard Company. SPARCstation trademark SPARC International, Inc. trademark Microsystems, Inc.
µPD78011BY, 78012BY, 78013Y, 78014Y
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. devices listed this document suitable aerospace equipment, submarine cables, nuclear reactor control systems life support systems. customers intend devices above applications they intend "Standard" quality grade devices applications intended NEC, please contact sales people advance. Application examples recommended Corporation Standard: Computer, Office equipment, Communication equipment, Test Measurement equipment, Machine tools, Industrial robots, Audio Visual equipment, Other consumer products, etc. Special: Automotive Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
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