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VT8235M Version CD South Bridge
Revision 2.03 March 16, 2005
Data Sheet
VT8235M Version CD South Bridge
Revision 2.03 March 16, 2005
VIA TECHNOLOGIES, INC.
Copyright Notice:
Trademark Notices:
VT8235M may only be used to identify products of VIA Technologies. is a registered trademark of VIA Technologies. AMD-K7 and Athlon are registered trademarks of Advanced Micro Devices. CeleronTM, PentiumTM, Pentium IITM, Pentium IIITM, Pentium 4TM, MMX and Intel are registered trademarks of Intel Corporation. Windows XPTM, Windows 2000TM, Windows METM, Windows 98 and Plug and Play are registered trademarks of Microsoft Corporation. PCI is a registered trademark of the PCI Special Interest Group. PS / 2 is a registered trademark of International Business Machines Corporation. All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.
Offices:
USA Office: 940 Mission Court Fremont, CA 94539 USA Tel: (510) 683-3300 Fax: (510) 683-3301 or (510) 687-4654 Web: http://www.viatech.com Taipei Office: st 1 Floor, No. 531 Chung-Cheng Road, Hsin-Tien Taipei, Taiwan ROC Tel: (886-2) 2218-5452 Fax: (886-2) 2218-5453 Web: http://www.via.com.tw
VT8235M Version CD V-Link South Bridge
REVISION HISTORY
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Revision History
VT8235M Version CD V-Link South Bridge
TABLE OF CONTENTS
REVISION HISTORY ..................................................................................III TABLE OF CONTENTS.................................................................................IV LIST OF FIGURES .................................................................................... VII LIST OF TABLES ..................................................................................... VII PRODUCT FEATURES.................................................................................. 1 OVERVIEW............................................................................................ 4 PINOUTS.............................................................................................. 6 PIN DESCRIPTIONS.................................................................................... 9 V-LINK PIN DESCRIPTIONS .............................................................................. 9 CPU, APIC AND CPU CONTROL PIN DESCRIPTIONS ........................................................ 10 MII, SERIAL EEPROM, LPC AND DMA PIN DESCRIPTIONS ................................................. 12 USB, SMB AND PROGRAMMABLE CHIP SELECT PIN DESCRIPTIONS ............................................ 13 EIDE INTERFACE PIN DESCRIPTIONS .................................................................... 14 SERIAL IRQ AND AC97 PIN DESCRIPTIONS ................................................................ 15 INTERNAL KEYBOARD CONTROLLER AND SPEAKER PIN DESCRIPTIONS ......................................... 16 GENERAL PURPOSE INPUT PIN DESCRIPTIONS ............................................................. 17 GENERAL PURPOSE OUTPUT AND GPIO PIN DESCRIPTIONS .................................................. 18 POWER MANAGEMENT AND EVENT DETECTION PIN DESCRIPTIONS ............................................ 19 CLOCK, RESETS, POWER STATUS, POWER AND GROUND PIN DESCRIPTIONS ..................................... 20 STRAP PIN DESCRIPTIONS .............................................................................. 21 REGISTERS........................................................................................... 22 REGISTER OVERVIEW ................................................................................. 22 REGISTER DESCRIPTIONS .............................................................................. 37 Legacy I / O Ports .................................................................................. 37
Keyboard Controller I / O Registers............................................................................ 38 DMA Controller I / O Registers ............................................................................... 40 Interrupt Controller I / O Registers............................................................................. 41 Timer / Counter Registers................................................................................... 41 CMOS / RTC I / O Registers.................................................................................. 42
Keyboard / Mouse Wakeup Index / Data Registers...................................................... 43 Keyboard / Mouse Wakeup Registers................................................................. 43 Memory Mapped I / O APIC Registers ................................................................ 44 Indexed I / O APIC Registers ........................................................................ 44 Configuration Space I / O ........................................................................... 46 Device 16 Function 0 Registers - USB 1.1 UHCI Ports 0-1 ................................................ 47
PCI Configuration Space Header.............................................................................. 47 USB-Specific Configuration Registers......................................................................... 48 USB I / O Registers ......................................................................................... 50
Device 16 Function 1 Registers - USB 1.1 UHCI Ports 2-3 ................................................ 51
PCI Configuration Space Header.............................................................................. 51 USB-Specific Configuration Registers......................................................................... 52
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Table of Content
VT8235M Version CD V-Link South Bridge
USB I / O Registers ......................................................................................... 54
Device 16 Function 2 Registers - USB 1.1 UHCI Ports 4-5 ................................................ 55
PCI Configuration Space Header.............................................................................. 55 USB-Specific Configuration Registers......................................................................... 56 USB I / O Registers ......................................................................................... 58
Device 16 Function 3 Registers - USB 2.0 EHCI........................................................ 59
PCI Configuration Space Header.............................................................................. 59 USB-Specific Configuration Registers......................................................................... 60 EHCI USB 2.0 I / O Registers................................................................................. 61
Device 17 Function 0 Registers - Bus Control and Power Management..................................... 62
PCI Configuration Space Header.............................................................................. 62 ISA Bus Control .......................................................................................... 63 Miscellaneous Control...................................................................................... 65 Function Control.......................................................................................... 66 Serial IRQ, LPC, and PC / PCI DMA Control .................................................................... 67 Plug and Play Control - PCI ................................................................................. 67 GPIO and Miscellaneous Control............................................................................. 68 Programmable Chip Select Control ............................................................................ 70 ISA Decoding Control...................................................................................... 71 Power Management-Specific Configuration Registers............................................................. 73 System Management Bus-Specific Configuration Registers ......................................................... 80 SMB GPIO Slave Command Codes ........................................................................... 80 General Purpose I / O Control Registers ......................................................................... 81 Watchdog Timer Registers .................................................................................. 82 Power Management I / O-Space Registers ....................................................................... 83 System Management Bus I / O-Space Registers................................................................... 92
Device 17 Function 1 Registers - Enhanced IDE Controller............................................... 95
PCI Configuration Space Header.............................................................................. 95 IDE-Controller-Specific Configuration Registers ................................................................. 97 IDE Power Management Registers........................................................................... 101 IDE Back Door Registers .................................................................................. 101 IDE I / O Registers ........................................................................................ 101
Device 17 Function 5 Registers - AC97 Audio Controller................................................ 102
PCI Configuration Space Header............................................................................. 102 Audio-Specific PCI Configuration Registers.................................................................... 103 I / O Base 0 Regs - Audio Scatter / Gather DMA ................................................................. 105
Device 17 Function 6 Registers - AC97 Modem Controller .............................................. 114
PCI Configuration Space Header............................................................................. 114 Modem-Specific PCI Configuration Registers .................................................................. 115 I / O Base 0 Regs - Modem Scatter / Gather DMA................................................................ 117
Device 18 Function 0 Registers - LAN ............................................................... 120
PCI Configuration Space Header............................................................................. 120 LAN-Specific PCI Configuration Registers .................................................................... 120 LAN I / O Registers........................................................................................ 122
FUNCTIONAL DESCRIPTIONS ........................................................................ 133 POWER MANAGEMENT ............................................................................... 133
Power Management Subsystem Overview ..................................................................... 133 Processor Bus States...................................................................................... 133 System Suspend States and Power Plane Control................................................................ 134 General Purpose I / O Ports .................................................................................. 134 Power Management Events ................................................................................. 135 System and Processor Resume Events......................................................................... 135 Legacy Power Management Timers .......................................................................... 136 System Primary and Secondary Events ........................................................................ 136 Peripheral Events......................................................................................... 136
ELECTRICAL SPECIFICATIONS ...................................................................... 137 ABSOLUTE MAXIMUM RATINGS ........................................................................ 137 DC CHARACTERISTICS............................................................................... 137 REGISTER BITS POWERED BY VBAT .................................................................... 138 Revision 2.03, March 16, 2005 -vTable of Content
VT8235M Version CD V-Link South Bridge
REGISTER BITS POWERED BY VSUS25 .................................................................. 138 PACKAGE MECHANICAL SPECIFICATIONS........................................................... 139
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VT8235M Version CD V-Link South Bridge
LIST OF FIGURES
FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. PC SYSTEM CONFIGURATION USING THE VT8235M VERSION CD.............................. 5 BALL DIAGRAM (TOP VIEW)................................................................. 6 POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM..................................... 133 SYSTEM BLOCK DIAGRAM USING THE P4X400 NORTH BRIDGE ............................. 135 MECHANICAL SPECIFICATIONS - 487 PIN BALL GRID ARRAY PACKAGE .................... 139 LEAD-FREE MECHANICAL SPECIFICATIONS - 487 PIN BALL GRID ARRAY PACKAGE ........ 140
LIST OF TABLES
TABLE 1. PIN LIST (NUMERICAL ORDER) ............................................................... 7 TABLE 2. PIN LIST (ALPHABETICAL ORDER) ........................................................... 8 TABLE 3. MEMORY MAPPED REGISTERS .............................................................. 22 TABLE 4. FUNCTION SUMMARY....................................................................... 22 TABLE 5. SYSTEM I / O MAP............................................................................ 22 TABLE 6. REGISTERS ................................................................................. 23 TABLE 7. KEYBOARD CONTROLLER COMMAND CODES ............................................... 39 TABLE 8. CMOS REGISTER SUMMARY ................................................................ 42 TABLE 9. APIC FIXED IRQ ROUTING .................................................................. 65 TABLE 10. PNP IRQ ROUTING TABLE .................................................................. 67
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Table of Content
VT8235M Version CD V-Link South Bridge
VT8235M VERSION CD
LOW COST V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE HIGH BANDWIDTH V-LINK CLIENT CONTROLLER INTEGRATED FAST ETHERNET, INTEGRATED DIRECT SOUND AC97 AUDIO, ULTRADMA-133 / 100 / 66 / 33 MASTER MODE EIDE CONTROLLER, SIX PORT USB 2.0 CONTROLLER, KEYBOARD / MOUSE CONTROLLER, RTC, LPC, SMBUS, SERIAL IRQ, PLUG AND PLAY, ACPI, AND PC2001 COMPLIANT ENHANCED POWER MANAGEMENT
PRODUCT FEATURES
Inter-operable with VIA Host-to-V-Link Host Controller - Combine with KT400A North Bridge for a complete Athlon system - Combine with CLE266 North Bridge for a complete VIA C3 / Pentium 3 system - Combine with P4X400 North Bridge for a complete Pentium 4 system High Bandwidth 533 MB / s 8-bit V-Link Client Controller - Supports 66 MHz V-Link Client interface with total bandwidth of 533 MB / sec - V-Link operates in 2x, 4x, and 8x modes - Full duplex commands with separate Strobe / Command - Request / Data split transaction - Configurable outstanding transaction queue for V-Link Client accesses - Auto Client Retry to eliminate V-Link Host-Client Retry cycles - Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency all V-Link transactions - Highly efficient V-Link arbitration with minimum overhead all V-Link transactions have predictable cycle length - Auto connect / reconnect capability and dynamic stop for minimum power consumption - Parity checking to insure correct data transfers
with known Command / Data duration for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow.
Integrated Peripheral Controllers - Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability - Integrated USB 2.0 Controller with three root hubs and six function ports - Dual channel UltraDMA-133 / 100 / 66 / 33 master mode EIDE controller - AC-link interface for AC-97 audio codec and modem codec - HSP modem support - Integrated DirectSound compatible digital audio controller - LPC interface for Low Pin Count interface to Super-I / O or ROM Integrated Legacy Functions - Integrated Keyboard Controller with PS2 mouse support - Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day / Month Alarm for ACPI - Integrated DMA, timer, and interrupt controller - Serial IRQ for docking and non-docking applications - Fast reset and Gate A20 operation
-1Product Feature
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VT8235M Version CD V-Link South Bridge · Concurrent PCI Bus Controller - 33 MHz operation - Supports up to six PCI masters - Peer concurrency - Concurrent multiple PCI master transactions i.e., allow PCI masters from both PCI buses active at the same time - Zero wait state PCI master and slave burst transfer rate - PCI to system memory data streaming up to 132Mbyte / sec (data sent to north bridge via high speed V-Link - - - - - - - - - - - ·
Interface) PCI master snoop ahead and snoop filtering Eight DW of CPU to PCI posted write buffers Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities Enhanced PCI command optimization (MRL, MRM, MWI, etc.) Four lines of post write buffers from PCI masters to DRAM Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters Delay transaction from PCI master accessing DRAM Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks) Symmetric arbitration between Host / PCI bus for optimized system performance Complete steerable PCI interrupts PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
Fast Ethernet Controller - High performance PCI master interface with scatter / gather and bursting capability - Standard MII interface to external PHYceiver - 1 / 10 / 100 MHz full and half duplex operation - Independent 2K byte FIFOs for receive and transmit - Flexible dynamically loadable EEPROM algorithm - Physical, Broadcast, and Multicast address filtering using hashing function - Magic packet and wake-on-address filtering - Software controllable power down UltraDMA-133 / 100 / 66 / 33 Master Mode EIDE Controller - Dual channel master mode hard disk controller supporting four Enhanced IDE devices - Transfer rate up to 133MB / sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-133 interface - Increased reliability using UltraDMA-133 / 100 / 66 transfer protocols - Thirty-two levels (doublewords) of prefetch and write buffers - Dual DMA engine for concurrent dual channel operation - Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant - Full scatter gather capability - Support ATAPI compliant devices including DVD devices - Support PCI native and ATA compatibility modes - Complete software driver support Direct Sound Ready AC97 Digital Audio Controller - AC-Link access to 4 CODECs (AC97 + AMC97 + MC97) - Multichannel Audio - Bus Master Scatter / Gather DMA - Dedicated read and write channels supporting simultaneous stereo playback and record - Dedicated read and write channels supporting simultaneous modem receive and transmit - 1 stereo DirectSound channel with source / volume control / mixer - 1 shared FM / SPDIF PCM read channel - 1 dedicated channel supporting multi-channel audio - 32-byte line-bufers for each SGD channel - Programmable 8bit / 16bit mono / stereo PCM data format support - AC97 2.1 compliant
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Product Feature
VT8235M Version CD V-Link South Bridge · System Management Bus Interface - Host interface for processor communications - Slave interface for external SMBus masters Universal Serial Bus Controller - USB v2.0 and Enhanced Host Controller Interface (EHCI) v1.0 compatible - USB v1.1 and Universal Host Controller Interface (UHCI) v1.1 compatible - Eighteen level (doublewords) data FIFO with full scatter and gather capability - Three root hubs and six function ports - Integrated physical layer transceivers with optional over-current detection status on USB inputs - Legacy keyboard and PS / 2 mouse support Sophisticated PC2001-Compatible Mobile Power Management - Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management - ACPI v2.0 Compliant - APM v1.2 Compliant - CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support - PCI bus clock run, Power Management Enable (PME) control, and PCI / CPU clock generator stop control - Supports multiple system suspend types: power-on suspends with flexible CPU / PCI bus reset options, - - - - - - - - - - - - ·
suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up Multiple suspend power plane controls and suspend status indicators One idle timer, one peripheral timer and one general purpose timer, plus 24 / 32-bit ACPI compliant timer Normal, doze, sleep, suspend and conserve modes Global and local device power control System event monitoring with two event classes Primary and secondary interrupt differentiation for individual channels Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open / close for system wake-up 32 general purpose input ports and 32 output ports Multiple internal and external SMI sources for flexible power management models Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field Thermal alarm on external temperature sensing circuit I / O pad leakage control
Plug and Play Controller - PCI interrupts steerable to any interrupt channel - Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, and audio - Microsoft Windows XPTM, Windows NTTM, Windows 2000TM, Windows 98 and plug and play BIOS compliant Built-in NAND-tree pin scan test capability 0.22um, 2.5V, low power CMOS process Single chip 27 x 27 mm, 1.0 mm ball pitch, 487 pin BGA
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Product Feature
VT8235M Version CD V-Link South Bridge
OVERVIEW
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Overview
VT8235M Version CD V-Link South Bridge
CPU / Cache Sideband Signals Init / A20M# INTR / NMI SMI / StopClk FERR / IGNNE Sleep Boot ROM Onboard LPC I / O
North Bridge Vlink Interface
MA / Command MD
System Memory DIMM Module ID
Expansion Cards PCI
LPC VT8235M 487 BGA
IDE Primary and Secondary USB 2.0 Ports 0-5 Keyboard / Mouse AC97 Link APIC GPIO, Power Control, Reset MII Fast Ethernet Interface
RTC Crystal
Figure 1. PC System Configuration Using the VT8235M Version CD
Revision 2.03, March 16, 2005
Overview
VT8235M Version CD V-Link South Bridge
PINOUTS
Figure 2. Ball Diagram (Top View)
GND GND
T RDY# DEV SEL#
CBE 2# FRM# I RDY# REQ 2# GNT 2# CBE 0# AD8 REQ 3# GNT 3# GND REQ 4# GNT 4# REQ5# GPI7 GNT5# GPO7 GND VSUS 25 VSUS 25 GND BAT LOW# THRM# VSUS 33 VSUS 33 VSUS 33 RTC X1 V BAT PWR GD
AD17 AD16 REQ 1# GNT 1# VCC 33 VCC 33 GND VCC VCC VCC VCC 33 VCC 33 GND VCC 33 VCC 33 VCC VCC VCC VCC 33 VCC 33 GND GND VSUS 33 RSM RST# GPIO A PCK RUN#
GPIO 11 AD19 AD18 REQ 0# GNT 0# GND
GPIO 12
AGP BZ#
MRX D3 MD IO MD CK MRX D2 GND VCC
MRX ERR MRX CLK MRX DV MRX D1 MRX D0 VCC
MTX D1 MTX D2 MTX D3 MII VCC MII VCC GND
MTX CLK MTX ENA MTX D0 MII VCC MII VCC VCC 33
EE CS# M CRS M COL MII VCC25 MII VCC25 VCC 33
EE DO EE DI EE CK USB OC4# USB OC5# VCC
USB OC0# USB OC1# USB OC2# VSUS USB USB OC3# VCC
USB GND USB GND USB GND USB GND GND VCC 33
USB P4+ USB P4- USB GND USB P5- USB P5+ VCC 33
USB GND USB GND USB GND USB GND USB GND USB GND
USB P2+ USB P2- USB GND USB P3- USB P3+ USB GND
USB GND USB GND USB GND USB GND USB GND USB GND
USB P0+ USB P0- USB GND USB P1- USB P1+ USB GND VCC VK VCC VK VCC VCC VCC VK VCC VK VCC VK VCC 33 VCC 33 VCC VCC GND GND VCC 33 VCC 33 VCC 33 SD IOW#
USB GND USB GND USB GND VCC UPLL GND UPLL VCC VK VAD 11 VAD 12 VAD 14 VAD 15 VCC VK VCC VK VCC VK PLL VCC PCI CLK APIC D0 VCC GND PD VREF PD DRQ PD D15 GND
VCC UPLL GND UPLL USB REXT USB CLK GND VAD 9 VAD 10 GND VL VREF VL COMP GND VCC VK VCC VK PLL GND NMI INTR APIC CLK APIC D1 PD COMP PD A0 GND PD D12
USB VCC USB VCC USB VCC USB VCC VAD 5 VBE 0# VAD 13 UP STB DN CMD VAD 6 V CLK VCC VK VCC VK VRD SLP GHI# SMI# TPO PD CS1# PD CS3# PD IOR# PD D0 PD D2 PD D4 PD D9 IRQ 14 IRQ 15
USB VCC USB VCC USB VCC VAD 8 GND VAD 0 DN STB GND VAD 3 UP CMD GND VCC VK VCC VK VID SEL INIT# A20M# SLP# PD A1 GND PD IOW# PD D1 GND PD D11 PD D5 GND PD D7
USB VCC USB VCC USB VCC V PAR VAD 4 VAD 1 DN STB# UP STB# VAD 2 VAD 7 VBE 1# VCC VK VCC VK DP SLP# STP CLK# IGN NE# FERR# PD A2 PD DAK# PD RDY PD D14 PD D13 PD D3 PD D10 PD D6 PD D8
SERR# PERR# STOP# CBE 1# AD11 AD10 AD7 AD5 AD3 AD20 CBE 3# AD27 AD29 INT A# INT D# AC SYNC AC SDO AC SDI3 MS DT CPU MISS EXT SMI# SUS CLK LID# SMB DT2 SMB CK2 SUS C# AD15 AD13 AD9 AD6 AD2 AD1 AD22 AD24 AD26 AD31 INT B# PCI RST# AC SDI0 AC SDI2 KB DT MS CK RING# SUS A# SMB ALRT# SMB DT1 PWR BTN# PWR OK# SUS B# PAR AD14 AD12 AD4 AD0 AD21 AD23 AD25 AD28 AD30 INT C# AC RST# AC BTCK AC SDI1 KB CK PME# SUS ST# GPO 0 SMB CK1 GPI 1 IN TRUD# GPI 0 RTC X2
GPIO GPIO 9 13 GPIO VGATE 15 GPIO8 GPIO 10 RAM VCC VCC 33 GPIO 14 RAM GND VCC 33
VCC 33 GPIO E GPIO D GPIO C PCI STP#
7 GPIO
8 Pins
11 LAN
12 Pins
17 USB
18 Pins
K11 PCI Pins L10 M N P R AC97 Pins T10
GND GND GND GND GND GND
V-Link L17 M N P R T17 CPU Pins Pins
U11 KB / MS Pins PM LPC 7
VCC 33 CPU STP# L REQ# L FRM# L AD3
U16 Pri IDE
VCC 33 GND
Pins Pins 8
VCC GND L AD2 L AD1 L AD0
X-Bus 9
VCC GND IOW# SPKR strap TEST
Pins 12
GND OSC SOE# strap MEM R# ROMCS # / strap
Sec 13
IDE 16
VCC GND SDD1 SA01 GND SDD2 SA02
Pins 17
VCC GND SD VREF SDD4 SA04 SDD3 SA03
Pins 18
GND VCC 33 SDD5 SA05 SDD7 SA07 SDD6 SA06
VCC 33 IOR# IO RDY SER IRQ MEM W#
VCC 33 SA19 strap SA18 strap SA17 strap SA16 strap
VCC 33 SD COMP SD RDY SD DRQ SDD0 SA00
GND VCC 33 SDD9 SA09 GND SDD8 SA08
SDA1 SDCS1# strap strap SD SDCS3# DAK# strap SDA0 GND strap SD IOR# SDA2 strap
SDD10 SDD13 SA10 SA13 SDD12 SDD15 SA12 SA15 SDD11 SDD14 SA11 SA14
Revision 2.03, March 16, 2005
Pin Diagram
VT8235M Version CD V-Link South Bridge
Table 1. Pin List (Numerical Order)
Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin #
AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 I I IO I IO IO I IO O IO IO I IO - IO IO IO IO O O IO IO IO IO O I P IO IO O IO O I IO IO IO IO I P IO IO P IO IO P O I P IO O O O I IO O IO IO I IO IO O IO IO IO IO IO IO IO IO IO O O I IO IO
Pin Name
RTCX1 RSMRST# GPIOD / GPIO30 LREQ# LAD2 IOW# IORDY / GPI19 SA18 / O18 / strap SOE# / strap XD7 XD4 SDRDY SDD01 / SA01 NC SDD05 / SA05 SDD09 / SA09 SDD10 / SA10 SDD13 / SA13 SDDACK# SDCS3# / strap PDD09 PDD05 PDD10 SMBCK2 / PWROK# GPI0 VBAT GPIOA / GPIO24 GPIOC / GPIO25 LFRM# LAD1 SPKR / strap SERIRQ SA17 / O17 / strap MEMR# XD6 XD3 SDDRQ GND SDD04 / SA04 SDD07 / SA07 GND SDD12 / SA12 SDD15 / SA15 GND SDA0 / strap IRQ14 GND PDD06 SUSC# SUSB# / GPO2 RTCX2 PWRGD PCKRUN# PCISTP# / GPO6 LAD3 LAD0 TEST MEMW# SA16 / O16 / strap ROMCS# / KBCS# / XD5 XD2 SDD00 / SA00 SDD02 / SA02 SDD03 / SA03 SDD06 / SA06 SDD08 / SA08 SDD11 / SA11 SDD14 / SA14 SDIOR# SDA2 / strap IRQ15 PDD07 PDD08
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Pin Lists
VT8235M Version CD V-Link South Bridge
Table 2. Pin List (Alphabetical Order)
Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin #
F19 F20 F21 A15 B15 C15 E15 D14 E14 B21 A21 D21 E21 B19 A19 D19 E19 B17 A17 D17 E17 C23 A24 A25 A26 B24 B25 B26 C24 C25 C26 D24 F25 F26 J26 J25 E26 E24 K24 K26 D25 F23 G23 G22 H22 G24 J22 K22 AE04 F24 L26 A23 D22 L24 C08 P25 K23 J23 D26 P24 T04 U04 AA04 AB04 AC04 AC05 D15 AC14 AC13 AF14 AE14 AD14 AF13 AE13 AD13 P P P I I I I I I IO IO IO IO IO IO IO IO IO IO IO IO AI P P P P P P P P P P IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO P IO IO P P I I OD I P IO OD P P P P P P P IO IO IO IO IO IO IO IO
Pin Name
USBGND USBGND USBGND USBOC0# USBOC1# USBOC2# USBOC3# USBOC4# USBOC5# USBP0- USBP0+ USBP1- USBP1+ USBP2- USBP2+ USBP3- USBP3+ USBP4- USBP4+ USBP5- USBP5+ USBREXT USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC VAD00 VAD01 VAD02 VAD03 VAD04 VAD05 VAD06 VAD07 VAD08 VAD09 VAD10 VAD11 VAD12 VAD13 VAD14 VAD15 VBAT VBE0# VBE1# VCCUPLL VCCUPLL VCLK VGATE / GPIO8 / PCRA VIDSEL / GIO28 VLCOMP VLVREF VPAR VRDPSLP / GPIO29 VSUS25 VSUS25 VSUS33 VSUS33 VSUS33 VSUS33 VSUSUSB XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
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Pin Lists
VT8235M Version CD V-Link South Bridge
PIN DESCRIPTIONS
V-Link Pin Descriptions V-Link Interface
Signal Name VAD15:0 Pin # K22, J22, G24, H22, G22, G23, F23, D25, K26, K24, E24, E26, J25, J26, F26, F25 D26 I / O Signal Description IO Address / Data Bus. Bits 0-7 are implemented and bits 8-15 are reserved for future use. VAD7:0 are used to send strap information to the chipset north bridge. At power up VAD7 reflects the state of a strap on SDCS3#, VAD6:4 reflect the state of straps on pins SDA2:0 and VAD3:0 reflect the state of straps on pins SA19:16. The specific interpretation of these straps is north bridge chip design dependent. IO Parity. If the VPAR function is implemented in a compatible manner on the north bridge, this pin should be connected to the north bridge VPAR pin (P4X333, P4X400, P4X800, KT400). If VPAR is not implemented in the north bridge chip or is incompatible with the 8235 (4x V-Link north bridges) connect this pin to an 8.2K pullup to 2.5V (Pro266, Pro266T, KT266, KT266A, KT333, P4X266, PN266, KN266, KM266, P4M266, P4N266). See app note AN222 for details. IO Byte Enables. VBE0# is used with VAD7-0 and VBE1# is used with VAD15-8 (VBE1# and VAD15-8 are reserved for future use). I V-Link Clock. O Command from Client-to-Host. I Command from Host-to-Client. O Strobe from Client-to-Host. O Complement Strobe from Client-to-Host. I Strobe from Host-to-Client. I Complement Strobe from Host-to-Client. AI V-Link Compensation.
VBE1:0# VCLK UPCMD DNCMD UPSTB UPSTB# DNSTB DNSTB# VLCOMP
L26, F24 L24 K25 J24 H24 H26 G25 G26 K23
Revision 2.03, March 16, 2005
Pin Descriptions
VT8235M Version CD V-Link South Bridge CPU, APIC and CPU Control Pin Descriptions CPU Interface
Advanced Programmable Interrupt Controller (APIC) Interface
CPU Speed Control Interface
AGPBZ# / GPI6
Revision 2.03, March 16, 2005
VT8235M Version CD V-Link South Bridge PCI Bus Interface
FRAME# IRDY# TRDY# STOP# SERR# PAR INTA# INTB# INTC# INTD# INTE# / GPI12, / GPO12, / PCGNTA, INTF# / GPI13, / GPO13, / PCGNTB, INTG# / GPI14, / GPO14, INTH# / GPI15, / GPO15 REQ5# / GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0# GNT5# / GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0# PCIRST# PCICLK PCKRUN#
B4 C4 A3 C3 C1 D3 P1, P2, P3, R1 A7, B8, D8, C7 N4 L4 H4 D4 C5 D6 P4 M4 J4 E4 D5 E6 R2 R22 AF5
PCI Request. These signals connect to the VT8235M Version CD from each PCI slot (or each PCI master) to request the PCI bus. To use pin N4 as REQ5#, Function 0 RxE4 must be set to 1 otherwise this pin will function as General Purpose Input 7.
PCI Grant. These signals are driven by the VT8235M Version CD to grant PCI access to a specific PCI master. To use pin P4 as GNT5#, Function 0 RxE4 must be set to 1 otherwise this pin will function as General Purpose Output 7.
O PCI Reset. This signal is used to reset devices attached to the PCI bus. I PCI Clock. This signal provides timing for all transactions on the PCI Bus. IO PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped (high) or running (low). The VT8235M Version CD drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping. Connect this pin to ground using a 100 resistor if the function is not used. Refer to the "PCI Mobile Design Guide" and an applicable VIA North Bridge Design Guide (e.g., KT400, CLE266, or P4X400) for more details.
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Pin Descriptions
VT8235M Version CD V-Link South Bridge MII, Serial EEPROM, LPC and DMA Pin Descriptions LAN Controller - Media Independent Interface (MII)
Serial EEPROM Interface
Signal Name Pin # I / O PU Signal Description A13 O EECS# Serial EEPROM Chip Select. C14 O EECK Serial EEPROM Clock. A14 I Serial EEPROM Data Output. Connect to EEPROM Data Out pin. EEDO B14 O Serial EEPROM Data Input. Connect to EEPROM Data In pin. EEDI These pins are disabled if the SDCS1# pin is strapped low to enable serial EEPROM connection via the MII interface.
Low Pin Count (LPC) Interface
Signal Name Pin # I / O PU Signal Description AE7 O LFRM# LPC Frame. AD7 I LREQ# LPC DMA / Bus Master Request. AF7, AD8, AE8, AF8 IO PU LPC Address / Data. LAD3-0 Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#
PC / PCI DMA
VT8235M Version CD V-Link South Bridge USB, SMB and Programmable Chip Select Pin Descriptions Universal Serial Bus 2.0 Interface
System Management Bus (SMB) Interface (I2C Bus)
Programmable Chip Selects
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Pin Descriptions
VT8235M Version CD V-Link South Bridge EIDE Interface Pin Descriptions UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface
Signal Name PDRDY / PDDMARDY / PDSTROBE SDRDY / SDDMARDY / SDSTROBE PDIOR# / PHDMARDY / PHSTROBE SDIOR# / SHDMARDY / SHSTROBE PDIOW# / PSTOP Pin # Y26 I / O Signal Description I EIDE Mode: Primary I / O Channel Ready. Device ready indicator UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device may assert DDMARDY to pause output transfers Primary Device Strobe. Input data strobe (both edges). The device may stop DSTROBE to pause input data transfers EIDE Mode: Secondary I / O Channel Ready. Device ready indicator UltraDMA Mode: Secondary Device DMA Ready. Output flow control. The device may assert DDMARDY to pause output transfers Secondary Device Strobe. Input data strobe (both edges). The device may stop DSTROBE to pause input data transfers EIDE Mode: Primary Device I / O Read. Device read strobe UltraDMA Mode: Primary Host DMA Ready. Primary channel input flow control. The host may assert HDMARDY to pause input transfers Primary Host Strobe. Output data strobe (both edges). The host may stop HSTROBE to pause output data transfers EIDE Mode: Secondary Device I / O Read. Device read strobe UltraDMA Mode: Secondary Host DMA Ready. Input flow control. The host may assert HDMARDY to pause input transfers Host Strobe B. Output strobe (both edges). The host may stop HSTROBE to pause output data transfers EIDE Mode: Primary Device I / O Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst. EIDE Mode: Secondary Device I / O Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst. Primary Device DMA Request. Primary channel DMA request Secondary Device DMA Request. Secondary channel DMA request Primary Device DMA Acknowledge. Primary channel DMA acknowledge Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge Primary Channel Interrupt Request. Secondary Channel Interrupt Request.
SDIOW# / SSTOP
PDDRQ SDDRQ PDDACK# SDDACK# IRQ14 IRQ15
Y22 AE15 W26 AD22 AE24 AF24
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Pin Descriptions
VT8235M Version CD V-Link South Bridge
UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (continued)
Signal Name PDCS1# PDCS3# SDCS1# / strap Pin # V24 W24 AC23 I / O O Signal Description Primary Master Chip Select. This signal corresponds to CS1FX# on the primary IDE connector. O Primary Slave Chip Select. This signal corresponds to CS3FX# on the primary IDE connector. O Secondary Master Chip Select. This signal corresponds to CS17X# on the secondary IDE connector. Strap low (resistor to ground) to enable serial EEPROM interface via the MII bus (this disables the EExx pins). This pin has an internal pullup to default to serial EEPROM interface via the EExx pins. O Secondary Slave Chip Select. This signal corresponds to CS37X# on the secondary IDE connector. Strap information is communicated to the north bridge via VAD7. O Primary Disk Address. PDA2:0 are used to indicate which byte in either the ATA command block or control block is being accessed. O Secondary Disk Address. SDA2:0 are used to indicate which byte in either the ATA command block or control block is being accessed. Strap information is communicated to the north bridge via VAD6:4. IO Primary Disk Data. IO / IO Secondary Disk Data. I Primary Disk Compensation. I Secondary Disk Compensation.
SDCS3# / strap PDA2-0 SDA2-0 / strap PDD15-0 SDD15-0 / SA15-0 PDCOMP SDCOMP
AD23 V26, V25, Y23 AF23, AC22, AE23 (see pin list) (see pin list) W23 AC15
Serial IRQ and AC97 Pin Descriptions Serial IRQ
Signal Name SERIRQ Pin # AE10 I / O I Signal Description Serial IRQ. This pin has an internal pull-up resistor.
AC97 Audio / Modem Interface
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Pin Descriptions
VT8235M Version CD V-Link South Bridge Internal Keyboard Controller and Speaker Pin Descriptions Internal Keyboard Controller
ISA Subset / Parallel BIOS ROM Interface
SA19-16 / GPO19-16 / straps SA15-0 / SDD15-0
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Pin Descriptions
VT8235M Version CD V-Link South Bridge General Purpose Input Pin Descriptions General Purpose Inputs
Revision 2.03, March 16, 2005
Pin Descriptions
VT8235M Version CD V-Link South Bridge General Purpose Output and GPIO Pin Descriptions General Purpose Outputs
General Purpose I / O
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Pin Descriptions
VT8235M Version CD V-Link South Bridge Power Management and Event Detection Pin Descriptions Power Management and Event Detection
INTRUDER# / GPI16 THRM# / GPI18 / AOLGPI
RING# / GPI3 BATLOW# / GPI5 CPUSTP# / GPO5 PCISTP# / GPO6 SUSA# / GPO1 SUSB# / GPO2 SUSC# SUSST1# / GPO3
SUSCLK CPUMISS / GPI17
AOLGPI / GPI18 / THRM#
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VT8235M Version CD V-Link South Bridge Clock, Resets, Power Status, Power and Ground Pin Descriptions Resets, Clocks, and Power Status
Signal Name PWRGD PWROK# PCIRST# OSC RTCX1 RTCX2 TEST TPO NC Pin # AF4 AE2 R2 AC12 AD4 AF3 AF9 U24 W22, AD17 I / O Signal Description I O O I I O I O - Power Good. Connected to the Power Good signal on the Power Supply. Internal logic powered by VBAT. Power OK. Internal logic powered by VSUS33. PCI Reset. Active low reset signal for the PCI bus. The VT8235M Version CD will assert this pin during power-up or from the control register. Oscillator. 14.31818 MHz clock signal used by the internal Timer. RTC Crystal Input: 32.768 KHz crystal or oscillator input. This input is used for the internal RTC and power-well power management logic and is powered by VBAT. RTC Crystal Output: 32.768 KHz crystal output. Internal logic powered by VBAT. Test. Test Pin Output. Output pin for test mode. No Connect. Reserved. Do not connect.
Power and Ground
VT8235M Version CD V-Link South Bridge Strap Pin Descriptions Strap Pins
AD12 Auto Reboot
L: Enable Auto Reboot H: Disable Auto Reboot (Default) AE9 CPU Frequency Strapping L: Enable CPU Frequency Strapping H: Disable CPU Frequency Strapping (Default) AF12 Internal Keyboard Controller L: Disable internal KBC H: Enable internal KBC (Default) AC23 Eliminate External LAN L: Enable. Use external EEPROM (Default) EEPROM H: Disable. Do not use external EEPROM Strap Pins for North Bridge Configuration Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details Check the North Bridge DS for details SA18 signal state is reflected on signal pin VD2 Check the North during power up for North Bridge configuration. Bridge DS for details SA17 signal state is reflected on signal pin, Check the North VD1 during power up for North Bridge Bridge DS for configuration. details SA16 signal state is reflected on signal pin, Check the North VD0 during power up for North Bridge Bridge DS for configuration. details SDCS3# signal state is reflected on signal pin VD7 during power up for North Bridge configuration. SDA2 signal state is reflected on signal pin VD6 during power up for North Bridge configuration. SDA1 signal state is reflected on signal pin VD5 during power up for North Bridge configuration. SDA0 signal states is reflected on signal pins VD4 during power up for North Bridge configuration. SA19 signal state is reflected on signal pin VD3 during power up for North Bridge configuration.
SDCS3# SDA2 SDA1 SDA0 SA19 SA18 SA17 SA16
AD23 NB Configuration AF23 NB Configuration
AC22 NB Configuration AE23 NB Configuration AC11 NB Configuration AD11 NB Configuration AE11 NB Configuration AF11 NB Configuration
Summary of Internal Pull-Up / Pull-Down Resistor Implementation Internal Pullups are present on pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD3:0, SDCS1# Internal Pulldowns are present on pins SA19-16 and all LAN pins
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Pin Descriptions
VT8235M Version CD V-Link South Bridge
REGISTERS
Register Overview
Table 5. System I / O Map
Function Actual Port Decoding Master DMA Controller 0000 0000 000x nnnn Master Interrupt Controller 0000 0000 001x xxxn Timer / Counter 0000 0000 010x xxnn Keyboard Controller 0000 0000 0110 xnxn KBC Data 0000 0000 0110 x0x0 Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1 KBC Command / Status 0000 0000 0110 x1x0 RTC / CMOS / NMI-Disable 0000 0000 0111 0nnn -available for system use- 0000 0000 0111 1xxx -reserved- (debug port) 0000 0000 1000 0000 DMA Page Registers 0000 0000 1000 nnnn -available for system use- 0000 0000 1001 000x System Control 0000 0000 1001 0010 -available for system use- 0000 0000 1001 nnnn Slave Interrupt Controller 0000 0000 101x xxxn Slave DMA Controller 0000 0000 110n nnnx -available for system use- 0000 0000 111x xxxx -available for system use
Table 3. Memory Mapped Registers
FEC00000 FEC00010 FEC00020 FEC00040 APIC Index APIC Data APIC IRQ Pin Assertion APIC EOI (8-bit) (32-bit) (8-bit) (8-bit)
CF8-CFB PCI Configuration Address 0000 1100 1111 10xx CFC-CFF PCI Configuration Data 0000 1100 1111 11xx D00-FFFF -available for system use-
Table 4. Function Summary
Bus Device Func Device ID Function 0 16 (10h) 0 3038h USB 1.1 UHCI Ports 0-1 0 16 (10h) 1 3038h USB 1.1 UHCI Ports 2-3 0 16 (10h) 2 3038h USB 1.1 UHCI Ports 4-5 0 16 (10h) 3 3104h USB 2.0 EHCI Ports 0-5 0 0 0 0 17 (11h) 17 (11h) 17 (11h) 17 (11h) 0 1 5 6 0 3074h 0571h 3059h 3068h Bus Control & Power Mgmt IDE Controller AC97 Audio Codec Controller MC97 Modem Codec Ctrlr
0 18 (12h)
3065h VIA LAN Controller
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Register Overview
VT8235M Version CD V-Link South Bridge
Table 6. Registers
Legacy I / O Registers Port 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Master DMA Controller Registers Channel 0 Base & Current Address Channel 0 Base & Current Count Channel 1 Base & Current Address Channel 1 Base & Current Count Channel 2 Base & Current Address Channel 2 Base & Current Count Channel 3 Base & Current Address Channel 3 Base & Current Count Status / Command Write Request Write Single Mask Write Mode Clear Byte Pointer FF Master Clear Clear Mask Read / Write Mask Default Acc RW RW RW RW RW RW RW RW RW WO WO WO WO WO WO RW Default Acc - - - RW - RW Default Acc RW RW RW WO Default Acc RW RW RW Legacy I / O Registers (continued) Port 87 83 81 82 8F 8B 89 8A DMA Page Registers DMA Page - DMA Channel 0 DMA Page - DMA Channel 1 DMA Page - DMA Channel 2 DMA Page - DMA Channel 3 DMA Page - DMA Channel 4 DMA Page - DMA Channel 5 DMA Page - DMA Channel 6 DMA Page - DMA Channel 7 Default Acc RW RW RW RW RW RW RW RW Default Acc RW
Port System Control Registers 92 System Control
Port Master Interrupt Controller Regs 20 Master Interrupt Control 21 Master Interrupt Mask 20 Master Interrupt Control Shadow 21 Master Interrupt Mask Shadow RW if shadow registers are disabled Port 40 41 42 43 Port 60 61 64 Timer / Counter Registers Timer / Counter 0 Count Timer / Counter 1 Count Timer / Counter 2 Count Timer / Counter Control Keyboard Controller Registers Keyboard Controller Data Misc Functions & Speaker Control Keyboard Ctrlr Command / Status
Port Slave Interrupt Controller Regs Default Acc A0 Slave Interrupt Control - A1 Slave Interrupt Mask - A0 Slave Interrupt Control Shadow - RW A1 Slave Interrupt Mask Shadow - RW RW accessible if shadow registers are disabled Port C0 C2 C4 C6 C8 CA CC CE D0 D2 D4 D6 D8 DA DC DE Slave DMA Controller Registers Channel 0 Base & Current Address Channel 0 Base & Current Count Channel 1 Base & Current Address Channel 1 Base & Current Count Channel 2 Base & Current Address Channel 2 Base & Current Count Channel 3 Base & Current Address Channel 3 Base & Current Count Status / Command Write Request Write Single Mask Write Mode Clear Byte Pointer FF Master Clear Clear Mask Read / Write Mask Default Acc RW RW RW RW RW RW RW RW RW WO WO WO WO WO WO RW
Port CMOS / RTC / NMI Registers Default Acc 70 CMOS Memory Address & NMI Disa WO 71 CMOS Memory Data (128 bytes) RW 74 CMOS Memory Address RW 75 CMOS Memory Data (256 bytes) RW NMI Disable is port 70h (CMOS Memory Address) bit-7. RTC control occurs via specific CMOS data locations (0-Dh). Ports 74-75 may be used to access CMOS if the internal RTC is disabled.
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Register Overview
VT8235M Version CD V-Link South Bridge
Game Port Registers (I / O Space) Offset 0 1 1 2-F Game Port (200-20F typical) -reservedGame Port Status Start One-Shot -reservedDefault Acc 00 - RO WO 00 -
Offset APIC Registers Default Acc 0 APIC ID 0000 0000 RW 1 APIC Version 0017 8003 RO 2 APIC Arbitration 0000 0000 RO 3 Boot Configuration 0000 0000 RW 4-F -reserved0000 0000 - 11-10 I / O Redirection- AIRQ0 xxx1xxxx xxxxxxxx RW 13-12 I / O Redirection- AIRQ1 xxx1xxxx xxxxxxxx RW 15-14 I / O Redirection- AIRQ2 xxx1xxxx xxxxxxxx RW 17-16 I / O Redirection- AIRQ3 xxx1xxxx xxxxxxxx RW 19-18 I / O Redirection- AIRQ4 xxx1xxxx xxxxxxxx RW 1B-1A I / O Redirection- AIRQ5 xxx1xxxx xxxxxxxx RW 1D-1C I / O Redirection- AIRQ6 xxx1xxxx xxxxxxxx RW 1F-1E I / O Redirection- AIRQ7 xxx1xxxx xxxxxxxx RW 21-20 I / O Redirection- AIRQ8 xxx1xxxx xxxxxxxx RW 23-20 I / O Redirection- AIRQ9 xxx1xxxx xxxxxxxx RW 25-24 I / O Redirection- AIRQ10 xxx1xxxx xxxxxxxx RW 27-26 I / O Redirection- AIRQ11 xxx1xxxx xxxxxxxx RW 29-28 I / O Redirection- AIRQ12 xxx1xxxx xxxxxxxx RW 2B-2A I / O Redirection- AIRQ13 xxx1xxxx xxxxxxxx RW 2D-2C I / O Redirection- AIRQ14 xxx1xxxx xxxxxxxx RW 2F-2E I / O Redirection- AIRQ15 xxx1xxxx xxxxxxxx RW 31-30 I / O Redirection- AIRQ16 xxx1xxxx xxxxxxxx RW 33-32 I / O Redirection- AIRQ17 xxx1xxxx xxxxxxxx RW 35-34 I / O Redirection- AIRQ18 xxx1xxxx xxxxxxxx RW 37-36 I / O Redirection- AIRQ19 xxx1xxxx xxxxxxxx RW 39-38 I / O Redirection- AIRQ20 xxx1xxxx xxxxxxxx RW 3B-3A I / O Redirection- AIRQ21 xxx1xxxx xxxxxxxx RW 3D-3C I / O Redirection- AIRQ22 xxx1xxxx xxxxxxxx RW 3F-3E I / O Redirection- AIRQ23 xxx1xxxx xxxxxxxx RW 40-4F -reserved0000 0000 - Note: The "I / O Redirection" registers are 64-bit registers, so each uses two consecutive index locations, with the lower 32 bits at the even index and the upper 32 bits at the odd index.
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Register Overview
VT8235M Version CD V-Link South Bridge
Device 16 Function 0 Registers - USB 1.1 UHCI Ports 0-1 Configuration Space USB Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E-1F 23-20 24-2B 2D-2C 2F-2E 30-33 34 35-3B 3C 3D 3E-3F Configuration Space Header Default Acc Vendor ID RO 1106 Device ID RO 3038 Command 0000 RW Status 0210 WC Revision ID RO nn Programming Interface 00 RO Sub Class Code RO 03 Base Class Code RO 0C -reserved00 - Latency Timer 16 RW -reserved00 - USB I / O Registers Base Port Address 00000301 RW -reserved00 - Sub Vendor ID RO 1106 Sub Device ID RO 3038 -reserved00 - Power Management Capabilities RO 80 -reserved00 - Interrupt Line 00 RW Interrupt Pin RO 01 -reserved00 - Configuration Space USB-Specific Registers Offset 40 41 42 43 44-47 48 49 4A 4B-5F 60 61-7F 83-80 84 85-BF C1-C0 C2-FF USB Control USB Miscellaneous Control 1 USB Miscellaneous Control 2 USB Miscellaneous Control 3 USB Miscellaneous Control 4 -reserved- (test, do not program) USB Miscellaneous Control 5 USB Miscellaneous Control 6 USB Miscellaneous Control 7 -reservedUSB Serial Bus Release Number -reservedPM Capability PM Capability Status -reservedUSB Legacy Support -reservedDefault 40 10 03 00 00 00 00 00 00 10 00 FFC20001 00 00 2000 00 Acc RW RW RW RW - RW RW RW - RO - RO RW - RW -
Memory Mapped I / O Registers - USB Controller Offset 1-0 3-2 5-4 7-6 B-8 C 11-10 13-12 14-1F USB I / O Registers USB Command USB Status USB Interrupt Enable Frame Number Frame List Base Address Start Of Frame Modify Port 0 Status / Control Port 1 Status / Control -reservedDefault 0000 0000 0000 0000 00000000 40 0080 0080 00 Acc RW WC RW RW RW RW WC WC -
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Register Overview
VT8235M Version CD V-Link South Bridge
Device 16 Function 1 Registers - USB 1.1 UHCI Ports 2-3 Configuration Space USB Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E-1F 23-20 24-2B 2D-2C 2F-2E 30-33 34 35-3B 3C 3D 3E-3F Configuration Space Header Default Acc Vendor ID RO 1106 Device ID RO 3038 Command 0000 RW Status 0210 WC Revision ID RO nn Programming Interface 00 RO Sub Class Code RO 03 Base Class Code RO 0C -reserved00 - Latency Timer 16 RW -reserved00 - USB I / O Registers Base Port Address 00000301 RW -reserved00 - Sub Vendor ID RO 1106 Sub Device ID RO 3038 -reserved00 - Power Management Capabilities RO 80 -reserved00 - Interrupt Line 00 RW Interrupt Pin RO 02 -reserved00 - Configuration Space USB-Specific Registers Offset 40 41 42 43 44-47 48 49 4A 4B-5F 60 61-7F 83-80 84 85-BF C1-C0 C2-FF USB Control USB Miscellaneous Control 1 USB Miscellaneous Control 2 USB Miscellaneous Control 3 USB Miscellaneous Control 4 -reserved- (test, do not program) USB Miscellaneous Control 5 USB Miscellaneous Control 6 USB Miscellaneous Control 7 -reservedUSB Serial Bus Release Number -reservedPM Capability PM Capability Status -reservedUSB Legacy Support -reservedDefault 40 10 03 00 00 00 00 00 00 10 00 FFC20001 00 00 2000 00 Acc RW RW RW RW - RW RW RW - RO - RO RW - RW -
Memory Mapped I / O Registers - USB Controller Offset 1-0 3-2 5-4 7-6 B-8 C 11-10 13-12 14-1F USB I / O Registers USB Command USB Status USB Interrupt Enable Frame Number Frame List Base Address Start Of Frame Modify Port 0 Status / Control Port 1 Status / Control -reservedDefault 0000 0000 0000 0000 00000000 40 0080 0080 00 Acc RW WC RW RW RW RW WC WC -
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Register Overview
VT8235M Version CD V-Link South Bridge
Device 16 Function 2 Registers - USB 1.1 UHCI Ports 4-5 Configuration Space USB Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E-1F 23-20 24-2B 2D-2C 2F-2E 30-33 34 35-3B 3C 3D 3E-3F Configuration Space Header Default Acc Vendor ID RO 1106 Device ID RO 3038 Command 0000 RW Status 0210 WC Revision ID RO nn Programming Interface 00 RO Sub Class Code RO 03 Base Class Code RO 0C -reserved00 - Latency Timer 16 RW -reserved00 - USB I / O Registers Base Port Address 00000301 RW -reserved00 - Sub Vendor ID RO 1106 Sub Device ID RO 3038 -reserved00 - Power Management Capabilities RO 80 -reserved00 - Interrupt Line 00 RW Interrupt Pin RO 03 -reserved00 - Configuration Space USB-Specific Registers Offset 40 41 42 43 44-47 48 49 4A 4B-5F 60 61-7F 83-80 84 85-BF C1-C0 C2-FF USB Control USB Miscellaneous Control 1 USB Miscellaneous Control 2 USB Miscellaneous Control 3 USB Miscellaneous Control 4 -reserved- (test, do not program) USB Miscellaneous Control 5 USB Miscellaneous Control 6 USB Miscellaneous Control 7 -reservedUSB Serial Bus Release Number -reservedPM Capability PM Capability Status -reservedUSB Legacy Support -reservedDefault 40 10 03 00 00 00 00 00 00 10 00 FFC20001 00 00 2000 00 Acc RW RW RW RW - RW RW RW - RO - RO RW - RW -
Memory Mapped I / O Registers - USB Controller Offset 1-0 3-2 5-4 7-6 B-8 C 11-10 13-12 14-1F USB I / O Registers USB Command USB Status USB Interrupt Enable Frame Number Frame List Base Address Start Of Frame Modify Port 0 Status / Control Port 1 Status / Control -reservedDefault 0000 0000 0000 0000 00000000 40 0080 0080 00 Acc RW WC RW RW RW RW WC WC -
Revision 2.03, March 16, 2005
Register Overview
VT8235M Version CD V-Link South Bridge
Device 16 Function 3 Registers - USB 2.0 EHCI Ports 0-5 Configuration Space USB Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E-F 13-10 14-2B 2D-2C 2F-2E 30-33 34 35-3B 3C 3D 3E-3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code Cache Line Size Latency Timer -reservedEHCI Mem Mapped I / O Base Addr -reservedSub Vendor ID Sub Device ID -reservedPower Management Capabilities -reservedInterrupt Line Interrupt Pin -reservedDefault 1106 3104 0000 0210 nn 20 03 0C 00 16 00 0000 0000 00 1106 3104 00 80 00 00 04 00 Acc RO RO RW WC RO RO RO RO RW RW - RW - RO RO - RO - RW RO - Memory Mapped I / O Registers - USB EHCI Offset 00 01 03-02 07-04 0B-08 0C-0F Offset 13-10 17-14 1B-18 1F-1C 23-20 27-24 2B-28 2C-4F 53-50 57-54 5B-58 5C-FF EHCI Capabilities Capability Register Length -reservedInterface Version Number Structure Parameters Capability Parameters -reservedHost Controller Operation USB Command USB Status USB Interrupt Enable USB Frame Index 4G Segment Selector Frame List Base Address Next Asynchronous List Address -reservedConfigured Flag Register Port 1 Status / Control Port 2 Status / Control -reservedDefault 00 00 0100 0000 3206 0000 6872 00 Default 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00 0000 0000 0000 0000 0000 0000 00 Acc RW - RO RO RO - Acc RW RW RW RW RW RW RW - RW RW RW -
Configuration Space USB-Specific Registers Offset 40 41-47 48 49 4A-4B 4C-4F 50-57 58-5D 5E-5F 60 61 63-62 64-67 6B-68 6F-6C 70-7F 83-80 84 85-FF USB Control Default Acc USB Miscellaneous Control 1 00 RW -reserved- (Do Not Program) 00 - USB Miscellaneous Control 5 RW A0 USB Miscellaneous Control 6 RW 20 -reserved- (Do Not Program) 00 - -reserved00 - -reserved- (test, do not program) 00 - -reserved- (Do Not Program) 00 - -reserved00 - USB Serial Bus Release Number 20 RO Frame Length Adjust RW 20 Port Wake Capability RW 0001 -reserved00 - Legacy Support Extended Capability 0000 0001 RW Legacy Support Control / Status 0000 0000 RW -reserved00 - PM Capability FFC20001 RO PM Capability Status 00 RW -reserved00 -
Revision 2.03, March 16, 2005
Register Overview
VT8235M Version CD V-Link South Bridge
Device 17 Function 0 Registers - Bus Control & Power Management Configuration Space Bus Control & PM Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-27 28-2B 2D-2C 2F-2E 30-33 34-3B 3C 3D 3E 3F Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code -reserved- (cache line size) -reserved- (latency timer) Header Type Built In Self Test (BIST) -reserved- (base address registers) -reserved- (unassigned) Sub Vendor ID Sub Device ID -reserved- (expan. ROM base addr) -reserved- (unassigned) -reserved- (interrupt line) -reserved- (interrupt pin) -reserved- (min gnt) -reserved- (max lat) Default 1106 3177 0087 0200 nn 00 01 06 00 00 80 00 00 00 00 00 00 00 00 00 00 00 Acc RO RO RW WC RO RO RO RO -
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