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VT8235M Version South Bridge
Revision 2.03 March 2005
Copyright Notice:
Copyright 2002-2005 Technologies Incorporated. Rights Reserved. part this document reproduced, transmitted, transcribed, stored retrieval system translated into language, form means, electronic, mechanical, magnetic, optical, chemical, manual otherwise without prior written permission Technologies Incorporated. material this document information only subject change without notice. Technologies Incorporated reserves right make changes product design without reservation without notice users.
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VT8235M only used identify products Technologies. registered trademark Technologies. AMD-K7and Athlonare registered trademarks Advanced Micro Devices. CeleronTM, PentiumTM, Pentium IITM, Pentium IIITM, Pentium 4TM, MMXand Intelare registered trademarks Intel Corporation. Windows XPTM, Windows 2000TM, Windows METM, Windows 98and Plug Playare registered trademarks Microsoft Corporation. PCIis registered trademark Special Interest Group. PS/2is registered trademark International Business Machines Corporation. trademarks properties their respective owners.
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license granted, implied otherwise, under patent patent rights Technologies. Technologies makes warranties, implied otherwise, regard this document products described this document. information provided this document believed accurate reliable publication date this document. However, Technologies assumes responsibility errors this document. Furthermore, Technologies assumes responsibility misuse information this document patent infringements that arise from this document. information product specifications within this document subject change time, without notice without obligation notify person such change.
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VT8235M Version V-Link South Bridge
REVISION HISTORY
Document Release Date Revision Initials 1.21 9/27/02 Fixed names PCREQA/B PCGNTA/B descriptions 1.22 10/24/02 Fixed register references MSCK MSDT descriptions Fixed VLVREF voltage V-Link mode Removed references nonexistent ports 72-73 11/20/02 Updated Rx23-20[10], 27-24[15-11], 6F[2-0], 70[6-0], 74[4-0], 1.31 12/11/02 Fixed IORDY signal name polarity diagram; fixed minor typos lists Added strap description VAD7 description; Fixed Func Rx7C[3-0], 98[7,3] Fixed logo page heading starting page 12/17/02 Fixed first feature bullets indicate current north bridge products Improved DPSLP# description; Fixed GPO22-23, 28-29 descriptions Fixed note description; Improved description RxE5[3] 1.41 1/3/03 Updated Port (bits 3-2) Port (bits Device Function added Rx83-80; renamed Rx48-49 Device Function fixed Rx4E register name; removed RxFD Fixed Rx3C[3-0] Device Function Device Function Fixed Rx2C-2F Device Function Function 1.42 1/3/03 Fixed Device table function summary 1.43 2/5/03 Changed Device Function Rx50[0] reserved 1.44 2/5/03 Updated feature bullets indicated compatibility with ACPI 2/25/03 Updated figure block diagram; Updated defaults description table Added strap SDCS1# ballout lists added strap description table Updated Device Function Rx83 default; Removed PMIO Rx5C[1] Device Function fixed Rx50[1] name, 95[2] description 1.51 3/3/03 Fixed EEDI EEDO directions; added register cross references GPIOC-E 1.52 3/18/03 Updated GPI/GPO default states Fixed PMIO Rx30[1] cross-reference Device Function Rx84 4/15/03 Fixed Rx3D default, fixed Rx8C[7-4],8D[4]; updated PMIO Rx10[3-0] Fixed incorrect JEDEC-spec reference mechanical specification diagram 4/29/03 Added "Version product name differentiate from "Version Fixed VT8233A Version VT8235ML South Bridge part references 1.71 6/9/03 Updated Func Rx59[3-2], PMIO RxB-8[31-24], Func Rx4C 1.72 6/30/03 Changed pins AD17 1.73 9/17/03 Removed power requirements table; Updated PMIO Rx5-4[12:10] 1.74 3/3/04 Moved straps separate table; Updated Trap registers Rx5C[0] Updated Dev18 Func Rx06[7:5], 07[7:3], 08[0], 09[0], 0C[4], 0D[1:0], 23-20[7], 4340[11], 6E[5:3], 6F[5:3] 1.75 4/20/04 Updated marking Mechanical Specification section; Fixed AD7, Prosperity 1.76 5/10/04 Updated Device18 Function Rx7B 1.77 7/9/04 Added lead-free package diagram mechanical specification section 1.78 8/11/04 Updated lead-free diagram mechanical specification 1.79 8/26/04 Updated APIC Fixed Routing Table register descriptions Fixed incorrect reference Device17 Function Rx81 9/3/04 Changed part VT8235M Version 2.01 11/4/04 Updated Rx48 Rx49 Device Function Updated definition D17F0 Rx80[5]; Added D17F0 RxEC-EF 2.02 11/23/04 Updated marking mechanical specification 2.03 3/16/05 Added USBREXT signal description updated copyright notice
Revision 2.03, March 2005
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Revision History
VT8235M Version V-Link South Bridge
TABLE CONTENTS
REVISION HISTORY .III TABLE CONTENTS.IV LIST FIGURES LIST TABLES PRODUCT FEATURES. OVERVIEW. PINOUTS. DESCRIPTIONS. V-LINK DESCRIPTIONS CPU, APIC CONTROL DESCRIPTIONS MII, SERIAL EEPROM, DESCRIPTIONS USB, PROGRAMMABLE CHIP SELECT DESCRIPTIONS EIDE INTERFACE DESCRIPTIONS SERIAL AC97 DESCRIPTIONS INTERNAL KEYBOARD CONTROLLER SPEAKER DESCRIPTIONS GENERAL PURPOSE INPUT DESCRIPTIONS GENERAL PURPOSE OUTPUT GPIO DESCRIPTIONS POWER MANAGEMENT EVENT DETECTION DESCRIPTIONS CLOCK, RESETS, POWER STATUS, POWER GROUND DESCRIPTIONS STRAP DESCRIPTIONS REGISTERS. REGISTER OVERVIEW REGISTER DESCRIPTIONS Legacy Ports
Keyboard Controller Registers. Controller Registers Interrupt Controller Registers. Timer Counter Registers. CMOS Registers.
Keyboard Mouse Wakeup Index Data Registers. Keyboard Mouse Wakeup Registers. Memory Mapped APIC Registers Indexed APIC Registers Configuration Space Device Function Registers UHCI Ports
Configuration Space Header. USB-Specific Configuration Registers. Registers
Device Function Registers UHCI Ports
Configuration Space Header. USB-Specific Configuration Registers.
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Table Content
VT8235M Version V-Link South Bridge
Registers
Device Function Registers UHCI Ports
Configuration Space Header. USB-Specific Configuration Registers. Registers
Device Function Registers EHCI.
Configuration Space Header. USB-Specific Configuration Registers. EHCI Registers.
Device Function Registers Control Power Management.
Configuration Space Header. Control Miscellaneous Control. Function Control. Serial IRQ, LPC, PC/PCI Control Plug Play Control GPIO Miscellaneous Control. Programmable Chip Select Control Decoding Control. Power Management-Specific Configuration Registers. System Management Bus-Specific Configuration Registers GPIO Slave Command Codes General Purpose Control Registers Watchdog Timer Registers Power Management I/O-Space Registers System Management I/O-Space Registers.
Device Function Registers Enhanced Controller.
Configuration Space Header. IDE-Controller-Specific Configuration Registers Power Management Registers. Back Door Registers Registers
Device Function Registers AC97 Audio Controller.
Configuration Space Header. Audio-Specific Configuration Registers. Base Regs Audio Scatter Gather
Device Function Registers AC97 Modem Controller
Configuration Space Header. Modem-Specific Configuration Registers Base Regs Modem Scatter Gather DMA.
Device Function Registers
Configuration Space Header. LAN-Specific Configuration Registers Registers.
FUNCTIONAL DESCRIPTIONS POWER MANAGEMENT
Power Management Subsystem Overview Processor States. System Suspend States Power Plane Control. General Purpose Ports Power Management Events System Processor Resume Events. Legacy Power Management Timers System Primary Secondary Events Peripheral Events.
ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS. REGISTER BITS POWERED VBAT Revision 2.03, March 2005 -vTable Content
VT8235M Version V-Link South Bridge
REGISTER BITS POWERED VSUS25 PACKAGE MECHANICAL SPECIFICATIONS.
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Table Content
VT8235M Version V-Link South Bridge
LIST FIGURES
FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE SYSTEM CONFIGURATION USING VT8235M VERSION BALL DIAGRAM (TOP VIEW). POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM. SYSTEM BLOCK DIAGRAM USING P4X400 NORTH BRIDGE MECHANICAL SPECIFICATIONS BALL GRID ARRAY PACKAGE LEAD-FREE MECHANICAL SPECIFICATIONS BALL GRID ARRAY PACKAGE
LIST TABLES
TABLE LIST (NUMERICAL ORDER) TABLE LIST (ALPHABETICAL ORDER) TABLE MEMORY MAPPED REGISTERS TABLE FUNCTION SUMMARY. TABLE SYSTEM MAP. TABLE REGISTERS TABLE KEYBOARD CONTROLLER COMMAND CODES TABLE CMOS REGISTER SUMMARY TABLE APIC FIXED ROUTING TABLE ROUTING TABLE
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Table Content
VT8235M Version V-Link South Bridge
VT8235M VERSION
COST V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE HIGH BANDWIDTH V-LINK CLIENT CONTROLLER INTEGRATED FAST ETHERNET, INTEGRATED DIRECT SOUND AC97 AUDIO, ULTRADMA-133/100/66/33 MASTER MODE EIDE CONTROLLER, PORT CONTROLLER, KEYBOARD MOUSE CONTROLLER, RTC, LPC, SMBUS, SERIAL IRQ, PLUG PLAY, ACPI, PC2001 COMPLIANT ENHANCED POWER MANAGEMENT
PRODUCT FEATURES
Inter-operable with Host-to-V-Link Host Controller Combine with KT400A North Bridge complete Athlon system Combine with CLE266 North Bridge complete Pentium system Combine with P4X400 North Bridge complete Pentium system High Bandwidth MB/s 8-bit V-Link Client Controller Supports V-Link Client interface with total bandwidth MB/sec V-Link operates modes Full duplex commands with separate Strobe Command Request Data split transaction Configurable outstanding transaction queue V-Link Client accesses Auto Client Retry eliminate V-Link Host-Client Retry cycles Intelligent V-Link transaction protocol eliminate data wait-state throttle transfer latency; V-Link transactions Highly efficient V-Link arbitration with minimum overhead; V-Link transactions have predictable cycle length Auto connect reconnect capability dynamic stop minimum power consumption Parity checking insure correct data transfers
with known Command Data duration both Host Client have consistent view transaction data depth buffer size avoid data overflow.
Integrated Peripheral Controllers Integrated Fast Ethernet Controller with Mbit capability Integrated Controller with three root hubs function ports Dual channel UltraDMA-133 master mode EIDE controller AC-link interface AC-97 audio codec modem codec modem support Integrated DirectSound compatible digital audio controller interface Count interface Super-I/O Integrated Legacy Functions Integrated Keyboard Controller with mouse support Integrated DS12885-style Real Time Clock with extended byte CMOS Day/Month Alarm ACPI Integrated DMA, timer, interrupt controller Serial docking non-docking applications Fast reset Gate operation
-1Product Feature
Revision 2.03, March 2005
VT8235M Version V-Link South Bridge Concurrent Controller operation Supports masters Peer concurrency Concurrent multiple master transactions; i.e., allow masters from both buses active same time Zero wait state master slave burst transfer rate system memory data streaming 132Mbyte/sec (data sent north bridge high speed V-Link
Interface) master snoop ahead snoop filtering Eight posted write buffers Byte merging write buffers reduce number cycles create further bursting possibilities Enhanced command optimization (MRL, MRM, MWI, etc.) Four lines post write buffers from masters DRAM Sixteen levels (double-words) prefetch buffers from DRAM access masters Delay transaction from master accessing DRAM Transaction timer fair arbitration between masters (granularity clocks) Symmetric arbitration between Host/PCI optimized system performance Complete steerable interrupts PCI-2.2 compliant, 3.3V interface with tolerant inputs
Fast Ethernet Controller High performance master interface with scatter gather bursting capability Standard interface external PHYceiver full half duplex operation Independent byte FIFOs receive transmit Flexible dynamically loadable EEPROM algorithm Physical, Broadcast, Multicast address filtering using hashing function Magic packet wake-on-address filtering Software controllable power down UltraDMA-133 Master Mode EIDE Controller Dual channel master mode hard disk controller supporting four Enhanced devices Transfer rate 133MB/sec cover mode multi-word mode drives, UltraDMA-133 interface Increased reliability using UltraDMA-133/100/66 transfer protocols Thirty-two levels (doublewords) prefetch write buffers Dual engine concurrent dual channel operation master programming interface SFF-8038i rev.1.0 Windows-95 compliant Full scatter gather capability Support ATAPI compliant devices including devices Support native compatibility modes Complete software driver support Direct Sound Ready AC97 Digital Audio Controller AC-Link access CODECs (AC97 AMC97 MC97) Multichannel Audio Master Scatter Gather Dedicated read write channels supporting simultaneous stereo playback record Dedicated read write channels supporting simultaneous modem receive transmit stereo DirectSound channel with source volume control mixer shared SPDIF read channel dedicated channel supporting multi-channel audio 32-byte line-bufers each channel Programmable 8bit 16bit mono stereo data format support AC97 compliant
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Product Feature
VT8235M Version V-Link South Bridge System Management Interface Host interface processor communications Slave interface external SMBus masters Universal Serial Controller v2.0 Enhanced Host Controller Interface (EHCI) v1.0 compatible v1.1 Universal Host Controller Interface (UHCI) v1.1 compatible Eighteen level (doublewords) data FIFO with full scatter gather capability Three root hubs function ports Integrated physical layer transceivers with optional over-current detection status inputs Legacy keyboard PS/2 mouse support Sophisticated PC2001-Compatible Mobile Power Management Supports both ACPI (Advanced Configuration Power Interface) legacy (APM) power management ACPI v2.0 Compliant v1.2 Compliant clock throttling clock stop control complete ACPI state support clock run, Power Management Enable (PME) control, PCI/CPU clock generator stop control Supports multiple system suspend types: power-on suspends with flexible CPU/PCI reset options,
suspend DRAM, suspend disk (soft-off), with hardware automatic wake-up Multiple suspend power plane controls suspend status indicators idle timer, peripheral timer general purpose timer, plus 24/32-bit ACPI compliant timer Normal, doze, sleep, suspend conserve modes Global local device power control System event monitoring with event classes Primary secondary interrupt differentiation individual channels Dedicated input pins power sleep buttons, external modem ring indicator, notebook open/close system wake-up general purpose input ports output ports Multiple internal external sources flexible power management models Enhanced integrated real time clock (RTC) with date alarm, month alarm, century field Thermal alarm external temperature sensing circuit leakage control
Plug Play Controller interrupts steerable interrupt channel Steerable interrupts integrated peripheral controllers: USB, floppy, serial, parallel, audio Microsoft Windows XPTM, Windows NTTM, Windows 2000TM, Windows 98and plug play BIOS compliant Built-in NAND-tree scan test capability 0.22um, 2.5V, power CMOS process Single chip ball pitch,
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Product Feature
VT8235M Version V-Link South Bridge
OVERVIEW
VT8235M Version South Bridge high integration, high performance, power-efficient, high compatibility device that supports Intel non-Intel based processor V-Link bridge functionality make complete Microsoft PC2001compliant PCI/LPC system. VT8235M Version includes standard intelligent peripheral controllers: IEEE 802.3 compliant Mbps master Ethernet with standard interface external PHYceiver. Master mode enhanced controller with dual channel engine interlaced dual channel commands. Dedicated FIFO coupled with scatter gather master mode operation allows high performance transfers between devices. addition standard mode operation, VT8235M Version also supports UltraDMA133, 100, standards allow reliable data transfer rates MB/sec. controller SFF-8038i v1.0 Microsoft Windows-family compliant. Universal Serial controller that v2.0 Universal v2.0 compliant. VT8235M Version includes three root hubs with function ports with integrated physical layer transceivers. controller allows plug play isochronous peripherals inserted into system with universal driver support. controller also implements legacy keyboard mouse support that legacy software transparently non-USB-aware operating system environment. Keyboard controller with mouse support. Real Time Clock with byte extended CMOS. addition standard functionality, integrated also includes date alarm, century field, other enhancements compatibility with ACPI standard. Notebook-class power management functionality compliant with ACPI legacy requirements. Multiple sleep states (power-on suspend, suspend-to-DRAM, suspend-to-Disk) supported with hardware automatic wake-up. Additional functionality includes event monitoring, clock throttling stop (Intel processor protocol), clock stop control, modular power, clock leakage control, hardware-based software-based event handling, general purpose I/O, chip select external SMI. Full System Management (SMBus) interface. Integrated bus-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Plug Play controller that allows complete steerability interrupts internal interrupts channels interrupt channel. additional steerable interrupt channel provided allow plug play reconfigurability onboard peripherals Windows family compliance. VT8235M Version also enhances functionality standard peripherals. integrated interrupt controller supports both edge level triggered interrupts channel channel. integrated controller supports type addition standard modes. Compliant with PCI-2.2 specification, VT8235M Version supports delayed transactions remote power management that slower peripherals block traffic bus. Special circuitry built allow concurrent operation without causing dead lock even PCI-to-PCI bridge environment. chip also includes eight levels (doublewords) line buffers from further enhance overall system performance.
Revision 2.03, March 2005
Overview
VT8235M Version V-Link South Bridge
Cache Sideband Signals Init A20M# INTR StopClk FERR IGNNE Sleep Boot Onboard
North Bridge Vlink Interface
MA/Command
System Memory DIMM Module
Expansion Cards
VT8235M
Primary Secondary Ports Keyboard Mouse AC97 Link APIC GPIO, Power Control, Reset Fast Ethernet Interface
Crystal
Figure System Configuration Using VT8235M Version
Revision 2.03, March 2005
Overview
VT8235M Version V-Link South Bridge
PINOUTS
Figure Ball Diagram (Top View)
RDY# SEL#
FRM# RDY# REQ5# GPI7 GNT5# GPO7 VSUS VSUS LOW# THRM# VSUS VSUS VSUS
AD17 AD16 VSUS RST# GPIO RUN#
GPIO AD19 AD18
GPIO
VCC25 VCC25
OC4# OC5#
OC0# OC1# OC2# VSUS OC3#
IOW#
UPLL UPLL APIC VREF
UPLL UPLL REXT VREF COMP INTR APIC APIC COMP
GHI# SMI# CS1# CS3# IOR#
INIT# A20M# SLP# IOW#
STB# STB# SLP# CLK# FERR# DAK#
SERR# PERR# STOP# AD11 AD10 AD20 AD27 AD29 SYNC SDI3 MISS SMI# LID# AD15 AD13 AD22 AD24 AD26 AD31 RST# SDI0 SDI2 RING# ALRT# BTN# AD14 AD12 AD21 AD23 AD25 AD28 AD30 RST# BTCK SDI1 PME# TRUD#
GPIO GPIO GPIO VGATE GPIO8 GPIO GPIO
GPIO GPIO GPIO STP#
GPIO
Pins
Pins
Pins
Pins AC97 Pins
V-Link Pins Pins
KB/MS Pins
STP# REQ# FRM#
AA20
Pins Pins
X-Bus
IOW# SPKR strap TEST
Pins
SOE# strap ROMCS #/strap
SDD1 SA01 SDD2 SA02
Pins
VREF SDD4 SA04 SDD3 SA03
Pins
SDD5 SA05 SDD7 SA07 SDD6 SA06
IOR#
SA19 strap SA18 strap SA17 strap SA16 strap
COMP SDD0 SA00
SDD9 SA09 SDD8 SA08
SDA1 SDCS1# strap strap SDCS3# DAK# strap SDA0 strap IOR# SDA2 strap
SDD10 SDD13 SA10 SA13 SDD12 SDD15 SA12 SA15 SDD11 SDD14 SA11 SA14
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Diagram
VT8235M Version V-Link South Bridge
Table List (Numerical Order)
Name Name Name Name
AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Name
RTCX1 RSMRST# GPIOD GPIO30 LREQ# LAD2 IOW# IORDY GPI19 SA18 strap SOE# strap SDRDY SDD01 SA01 SDD05 SA05 SDD09 SA09 SDD10 SA10 SDD13 SA13 SDDACK# SDCS3# strap PDD09 PDD05 PDD10 SMBCK2 PWROK# GPI0 VBAT GPIOA GPIO24 GPIOC GPIO25 LFRM# LAD1 SPKR strap SERIRQ SA17 strap MEMR# SDDRQ SDD04 SA04 SDD07 SA07 SDD12 SA12 SDD15 SA15 SDA0 strap IRQ14 PDD06 SUSC# SUSB# GPO2 RTCX2 PWRGD PCKRUN# PCISTP# GPO6 LAD3 LAD0 TEST MEMW# SA16 strap ROMCS#/KBCS#/ SDD00 SA00 SDD02 SA02 SDD03 SA03 SDD06 SA06 SDD08 SA08 SDD11 SA11 SDD14 SA14 SDIOR# SDA2 strap IRQ15 PDD07 PDD08
AD05 USBVCC AD02 SLP# USBVCC AD00 FERR# TRDY# USBVCC ACSDI3 /IO21/PCS1# /SB# CBE2# CBE1# REQ3# AD17 AD15 VAD12 KBDT KBRC GPIO11 KBCK A20G GPIO12 INTE# PCGNTA REQ2# UPSTB AGPBZ# GPI6 GNT1# APICD1 MRXD3 REQ0# UPSTB# AD03 MRXERR GPIO10 PDCS1# AD01 MTXD1 GPIO14 INTG# PDA1 AD21 MTXCLK MRXD2 PDA2 EECS# MRXD1 GNT3# MSDT IRQ12 EEDO VAD14 MSCK IRQ1 MIIVCC USBOC0# PME# MIIVCC VLVREF DNCMD BATLOW# GPI5 MIIVCC25 USBGND USBP4+ USBOC4# VAD03 VAD02 USBGND VSUSUSB PDCOMP AD20 USBP2+ PDCS3# USBGND AD22 USBP5- USBGND AD23 USBP0+ PDDACK# USBGND USBP3- CPUMISS GPI17 USBGND VAD15 RING# GPI3 VCCUPLL USBGND USBP1- SUSST1# GPO3 USBVCC VLCOMP VAD06 THRM# GPI18 USBVCC VCCUPLL USBCLK UPCMD PDDRQ USBVCC VAD07 PDA0 USBVCC CBE3# VAD08 PDIOR# DEVSEL# AD24 VPAR PDIOW# FRAME# AD11 AD25 PDRDY AA01 EXTSMI# GPI2 AD16 AD13 REQ4# AD19 AD14 AA02 SUSA# GPO1 GPIO9 PCREQB GNT2# VCLK AA03 GPO0 GPIO13 INTF# PCGNTB GNT0# AA04 VSUS33 MDIO VBE1# AA22 PDD15 RAMVCC AD27 AA23 MRXCLK RAMGND AD26 MTXD2 AA24 PDD00 AD28 MTXENA MRXD0 AA25 PDD01 MCRS GNT4# AA26 PDD14 MIIVCC EEDI AD29 AB01 SUSCLK GPO4 MIIVCC AD31 USBOC1# MIIVCC25 AB02 SMBALRT# AD30 USBOC5# AB03 SMBCK1 USBGND USBP4- USBOC3# REQ5# GPI7 AB04 VSUS33 AB22 INTA# USBGND USBP2- USBP5+ INTB# AB23 PDD12 INTC# AB24 PDD02 USBGND USBGND AB25 USBP0- USBP3+ GNT5# GPO7 AB26 PDD13 USBGND USBGND PLLVCC USBP1+ AC01 LID# GPI4 GNDUPLL PLLGND VRDPSLP GPIO29 AC02 SMBDT1 USBVCC GNDUPLL VIDSEL GPIO28 AC03 GPI1 USBVCC DPSLP# GPIO23 VAD05 USBVCC AC04 VSUS33 SERR# INTD# AC05 VSUS33 PERR# VAD04 PCIRST# AC06 GPIOE GPIO31 AD10 ACRST# AC07 CPUSTP# GPO5 STOP# AD09 IRDY# AC08 AD12 REQ1# PCICLK AC09 AD18 CBE0# AC10 IOR# GHI# GPIO22 GPIO15 INTH# AC11 SA19 strap USBGND VGATE GPIO8 PCREQA USBGND INIT# AC12 MDCK STPCLK# AC13 USBGND ACSYNC MRXDV AC14 USBGND ACSDIN0 MTXD3 VAD09 AC15 SDCOMP ACBITCLK MTXD0 VBE0# AC16 MCOL VAD00 VSUS25 AC17 EECK APICD0 VAD01 AC20 AD07 USBOC2# INTR AC21 SDIOW# AD06 SMI# AC22 SDA1 strap USBGND AD04 A20M# AC23 SDCS1# strap USBGND AD08 IGNNE# AC24 PDD04 USBGND ACSDOUT VAD11 AC25 PDD11 USBGND ACSDI2 /IO20/PCS0# AC26 PDD03 VAD10 USBGND ACSDIN1 VAD13 AD01 SMBDT2 GPIO26 USBGND DNSTB AD02 PWRBTN# USBGND VSUS25 DNSTB# APICCLK USBREXT AD03 INTRUD# GPI16 pins pins): F6,11, L11-16, M11-16, N5,11-16, P11-16, R11-16, T11-16, V21, W21, AA5, AB5,12-13,18-19 pins pins): F9-10,14-15, J5,21, K5,21, T5,21, U5,21-22, AB8-9,16-17 VCC33 pins pins): F5,7-8,12-13,16-17, P5,21, R5,21, Y5,21, AA21, AB6-7,10-11,14-15,20-21 VCCVK pins pins): F22, G21, H21, L21-22, M21-26, N21-26
Revision 2.03, March 2005
Lists
VT8235M Version V-Link South Bridge
Table List (Alphabetical Order)
Name Name Name Name
AE04 AA04 AB04 AC04 AC05 AC14 AC13 AF14 AE14 AD14 AF13 AE13 AD13
Name
USBGND USBGND USBGND USBOC0# USBOC1# USBOC2# USBOC3# USBOC4# USBOC5# USBP0- USBP0+ USBP1- USBP1+ USBP2- USBP2+ USBP3- USBP3+ USBP4- USBP4+ USBP5- USBP5+ USBREXT USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC USBVCC VAD00 VAD01 VAD02 VAD03 VAD04 VAD05 VAD06 VAD07 VAD08 VAD09 VAD10 VAD11 VAD12 VAD13 VAD14 VAD15 VBAT VBE0# VBE1# VCCUPLL VCCUPLL VCLK VGATE/GPIO8/PCRA VIDSEL GIO28 VLCOMP VLVREF VPAR VRDPSLP/GPIO29 VSUS25 VSUS25 VSUS33 VSUS33 VSUS33 VSUS33 VSUSUSB
A20M# MIIVCC25 AC11 SA19 strap ACBITCLK AE23 SDA0 strap MRXCLK ACRST# MRXD0 AC22 SDA1 strap ACSDIN0 MRXD1 AF23 SDA2 strap ACSDIN1 MRXD2 AC15 SDCOMP ACSDI2 /IO20/PCS0# MRXD3 AC23 SDCS1# strap ACSDI3 /IO21/PCS1# /SLPB# MRXDV AD23 SDCS3# strap ACSDOUT AA23 MRXERR AF15 SDD00 SA00 ACSYNC AB22 AD16 SDD01 SA01 MSCK IRQ1 AD00 AB25 AF16 SDD02 SA02 MSDT IRQ12 AD01 AF17 SDD03 SA03 MTXCLK AC08 AD02 MTXD0 AE17 SDD04 SA04 AC09 AD03 MTXD1 AD18 SDD05 SA05 AC16 AD04 MTXD2 AF18 SDD06 SA06 AC17 AD05 MTXD3 AE18 SDD07 SA07 AC20 AD06 MTXENA AF19 SDD08 SA08 AE16 AD07 AD19 SDD09 SA09 AE19 AD08 AD20 SDD10 SA10 AD17 AE22 AD09 AF20 SDD11 SA11 AE25 AD10 AC12 AE20 SDD12 SA12 GNDUPLL AD11 AD21 SDD13 SA13 GNDUPLL AD12 GNT0# AF05 PCKRUN# AF21 SDD14 SA14 AD13 AE21 SDD15 SA15 GNT1# PCICLK AD14 GNT2# PCIRST# AD22 SDDACK# AD15 GNT3# AF06 PCISTP# GPO6 AE15 SDDRQ AD16 GNT4# PDA0 AF22 SDIOR# AD17 GNT5# GPO7 PDA1 AC21 SDIOW# AD18 AE03 GPI0 PDA2 AD15 SDRDY AD19 AC03 GPI1 AE10 SERIRQ PDCOMP AD20 PDCS1# SERR# GPIO9 PCREQB AD21 GPIO10 PDCS3# SLP# AD22 GPIO11 AA24 PDD00 AB02 SMBALRT# AD23 GPIO12/INTE#/PCGA AA25 PDD01 AB03 SMBCK1 AD24 GPIO13/INTF#/PCGB AB24 PDD02 AE01 SMBCK2 GPIO27 AD25 GPIO14 INTG# AC26 PDD03 AC02 SMBDT1 AD26 GPIO15 INTH# AC24 PDD04 AD01 SMBDT2 GPIO26 AD27 AE05 GPIOA GPIO24 AD25 PDD05 SMI# AD28 AE06 GPIOC GPIO25 AE26 PDD06 AD12 SOE# strap AD29 AD06 GPIOD GPIO30 AF25 PDD07 AE09 SPKR strap AD30 AC06 GPIOE GPIO31 AF26 PDD08 STOP# AD31 AA03 GPO0 AD24 PDD09 STPCLK# AGPBZ# GPI6 IGNNE# AD26 PDD10 AA02 SUSA# GPO1 APICCLK INIT# AC25 PDD11 AF02 SUSB# GPO2 APICD0 INTA# AB23 PDD12 AF01 SUSC# APICD1 INTB# AB26 PDD13 AB01 SUSCLK GPO4 BATLOW# GPI5 INTC# AA26 PDD14 SUSST1# GPO3 CBE0# INTD# AA22 PDD15 AF09 TEST CBE1# INTR PDDACK# THRM# GPI18 CBE2# AD03 INTRUD# GPI16 PDDRQ CBE3# AC10 IOR# PDIOR# TRDY# CPUMISS GPI17 AD10 IORDY GPI19 PDIOW# UPCMD AC07 CPUSTP# GPO5 AD09 IOW# PDRDY UPSTB DEVSEL# IRDY# PERR# UPSTB# DNCMD USBCLK AE24 IRQ14 PLLGND DNSTB AF24 IRQ15 PLLVCC USBGND DNSTB# KBCK A20G PME# USBGND DPSLP# GPIO23 KBDT KBRC AD02 PWRBTN# USBGND EECK AF08 LAD0 AF04 PWRGD USBGND EECS# AE08 LAD1 AE02 PWROK# USBGND EEDI AD08 LAD2 RAMGND USBGND EEDO AF07 LAD3 RAMVCC USBGND AA01 EXTSMI# GPI2 AE07 LFRM# REQ0# USBGND FERR# AC01 LID# GPI4 REQ1# USBGND FRAME# REQ2# AD07 LREQ# USBGND GHI# GPIO22 MCOL REQ3# USBGND MCRS REQ4# USBGND REQ5# GPI7 MDCK USBGND MDIO RING# GPI3 USBGND AE12 MEMR# AF12 ROMCS#/KBCS#/str USBGND AF10 MEMW# AD05 RSMRST# USBGND AD04 RTCX1 MIIVCC USBGND AF03 RTCX2 MIIVCC USBGND AF11 SA16 strap USBGND MIIVCC AE11 SA17 strap USBGND MIIVCC MIIVCC25 AD11 SA18 strap USBGND pins pins): F6,11, L11-16, M11-16, N5,11-16, P11-16, R11-16, T11-16, V21, W21, AA5, AB5,12-13,18-19 pins pins): F9-10,14-15, J5,21, K5,21, T5,21, U5,21-22, AB8-9,16-17 VCC33 pins pins): F5,7-8,12-13,16-17, P5,21, R5,21, Y5,21, AA21, AB6-7,10-11,14-15,20-21 VCCVK pins pins): F22, G21, H21, L21-22, M21-26, N21-26
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Lists
VT8235M Version V-Link South Bridge
DESCRIPTIONS
V-Link Descriptions V-Link Interface
Signal Name VAD[15:0] K22, J22, G24, H22, G22, G23, F23, D25, K26, K24, E24, E26, J25, J26, F26, Signal Description Address Data Bus. Bits implemented bits 8-15 reserved future use. VAD[7:0] used send strap information chipset north bridge. power VAD7 reflects state strap SDCS3#, VAD[6:4] reflect state straps pins SDA[2:0] VAD[3:0] reflect state straps pins SA[19:16]. specific interpretation these straps north bridge chip design dependent. Parity. VPAR function implemented compatible manner north bridge, this should connected north bridge VPAR (P4X333, P4X400, P4X800, KT400). VPAR implemented north bridge chip incompatible with 8235 V-Link north bridges) connect this 8.2K pullup 2.5V (Pro266, Pro266T, KT266, KT266A, KT333, P4X266, PN266, KN266, KM266, P4M266, P4N266). note AN222 details. Byte Enables. VBE0# used with VAD[7-0] VBE1# used with VAD[15-8] (VBE1# VAD[15-8] reserved future use). V-Link Clock. Command from Client-to-Host. Command from Host-to-Client. Strobe from Client-to-Host. Complement Strobe from Client-to-Host. Strobe from Host-to-Client. Complement Strobe from Host-to-Client. V-Link Compensation.
VPAR
VBE[1:0]# VCLK UPCMD DNCMD UPSTB UPSTB# DNSTB DNSTB# VLCOMP
L26,
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Descriptions
VT8235M Version V-Link South Bridge CPU, APIC Control Descriptions Interface
Signal Name A20M# Signal Description Mask. Connect mask input control address bit-20 generation. Logical combination A20GATE input (from internal external keyboard controller) Port bit-1 (Fast_A20). Numerical Coprocessor Error. This signal tied coprocessor error signal FERR# CPU. Internally generates interrupt active. Output voltage swing programmable 1.5V 2.5V Device Function Rx67[2]. Ignore Numeric Error. This connected "ignore error" pin. IGNNE# Initialization. VT8235M Version asserts INIT# detects shut-down special INIT# cycle soft reset initiated register Interrupt. INTR driven VT8235M Version signal that INTR interrupt request pending needs service. Non-Maskable Interrupt. used force non-maskable interrupt CPU. VT8235M Version generates when SERR# asserted. Sleep. Used sleep. SLP# System Management Interrupt. SMI# asserted VT8235M Version SMI# response different Power-Management events. Stop Clock. STPCLK# asserted VT8235M Version throttle STPCLK# processor clock. Note: Connect each above signals pullup resistors VCC_CMOS (see Design Guide).
Advanced Programmable Interrupt Controller (APIC) Interface
Signal Name APICD1 APICD0 APICCLK Signal Description Internal APIC Data Function Rx58[6] Internal APIC Data Function Rx58[6] APIC Clock.
Speed Control Interface
Signal Name VGATE GPI8 GPO8 PCREQA VIDSEL GPI2 GPO2 VRDSLP GPI29 GPO29 GHI# GPI22 GPO22 DPSLP# GPI23 GPO23 CPUMISS GPI17 Signal Description Voltage Gate. Signal from voltage regulator. High indicates voltage regulator output stable. This performs VGATE function Device Function Rx53[7] E5[4] E4[3] Voltage Regulator Select. Connected voltage regulator. selects voltage from CPU; high selects different fixed voltage (the lower voltage used deep sleep mode). This performs VIDSEL function Func RxE5[3] Voltage Regulator Deep Sleep. Connected voltage regulator. High selects proper voltage deep sleep mode. This performs VRDPSLP function Function RxE5[3] Speed Select. Connected voltage regulator, used select high speed speed (H). This performs GHI# function Function RxE5[3] Deep Sleep. This performs DPSLP# function Device Function RxE5[3]=0. Missing. Used detect physical presence chip socket. High indicates present. Connect CPUMISS socket. state this read SMBus registers. This used CPUMISS GPI17 same time. Busy. indicates that master cycle progress (CPU speed transitions will postponed this input asserted low). Connected AGPBZ# pin. -10Pin Descriptions
AGPBZ# GPI6
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VT8235M Version V-Link South Bridge Interface
Signal Name AD[31:0] CBE[3:0]# DEVSEL# (see list) Signal Description Address Data Bus. Multiplexed address data. address driven with FRAME# assertion data driven received following cycles. Command Byte Enable. command driven with FRAME# assertion. Byte enables corresponding supplied requested data driven following clocks. Device Select. VT8235M Version asserts this signal claim transactions through positive subtractive decoding. input, DEVSEL# indicates response VT8235M Version CD-initiated transaction also sampled when decoding whether subtractively decode cycle. Frame. Assertion indicates address phase transfer. Negation indicates that more data transfer desired cycle initiator. Initiator Ready. Asserted when initiator ready data transfer. Target Ready. Asserted when target ready data transfer. Stop. Asserted target request master stop current transaction. System Error. SERR# pulsed active device that detects system error condition. Upon sampling SERR# active, VT8235M Version programmed generate CPU. Parity. single parity provided over AD[31:0] C/BE[3:0]#. Interrupt Request. INTA# through INTD# pins typically connected INTA#-INTD# pins table below. INTE-H# enabled setting Device Function Rx5B[1] BIOS settings must match physical connection method. INTA# INTB# INTC# INTD# Slot INTA# INTB# INTC# INTD# Slot INTB# INTC# INTD# INTE# Slot INTC# INTD# INTE# INTF# Slot INTD# INTE# INTF# INTG# Slot INTE# INTF# INTG# INTH# Slot INTF# INTG# INTH# INTA#
FRAME# IRDY# TRDY# STOP# SERR# INTA# INTB# INTC# INTD# INTE# GPI12, GPO12, PCGNTA, INTF# GPI13, GPO13, PCGNTB, INTG# GPI14, GPO14, INTH# GPI15, GPO15 REQ5# GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0# GNT5# GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0# PCIRST# PCICLK PCKRUN#
Request. These signals connect VT8235M Version from each slot each master) request bus. REQ5#, Function RxE4 must otherwise this will function General Purpose Input
Grant. These signals driven VT8235M Version grant access specific master. GNT5#, Function RxE4 must otherwise this will function General Purpose Output
Reset. This signal used reset devices attached bus. Clock. This signal provides timing transactions Bus. Clock Run. This signal indicates whether clock will stopped (high) running (low). VT8235M Version drives this signal when clock running (default reset) releases when stops clock. External devices assert this signal request that clock restarted prevent from stopping. Connect this ground using resistor function used. Refer "PCI Mobile Design Guide" applicable North Bridge Design Guide (e.g., KT400, CLE266, P4X400) more details.
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Descriptions
VT8235M Version V-Link South Bridge MII, Serial EEPROM, Descriptions Controller Media Independent Interface (MII)
Signal Name MCOL MCRS MDCK MDIO MRXCLK MRXD[3-0] MRXDV MRXERR MTXCLK MTXD[3-0] MTXENA MIIVCC MIIVCC25 RAMVCC RAMGND D10, C11, B11, A11, D11, D12, E11, D13, Power Power Power Power Signal Description Collision Detect. From external PHY. Carrier Sense. Asserted external when media active. Management Data Clock. Sent external timing reference MDIO Management Data I/O. Read from written bit. Receive Clock. clock recovered PHY. Receive Data. Parallel receive data lines driven external synchronous with MRXCLK. Receive Data Valid. Receive Error. Asserted when detects data decoding error. Transmit Clock. Always active clock supplied PHY. Transmit Data. Parallel transmit data lines synchronized MTXCLK. Transmit Enable. Signals that transmit active from port PHY. Interface Power. 3.3V ±5%. Suspend Power. 2.5V ±5%. Power Internal RAM. 2.5V ±5%. Ground Internal RAM.
Serial EEPROM Interface
Signal Name Signal Description EECS# Serial EEPROM Chip Select. EECK Serial EEPROM Clock. Serial EEPROM Data Output. Connect EEPROM Data pin. EEDO Serial EEPROM Data Input. Connect EEPROM Data pin. EEDI These pins disabled SDCS1# strapped enable serial EEPROM connection interface.
Count (LPC) Interface
Signal Name Signal Description LFRM# Frame. LREQ# Master Request. AF7, AD8, AE8, Address Data. LAD[3-0] Note: Connect interface LPCRST# (LPC Reset) signal PCIRST#
Signal Name PCREQA GPI8 GPO8 VGATE PCREQB GPI9 GPO9 PCGNTA GPI12 GPO12 PCGNTB GPI13 GPO13 Revision 2.03, March 2005 Signal Description Request Device Function Rx53[7] Request Device Function Rx53[7] Grant Device Function Rx53[7] Grant Device Function Rx53[7] -12Pin Descriptions
VT8235M Version V-Link South Bridge USB, Programmable Chip Select Descriptions Universal Serial Interface
Signal Name USBP0+ USBP0- USBP1+ USBP1- USBP2+ USBP2- USBP3+ USBP3- USBP4+ USBP4- USBP5+ USBP5- USBCLK USBREXT USBOC0# USBOC1# USBOC2# USBOC3# USBOC4# USBOC5# USBVCC USBGND VSUSUSB VCCUPLL GNDUPLL (see list) (see list) A23, B23, Power Power Power Power Power Signal Description Port Data Port Data Port Data Port Data Port Data Port Data Port Data Port Data Port Data Port Data Port Data Port Data Clock. 48MHz clock input interface External Resistor. Port Over Current Detect. Port disabled low. Port Over Current Detect. Port disabled low. Port Over Current Detect. Port disabled low. Port Over Current Detect. Port disabled low. Port Over Current Detect. Port disabled low. Port Over Current Detect. Port disabled low. Port Differential Output Interface Logic Voltage. 3.3V Port Differential Output Interface Logic Ground. Suspend Power. 2.5V ±5%. Analog Voltage. 2.5V ±5%. Analog Ground.
System Management (SMB) Interface (I2C Bus)
Signal Name SMBCK1 SMBCK2 GPI27 GPO27 SMBDT1 SMBDT2 GPI26 GPO26 SMBALRT# Signal Description Channel Clock. Channel Clock. Rx95[2] Channel Data. Channel Data. Rx95[2] Alert. (enabled System Management space Rx08[3] When chip enabled allow assertion generates interrupt power management resume event. Connect pullup VSUS33 used.
Programmable Chip Selects
Signal Name PCS0# GPIO20 ACSDIN2 PCS1# GPIO21 ACSDIN3 SLPBTN# Signal Description Programmable Chip Select RxE4[6]=1, E5[1]=1 Programmable Chip Select RxE4[6]=1, E5[2]=1
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Descriptions
VT8235M Version V-Link South Bridge EIDE Interface Descriptions UltraDMA-133 Enhanced Interface
Signal Name PDRDY PDDMARDY PDSTROBE SDRDY SDDMARDY SDSTROBE PDIOR# PHDMARDY PHSTROBE SDIOR# SHDMARDY SHSTROBE PDIOW# PSTOP Signal Description EIDE Mode: Primary Channel Ready. Device ready indicator UltraDMA Mode: Primary Device Ready. Output flow control. device assert DDMARDY pause output transfers Primary Device Strobe. Input data strobe (both edges). device stop DSTROBE pause input data transfers EIDE Mode: Secondary Channel Ready. Device ready indicator UltraDMA Mode: Secondary Device Ready. Output flow control. device assert DDMARDY pause output transfers Secondary Device Strobe. Input data strobe (both edges). device stop DSTROBE pause input data transfers EIDE Mode: Primary Device Read. Device read strobe UltraDMA Mode: Primary Host Ready. Primary channel input flow control. host assert HDMARDY pause input transfers Primary Host Strobe. Output data strobe (both edges). host stop HSTROBE pause output data transfers EIDE Mode: Secondary Device Read. Device read strobe UltraDMA Mode: Secondary Host Ready. Input flow control. host assert HDMARDY pause input transfers Host Strobe Output strobe (both edges). host stop HSTROBE pause output data transfers EIDE Mode: Primary Device Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted host prior initiation UltraDMA burst; negated host before data transferred UltraDMA burst. Assertion STOP host during after data transfer UltraDMA mode signals termination burst. EIDE Mode: Secondary Device Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted host prior initiation UltraDMA burst; negated host before data transferred UltraDMA burst. Assertion STOP host during after data transfer UltraDMA mode signals termination burst. Primary Device Request. Primary channel request Secondary Device Request. Secondary channel request Primary Device Acknowledge. Primary channel acknowledge Secondary Device Acknowledge. Secondary channel acknowledge Primary Channel Interrupt Request. Secondary Channel Interrupt Request.
AD15
AF22
SDIOW# SSTOP
AC21
PDDRQ SDDRQ PDDACK# SDDACK# IRQ14 IRQ15
AE15 AD22 AE24 AF24
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Descriptions
VT8235M Version V-Link South Bridge
UltraDMA-133 Enhanced Interface (continued)
Signal Name PDCS1# PDCS3# SDCS1# strap AC23 Signal Description Primary Master Chip Select. This signal corresponds CS1FX# primary connector. Primary Slave Chip Select. This signal corresponds CS3FX# primary connector. Secondary Master Chip Select. This signal corresponds CS17X# secondary connector. Strap (resistor ground) enable serial EEPROM interface (this disables EExx pins). This internal pullup default serial EEPROM interface EExx pins. Secondary Slave Chip Select. This signal corresponds CS37X# secondary connector. Strap information communicated north bridge VAD[7]. Primary Disk Address. PDA[2:0] used indicate which byte either command block control block being accessed. Secondary Disk Address. SDA[2:0] used indicate which byte either command block control block being accessed. Strap information communicated north bridge VAD[6:4]. Primary Disk Data. Secondary Disk Data. Primary Disk Compensation. Secondary Disk Compensation.
SDCS3# strap PDA[2-0] SDA[2-0] strap PDD[15-0] SDD[15-0] SA[15-0] PDCOMP SDCOMP
AD23 V26, V25, AF23, AC22, AE23 (see list) (see list) AC15
Serial AC97 Descriptions Serial
Signal Name SERIRQ AE10 Signal Description Serial IRQ. This internal pull-up resistor.
AC97 Audio Modem Interface
Signal Name Signal Description AC97 Reset. ACRST# AC97 Clock. ACBTCK AC97 Sync. ACSYNC AC97 Serial Data Out. ACSDO ACSDIN0 (VSUS33) AC97 Serial Data ACSDIN1 (VSUS33) AC97 Serial Data ACSDIN2 GPIO20 PCS0# AC97 Serial Data RxE4[6]=0,E5[1]=0, PMIO Rx4C[20]=1 ACSDIN3 GPIO21 PCS1# SLPBTN# AC97 Serial Data RxE4[6]=0,E5[2]=0, PMIO Rx4C[21]=1 supply voltage ACSDIN0-1 VSUS33 these inputs support wake-up modem ring.
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Descriptions
VT8235M Version V-Link South Bridge Internal Keyboard Controller Speaker Descriptions Internal Keyboard Controller
Signal Name MSCK IRQ1 Signal Description MultiFunction (Internal mouse controller enabled Rx51[1]) Rx51[2]=1 Mouse Clock. From internal mouse controller. Rx51[2]=0 Interrupt Request Interrupt input MSDT IRQ12 MultiFunction (Internal mouse controller enabled Rx51[1]) Rx51[2]=1 Mouse Data. From internal mouse controller. Rx51[2]=0 Interrupt Request Interrupt input KBCK KA20G MultiFunction (Internal keyboard controller enabled Rx51[0]) Rx51[0]=1 Keyboard Clock. From internal keyboard controller Rx51[0]=0 Gate A20. Input from external keyboard controller. KBDT KBRC MultiFunction (Internal keyboard controller enabled Rx51[0]) Rx51[0]=1 Keyboard Data. From internal keyboard controller. Rx51[0]=0 Keyboard Reset. From external keyboard controller (KBC) CPURST# generation KBCS# ROMCS# strap AF12 Keyboard Chip Select (Rx51[0]=0). external keyboard controller chip. Strap high enable ROM: Note: KBCK, KBDT, MSCK, MSDT powered VSUS33 suspend voltage plane.
Subset Parallel BIOS Interface
Signal Name ROMCS# KBCS# strap SPKR strap MEMR# MEMW# IOR# IOW# IORDY GPI19 SOE# strap XD[7-0] AF12 AE12 AF10 AC10 AD10 AD12 AD13, AE13, AF13, AD14, AE14, AF14, AC13, AC14 AC11, AD11, AE11, AF11 (see list) Signal Description Chip Select (Rx51[0]=1). Chip Select BIOS ROM. Strap high enable ROM. Speaker. Strap enable (high disable) frequency strapping. Memory Read. Memory Write. Read. Write. Ready. Used insert wait states memory cycles. RxE5[0] Tranceiver Output Enable. Strap enable auto reboot. Bus. input BIOS data data from other on-board memory devices. System Address 19-16. Strap states passed North Bridge VAD[3-0]. Functions SA[19-16] RxE4[5] System Address 15-0.
SA[19-16] GPO[19-16] straps SA[15-0] SDD[15-0]
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Descriptions
VT8235M Version V-Link South Bridge General Purpose Input Descriptions General Purpose Inputs
Signal Name GPI0 GPI1 GPI2 EXTSMI# GPI3 RING# GPI4 LID# GPI5 BATLOW# GPI6 AGPBZ# GPI7 REQ5# GPI8 GPO8 PCREQA VGATE GPI9 GPO9 PCREQB GPI10 GPO10 GPI11 GPO11 GPI12 GPO12 INTE# PCGNTA GPI13 GPO13 INTF# PCGNTB GPI14 GPO14 INTG# GPI15 GPO15 INTH# GPI16 INTRUDER# GPI17 CPUMISS GPI18 THRM# AOLGPI GPI19 IORDY GPI20 GPO20 ACSDIN2 PCS0# (VBAT) (VSUS33) (VSUS33) (VSUS33) (VSUS33) (VSUS33) AD10 Signal Description General Purpose Input Status PMIO Rx20[0] General Purpose Input Status PMIO Rx20[1] General Purpose Input Status PMIO Rx20[4] General Purpose Input Status PMIO Rx20[8] General Purpose Input Status PMIO Rx20[11] General Purpose Input Status PMIO Rx20[12] General Purpose Input Status PMIO Rx20[5] General Purpose Input RxE4[2] General Purpose Input RxE4[3] E5[4]=0, 53[7] General Purpose Input RxE4[3] 53[7] General Purpose Input RxE4[3] General Purpose Input RxE4[3] General Purpose Input RxE4[4] 5B[1]=0, 53[7]=0 General Purpose Input RxE4[4] 5B[1]=0, 53[7]=0 General Purpose Input RxE4[4] 5B[1]=0 General Purpose Input RxE4[4] 5B[1]=0 (VBAT) General Purpose Input Status PMIO Rx20[6] General Purpose Input Status PMIO Rx20[5] General Purpose Input Rx8C[3] General Purpose Input RxE5[0] General Purpose Input RxE4[6]=1, E5[1]=0, PMIO 4C[20] GPI21 GPO21 ACSDIN3 PCS1# SLPBTN# General Purpose Input RxE4[6]=1, E5[2]=0 PMIO 4C[21] GPI22 GPO22 GHI# General Purpose Input RxE5[3] PMIO 4C[22] GPI23 GPO23 DPSLP# General Purpose Input RxE5[3] PMIO 4C[23] GPI24 GPO24 GPIOA General Purpose Input RxE6[0] GPI25 GPO25 GPIOC General Purpose Input RxE6[1] GPI26 GPO26 SMBDT2 (VSUS33) General Purpose Input Rx95[2] 95[3] GPI27 GPO27 SMBCK2 (VSUS33) General Purpose Input Rx95[2] 95[3] GPI28 GPO28 VIDSEL General Purpose Input RxE5[3] PMIO 4C[28] GPI29 GPO29 VRDSLP General Purpose Input RxE5[3] PMIO 4C[29] GPI30 GPO30 GPIOD General Purpose Input RxE6[6] GPI31 GPO31 GPIOE General Purpose Input RxE6[7] Note: Default function underlined signal name column above. Note: Input status above pins 31-0 also available PMIO Rx4B-48[31-0] Note: also Power Management register Rx50 input change status GPI16-19 24-27 Note: also Power Management register Rx52 SCI/SMI select GPI16-19 24-27 Note: also Power Management register Rx4C. General purpose input pins 20-31 shared with (open drain) general purpose output functions, these pins input pin, must written corresponding PMIO Rx4C.
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Descriptions
VT8235M Version V-Link South Bridge General Purpose Output GPIO Descriptions General Purpose Outputs
Signal Name Signal Description General Purpose Output GPO0 (VSUS33) GPO1 SUSA# (VSUS33) General Purpose Output Rx94[2] GPO2 SUSB# (VSUS33) General Purpose Output Rx94[3] GPO3 SUSST1# (VSUS33) General Purpose Output Rx94[4] GPO4 SUSCLK (VSUS33) General Purpose Output Rx95[1] GPO5 CPUSTP# General Purpose Output RxE4[0] GPO6 PCISTP# General Purpose Output RxE4[1] GPO7 GNT5# General Purpose Output RxE4[2] GPO8 GPI8 PCREQA VGATE General Purpose Output RxE4[3]=1, E5[4]=0, 53[7]=0 GPO9 GPI9 PCREQB General Purpose Output RxE4[3]=1, 53[7]=0 GPO10 GPI10 General Purpose Output RxE4[3]=1 GPO11 GPI11 General Purpose Output RxE4[3]=1 GPO12 GPI12 INTE# PCGNTA General Purpose Output RxE4[4]=1, 5B[1]=0, 53[7]=0 GPO13 GPI13 INTF# PCGNTB General Purpose Output RxE4[4]=1, 5B[1]=0, 53[7]=0 GPO14 GPI14 INTG# General Purpose Output RxE4[4]=1, 5B[1]=0 GPO15 GPI15 INTH# General Purpose Output RxE4[4]=1, 5B[1]=0 GPO16 SA16 strap AF11 General Purpose Output RxE4[5] GPO17 SA17 strap AE11 General Purpose Output RxE4[5] GPO18 SA18 strap AD11 General Purpose Output RxE4[5] GPO19 SA19 strap AC11 General Purpose Output RxE4[5] GPO20 GPI20 ACSDIN2 PCS0# General Purpose Output RxE4[6]=1, E5[1]=0 GPO21 GPI21 ACSDIN3 PCS1# /SLPBTN# General Purpose Output RxE4[6]=1, E5[2]=0 GPO22 GPI22 GHI# General Purpose Output RxE5[3]=1 GPO23 GPI23 DPSLP# General Purpose Output RxE5[3]=1 GPO24 GPI24 GPIOA O/OD General Purpose Output RxE6[0] GPO25 GPI25 GPIOC O/OD General Purpose Output RxE6[1] GPO26 GPI26 SMBDT2 (VSUS33) General Purpose Output Rx95[2] 95[3] GPO27 GPI27 SMBCK2 (VSUS33) General Purpose Output Rx95[2] 95[3] GPO28 GPI28 VIDSEL General Purpose Output RxE5[3] GPO29 GPI29 VRDSLP General Purpose Output RxE5[3] GPO30 GPI30 GPIOD O/OD General Purpose Output RxE6[6] GPO31 GPI31 GPIOE O/OD General Purpose Output RxE6[7] Note: output state each above general purpose outputs selectable Power Management registers Rx4C-48 Note: output types GPO24-25 30-31 selectable (see Function RxE7) Note: Default functions underlined table above. suspend voltage only used maintaining operation function thses pins (Device Function Rx95[3] power lost, GPIO function these pins state PMIO Rx4C[27:26} (which determines output level) will lost also.
General Purpose
Signal Name Signal Description GPIOA GPI24 GPO24 General Purpose RxE6[0] GPIOC GPI25 GPO25 General Purpose RxE6[1] GPIOD GPI30 GPO30 General Purpose RxE6[6] GPIOE GPI31 GPO31 General Purpose RxE6[7] output type above pins selected either (see Device Function RxE7)
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Descriptions
VT8235M Version V-Link South Bridge Power Management Event Detection Descriptions Power Management Event Detection
Signal Name PWRBTN# SLPBTN# GPIO21 ACSDIN3 PCS1# RSMRST# EXTSMI# GPI2 PME# SMBALRT# LID# GPI4 Signal Description Power Button. Used Power Management subsystem monitor external system on/off button switch. Internal logic powered VSUS33. Sleep Button. Used Power Management subsystem monitor external sleep button switch. RxE4[6] 80[6] E5[2] PMIO Rx4C[21] Resume Reset. Resets internal logic connected VSUS33 power plane also resets portions internal logic. Internal logic powered VBAT. External System Management Interrupt. When enabled allow falling edge this input causes SMI# generated enter mode. (10K VSUS33 used) (3.3V only) Power Management Event. (10K VSUS33 used) Alert. When programmed allow (SMB Rx8[3]=1), assertion generates IRQ, SMI, power management event. (10K VSUS33 used) Notebook Computer Display Open Closed Monitor. Used Power Management subsystem monitor opening closing display notebook computers. used detect either low-to-high high-to-low transitions generate SMI#. (10K VSUS33 used) Intrusion Indicator. value this read PMIO Rx20[6] Thermal Alarm Monitor. Rx8C[3] Rising falling edges (selectable PMIO Rx2C[6]) detected status PMIO Rx20[10]. Setting this status then used generate SMI. THRM# also used enable duty cycle control stop-clock (STPCLK#) automatically limit maximum temperature (see Device Function Rx8C[7-3]). Ring Indicator. connected external modem circuitry allow system re-activated received phone call. (10K VSUS33 used) Battery Indicator. (10K VSUS33 used) (3.3V only) Clock Stop (RxE4[0] Signals system clock generator disable clock outputs. connected used. Clock Stop (RxE4[1] Signals system clock generator disable clock outputs. connected used. Suspend Plane Control (Rx94[2]=0). Asserted during power management POS, STR, suspend states. Used control primary power plane. (10K VSUS33 used) Suspend Plane Control (Rx94[3]=0). Asserted during power management suspend states. Used control secondary power plane. (10K VSUS33 used) Suspend Plane Control. Asserted during power management suspend state. Used control tertiary power plane. Also connected power-on circuitry. (10K VSUS33 used) Suspend Status (Rx94[4] Typically connected North Bridge provide information host clock status. Asserted when system stop host clock, such Stop Clock during POS, STR, suspend states. Connect VSUS33. Suspend Clock. 32.768 output clock North Bridge (e.g., KT400A, CLE266 P4X400) DRAM refresh purposes. Stopped during Suspend-to-Disk Soft-Off modes. Connect VSUS33. Missing. Used detect physical presence chip socket. High indicates present. Connect CPUMISS socket. state this read SMBus registers. This used CPUMISS GPI17 same time. Alert LAN. state this read SMBus registers. This used AOLGPI, GPI18 THRM# same time. -19Pin Descriptions
INTRUDER# GPI16 THRM# GPI18 AOLGPI
RING# GPI3 BATLOW# GPI5 CPUSTP# GPO5 PCISTP# GPO6 SUSA# GPO1 SUSB# GPO2 SUSC# SUSST1# GPO3
SUSCLK CPUMISS GPI17
AOLGPI GPI18 THRM#
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VT8235M Version V-Link South Bridge Clock, Resets, Power Status, Power Ground Descriptions Resets, Clocks, Power Status
Signal Name PWRGD PWROK# PCIRST# RTCX1 RTCX2 TEST AC12 W22, AD17 Signal Description Power Good. Connected Power Good signal Power Supply. Internal logic powered VBAT. Power Internal logic powered VSUS33. Reset. Active reset signal bus. VT8235M Version will assert this during power-up from control register. Oscillator. 14.31818 clock signal used internal Timer. Crystal Input: 32.768 crystal oscillator input. This input used internal power-well power management logic powered VBAT. Crystal Output: 32.768 crystal output. Internal logic powered VBAT. Test. Test Output. Output test mode. Connect. Reserved. connect.
Power Ground
Signal Name VCC33 (see list) (see list) Signal Description Power. 3.3V Core Power. 2.5V ±5%. This supply turned only when mechanical switch power supply turned PWRON signal conditioned high. Note: VT8233A Version (VT8235ML) core voltage 3.3V board designs that intended allow either VT8235M Version VT8233A Version (VT8235ML) should take this difference into account allow core voltage selected either 2.5V (for VT8235M Version 3.3V (for VT8233A Version VT8235ML). (see list) Ground. Connect primary motherboard ground plane. AA4, AB4, Suspend Power. 3.3V ±5%. Always available unless mechanical switch VSUS33 AC4, power supply turned off. "soft-off" state implemented, then this connected VCC33. Signals powered referenced this plane are: PWRGD, RSMRST#, PWRBTN#, SMBCK1/2, SMBDT1/2, GPO0, SUSA# GPO1, SUSB# GPO2, SUSC#, SUSST1# GPO3, SUSCLK GPO4, GPI1, GPI2 EXTSMI#, GPI3 RING#, GPI4 LID, GPI5 BATLOW#, GPI6 PME#, SMBALRT# Suspend Power. 2.5V ±5%. VSUS25 Suspend Power. 2.5V ±5%. VSUSUSB Battery. Battery input internal (RTCX1, RTCX2) VBAT V-Link Voltage Reference. 0.9V transfers 0.625V transfers. VLVREF (see list) V-Link Compensation Circuit Voltage. 2.5V VCCVK D11, D12, Power. 3.3V ±5%.Power Media Independent Interface (interface MIIVCC E11, external PHY). Connect VCC33 through ferrite bead. D13, Suspend Power. 2.5V ±5%. MIIVCC25 Power. 2.5V ±5%. Power internal RAM. Connect RAMVCC through ferrite bead. Ground. Connect through ferrite bead. RAMGND (see list) Differential Output Power. 3.3V ±5%. Power differential outputs USBVCC (USBP0+, P0-, P1+, P1-, P2+, P2-, P3+, P3-, P4+, P4-, P5+, P5-). Connect VSUS33 through ferrite bead. (see list) Differential Output Ground. Connect through ferrite bead. USBGND A23, Analog Voltage. 2.5V ±5%. Connect through ferrite bead. VCCUPLL B23, Analog Ground. Connect through ferrite bead. GNDUPLL Analog Power. 2.5V ±5%. Connect through ferrite bead. PLLVCC Analog Ground. Connect through ferrite bead. PLLGND Created resistive voltage divider 3.3V ground (see Design Guide) Revision 2.03, March 2005 -20Pin Descriptions
VT8235M Version V-Link South Bridge Strap Descriptions Strap Pins
Strap Pins VT8235M Version Configuration Signal Name Strap_SOE# SPKR ROMCS# KBCS# SDCS1# Function Description Note
AD12 Auto Reboot
Enable Auto Reboot Disable Auto Reboot (Default) Frequency Strapping Enable Frequency Strapping Disable Frequency Strapping (Default) AF12 Internal Keyboard Controller Disable internal Enable internal (Default) AC23 Eliminate External Enable. external EEPROM (Default) EEPROM Disable. external EEPROM Strap Pins North Bridge Configuration Check North Bridge details Check North Bridge details Check North Bridge details Check North Bridge details Check North Bridge details SA18 signal state reflected signal VD[2] Check North during power North Bridge configuration. Bridge details SA17 signal state reflected signal pin, Check North VD[1] during power North Bridge Bridge configuration. details SA16 signal state reflected signal pin, Check North VD[0] during power North Bridge Bridge configuration. details SDCS3# signal state reflected signal VD[7] during power North Bridge configuration. SDA2 signal state reflected signal VD[6] during power North Bridge configuration. SDA1 signal state reflected signal VD[5] during power North Bridge configuration. SDA0 signal states reflected signal pins VD[4] during power North Bridge configuration. SA19 signal state reflected signal VD[3] during power North Bridge configuration.
SDCS3# SDA2 SDA1 SDA0 SA19 SA18 SA17 SA16
AD23 Configuration AF23 Configuration
AC22 Configuration AE23 Configuration AC11 Configuration AD11 Configuration AE11 Configuration AF11 Configuration
Summary Internal Pull-Up Pull-Down Resistor Implementation Internal Pullups present pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD[3:0], SDCS1# Internal Pulldowns present pins SA[19-16] pins
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Descriptions
VT8235M Version V-Link South Bridge
REGISTERS
Register Overview
following tables summarize configuration registers VT8235M Version These tables also document power-on default value ("Default") access type ("Acc") each register. Access type definitions used (Read/Write), (Read/Only), reserved used (essentially same RO), just (Read Write Clear individual bits). Registers indicated have some read/only bits that always read back fixed value (usually unused); registers designated have some read-only read write bits (see individual register descriptions details). Detailed register descriptions provided following section this document. offset default values shown hexadecimal unless otherwise indicated Port 00-1F 20-3F 40-5F 60-6F (60h) (61h) (64h) 70-77 78-7F 81-8F 90-91 93-9F A0-BF C0-DF E0-FF 100-CF7
Table System
Function Actual Port Decoding Master Controller 0000 0000 000x nnnn Master Interrupt Controller 0000 0000 001x xxxn Timer Counter 0000 0000 010x xxnn Keyboard Controller 0000 0000 0110 xnxn Data 0000 0000 0110 x0x0 Misc Functions Spkr Ctrl 0000 0000 0110 xxx1 Command Status 0000 0000 0110 x1x0 RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn -available system use- 0000 0000 0111 1xxx -reserved- (debug port) 0000 0000 1000 0000 Page Registers 0000 0000 1000 nnnn -available system use- 0000 0000 1001 000x System Control 0000 0000 1001 0010 -available system use- 0000 0000 1001 nnnn Slave Interrupt Controller 0000 0000 101x xxxn Slave Controller 0000 0000 110n nnnx -available system use- 0000 0000 111x xxxx -available system use*
Table Memory Mapped Registers
FEC00000 FEC00010 FEC00020 FEC00040 APIC Index APIC Data APIC Assertion APIC (8-bit) (32-bit) (8-bit) (8-bit)
CF8-CFB Configuration Address 0000 1100 1111 10xx CFC-CFF Configuration Data 0000 1100 1111 11xx D00-FFFF -available system use-
"APIC" "Advanced Programmable Interrupt Controller"
Table Function Summary
Device Func Device Function (10h) 3038h UHCI Ports (10h) 3038h UHCI Ports (10h) 3038h UHCI Ports (10h) 3104h EHCI Ports (11h) (11h) (11h) (11h) 3074h 0571h 3059h 3068h Control Power Mgmt Controller AC97 Audio Codec Controller MC97 Modem Codec Ctrlr
(12h)
3065h Controller
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Table Registers
Legacy Registers Port Master Controller Registers Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read Write Mask Default Default Default Default Legacy Registers (continued) Port Page Registers Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel Default Default
Port System Control Registers System Control
Port Master Interrupt Controller Regs Master Interrupt Control Master Interrupt Mask Master Interrupt Control Shadow Master Interrupt Mask Shadow shadow registers disabled Port Port Timer/Counter Registers Timer Counter Count Timer Counter Count Timer Counter Count Timer Counter Control Keyboard Controller Registers Keyboard Controller Data Misc Functions Speaker Control Keyboard Ctrlr Command Status
Port Slave Interrupt Controller Regs Default Slave Interrupt Control Slave Interrupt Mask Slave Interrupt Control Shadow Slave Interrupt Mask Shadow accessible shadow registers disabled Port Slave Controller Registers Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read Write Mask Default
Port CMOS Registers Default CMOS Memory Address Disa CMOS Memory Data (128 bytes) CMOS Memory Address CMOS Memory Data (256 bytes) Disable port (CMOS Memory Address) bit-7. control occurs specific CMOS data locations (0-Dh). Ports 74-75 used access CMOS internal disabled.
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Keyyboard Mouse Wakeup Registers (I/O Space) Default Port Mouse Wakeup Registers 002E Keyboard Mouse Wakeup Index 002F Keyboard Mouse Wakeup Data Keyboard Mouse Wakeup registers (index values E0-EF defined below) accessible Function Configuration register Rx51[1] Keyboard Mouse Wakeup Registers (Indexed Port 2E/2F) Offset Reserved 00-DF -reservedOffset EC-EF Mouse Wakeup (Rx51[1]=1) Keyboard Mouse Wakeup Enable Keyboard Wakeup Scan Code Keyboard Wakeup Scan Code Keyboard Wakeup Scan Code Keyboard Wakeup Scan Code Keyboard Wakeup Scan Code Keyboard Wakeup Scan Code Keyboard Wakeup Scan Code Keyboard Wakeup Scan Code Mouse Wakeup Scan Code Mouse Wakeup Scan Code Mouse Wakeup Scan Code Mask -reservedDefault Default Memory Mapped Registers IOAPIC Address FEC00000 FEC00001-0F FEC00010-13 FEC00014-1F FEC00020 FEC00021-3F FEC00040 FEC00041-FF APIC Index Data APIC Register Index -reservedAPIC Register Data -reservedAPIC Assertion -reservedAPIC -reservedDefault 0000 0000
Game Port Registers (I/O Space) Offset Game Port (200-20F typical) -reservedGame Port Status Start One-Shot -reservedDefault
Offset APIC Registers Default APIC 0000 0000 APIC Version 0017 8003 APIC Arbitration 0000 0000 Boot Configuration 0000 0000 -reserved0000 0000 11-10 Redirection- AIRQ0 xxx1xxxx xxxxxxxx 13-12 Redirection- AIRQ1 xxx1xxxx xxxxxxxx 15-14 Redirection- AIRQ2 xxx1xxxx xxxxxxxx 17-16 Redirection- AIRQ3 xxx1xxxx xxxxxxxx 19-18 Redirection- AIRQ4 xxx1xxxx xxxxxxxx 1B-1A Redirection- AIRQ5 xxx1xxxx xxxxxxxx 1D-1C Redirection- AIRQ6 xxx1xxxx xxxxxxxx 1F-1E Redirection- AIRQ7 xxx1xxxx xxxxxxxx 21-20 Redirection- AIRQ8 xxx1xxxx xxxxxxxx 23-20 Redirection- AIRQ9 xxx1xxxx xxxxxxxx 25-24 Redirection- AIRQ10 xxx1xxxx xxxxxxxx 27-26 Redirection- AIRQ11 xxx1xxxx xxxxxxxx 29-28 Redirection- AIRQ12 xxx1xxxx xxxxxxxx 2B-2A Redirection- AIRQ13 xxx1xxxx xxxxxxxx 2D-2C Redirection- AIRQ14 xxx1xxxx xxxxxxxx 2F-2E Redirection- AIRQ15 xxx1xxxx xxxxxxxx 31-30 Redirection- AIRQ16 xxx1xxxx xxxxxxxx 33-32 Redirection- AIRQ17 xxx1xxxx xxxxxxxx 35-34 Redirection- AIRQ18 xxx1xxxx xxxxxxxx 37-36 Redirection- AIRQ19 xxx1xxxx xxxxxxxx 39-38 Redirection- AIRQ20 xxx1xxxx xxxxxxxx 3B-3A Redirection- AIRQ21 xxx1xxxx xxxxxxxx 3D-3C Redirection- AIRQ22 xxx1xxxx xxxxxxxx 3F-3E Redirection- AIRQ23 xxx1xxxx xxxxxxxx 40-4F -reserved0000 0000 Note: "I/O Redirection" registers 64-bit registers, each uses consecutive index locations, with lower bits even index upper bits index.
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Register Overview
VT8235M Version V-Link South Bridge
Device Function Registers UHCI Ports Configuration Space Header Registers Offset E-1F 23-20 24-2B 2D-2C 2F-2E 30-33 35-3B 3E-3F Configuration Space Header Default Vendor 1106 Device 3038 Command 0000 Status 0210 Revision Programming Interface Class Code Base Class Code -reserved00 Latency Timer -reserved00 Registers Base Port Address 00000301 -reserved00 Vendor 1106 Device 3038 -reserved00 Power Management Capabilities -reserved00 Interrupt Line Interrupt -reserved00 Configuration Space USB-Specific Registers Offset 44-47 4B-5F 61-7F 83-80 85-BF C1-C0 C2-FF Control Miscellaneous Control Miscellaneous Control Miscellaneous Control Miscellaneous Control -reserved- (test, program) Miscellaneous Control Miscellaneous Control Miscellaneous Control -reservedUSB Serial Release Number -reservedPM Capability Capability Status -reservedUSB Legacy Support -reservedDefault FFC20001 2000
Memory Mapped Registers Controller Offset 11-10 13-12 14-1F Registers Command Status Interrupt Enable Frame Number Frame List Base Address Start Frame Modify Port Status Control Port Status Control -reservedDefault 0000 0000 0000 0000 00000000 0080 0080
Rx42[4]
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Register Overview
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Device Function Registers UHCI Ports Configuration Space Header Registers Offset E-1F 23-20 24-2B 2D-2C 2F-2E 30-33 35-3B 3E-3F Configuration Space Header Default Vendor 1106 Device 3038 Command 0000 Status 0210 Revision Programming Interface Class Code Base Class Code -reserved00 Latency Timer -reserved00 Registers Base Port Address 00000301 -reserved00 Vendor 1106 Device 3038 -reserved00 Power Management Capabilities -reserved00 Interrupt Line Interrupt -reserved00 Configuration Space USB-Specific Registers Offset 44-47 4B-5F 61-7F 83-80 85-BF C1-C0 C2-FF Control Miscellaneous Control Miscellaneous Control Miscellaneous Control Miscellaneous Control -reserved- (test, program) Miscellaneous Control Miscellaneous Control Miscellaneous Control -reservedUSB Serial Release Number -reservedPM Capability Capability Status -reservedUSB Legacy Support -reservedDefault FFC20001 2000
Memory Mapped Registers Controller Offset 11-10 13-12 14-1F Registers Command Status Interrupt Enable Frame Number Frame List Base Address Start Frame Modify Port Status Control Port Status Control -reservedDefault 0000 0000 0000 0000 00000000 0080 0080
Rx42[4]
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Register Overview
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Device Function Registers UHCI Ports Configuration Space Header Registers Offset E-1F 23-20 24-2B 2D-2C 2F-2E 30-33 35-3B 3E-3F Configuration Space Header Default Vendor 1106 Device 3038 Command 0000 Status 0210 Revision Programming Interface Class Code Base Class Code -reserved00 Latency Timer -reserved00 Registers Base Port Address 00000301 -reserved00 Vendor 1106 Device 3038 -reserved00 Power Management Capabilities -reserved00 Interrupt Line Interrupt -reserved00 Configuration Space USB-Specific Registers Offset 44-47 4B-5F 61-7F 83-80 85-BF C1-C0 C2-FF Control Miscellaneous Control Miscellaneous Control Miscellaneous Control Miscellaneous Control -reserved- (test, program) Miscellaneous Control Miscellaneous Control Miscellaneous Control -reservedUSB Serial Release Number -reservedPM Capability Capability Status -reservedUSB Legacy Support -reservedDefault FFC20001 2000
Memory Mapped Registers Controller Offset 11-10 13-12 14-1F Registers Command Status Interrupt Enable Frame Number Frame List Base Address Start Frame Modify Port Status Control Port Status Control -reservedDefault 0000 0000 0000 0000 00000000 0080 0080
Rx42[4]
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Device Function Registers EHCI Ports Configuration Space Header Registers Offset 13-10 14-2B 2D-2C 2F-2E 30-33 35-3B 3E-3F Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer -reservedEHCI Mapped Base Addr -reservedSub Vendor Device -reservedPower Management Capabilities -reservedInterrupt Line Interrupt -reservedDefault 1106 3104 0000 0210 0000 0000 1106 3104 Memory Mapped Registers EHCI Offset 03-02 07-04 0B-08 0C-0F Offset 13-10 17-14 1B-18 1F-1C 23-20 27-24 2B-28 2C-4F 53-50 57-54 5B-58 5C-FF EHCI Capabilities Capability Register Length -reservedInterface Version Number Structure Parameters Capability Parameters -reservedHost Controller Operation Command Status Interrupt Enable Frame Index Segment Selector Frame List Base Address Next Asynchronous List Address -reservedConfigured Flag Register Port Status Control Port Status Control -reservedDefault 0100 0000 3206 0000 6872 Default 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Rx42[4]
Rx42[4]
Configuration Space USB-Specific Registers Offset 41-47 4A-4B 4C-4F 50-57 58-5D 5E-5F 63-62 64-67 6B-68 6F-6C 70-7F 83-80 85-FF Control Default Miscellaneous Control -reserved- Program) Miscellaneous Control Miscellaneous Control -reserved- Program) -reserved00 -reserved- (test, program) -reserved- Program) -reserved00 Serial Release Number Frame Length Adjust Port Wake Capability 0001 -reserved00 Legacy Support Extended Capability 0000 0001 Legacy Support Control Status 0000 0000 -reserved00 Capability FFC20001 Capability Status -reserved00
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Device Function Registers Control Power Management Configuration Space Control Header Registers Offset 10-27 28-2B 2D-2C 2F-2E 30-33 34-3B Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code -reserved- (cache line size) -reserved- (latency timer) Header Type Built Self Test (BIST) -reserved- (base address registers) -reserved- (unassigned) Vendor Device -reserved- (expan. base addr) -reserved- (unassigned) -reserved- (interrupt line) -reserved- (interrupt pin) -reserved- (min gnt) -reserved- (max lat) Default 1106 3177 0087 0200 Offset Function Control Function Control Function Control Default
Offset Serial IRQ, PC/PCI Control Default Serial Control PC/PCI Control Offset Offset Offset 5D-5C 5F-5E 61-60 63-62 68-6B Offset 71-70 73-72 70-78 7D-7F Plug Play Control Interrupt Polarity Routing INTA Routing INTB-C Routing INTD GPIO Miscellaneous Control Miscellaneous Control Miscellaneous Control Bandwidth Control Miscellaneous Control Programmable Chip Select Control PCS0# Port Address PCS1# Port Address PCS2# Port Address PCS3# Port Address PCS[1-0]# Port Address Mask PCS[3-2]# Port Address Mask Programmable Chip Select Control Output Control -reservedMiscellaneous Positive Decoding Control Positive Decoding Control Positive Decoding Control Positive Decoding Control Vendor Backdoor Device Backdoor -reservedPnP IRQ/DRQ Test prog) Test program) Test program) Control -reservedDefault Default Default 0000 0000 0000 0000 Default
Configuration Space PCI-to-ISA Bridge-Specific Registers Offset 44-47 4A-4B Offset Control Control BIOS Decode Control Line Buffer Control Delay Transaction Control -reservedRead Pass Write Control Control -reservedMiscellaneous Control Interrupt Routing -reservedInternal Test Mode Interface Control Default Default
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Configuration Space Power Management Registers Offset 85-84 87-86 8B-88 8E-8F 93-90 9B-A0 A4-BF C3-C0 C7-C4 C8-CF Power Management General Configuration General Configuration ACPI Interrupt Select -reservedPrimary Interrupt Channel Secondary Interrupt Channel Power Mgmt Base (256 Bytes) Host Power Mgmt Control Throttle Clock Stop Control -reservedGP Timer Control Power Well Control Miscellaneous Control Power Reset Control -reservedGP2 Timer Control Timer Timer -reservedWrite value Offset (Prog Intfc) Write value Offset (Sub Class) Write value Offset (Base Class) -reservedPower Management Capability Power Management Capability -reservedDefault 0000 0000 0000 0001 0000 0000 0002 0001 0000 0000 Configuration Space SMBus Registers Offset D1-D0 D7-DF System Management Default SMBus Base Bytes) 0001 SMBus Host Configuration SMBus Host Slave Command SMBus Slave Address Shadow Port SMBus Slave Address Shadow Port SMBus Revision -reserved00
Configuration Space General Purpose Registers Offset E2-E3 General Purpose Inversion Control Select -reservedGPO Select GPIO Select GPIO Select Output Type Default
Configuration Space Watchdog Timer Registers Offset EB-E8 ED-FF Watchdog Timer Watchdog Timer Memory Base Watchdog Timer Control -reservedDefault
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Space Power Management Registers Offset Offset 13-10 16-1F Offset 21-20 23-22 25-24 26-27 Offset 29-28 2B-2A 2D-2C 33-30 37-34 3B-38 3C-3F Offset 43-44 46-47 4B-48 4F-4C 53-57 59-58 5D-FF Basic Control Status Registers Power Management Status Power Management Enable Power Management Control -reservedPower Management Timer -reservedProcessor Registers Processor Control Processor LVL2 Processor LVL3 -reservedGeneral Purpose Registers General Purpose Status General Purpose Enable General Purpose Enable -reservedGeneric Registers Global Status Global Enable Global Control -reservedSMI Command Primary Activity Detect Status Primary Activity Detect Enable Timer Reload Enable -reservedGeneral Purpose Registers Extended Trap Status -reservedExtended Trap Enable -reservedSMI Resume Status -reservedGPI Port Input Value Port Output Value Change Status -reservedGPI Change SCI/SMI Select -reservedI/O Trap Address Trap Command Byte -reservedCPU Performance Control -reservedDefault 0000 0000 0000 0000 0000 Default 0000 0000 Default 0000 0000 0000 Default 0000 0000 0010 0000 0000 0000 0000 0000 0000 Default input Space System Management Registers Offset System Management SMBus Host Status SMBus Slave Status SMBus Host Control SMBus Host Command SMBus Host Address SMBus Host Data SMBus Host Data SMBus Block Data SMBus Slave Control SMBus Shadow Command SMBus Slave Event SMBus Slave Data -reservedSMBus GPIO Slave Address Default 0000 0000
System Management Command Codes Code System Management SMBus GPIO Slave Input Data SMBus GPIO Slave Output Data SMBus GPIO Slave Polarity Inversion SMBus GPIO Slave Configuration Default
FFFFCFFF 0000
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Device Function Registers Controller Configuration Space Header Registers Offset Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code -reserved13-10 Base Address Data Command 17-14 Base Address Control Status 1B-18 Base Address Data Command 1F-1C Base Address Control Status 23-20 Base Address Master Control 24-2B -reserved- (unassigned) 2D-2C Vendor 2F-2E Device 30-33 -reserved- (expan base addr) Capability Pointer 35-3B -reserved- (unassigned) Interrupt Line Interrupt Minimum Grant Maximum Latency Configuration Space IDE-Specific Registers (continued) Offset Configuration Space Registers Default 53-50 UltraDMA Extended Timing Control 07070707 UltraDMA FIFO Control Clock Gating 56-5F -reserved00 61-60 Primary Sector Size 0200 62-67 -reserved00 69-68 Secondary Sector Size 0200 69-6F -reserved00 Primary Status Primary Interrupt Control 72-77 -reserved00 Secondary Status Secondary Interrupt Control 7A-7F -reserved00 83-80 Primary Descriptor Address 0000 0000 84-87 -reserved00 8B-88 Secondary Descriptor Addr 0000 0000 8C-BF -reserved00 C3-C0 Power Management Capabilities 0002 0001 C7-C4 Power State 0000 0000 C8-CF -reserved00 Offset Back Door Registers Back Door Revision -reservedD3-D2 Back Door Device D5-D4 Back Door Vender D7-D6 Back Door Device D8-FF -reservedDefault 0571 0000 0000
Default 1106 0571 0080 0290 000001F1 000003F5 00000171 00000375 0000CC01 0000 0000
Configuration Space IDE-Specific Registers Offset Configuration Space Registers Default Chip Enable Configuration Configuration FIFO Configuration Miscellaneous Control Miscellaneous Control Miscellaneous Control A8A8A8A8 4B-48 Drive Timing Control Address Setup Time -reserved- program) Non-170 Port Access Timing Non-1F0 Port Access Timing
Registers Controller (SFF 8038 v1.0 Compliant Offset Registers Default Primary Channel Command -reserved00 Primary Channel Status -reserved00 Primary Channel Table Addr Secondary Channel Command -reserved00 Secondary Channel Status -reserved00 Secondary Channel Table Addr
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Device Function Registers AC/MC97 Codecs Function Configuration Space AC97 Header Registers Offset 13-10 17-14 1B-18 1F-1C 23-20 27-24 28-29 2F-2C 33-30 35-3B Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code -reservedBase Address Control/Status Base Address (reserved) Base Address (reserved) Base Address (reserved) Base Address (reserved) Base Address (reserved) -reservedSubsystem SubVendor Expansion (reserved) Capture Pointer -reservedInterrupt Line Interrupt Minimum Grant Maximum Latency Default 1106 3059 0000 0210 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Function Configuration Space MC97 Header Registers Offset 13-10 17-14 1B-18 1F-1C 23-20 27-24 28-29 2F-2C 33-30 35-3B Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code -reservedBase Address Control/Status Base Address (reserved) Base Address (reserved) Base Address (reserved) Base Address (reserved) Base Address (reserved) -reservedSubsystem SubVendor Expansion (reserved) Capture Pointer -reservedInterrupt Line Interrupt Minimum Grant Maximum Latency Default 1106 3068 0000 0200 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Configuration Space Audio Codec-Specific Registers Offset 45-47 4B-48 4C-BF C3-C0 C7-C4 C8-FF Audio Codec Link Control AC-Link Interface Status AC-Link Interface Control Function Enable -reservedMC97 Interface Control -reservedTest Mode (reserved) -reservedPower Management Capability Power State -reservedDefault 0002 0001 0000 0000
Configuration Space Modem Codec-Specific Registers Offset Modem Codec Link Control AC-Link Interface Status AC-Link Interface Control Function Enable -reserved44 MC97 Interface Control 45-47 -reserved4B-48 Test Mode (reserved) 4C-CF -reservedD3-D0 Power Management Capability D7-D4 Power State D8-FF -reservedDefault 0002 0001 0000 0000
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Function Base Registers AC97 Audio Offset x7-x4 xB-x8 xF-xC 47-44 4B-48 4F-4C 50-5F 67-64 6B-68 6F-6C 77-74 7B-78 7F-7C Offset 83-80 87-84 8B-88 8F-8C 90-9F A0-FF AC97 Registers Channel Status Channel Control Channel Left Volume Channel Right Volume Channel Table Pointer Base Channel Current Address Stop Index Data Type Sample Rate Channel Current Count Channel Status Channel Control Channel Format Channel Scratch Channel Table Pointer Base Channel Current Address Channel Slot Select Channel Current Count -reservedSGD Write Channel Status Write Channel Control Write Channel Format Write Channel Select Write Channel Table Base Write Channel Current Addr Write Channel Stop Index Write Channel Current Count Write Channel Status Write Channel Control Write Channel Format Write Channel Select Write Channel Table Base Write Channel Current Addr Write Channel Stop Index Write Channel Current Count AC97 Audio Codec Registers AC97 Controller Command Status Global Shadow Modem Codec Intr Status GPIO Modem Codec Interrupt Enable Shadow Config Registers 40-4F -reservedDefault 0000 0000
FF0F FFFF
Function Base Registers MC97 Modem Offset 10-17 18-1F 20-27 28-2F 30-37 38-3F 47-44 4B-48 4F-4C 57-54 5B-58 5F-5C 60-7F MC97 Registers Read Channel Status Read Channel Control Read Channel Type -reservedSGD Read Chan Table Pointer Base Read Channel Current Address -reserved- (Test) Read Channel Current Count Write Channel Status Write Channel Control Write Channel Type -reservedSGD Write Channel Table Base Write Channel Current Address Reserved (Test) Write Channel Current Count -reservedDefault 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 FF00 0000 0000 0000 0000 0000 FF00 0000 0000 0000 0000 0000 FF00 0000 0000 0000 Default 0000 0000 0000 0000 0000 0000 0000 0000
Offset 83-80 87-84 8B-88 8F-8C 90-9F A0-FF
AC97 Modem Codec Registers AC97 Controller Command Status Global Shadow Modem Codec Intr Status GPIO Modem Codec Interrupt Enable Shadow Config Registers 40-4F -reserved-
Default 0000 0000 0000 0000 0000 0000 0000 0000
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Register Overview
VT8235M Version V-Link South Bridge
Device Function Registers Configuration Space Header Registers Default Offset Configuration Space Header Vendor 1106 Device 3065 Command 0000 Status 0470 Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST 13-10 Base Address 0000 0000 17-14 Memory Base Address 0000 0000 18-27 -reserved00 2B-28 Card Pointer 0000 0000 2C-2F -reserved00 33-30 Expansion Base Address 0000 0000 Capabilities Offset 35-3C -reserved00 Interrupt 3E-3F -reserved00 Configuration Space Device Specific Registers Default Offset Power Management Capability Next Item Pointer 43-42 Power Management Configuration 0002 47-44 Power Management Control Status 0000 0000 48-FF -reserved00
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Register Overview
VT8235M Version V-Link South Bridge
Space Registers Offset Power Management Ethernet Address Receive Control Transmit Control Command Command -reservedC Interrupt Status Interrupt Status Interrupt Mask Interrupt Mask 17-10 Multicast Address 1B-18 Receive Address 1F-1C Transmit Address 23-20 Receive Status 27-24 Receive Data Buffer Control 2B-28 Receive Data Buffer Start Address 2F-2C Receive Data Buffer Branch Address 30-3F -reserved43-40 Transmit Status 47-44 Transmit Data Buffer Control 4B-48 Transmit Data Buffer Start Address 4F-4C Transmit Data Buffer Branch Addr 50-6B -reserved6C Address Status Buffer Control Buffer Control Management Port Command Management Port Address 73-72 Management Port Data EEPROM Command Status 75-77 -reserved78 EEPROM Control Space Registers (continued) Offset Power Management Configuration Configuration Configuration 7C-7F -reserved80 Miscellaneous Miscellaneous -reserved83 Sticky Hardware Control Interrupt Status -reserved86 Interrupt Mask 87-8B -reserved8D-8C Flash Address -reserved8F Flash Write Data Output Flash Read Write Command Flash Write Data Input -reserved93 Flash Checksum 95-94 Suspend Mode Address Suspend Mode Address -reserved99-98 Pause Timer Pause Status -reserved9D-9C Soft Timer 9F-9E Soft Timer A0/A4 Wake Control Clear A1/A5 Power Configuration Clear A2/A6 -reserved- program) A3/A7 Wake Config Clear A8-AF -reservedB3-B0 Pattern B7-B4 Pattern BB-B8 Pattern BF-BC Pattern CF-C0 Byte Mask DF-D0 Byte Mask EF-E0 Byte Mask FF-F0 Byte Mask
Default
0000 0400 0000 0000
0000 0000 0000 0000
0000
Default 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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Register Overview
VT8235M Version V-Link South Bridge Register Descriptions
Legacy Ports This group registers includes Controllers, Interrupt Controllers, Timer/Counters well number miscellaneous ports originally implemented using discrete logic original PC/AT motherboards. registers listed integrated on-chip. These registers implemented precise manner backwards compatibility with previous generations hardware. These registers listed information purposes only. Detailed descriptions actions programming these registers included numerous industry publications (duplication that information here beyond scope this document). these registers reside space. Port Misc Functions Speaker Control. SERR# Status SERR# been asserted default SERR# asserted agent Note: This when SERR# signal asserted. Once set, this cleared setting bit-2 this register. Bit-2 should cleared enable recording next SERR# (i.e., bit-2 must enable this set). IOCHK# Status IOCHK# been asserted. default IOCHK asserted agent Note: This when IOCHCK# signal asserted. Once set, this cleared setting bit-3 this register. Bit-3 should cleared enable recording next IOCHCK# (i.e., bit-3 must enable this set). IOCHCK# generates enabled. Timer/Counter Output This reflects output Timer/Counter without synchronization. Refresh Detected.RO This toggles every rising edge REFRESH# signal. IOCHK# Enable Enable (see bit-6 above) default Disable (force IOCHCK# inactive clear "IOCHCK# Active" condition bit-6) SERR# Enable Enable (see bit-7 above) default Disable (force SERR# inactive clear "SERR# Active" condition bit-7) Speaker Enable Disable. default Enable Timer/Ctr output drive SPKR Timer/Counter Enable Disable. default Enable Timer/Counter Port System Control. Reserved .always reads Address Line Enable disabled forced (real mode) default address line enabled High Speed Reset Normal Briefly pulse system reset switch from protected mode real mode
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Legacy Registers
VT8235M Version V-Link South Bridge
Keyboard Controller Registers keyboard controller handles keyboard mouse interfaces. ports used: port port Reads from port return status byte. Writes port command codes (see command code list following register descriptions). Input output data transferred port "Control" register also available. accessable writing commands command port (port 64h); control byte written first sending command port, then sending control byte value. control register read sending command port 64h, waiting "Output Buffer Full" status then reading control byte value from port 60h. Traditional (non-integrated) keyboard controllers have "Input Port" "Output Port" that control pins dedicated specific functions. integrated version, connections hard wired listed below. Outputs "open-collector" allow input these pins, output value that would high (non-driving) desired input value read input port. These ports defined follows: Input Port Keyboard Data Mouse Data Output Port System Reset Execute Reset) Gaste Enabled) Mouse Data Mouse Clock Keyboard Clock Keyboard Data Test Port Keyboard Clock Mouse Clock Port Keyboard Controller Input Buffer. Only write port port bit-1 (1=full). Port Keyboard Controller Output Buffer. Only read from port port bit-0 (0=empty). Port Keyboard Mouse Status Parity Error parity error (odd parity received). default Even parity occurred last byte received from keyboard mouse General Receive Transmit Timeout error default Error Mouse Output Buffer Full Mouse output buffer empty default Mouse output buffer holds mouse data Keylock Status Locked Free Command Data Last write data write. default Last write command write System Flag Power-On Default. default Self Test Successful Input Buffer Full Input Buffer Empty default Input Buffer Full Keyboard Output Buffer Full Keyboard Output Buffer Empty default Keyboard Output Buffer Full Control Register.(R/W Commands 20h/60h) Reserved .always reads Compatibility Disable scan conversion Convert scan codes format; convert 2byte break sequences 1-byte PC-compatible break codes default Mouse Interface Enable. default Disable Keyboard Interface Enable. default Disable Reserved .always reads System Flag default=0 This read back status register bit-2 Mouse Interrupts Disable. default Enable Generate interrupt IRQ12 when mouse data comes into output buffer Keyboard Interrupts Disable. default Enable Generate interrupt IRQ1 when output buffer been written.
Hardwired Internal Connections Keyboard Data (Open Collector) Keyboard Data Keyboard Clock (Open Collector) Keyboard Mouse Data (Open Collector) Mouse Data Mouse Clock (Open Collector) Mouse Clock Keyboard Interrupt IRQ1 Mouse Interrupt IRQ12 Input Output Test Port Command Codes transfers input port data output buffer. copies output port values output buffer. transfers test input port data output buffer. above definitions provided reference only actual keyboard mouse control longer performed bit-by using above ports controlled directly keyboard mouse controller internal logic. Data sent received using command codes listed following page.
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Legacy Registers
VT8235M Version V-Link South Bridge
Port Keyboard Mouse Command This port used send commands keyboard mouse controller. command codes recognized VT8235M Version listed table below.
Table Keyboard Controller Command Codes
Code 21-3Fh 61-7Fh Keyboard Command Code Description Read Control Byte (next byte Control Byte) Read SRAM Data (next byte Data Byte) Write Control Byte (next byte Control Byte) Write SRAM Data (next byte Data Byte) Output Keyboard Controller Version Test Password installed (always returns indicate installed) Disable Mouse Interface Enable Mouse Interface Mouse Interface Test (puts test results port 60h) (value: 0=OK, 1=clk stuck low, 2=clk stuck high, 3=data stuck 4=data stuck FF=general error) self test (returns not) Keyboard Interface Test (see Mouse Test) Disable Keyboard Interface Enable Keyboard Interface Return Version Read Input Port (read input data output buffer) Poll Input Port (read Mouse Data continuously status Unblock Mouse Output (use before change active mode) Reblock Mouse Output (protection mechanism Read Mode (output mode info port output buffer: bit-0=0 ISA, PS/2) Read Output Port (copy output port values port Write Output Port (data byte following written keyboard output port came from keyboard) Write Keyboard Output Buffer clear status bit-5 (write following byte keyboard) Write Mouse Output Buffer status bit-5 (write following byte mouse; value mouse input buffer appears have come from mouse) Write Mouse (write following byte mouse) Read Keyboard Clock Mouse Clock (return bits respectively response byte) Mouse Clock command Mouse Data command Gate command Pulse Mouse Clock 6usec Pulse Mouse Data 6usec Pulse Gate 6usec command Pulse System Reset 6usec
other codes listed undefined.
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Legacy Registers
VT8235M Version V-Link South Bridge
Controller Registers Ports 00-0F Master Controller Channels Master Controller control System Channels 0-3. There Master Controller registers: Address Bits 15-0 0000 0000 000x 0000 0000 0000 000x 0001 0000 0000 000x 0010 0000 0000 000x 0011 0000 0000 000x 0100 0000 0000 000x 0101 0000 0000 000x 0110 0000 0000 000x 0111 0000 0000 000x 1000 0000 0000 000x 1001 0000 0000 000x 1010 0000 0000 000x 1011 0000 0000 000x 1100 0000 0000 000x 1101 0000 0000 000x 1110 0000 0000 000x 1111 Register Name Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Mask Bits Ports 80-8F Page Registers There eight Page Registers, each channel. These registers provide bits 16-23 24-bit address each channel (bits 0-15 stored registers Master Slave Controllers). They located following Port addresses: Address Bits 15-0 0000 0000 1000 0111 0000 0000 1000 0011 0000 0000 1000 0001 0000 0000 1000 0010 0000 0000 1000 1111 0000 0000 1000 1011 0000 0000 1000 1001 0000 0000 1000 1010 Register Name Channel Page (M-0) Channel Page (M-1) Channel Page (M-2) Channel Page (M-3) Channel Page (S-0).RW Channel Page (S-1).RW Channel Page (S-2).RW Channel Page (S-3)
Controller Shadow Registers Controller shadow registers enabled setting function Rx77 shadow registers enabled, they read back indicated port instead standard controller registers (writes unchanged). Port -Channel Base Address Port -Channel Byte Count. Port -Channel Base Address Port -Channel Byte Count. Port -Channel Base Address Port -Channel Byte Count. Port -Channel Base Address Port -Channel Byte Count. Port -1st Read Channel Command Register Port -2nd Read Channel Request Register Port -3rd Read Channel Mode Register Port -4th Read Channel Mode Register Port -5th Read Channel Mode Register Port -6th Read Channel Mode Register Port -Channel Read Mask Port -Channel Base Address Port -Channel Byte Count. Port -Channel Base Address Port -Channel Byte Count Port -Channel Base Address Port -Channel Byte Count Port -1st Read Channel Command Register Port -2nd Read Channel Request Register Port -3rd Read Channel Mode Register Port -4th Read Channel Mode Register Port -5th Read Channel Mode Register Port -6th Read Channel Mode Register Port -Channel Read Mask.
Ports C0-DF Slave Controller Channels Slave Controller control System Channels 4-7. There Slave Controller registers: Address Bits 15-0 0000 0000 1100 000x 0000 0000 1100 001x 0000 0000 1100 010x 0000 0000 1100 011x 0000 0000 1100 100x 0000 0000 1100 101x 0000 0000 1100 110x 0000 0000 1100 111x 0000 0000 1101 000x 0000 0000 1101 001x 0000 0000 1101 010x 0000 0000 1101 011x 0000 0000 1101 100x 0000 0000 1101 101x 0000 0000 1101 110x 0000 0000 1101 111x Register Name Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read/Write Mask Bits
Note that bits address decoded. Master Slave Controllers compatible with Intel 8237 Controller chip. Detailed description 8237 controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
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Legacy Registers
VT8235M Version V-Link South Bridge
Interrupt Controller Registers Ports 20-21 Master Interrupt Controller Master Interrupt Controller controls system interrupt channels 0-7. registers control Master Interrupt Controller. They are: Address Bits 15-0 0000 0000 001x xxx0 0000 0000 001x xxx1 Register Name Master Interrupt Control Master Interrupt Mask Interrupt Controller Shadow Registers following shadow registers enabled setting function Rx47[4]. shadow registers enabled, they read back indicated port instead standard interrupt controller registers (writes unchanged). Port Master Interrupt Control Shadow Port Slave Interrupt Control Shadow Reserved .always reads OCW3 (POLL) OCW3 (RIS) OCW3 (SMM) OCW2 ICW4 (SFNM) ICW4 (AEOI) ICW1 (LTIM) Port Master Interrupt Mask Shadow. Port Slave Interrupt Mask Shadow Reserved .always reads T7-T3 Interrupt Vector Address Timer Counter Registers Ports 40-43 Timer Counter Registers There Timer Counter registers: Address Bits 15-0 0000 0000 010x xx00 0000 0000 010x xx01 0000 0000 010x xx10 0000 0000 010x xx11 Register Name Timer Counter Count Timer Counter Count Timer Counter Count Timer Counter Mode
Note that bits address decoded. Master Interrupt Controller compatible with Intel 8259 Interrupt Controller chip. Detailed descriptions 8259 Interrupt Controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications. Ports A0-A1 Slave Interrupt Controller Slave Interrupt Controller controls system interrupt channels 8-15. slave system interrupt controller also occupies register locations: Address Bits 15-0 0000 0000 101x xxx0 0000 0000 101x xxx1 Register Name Slave Interrupt Control Slave Interrupt Mask
Note that address bits decoded. Slave Interrupt Controller compatible with Intel 8259 Interrupt Controller chip. Detailed descriptions 8259 Interrupt Controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Note that bits address decoded. Timer Counters compatible with Intel 8254 Timer Counter chip. Detailed descriptions 8254 Timer Counter operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Timer Counter Shadow Registers following shadow registers enabled readback setting function Rx47[4]. shadow registers enabled, they read back indicated port instead standard timer counter registers (writes unchanged). Port Counter Base Count Value (LSB 2nd)RO Port Counter Base Count Value (LSB 2nd)RO Port Counter Base Count Value (LSB 2nd)RO
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Legacy Registers
VT8235M Version V-Link South Bridge
CMOS Registers Port CMOS Address.RW Disable Enable Generation. asserted encountering SERR# bus. Disable Generation .default CMOS Address (lower bytes) Port CMOS Data.RW CMOS Data (128 bytes) Note: Ports 70-71 accessed Device Function Rx51 bit-3 select internal RTC. Rx51 bit-3 zero, accesses ports 70-71 will directed external RTC. Offset Description Binary Range Range Seconds 00-3Bh 00-59h Seconds Alarm 00-3Bh 00-59h Minutes 00-3Bh 00-59h Minutes Alarm 00-3Bh 00-59h Hours 12hr: 01-1Ch 01-12h 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h Hours Alarm 12hr: 01-1Ch 01-12h 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h Week Sun=1: 01-07h 01-07h Month 01-1Fh 01-31h Month 01-0Ch 01-12h Year 00-63h 00-99h Register Update Progress DV2-0 Divide (010=ena keep time) RS3-0 Rate Select Periodic Interrupt Register SQWE 24/12 Register IRQF Register Inhibit Update Transfers Periodic Interrupt Enable Alarm Interrupt Enable Update Ended Interrupt Enable function (read/write bit) Data Mode (0=BCD, 1=binary) Hours Byte Format (0=12, 1=24) Daylight Savings Enable Interrupt Request Flag Periodic Interrupt Flag Alarm Interrupt Flag Update Ended Flag Unused (always read Reads VBAT voltage Unused (always read
Port CMOS Address.RW CMOS Address (256 bytes) Port CMOS Data.RW CMOS Data (256 bytes) Note: Ports 74-75 accessed only Rx4E bit-3 (Port 74/75 Access Enable) enable port 74/75 access. Ports 70-71 compatible with industrystandards used access lower bytes 256-byte on-chip CMOS RAM. Ports 7475 used access full on-chip extended 256-byte space cases where on-chip disabled. system Real Time Clock (RTC) part "CMOS" block. control registers located specific offsets CMOS data area (00Dh 7D-7Fh). Detailed descriptions CMOS operation programming obtained from VT82887 Data Book numerous other industry publications. reference, definition register locations bits summarized following table:
Note:
Note:
0E-7C Software-Defined Storage Registers (111 Bytes) Offset Extended Functions Date Alarm Month Alarm Century Field Binary Range Range 01-1Fh 01-31h 01-0Ch 01-12h 13-14h 19-20h
80-FF Software-Defined Storage Registers (128 Bytes)
Table CMOS Register Summary
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Legacy Registers
VT8235M Version V-Link South Bridge
Keyboard Mouse Wakeup Index Data Registers Keyboard Mouse Wakeup registers accessed performing operations from index data pair registers system space port addresses 2Fh. registers accessed using this mechanism used initialize Keyboard Mouse Wakeup functions index values range E0-EF. Keyboard Mouse Wakeup initialization accomplished three steps: Enter initialization mode (set Function Rx51[1] Initialize chip Write index port Read write data from port Repeat desired registers Exit initialization mode (set Function Rx51[1] Port Keyboard Wakeup Index Index Value Function configuration space register Rx51[1] must enable access configuration registers. Port Keyboard Wakeup Data.RW Data Value Index Keyboard Wakeup Scan Code (F0h). Keyboard Wakeup First Scan Code .def Index Keyboard Wakeup Scan Code (00h) Keyboard Wakeup Second Scan Code .def Index Keyboard Wakeup Scan Code (00h) Keyboard Wakeup Third Scan Code .def Index Keyboard Wakeup Scan Code (00h) Keyboard Wakeup Fourth Scan Code .def Index Keyboard Wakeup Scan Code (00h) Keyboard Wakeup Fifth Scan Code.def Index Keyboard Wakeup Scan Code (00h) Keyboard Wakeup Sixth Scan Code .def Index Keyboard Wakeup Scan Code (00h) Keyboard Wakeup Seventh Scan Code.def Index Keyboard Wakeup Scan Code (00h) Keyboard Wakeup Eighth Scan Code.def Index -Mouse Wakeup Scan Code (09h) Mouse Wakeup Scan Code 1.def Index -Mouse Wakeup Scan Code 2(00h) Mouse Wakeup Scan Code 2.def Index -Mouse Wakeup Scan Code Mask (00h) Mouse Wakeup Scan Code Mask.def
Keyboard Mouse Wakeup Registers These registers accessed port index data register pair with Function Rx51[1] using indicated index values below Index Keyboard Mouse Wakeup Enable (08h).RW Reserved always reads Reserved Program). default Win98 Keyboard Power Wake-up Disable Enable .default Password Wake-up Disable .default Enable PS/2 Mouse Wake-up Disable .default Enable Keyboard Wake-up Disable .default Enable
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Configuration Registers
VT8235M Version V-Link South Bridge
Memory Mapped APIC Registers Memory Address FEC00000 APIC Index.RW APIC Index default 8-bit pointer APIC registers. Memory Address FEC00013-10 APIC Data 31-0 APIC Data default 0000 0000h Data APIC register pointed APIC index Memory Address FEC00020 APIC AssertionWO Reserved always reads APIC Number.default undefined this interrupt. Valid values 0-23 only. Memory Address FEC00040 APIC Redirection Entry Clear.default undefined When write issued this register, APIC will check this field compare with vector field each entry redirection table. When match found, "Remote_IRR" that Redirection Entry will cleared. Indexed APIC Registers Offset APIC Identification (0000 0000h) 31-28 Reserved .always reads 27-24 APIC Identification. default Software must program this value before using APIC. 23-0 Reserved .always reads Offset APIC Version (00178003) 31-24 Reserved .always reads 23-16 Maximum Redirection .always reads Equal number APIC interrupt pins minus one. this APIC, this value decimal). Always reads indicate that assertion register implemented that devices allowed write cause interrupts. 14-8 Reserved .always reads APIC Version.always reads implementation version this APIC 03h. Offset APIC Arbitration (0000 0000h) 31-28 Reserved .always reads 27-24 APIC Arbitration ID.always reads 23-0 Reserved .always reads Offset Boot Configuration (0000 0000h). 31-1 Reserved .always reads Interrupt Delivery Mechanism APIC Serial default Front Side Message
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Memory Mapped APIC Registers
VT8235M Version V-Link South Bridge
Offset 3F-10 Redirection Table This table contains registers, with dedicated table entry each APIC interrupt signals. Each 64-bit register consists 32-bit values consecutive index locations, with bits even index upper bits index. default value registers xxx1 xxxx xxxx xxxxh. Offset 11-10 Redirection APIC IRQ0 Offset 13-12 Redirection APIC IRQ1 Offset 15-14 Redirection APIC IRQ2 Offset 17-16 Redirection APIC IRQ3 Offset 19-18 Redirection APIC IRQ4 Offset 1B-1A Redirection APIC IRQ5.RW Offset 1D-1C Redirection APIC IRQ6 Offset 1F-1E Redirection APIC IRQ7 Offset 21-20 Redirection APIC IRQ8 Offset 23-22 Redirection APIC IRQ9 Offset 25-24 Redirection APIC IRQ10 Offset 27-26 Redirection APIC IRQ11 Offset 29-28 Redirection APIC IRQ12 Offset 2B-2A Redirection APIC IRQ13.RW Offset 2D-2C Redirection APIC IRQ14 Offset 2F-2E Redirection APIC IRQ15 Offset 31-30 Redirection APIC IRQ16 Offset 33-32 Redirection APIC IRQ17 Offset 35-34 Redirection APIC IRQ18 Offset 37-36 Redirection APIC IRQ19 Offset 39-38 Redirection APIC IRQ20 Offset 3B-3A Redirection APIC IRQ21.RW Offset 3D-3C Redirection APIC IRQ22 Offset 3F-3E Redirection APIC IRQ23 Format Each Redirection Table Entry: Physical Mode (bit-11=0) 63-60 Reserved .always reads 59-56 APIC default undefined Logical Mode (bit-11=1) 63-56 Destination default undefined 55-17 Reserved .always reads
Interrupt Masked masked. default Masked Trigger Mode Edge Sensitive default Level Sensitive Remote (Level Sensitive Interrupts Only) message with matching interrupt vector received from local APIC Level sensitive interrupt sent IOAPIC accepted local APIC(s) Interrupt Input Polarity Active High default Active Delivery Status. Contains current status delivery this interrupt. Idle activity) Send Pending (the interrupt been injected delivery temporarily delayed either because APIC busy because receiving APIC unit cannot currently accept interrupt) Destination Mode Determines interpretation bits 56-63. Physical Mode default Logical Mode
10-8 Delivery Mode Specifies APICs listed destination field should upon reception this signal Fixed default Lowest Priority -reserved100 INIT -reserved111 External Interrupt Vector Contains interrupt vector this interrupt. Vector values range from FEh.
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Memory Mapped APIC Registers
VT8235M Version V-Link South Bridge
Configuration Space Configuration space accesses functions configuration mechanism (see specification revision more details). ports respond only double-word accesses. Byte word accesses will passed unchanged. Port CFB-CF8 Configuration Address Configuration Space Enable Disabled .default Convert configuration data port writes configuration cycles 30-24 Reserved always reads 23-16 Number Used choose specific system 15-11 Device Number Used choose specific device system 10-8 Function Number Used choose specific function selected device supports multiple functions Register Number Used select specific doubleword device's configuration space Fixed always reads Port CFF-CFC Configuration Data There "functions" implemented VT8235M Version (see Table page 22). following sections describe registers register bits these functions.
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Configuration Space Registers
VT8235M Version V-Link South Bridge
Device Function Registers UHCI Ports This Universal Serial host controller interface fully compatible with UHCI specification v1.1. There sets software accessible registers: configuration registers registers. configuration registers located Device Function configuration space VT8235M Version registers defined UHCI specification v1.1. registers this function control ports (see function ports function ports 4-5). Configuration Space Header Offset Vendor (1106h) 15-0 Vendor (1106h Technologies) Offset Device (3038h) 15-0 Device (3038h VT8235M-CD Controller) Offset Command (0000h).RW 15-8 Reserved always reads Reserved (address stepping) .fixed Reserved (parity error response) .fixed Reserved (VGA palette snoop) .fixed Memory Write Invalidate default=0 (disabled) Reserved (special cycle monitoring).fixed Master default=0 (disabled) Memory Space. default=0 (disabled) Space default=0 (disabled) Offset Status (0210h) Reserved (detected parity error). always reads Signalled System Error default=0 Received Master Abort. default=0 Received Target Abort default=0 Signalled Target Abort. default=0 10-9 DEVSEL# Timing Fast Medium.default (fixed) Slow Reserved Reserved .fixed (PCI PMI) Offset 23-20 Register Base Address. 31-16 Reserved .always reads 15-5 Register Base Address. Port Address base 32-byte Register block, corresponding AD[15:5] 00001b Offset Revision (nnh) Silicon Revision Code indicates first silicon)
Offset Programming Interface (00h) Offset Class Code (03h=USB Controller) Offset Base Class Code (0Ch=Serial Controller)RO
Offset Latency Timer (16h)
Offset 2D-2C Vendor (1106h). Offset 2F-2E Device (3038h). Rx42[4]
Offset Power Management Capabilities (80h)
Offset Interrupt Line (00h). Reserved .always reads Interrupt Routing 0000 Disabled. default 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 Disabled Offset Interrupt (01h). Interrupt Pin.default (INTA#)
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Device Function UHCI Registers Ports
VT8235M Version V-Link South Bridge
USB-Specific Configuration Registers Offset Miscellaneous Control (40h) Reserved always reads Babble Option This controls whether port disabled when (End-Of-Frame) babble occurs. Babble unexpected activity that persists into interval. When this port with babble disabled. When disabled Automatically disable babbled port when babble occurs Don't disable babbled port .default Parity Check Disable .default Enable Frame Interval Select msec frame time .default msec frame time Data Length Option Support length 1280.default Support length 1023 Transfer Descriptor) Improve FIFO Latency Improve latency packet size bytes .def Disable improvement Option Enhanced performance burst access with better FIFO latency).default Normal performance burst access with normal FIFO latency) Reserved always reads Offset Miscellaneous Control (10h) Improvement This controls whether Specification followed when stuffing error occurs before (End-Of-Packet). stuffing error results when receiver sees seven consecutive ones packet. Under specification 1.1, when this occurs interval just before EOP, receiver will accept packet. Under specification 1.0, packet ignored. Spec Compliant (packet accepted) Spec Compliant (packet ignored) Reserved Program) default Trap Option Under UHCI spec, port trapped only when corresponding enable bits set. When this set, trap without checking enable bits. trap 60/64 status bits only when trap 60/64 enable bits default trap 60/64 status bits without checking enable bits A20Gate Pass Through Option This controls whether A20Gate pass-through sequence defined UHCI) followed. A20Gate sequence consists commands. When this 4-command sequence followe
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