1,048,576-word 4-bit Dynamic Random Access Memory Rev. Dec. 1994

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1,048,576-word 4-bit Dynamic Random Access Memory Rev. Dec. 1994

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ADE-203-D177B
1,048,576-word 4-bit Dynamic Random Access Memory
Rev. Dec. 1994
Hitachi HM51W4400B/BL CMOS dynamic organized 1,048,576-word 4-bit. HM51W4400B/BL realized higher density, higher performance various functions employing CMOS process technology some CMOS circuit design technologies. HM51W4400B/BL offers Fast Page Mode high speed access mode. Multiplexed address input permits HM51W4400B/BL packaged standard 300-mil 26-pin plastic 26-pin plastic TSOP Test function Battery back operation Self refresh operation (L-version)
HM51W4400B Series HM51W4400BL Series (Low Power Version)
Ordering Information
Type HM51W4400BS-6 HM51W4400BS-7 HM51W4400BS-8 HM51W4400BLS-6 HM51W4400BLS-7 HM51W4400BLS-8 HM51W4400BTT-6 HM51W4400BTT-7 HM51W4400BTT-8 HM51W4400BLTT-6 HM51W4400BLTT-7 HM51W4400BLTT-8 Access time 26-pin plastic TSOPII (TTP-26/20D) Package 300-mli 26-pin plastic (CP-26/20D)
Features
Single High speed Access time ns/70 ns/80 (max) power dissipation Active mode mW/252 mW/216 (max) Standby mode (max) 0.18 (max) (L-version) Fast page mode capability 1024 refresh cycles 1024 refresh cycles (L-version) variations refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version)
HM51W4400B/BL Series
Arrangement
HM51W4400BS/BLS Series HM51W4400BTT/BTT Series
I/O1 I/O2
I/O4 I/O3
I/O1 I/O2
I/O4 I/O3
(Top view)
(Top view)
Description
name I/O1 I/O4 Function Address input Refresh address input Data-in/Data-out address strobe Column address strobe Read/Write enable Output enable Power typ) Ground
Block Diagram
Driver
Driver
Control Circuit
Memory Array
Memory Array
I/O1
I/O1 Buffer
Column Decoder
Driver Driver
Column Decoder Memory Array Memory Array
Memory Array
Driver Driver
Control Circuit
Memory Array
Address Buffer I/O2 I/O2 Buffer
Column Decoder
Driver Driver
Column Decoder Memory Array
Memory Array
Control Circuit
Decoder Peripheral Circuit
Address A0-A9
Driver Driver
Memory Array
Memory Array Column Decoder
I/O3
I/O3 Buffer
Control Circuit
Column Decoder
Driver Driver
Memory Array
Driver Driver
Memory Array Memory Array
Memory Array
Column Address Buffer
Driver Driver
I/O4
I/O4 Buffer
Column Decoder
Column Decoder Memory Array
Memory Array
HM51W4400B/BL Series
HM51W4400B/BL Series
Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Symbol Iout Topr Tstg Value -0.5 +4.6 -0.5 +4.6 +125 Unit
Recommended Operating Conditions +70°C)
Parameter Supply voltage Symbol Input high voltage Input voltage Note: -0.3 Unit Note
voltage referred VSS.
HM51W4400B/BL Series
Characteristics +70°C,
HM51W4400B/BL Parameter Operating current Standby current Symbol ICC1 ICC2 Unit Test conditions RAS, cycling interface RAS, Dout High-Z CMOS interface RAS, Dout High-Z CMOS interface RAS, Address Dout High-Z Dout enable tRAS VIH, VIL, Address Dout High-Z RAS, VIL, Address VIL, Dout High-Z Vout Dout disable High Iout Iout Notes
Standby current (L-version)
ICC2
RAS-only refresh current Standby current
ICC3 ICC5
CAS-before-RAS refresh current Fast page mode current Battery back operating current (Standby with refresh) (L-version)
ICC6 ICC7 ICC10
Self-refresh current (L-version) Input leakage current Output leakage current
ICC11
Output high voltage Output voltage
HM51W4400B/BL Series
Notes: depends output load condition when device selected. specified output open condition. Address changed twice less while VIL. Address changed once less while VIH.
Capacitance +70°C,
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI/O Unit Notes
Notes: Capacitance measured with Boonton Meter effective capacitance measuring method. disable Dout.
HM51W4400B/BL Series
Characteristics +70°C, *14, *15,
Test Conditions Input rise fall times Input timing reference levels Output timing reference levels Output load gate (100 (Including scope jig)
Read, Write, Read-Modify-Write Refresh Cycles (Common parameters)
HM51W4400B/BL Parameter Random read write cycle time precharge time pulse width pulse width address setup time address hold time Column address setup time Column address hold time delay time column address delay time hold time hold time precharge time delay time delay time from setup time from Transition time (rise fall) Refresh period Refresh period (L-version) Symbol tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tREF tREF Unit Notes
10000 10000
10000 10000
10000 10000
HM51W4400B/BL Series
Read Cycle
HM51W4400B/BL Parameter Access time from Access time from Access time from address Access time from Read command setup time Read command hold time Read command hold time Column address lead time Output buffer turn-off time Output buffer turn-off time delay time pulse width Symbol tRAC tCAC tOAC tRCS tRCH tRRH tRAL tOFF1 tOFF2 tCDD tOEP Unit Notes
Write Cycle
HM51W4400B/BL Parameter Write command setup time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tRWL tCWL Unit Notes
HM51W4400B/BL Series
Read-Modify-Write Cycle
HM51W4400B/BL Parameter Read-modify-write cycle time delay time delay time Column address delay time hold time from Symbol tRWC tRWD tCWD tAWD tOEH Unit Notes
Refresh Cycle
HM51W4400B/BL Parameter setup time (CBR refresh cycle) hold time (CBR refresh cycle) precharge hold time precharge time normal mode Symbol tCSR tCHR tRPC tCPN Unit Notes
Fast Page Mode Ccycle
HM51W4400B/BL Parameter Fast page mode cycle time Fast page mode pulse width Access time from precharge hold time from precharge Symbol tRASC tACP tRHCP Unit Notes
Fast page mode precharge time
100000
100000
100000
HM51W4400B/BL Series
Fast Page Mode Read-Modify-Write Cycle
HM51W4400B/BL Parameter Fast page mode read-modify-write cycle time Fast page mode read-modify-write cycle precharge delay time Symbol tPCM tCPW Unit Notes
Test Mode Cycle
HM51W4400B/BL Parameter Test mode setup time Test mode hold time Symbol Unit Notes
Counter Test Cycle
HM51W4400B/BL Parameter precharge time counter test cycle Symbol tCPT Unit Notes
Self-Refresh Mode (L-version)
HM51W4400B/BL Parameter pulse width (self-refresh) precharge time (self-refresh) hold time (self-refresh) Symbol tRASS tRPS tCHS Unit Notes
HM51W4400B/BL Series
Notes: measurements assume Assumes that tRCD tRCD (max) tRAD tRAD (max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent loads Assumes that tRCD tRCD (max) tRAD tRAD (max). Assumes that tRCD tRCD (max) tRAD tRAD (max). tOFF (max) defines time which output achieves open circuit condition referred output voltage levels. (min) (max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD (max) limit insures that tRAC (max) met, tRCD (max) specified reference point only, tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation with tRAD (max) limit insures that tRAC (max) met, tRAD (max) specified reference point only, tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. tWCS, tRWD, tCWD, tCPW tAWD restrictive operating parameters. They included data sheet electrical characteristics only; tWCS tWCS (min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD tRWD (min), tCWD tCWD (min), tCPW tCPW (min) tAWD tAWD (min), cycle read-modify-write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referred leading edge early write cycle leading edge delayed write read-modify-write cycle. tRASC defines pulse width fast page mode cycles. Access time determined longest among tAA, tCAC tACP. initial pause required after power followed minimum eight initialization cycles (RAS-only refresh cycle CAS-before-RAS refresh cycle). internal refresh counter used, minimum eight CAS-before-RAS refresh cycles required. delayed write read-modify-write cycles, must disable output buffer prior applying data device. Test mode operation specified this data sheet 2-bit test function controlled control address bits CA0. This test mode operation performed WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will performed normal read cycles WCBR refresh cycles. When state test bits accord each other, condition output data high level. When state test bits accord, cond-tion output data level. order this test mode operation, perform RAS-only refresh cycle CAS-before-RAS refresh cycle. test mode read cycle, value tRAC, tAA, tCAC, tOAC tACP delayed specified value. These parameters should specified test mode cycles adding above value specified value this data sheet. Either tRCH tRRH must satisfied tRAS (min) tRWD (min) tRWL (min) read-modify-write cycle. tCAS (min) tCWD (min) tCWL (min) read-modify-write cycle.
HM51W4400B/BL Series
Timing Waveforms*21
Read Cycle
Address
Column
Dout High-Z OFF1
Dout OFF2
Notes:
(min) (max), (min) (max))
Invalid Dout
HM51W4400B/BL Series
Early Write Cycle
Address
Column
Dout
High-Z*
(min)
HM51W4400B/BL Series
Delayed Write Cycle
Column
Address
Dout
Invalid Dout*
High-Z
OFF2
Invalid Dout comes out, when level.
HM51W4400B/BL Series
Read-Modify-Write Cycle
tCAH
Address
Column
High-Z
Dout
Dout
OFF2
HM51W4400B/BL Series
RAS-Only Refresh Cycle
tRPC tCRP
Address
Dout
High-Z
Refresh address (AX0 AX9)
HM51W4400B/BL Series
CAS-Before-RAS Refresh Cycle
Address
OFF1 High-Z
Dout
HM51W4400B/BL Series
Hidden Refresh Cycle
(Read)
(Refresh)
(Refresh)
Address Column Dout Dout OFF2 High-Z tDZO OFF1
HM51W4400B/BL Series
Fast Page Mode Read Cycle
RASC RHCP
Address tASC Column Column Column
High-Z High-Z tCAC OFF1 Dout OFF2 Dout Dout
High-Z OFF1 Dout OFF2 OFF2 OFF1
HM51W4400B/BL Series
Fast Page Mode Early Write Cycle
RASC
Address
Column
Column
Column
Dout
High-Z
HM51W4400B/BL Series
Fast Page Mode Delayed Write Cycle
RASC
tRCD
Column
Address
Column
Column
Dout
High-Z
HM51W4400B/BL Series
Fast Page Mode Read-Modify-Write Cycle
RASC
Address
Column
Column
Column
High-Z tOAC Dout Dout OFF2 Dout OFF2 High-Z Dout OFF2
High-Z
tOEP
HM51W4400B/BL Series
Test Mode Cycle
Cycle**
Test Mode Cycle
*,** Reset Cycle
Normal Mode
RAS-only refresh Address, Din,
Test Mode Cycle WE-and-CAS-Before RAS-Refresh Cycle
CPN@
Address OFF1 High-Z
Dout
HM51W4400B/BL Series
CAS-Before-RAS Refresh Counter Check Cycle (Read)
tCRP
Address
Column
High-Z
OFF1
Dout
Dout OFF2
HM51W4400B/BL Series
CAS-Before-RAS Refresh Counter Check Cycle (Write)
Address
Column
Dout
High-Z
HM51W4400B/BL Series
Self Refresh Cycle
RASS
OFF1 Dout High-Z
Address
self refresh current achieved introducing extremely long internal refresh cycle. Therefore some care needs taken refresh. Please tRASS timing, tRASS During this period, device transition state from normal operation mode self refresh mode. tRASS then precharge time should tRPS instead tRP. only refresh burst refresh mode normal read/write cycle, 1024 cycles distributed refresh with 15.6 interval should executed within immediately after exiting from before entering into self refresh mode. distributed refresh mode with 15.6 interval normal read/write cycle, refresh should executed within 15.6 immediately after exiting from before entering into self refresh mode. Repetitive self refresh mode without refreshing memory allowed. Once exit from self refresh mode, memory cells need refreshed before re-entering self refresh mode again.

1,048,576-word 4-bit Dynamic Random Access Memory Rev. Dec. 1994

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