µPD78011B, 78012B, 78013, 78014 8-BIT SINGLE-CHIP MICROCOMPUTER

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µPD78011B, 78012B, 78013, 78014 8-BIT SINGLE-CHIP MICROCOMPUTER

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INTEGRATED CIRCUIT
µPD78011B, 78012B, 78013, 78014
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
µPD78011B/78012B/78013/78014 prodcts µPD78014 subseries within 78K/0 Series. µPD78011B/78012B/78013/78014 have 8-bit resolution converter, timer, serial interface, interrupt control, many other peripheral hardware functions. one-time PROM EPROM product µPD78P014 capable operating same power supply voltage range mask product other development tools also provided.
Functions described detail following User's Manual, which should read when carring design work. µPD78014, 78014Y Series User's Manual: IEU-1343
FEATURES
Large on-chip
Item Product Name Data Memory Internal HighSpeed bytes Package Buffer bytes 64-pin plastic shrink (750 mil) 64-pin plastic 1024bytes
Program Memory (ROM) bytes bytes bytes bytes
µPD78011B µPD78012B µPD78013 µPD78014
External memory expansion space bytes Instruction execution time varied from high-speed (0.4 ultra-low-speed (122 ports: (N-ch open-drain 8-bit resolution converter channels Serial interface channels Timer channels Operating voltage range
Application
Telephone, VCR, audio, camera, home appliances, etc.
information this document subject change without notice. Document IC-3179D (O.D.No. IC-8201F) Date Published January 1995 Printed Japan
mark shows major revised points.
1992
µPD78011B, 78012B, 78013, 78014
ORDERING INFORMATION
Ordering Code Package 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic plastic plastic plastic plastic shrink (750 shrink (750 shrink (750 shrink (750 mil) mil) mil) mil) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard
Remarks
indicates code
Please refer "Quality grade Semiconductor Devices" (Document number IEI-1209) published Corporation know specification quality grade devices recommended applications.
78K/0 SERIES DEVELOPMENT
PD78078Y SubSeries PD78064Y SubSeries
Products under Development
Products Volume Production
PD78078 SubSeries
100-pin package 8-bit timer/event counter added External expansion function enhanced
PD78064 SubSeries
100-pin package controller/driver, UART added 16-bit timer/event counter function enhanced
series products compatible with bus.
PD78054Y SubSeries PD78054 SubSeries
80-pin package UART, converter, Real-time output port added 16-bit timer/event counter function enhanced
PD78098 SubSeries
80-pin package IEBuscontroller added
PD78018FY SubSeries PD78014Y SubSeries PD78014 SubSeries PD78018F SubSeries
64-pin package Low-voltage, high-speed operation possible
PD78083 SubSeries
42/44-pin package UART, converter, 8-bit timer/event counter function enhanced
64-pin package converter, bit-timer/event counter function, with automatic transmit/receive function added Multiplication/division instruction added PD78044A SubSeries
PD780208 SubSeries
100-pin package controller/driver function enhanced
PD78044 SubSeries
80-pin package Automatic transmit/receive function added 6-bit up/down counter added controller/driver function enhanced
PD78024 SubSeries PD78002Y SubSeries PD78002 SubSeries
64-pin package 64-pin package converter, bit-timer/event counter, FIB® controller/driver, Multiplication/division instruction added
µPD78011B, 78012B, 78013, 78014
OVERVIEW FUNCTION (1/2)
Item Product Name Internal highspeed Buffer bytes bytes bytes bytes bits registers bits registers banks) On-chip instruction execution time cycle modification function µs/0.8 µs/1.6 µs/3.2 µs/6.4 10.0 operation) 32.768 operation) 16-bit operation Multiplication/division bits bits,16 bits bits) manipulation (set, reset, test, boolean operation) correction, etc. bytes bytes 1024 bytes bytes
µPD78011B
µPD78012B
µPD78013
µPD78014
Internal memory
Memory space General registers Instruction cycle When main system clock selected When subsystem clock selected Instruction
ports
Total CMOS input CMOS N-channel open-drain withstand voltage)
converter
8-bit resolution channels Operable over wide power supply voltage range: 3-wire/SBI/2-wire mode selectable: channel 3-wire mode (on-chip max. bytes automatic data transmit/receive function): channel 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Serial interface
Timer
Timer output Clock output
(14-bit output 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 main system clock 10.0 operation), 32.768 subsystem clock 32.768 operation) kHz, kHz, main system clock 10.0 operation) Internal External: Internal
Buzzer output Vectored interrupts Maskable interrupts Non-maskable interrupt Software interrupt
Internal
µPD78011B, 78012B, 78013, 78014
OVERVIEW FUNCTION (2/2)
Item Product Name Test input
µPD78011B
Internal External +85°C
µPD78012B
µPD78013
µPD78014
Operating voltage range Operating temperature range Package
64-pin plastic shrink (750 mil) 64-pin plastic
µPD78011B, 78012B, 78013, 78014
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS
PORT PINS OTHER PORTS CIRCUIT RECOMMENDED CONNECTION UNUSED PINS
MEMORY SPACE PERIPHEL HARDWARE FUNCTION FEATURES
PORTS CLOCK GENERATOR TIMER/EVENT COUNTER CLOCK OUTPUT CONTROL CIRCUIT BUZZER OUTPUT CONTROL CIRCUIT CONVERTOR SERIAL INTERFACES
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS TEST FUNCTIONS
EXTERNAL DEVICE EXPANTION FUNCTIONS STANDBY FUNCTIONS RESET FUNCTIONS
INSTRUCTION ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVE (REFERENCE VALUES) PACKAGE INFORMATION RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78011B, 78012B, 78013, 78014
CONFIGURATION (Top View)
64-Pin Plastic Shrink (750 mil)
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13
P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P57/A15 P56/A14
Caution
Always connect (Internally Connected) directly. Always connect AVDD VDD. Always connect AVSS VSS.
µPD78011BCW- µPD78013CW- µPD78012BCW- µPD78014CW-
µPD78011B, 78012B, 78013, 78014
64-Pin Plastic
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P27/SCK0
P22/SCK1
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
P12/ANI2
P21/SO1
P23/STB
P20/SI1
P11/ANI1 P10/ANI0 P04/XT1 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 RESET P67/ASTB P66/WAIT
µPD78011BGC- -AB8 µPD78012BGC- -AB8 µPD78013GC- -AB8 µPD78014GC- -AB8
P50/A8
P47/AD7
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
Caution
Always connect (Internally Connected) directly. Always connect AVDD VDD. Always connect AVSS VSS.
P65/WR
P64/RD
µPD78011B, 78012B, 78013, 78014
Port Port Port Port Port Port Port
WAIT ASTB XT1, RESET ANI0 ANI7 AVDD AVSS AVREF
Address/Data Address Read Strobe Write Strobe Wait Address Strobe Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Ground Internally Connected
INTP0 INTP3 Interrupt From Peripherals Timer Input SB0, SI0, SO0, SCK0, SCK1 BUSY Timer Output Serial Serial Input Serial Output Serial Clock Programmable Clock Buzzer Clock Strobe Busy
BLOCK DIAGRAM
TO0/P30 TI0/INTP0/P00
16-bit TIMER/ EVENT COUNTER
PROGRAM COUNTER
PORT0
P01-P03
TO1/P31 TI1/P33
8-bit TIMER/ EVENT COUNTER PROGRAM MEMORY GENERAL REG. DECODE CONTROL
PORT1
P10-P17
TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER
PORT2 DATA MEMORY PORT3
P20-P27
P30-P37
WATCHDOG TIMER
PORT4 WATCH TIMER
P40-P47
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24
SERIAL INTERFACE
PORT5
P50-P57
PORT6
P60-P67
µPD78011B, 78012B, 78013, 78014
SERIAL INTERFACE
BUZZER OUTPUT
CLOCK OUTPUT CONTROL
CLOCK DIVIDER
CLOCK GENERATOR MAIN
STAND CONTROL
AD0/P40AD7/P47 A8/P50A15/P57
ANI0/P10 -ANI7/P17 AVDD AVSS AVREF INTP0/P00 -INTP3/P03
CONVERTER
BUZ/P36
PCL/P35
P04/XT1
EXTERNAL ACCESS
RD/P64 WR/P65 WAIT/P66 ASTB/P67
INTERRUPT CONTROL
RESET
Remarks
Internal capacity varies depending product.
µPD78011B, 78012B, 78013, 78014
FUNCTIONS
PORT PINS (1/2)
Input Input/ output Port 5-bit port Input only Input/output specified bit-wise. When used input port, pull-up resistor used software. Input only Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software.*2 Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor used software. Function After Reset Input Input DualFunction INTP0/TI0 INTP1 INTP2 INTP3 Input Input/ output Input Input ANI0 ANI7
Name P04*1
Input/ output
Input
SCK1 BUSY SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 8-bit input/output port. Input/output specified 1-bit units. When used input port, pull-up resistor used software.
Input
Input/ output
Port 8-bit input/output port. Input/output specified 8-bit unit. When used input port, pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Input
When using P04/XT1 pins input port, (REC) processor control register. on-chip feedback register subsystem clock oscillator. When using P10/ANI0 P17/ANI7 pins converter analog input, pull-up resistor automatically unused.
µPD78011B, 78012B, 78013, 78014
PORT PINS (2/2)
Input/ output Function Port 8-bit input/output port. driven directly. Input/output specified bit-wise. When used input port, pull-up resistor used software. Port 8-bit input/output port. Input/output specified bit-wise. After Reset Input DualFunction
Name
Input/ output
N-ch open-drain input/output port. Input On-chip pull-up resistor specified mask option. driven directly. WAIT ASTB
When used input port, pull-up resistor used software.
Caution
When pull-up resistors used (specified mask option), low-level input leak current increases with -200 (MAX.) under either following conditions.
When external device expansion function used low-level input pin. During 3-clock period when read instruction executed port (P6) port mode register (PM6).
OTHER PORTS (1/2)
Input Function External interrupt input which effective edge (rising edge, falling edge, both rising edge falling edge) specified. Falling edge detection external interrupt input. Input Serial interface serial data input. Input After Reset Input DualFunction P00/TI0 P25/SB0 Output Serial interface serial data output. Input P26/SB1 Input /output Input /output Output Input Serial interface serial data input/output. Input P25/SI0 P26/SO0 Serial interface serial clock input/output. Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Input Input
Name INTP0 INTP1 INTP2 INTP3 SCK0 SCK1 BUSY
µPD78011B, 78012B, 78013, 78014
OTHER PORTS (2/2)
DualFunction P00/INTP0 Input Output Output Input /output Output Output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Low-order address/data external memory expansion. Input Input Input Input Input
Name
Input
Function External count clock input 16-bit timer (TM0). External count clock input 8-bit timer (TM1). External count clock input 8-bit timer (TM2).
After Reset Input
Output
16-bit timer output (shared 14-bit output). 8-bit timer output.
WAIT ASTB
High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Output
Wait insertion external memory access. Strobe output which latches address information output port port access external memory. converter analog input. converter reference voltage input. converter analog power supply. Connected VDD. converter ground potential. Connected VSS. System reset input. Main system clock oscillation crystal connection.
Input Input
ANI0 ANI7 AVREF AVDD AVSS RESET
Input Input Input Input Input
Input
Subsystem clock oscillation crystal connection.
Input
Positive power supply. Ground potential. Internal connection. Connected directly.
µPD78011B, 78012B, 78013, 78014
CIRCUITS RECOMMENDED CONNECTION UNUSED PINS input/output circuit type each recommended connection unused pins shown Table input/output circuit configuration each type, Fig. 3-1. Table Input/Output Circuit Type Each (1/2)
Name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 P17/ANI7
Input/output Circuit Type
Input Input/output
Recommended Connection when Used Connected Input Output Connected Leave open.
Input Input/output
Connected Input Output Input Output Connected Leave open. Connected Leave open.
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7
10-A
Input/output
Input/output
Input Output
Connected Leave open.
Input/output
Input Output Input Output
Connected Leave open. Connected Leave open.
P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB
13-B
Input/output
µPD78011B, 78012B, 78013, 78014
Table Input/Output Circuit Type Each (2/2)
Name RESET AVREF AVDD AVSS Input/Output Circuit Type Input Leave open. Connected Connected Connected Connected directly. Recommended Connection when Used
µPD78011B, 78012B, 78013, 78014
Fig. Input/Output Circuits
Type Type 10-A
pullup enable
P-ch
data open drain output disable
P-ch N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type pullup enable data output disable input enable Type pullup enable data output disable
P-ch
Type
pullup enable data
P-ch P-ch N-ch P-ch N-ch (Threshold Voltage)
P-ch N-ch
output disable Comparator
input enable
P-ch P-ch N-ch
Type 13-B
Mask Option data output disable N-ch P-ch
Middle-High Voltage Input Buffer
Type pullup enable data output disable
P-ch
Type
feedback cut-off P-ch
P-ch N-ch
µPD78011B, 78012B, 78013, 78014
MEMORY SPACE
memory µPD78011B/78012B/78013/78014 shown 4-1.
Fig.4-1 Memory
FFFFH Special Function Registers (SFR) Bits FF00H FEFFH FEE0H FEDFH General Registers Bits
Internal High-Speed RAM*
mmmmH mmmmH-1 Prohibited Data Memory Space FAE0H FADFH FAC0H FABFH FA80H FA7FH Program Memory Space nnnnH+1 nnnnH Buffer Bits
nnnnH Program Area 1000H 0FFFH CALLF Entry Area Prohibited 0800H 07FFH Program Area External Memory 0080H 007FH CALLT Table Area 0040H 003FH Internal ROM* Vector Table Area 0000H
0000H
Remarks
Shaded area indicates internal memory.
Intermal internal high-speed capacities vary depending product (see table below).
Product Name Intenal Address nnnnH 1FFFH 3FFFH 5FFFH 7FFFH FB00H Internal High-Speed StartAddress mmmmH FD00H
µPD78011B µPD78012B µPD78013 µPD78014
µPD78011B, 78012B, 78013, 78014
PERIPHERAL HARDWARE FUNCTION FEATURES
PORTS
port following three types CMOS input (P00, P04) CMOS input/output (P01 P03, port port P67) N-ch open-drain input/output(15V withstand voltage) (P60 P63) Total
Table Functions Ports
Port Name Port Name P00, Port Port Port Port Dedicated Input port Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Input/output ports. Input/output specified 8-bit units. When used input port, pull-up resistor used software. Test input flag (KRIF) falling edge detection. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. driven directly. N-ch open-drain input/output port. Input/output specified bit-wise. On-chip pull-up resistor specified mask option. driven directly. Input/output ports. Input/output specified bit-wise. When used input port, pull-up resistor used software. Function
Port
Port
Caution
When pull-up resistors used (specified mask option), low-level input leak current increases with (MAX.) under either following conditions. When external device expansion function used low-level input pin. During 3-clock period when read instruction executed port (P6) port mode register (PM6).
µPD78011B, 78012B, 78013, 78014
CLOCK GENERATOR
There types clock generator: main system clock subsystem clock. instruction exection time changed. 0.4µs/0.8µs/1.6µs/3.2µs/6.4µs (Main system clock: 10.0 operation) 122µs (Subsystem clock: 32.768 operation)
Fig. Clock Generator Block Diagram
XT1/P04
Subsystem Clock Osicillator
Watch Timer Clock Output Function Prescaler
Main System Clock Osicillator
Prescaler
Clock Peripheral Hardware
STOP
Selector
Standby Control Circuit
Wait Control Circuit
Clock (fCPU)
INTP0 Sampling Clock
µPD78011B, 78012B, 78013, 78014
TIMER/EVENT COUNTER following five channels incorporated timer/event counter. 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Table Types Features Timer/Event Counter
16-bit Timer/Event Counter Type Interval timer Externanal event counter Functions Timer output output Pulse width mesurement Sqare wave output Interrupt request channel channel output output input output 8-bit Timer/Event Counter channels channels outputs outputs
Watch Timer 1channel
Watchdog Timer channel
µPD78011B, 78012B, 78013, 78014
Fig. 16-bit Timer/Enent Counter Block Diagram
Internal
16-Bit Compare Register (CR00) Pulse Output Control Circuit 16-Bit Timer Register (TM0) Clear Selector Output Control Circuit
INTTM0
Match
TO0/P30
fX/2 fX/22 fX/23 TI0/INTP0/P00
Edge Detection Circuit Selector
INTP0 16-Bit Capture Register (CR01)
Internal
Fig. 8-bit Timer/Enent Counter Block Diagram
Internal INTIM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector
Match
Output Control Circuit
TO2/P32 INTTM2
fX/22-fX/210 fX/212 TI1/P33
Selector 8-Bit Timer Register (TM1) Clear Selector
8-Bit Timer Register (TM2) Clear
fX/22-fX/210 fX/2
Selector Selector Output Control Circuit Internal
TI2/P34
TO1/P31
µPD78011B, 78012B, 78013, 78014
Fig. Watch Timer Block Diagram
fX/28
Selector Prescaler
Selector
5-Bit Counter
Selector INTWT
Selector
INTTM3
Fig. Watchdog Timer Block Diagram
Prescaler
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
µPD78011B, 78012B, 78013, 78014
CLOCK OUTPUT CONTROL CIRCUIT clock with following frequencies output clock output. 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 (Main system clock: 10.0 operation) 32.768 (Subsystem clock: 32.768 operation)
Fig. Clock Output Control Block Diagram
fX/23 fX/24 fX/25 fX/26 fX/27 fX/28
Selector Synchronization Circuit Output Control Circuit PCL/P35
BUZZER OUTPUT CONTROL CIRCUIT clock with following frequencies output buzzer output. kHz/4.9 kHz/9.8 (Main system clock: 10.0 operation)
Fig. Buzzer Output Control Block Diagram
fX/210 fX/211 fX/212
Selector Output Control Circuit BUZ/P36
µPD78011B, 78012B, 78013, 78014
CONVERTER converter on-chip eight 8-bit resolution channels. There following method start conversion. Hardware starting Software starting
Fig. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive Approxmation Register (SAR) AVSS Selector Selector Sample Hold Circuit Voltage Comparator AVDD AVREF
INTP3/P03
Falling Edge Detector
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
µPD78011B, 78012B, 78013, 78014
SERIAL INTERFACES There on-chip clocked serial interfaces follows. Serial Interface channel Serial Interface channel Table Type Function Serial Interface
Function 3-wire serial mode 3-wire serial mode with automatic data transmit /receive function (Serial Interface) mode 2-wire serial modeq (MSB-first)
(MSB-first)
Serial Interface Channel
(MSB/LSB-first switchable)
Serial Interface Channel
(MSB/LSB-first switchable) (MSB/LSB-first switchable)
Fig. Serial Interface Channel Block Diagram
Internal
SI0/SB0/P25
Selector Serial Shift Register (SIO0) Output Latch
SO0/SB1/P26
Selector
Release/Command/ Acknowledge Detection Circuit Serial Counter
Busy/Acknowlede Output Circuit
SCK0/P27
Interrupt Request Signal Generator
INTCSI0
fx/22-fx/29
Serial Clock Control Circuit Selector
µPD78011B, 78012B, 78013, 78014
Fig. 5-10 Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer
SI1/P20
Serial Shift Register (SIO0)
SO1/P21
STB/P23
BUSY/P24
Handshake Control Circuit
SCK/P22
Serial Counter
Interrupt Request Signal Generator
INTCSI1
fX/22 fX/29
Serial Clock Control Circuit Selector
µPD78011B, 78012B, 78013, 78014
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS There interrupt functions different kind shown below. Non-maskable interrupt Maskable interrupt Software interrupt
Table Interrupt Source List
Interrupt Source Interrupt Type Default Priority*1 Name INTWDT Trigger Watchdog timer overflow (with nonmaskable interrupt selected) Watchdog timer overflow (with interval timer selected) INTP0 INTP1 INTP2 INTP3 INTCSI0 INTCSI1 INTTM3 Serial interface channel transfer Serial interface channel transfer Reference time interval signal from watch timer timer/event counter match signal generation 8-bit timer/event counter match signal generation 8-bit timer/event counter match signal generation converter conversion instruction execution Internal Internal input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H 0012H Internal /External Vector Table Address Basic*2 Configuratin Type Internal 0004H
Non-maskable
Maskable
INTWDT
INTTM0
0014H
INTTM1
0016H
INTTM2
0018H
Software
INTAD
001AH 003EH
default pririty priority applicable when more than maskable interrupt generated. highest priority lowest. Basic configuration types correspond next page.
µPD78011B, 78012B, 78013, 78014
Fig. Basic Interrupt Function Configuration (1/2)
Internal Non-Maskable Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal Maskable Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External Maskable Interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78011B, 78012B, 78013, 78014
Fig. Basic Interrupt Function Configuration (2/2) External Maskable Interrupt (Except INTP0)
Internal
External Interrupt Mode Register (INTM0)
Interrupt Request
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software Interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Remarks
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority spcification flag
µPD78011B, 78012B, 78013, 78014
TEST FUNCTIONS There test functions shown Table 6-2.
Table Test Source List
Test Source Internal/External Name INTWT INTPT4 Trigger Watch timer overflow Port falling edge detection Internal External
Fig. Test Function Basic Configuration
Internal
Test Input
Standby Release Signal
Remarks
Test input flag
Test mask flag
µPD78011B, 78012B, 78013, 78014
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion function used connect external devices areas other than internal ROM, SFR. Ports used connection with external devices.
STANDBY FUNCTIONS
There following standby functions reduce current dissipation. HALT mode operating clock stopped. average consumption current reduced intermittent operation combination with normal operat mode. STOP mode main system clock oscillation stopped. whole operation main system clock stopped, that system operates withultra-low power consumption using only subsystem clock.
Fig. Standby Functions
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock Operation* HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply stopped, oscillation)
HALT Mode* (Clock supply stopped, oscillation)
power consumption reduced stopping main system clock. When operating subsystem clock, stop main system clock. STOP instruction cannot used.
Caution
When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program program.
RESET FUNCTIONS
There following reset methods. External reset input RESET pin. Internal reset watchdog timer runaway time detection.
µPD78011B, 78012B, 78013, 78014
INSTRUCTION
8-Bit Instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Operand #byte Operand ADDC SUBC ADDC SUBC ADDC SUBC sadder ADDC SUBC !adder16 PUSH [DE] [HL] ROR4 ROL4 [HL+byte] [HL+B] [HL+C] MULU DIVUW DBNZ DBNZ ADDC SUBC ADDC SUBC ADDC SUBC saddr !addr16 [DE] [HL] [HL+byte] [HL+B] [HL+C] ADDC SUBC RORC ROLC $adder16 None
Except
µPD78011B, 78012B, 78013, 78014
16-Bit Instruction MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Operand Operand #byte ADDW SUBW CMPW MOVW MOVW* INCW, DECW PUSH, sfrp sadderp !adder16 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW MOVW None
Only when rp=BC,
Manipulation Instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Operand A.bit Operand A.bit MOV1 BTCLR sfr.bit MOV1 BTCLR saddr.bit MOV1 BTCLR PSW.bit MOV1 BTCLR [HL].bit MOV1 BTCLR MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 sfr.bit saddr.bit PWS.bit [HL].bit $addr16 None
µPD78011B, 78012B, 78013, 78014
Call Instruction/Branch Instruction CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Operand Operand Basic instruction CALL, CALLF CALLT BNC, Compound instruction BTCLR, DBNZ !addr16 !addr11 [addr5] $addr16
Other Instruction ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78011B, 78012B, 78013, 78014
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol AVDD AVREF AVSS Input voltage Output voltage Analog input voltage Output current high P17, P27, total P03, P47, P57, total Output current Effective value P47, total Peak value Effective value P03, P56, P57, IOL* total P03, total Effective value Peak value Effective value +150 Peak value Peak value Analog input P04, P17, P27, toP37 toP47, P57, P67, Open-drain Test Conditions Rating -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 AVSS -0.3 AVREF Unit
P17, P27, Peak value total Operating temperature Storage temperature Topt Tstg Effective value
Effective value should calculated follows: [Effective value] [Peak value] duty Product quality suffer absolute maximum rating exceeded even single parameter even momentarily. That absolute maximuam ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded.
Caution
µPD78011B, 78012B, 78013, 78014
Capacitance
Parameter Input capacitance capacitance Unmeasured pins returned Symbol Test Conditions Unmeasured pins returned P03, P17, P27, toP37, toP47, P57, MIN. TYP. MAX. Unit
Remarks
characteristics dual-function port same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics
Resonator Ceramic resonator
Recommended Circuit
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Oscillator frequency (fX)
Oscillator voltage range
Oscillation stabilization time
After reaches oscillator voltage range MIN.
Crystal resonator
Oscillator frequency (fX) 8.38
Oscillation stabilization time
External clock
input
frequency (fX)
10.0
input
µPD74HCU04
high/low level width (tXH tXL)
42.5
Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reset STOP mode release.
Caution
When using main system clock oscillator, wirinin area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor groundshould same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
µPD78011B, 78012B, 78013, 78014
Subsystem Clock Oscillation Circuit Characteristics
Resonator Recommended Circuit Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Crystal resonator
Oscillator frequency (fXT)
32.768
Oscillation stabilization time
External clock
input
frequency (fXT)
input high/low level width (tXTH tXTL)
Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reaches oscillator voltage MIN. Caution When using subsystem clock oscillator, wiring area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. subsystem clock oscillation circuit circuit with amplification level,more prone misoperation noise than main system clock. Particular care therefore required with wiring method when subsystem clock used.
µPD78011B, 78012B, 78013, 78014
Recommended Oscillation Circuit Constant Main system clock: Ceramic resonator
µPD78011B, 78012B
Manufacture Frequency (MHz) (pF) Murata Mfg. Co., Ltd. CSB1000J 1.00 1.01 1.25 1.26 1.79 (pF) Built-in Built-in Built-in Built-in MIN. MAX. Recommended Circuit Constant Oscillator Voltage Range
Product Name
1.80 2.44
Kyocera KBR-4.19MWS 4.19 KBR-4.19MKS KBR-4.19MSA 4.19 PBRC4.19A KBR-10.0M KBR-1000F 1.00 KBR-1000Y 10.0 Built-in
2.45 4.18
Built-in
4.19 6.00
Built-in
6.01 10.0
Built-in
µPD78013, 78014
Recommended Circuit Constant Manufacture Product Name CSB1000J Frequency (MHz) 1.00 1.01 1.25 1.26 1.79 (pF) (pF) Built-in Built-in Built-in Built-in Oscillator Voltage Range MIN. MAX.
Murata Mfg. Co., Ltd.
1.80 2.44
Built-in
2.45 4.18
Built-in
4.19 6.00
Built-in
6.01 10.0
Built-in
Remarks
indicate frequency.
µPD78011B, 78012B, 78013, 78014
Subsystem clock: Cristal resonator
µPD78011B, 78012B
Recommended Manufacture Frequency Products (MHz) (pF) (pF) MIN. MAX. Circuit Constant Oscillator Voltage Range
Daishinku
DT-38 (1TA632 E00, load capacitance 32.768
µPD78013, 78014
Recommended Frequency Manufacture Product Name (MHz) (pF) (pF) MIN. MAX. Circuit Constant Oscillator Voltage Range
Daishinku
DT-38 (1TA632 E00, load capacitance 32.768
µPD78011B, 78012B, 78013, 78014
Characteristics
Parameter Input voltage high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage Test Conditions P17, P21, P23, P32, P37, P47, P57, P03, P20, P22, P27, P33, P34, RESET XT1/P04, VDD-0.3 VIL1 VIL2 VIL3 VIL4 VIL5 Output voltage high Output voltage VOL1 VOH1 P17, P21, P23, P32, P47, P57, P03, P20, P22, P27, P33, P34, RESET XT1/P04, V,IOH -100 P57, P03, P17, P37, P47, open-drain pulled-up VDD-1.0 VDD-0.5 Open-drain MIN. VDD-0.5 VDD-0.5 TYP. MAX. Unit
VOL2
SB0, SB1, SCK0
VOL3 Input leakage current high
P03, P17, P27, P37, P47, P57, RESET
ILIH1
ILIH2 ILIH3 Input leakage current
XT1/P04, P03, P17, P27, P37, P47, P57, RESET
ILIL1 ILIL2 ILIL3
XT1/P04, Other than above
-200 -3*2
When memory expansion mode used memory expansion mode register (MM) with on-chip pullup resistor mask option. When pull-up resistors used (specified mask option), low-level input leakage current increases with -200 (MAX.) under either following conditions.
When external device expansion function used level input pin. During 3-clock period when read instruction executed port (P6) port mode registor (PM6). characteristics dual-function port same unless specified otherwise.
Remarks
µPD78011B, 78012B, 78013, 78014
Characteristics
Parameter Output leakage current high Output leakage current Mask option pullup resister Software pullup resister P03, P17, P27, P37, P47, P57, 8.38 Crystal oscillation operating mode 8.38 Crystal oscillation HALT mode 32.768 Crystal oscillation operating mode 32.768 Crystal oscillation HALT mode STOP mode When feedback resister used STOP mode When feedback resister unused ILOL Symbol ILOH1 VOUT Test Conditions MIN. TYP. MAX. Unit
VOUT
Power supply current
0.05
22.5 1650
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Operating high-speed mode (when processor clock control register 00H). Operating low-speed mode (when processor clock control register 04H). AVREF current port current excluded. Remarks characteristics dual-function port same unless specified otherwise.
µPD78011B, 78012B, 78013, 78014
Characteristics Basic Operation
Parameter Cycle time (Min. instruction execution time) Operationg subsystem clock input frequency input high/ low-level width Interrupt input high/low-level width tTIH tTIL tINTH tINTL INTP0 INTP1 INTP3 RESET level width tRSL 8/fsam* Symbol Test Conditions Operating main system clock VDD=4.5 MIN. 0.96 TYP. MAX. Unit
combination with bits (SCS0) (SCS1) sampling clock select register, selection fsam possible between fX/2N+1, fX/64 fx/128 (when
µPD78011B, 78012B, 78013, 78014
µPD78011B, 78012B, 78013, 78014
main system clock operation)
µPD78P014 (Reference)
main system clock operation)
Cycle Time (µs)
Operation Guaranteed Range
Cycle Time (µs)
Operation Guaranteed Range
Supply Voltage
Supply Voltage
Remarks
indicates Ta=-40 indicates Ta=-40
Caution
operation guaranteed range µPD78011B, 78012B, 78013 78014 differs from that
µPD78P014.
µPD78011B, 78012B, 78013, 78014
Read/Write Operation
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from delay time from write data tWDWR 0.5tCY-170 Address hold time from tWRADH delay time from WAIT delay time from WAIT tWTRD tWTWR 0.5tCY 0.5tCY tCY+100 2.5tCY+80 2.5tCY+80 =4.5 0.5tCY tCY+60 tRDWD 0.5tCY-120 0.5tCY tRDADH tCY+50 tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST (0.5+2n)tCY (2.5+2n)tCY 0.5tCY-30 1.5tCY tCY-10 tCY+40 (1.5+2n)tCY-20 (2.5+2n)tCY-20 0.5tCY 1.5tCY 0.5tCY (2+2n)tCY Load resistor Test Conditions MIN. 0.5tCY 0.5tCY-30 (2+2n)tCY-50 (3+2n)tCY-100 (1+2n)tCY-25 (2.5+2n)tCY-100 MAX. Unit
Remarks
TCY/4 indicates number waits. indicates load capacitance P40/AD0 P47/AD7, P50/A8 P57/A15, P64/ P65/WR, P66/WAIT,P67/ASTB pins).
µPD78011B, 78012B, 78013, 78014
Serial Interface 3-wire serial mode (SCK. Internal clock output)
Parameter cycle time
Symbol
Test Conditions
MIN. 3200
TYP.
MAX.
Unit
tKCY1
high/low-level width
tKH1 tKL1
tKCY1/2-50 tKCY1/2-150 1000
setup time SCK) hold time (from SCK) output delay time from
tSIK1 tKSI1 tKSO1
load capacitance output line.
3-wire serial mode (SCK. External clock input)
Parameter cycle time
Symbol
Test Conditions
MIN. 3200
TYP.
MAX.
Unit
tKCY2
high/low-level width
tKH2 tKL2
1600 1000
setup time SCK) hold time (from SCK) output delay time from
tSIK2 tKSI2
tKSO2
rise, fall time (When serial interface channel used)
When external device expansion function used When 16-bit timer output function When external device expansion function used When 16-bit timer output function used used
1000
rise, fall time (When serial interface channel used)
When external device expansion function used When external device expansion function used 1000
load capacitance output line.
µPD78011B, 78012B, 78013, 78014
mode (SCK. Internal clock output)
Parameter Symbol Test Conditions MIN. 3200 TYP. MAX. Unit
cycle time
tKCY3 tKH3 tKL3
high/low-level width
tKCY3/2-50 tKCY3/2-150
SB0, setup time SCK)
tSIK3
SB0, hold time (from SCK) SB0, output delay time from
tKSI3
tKCY3/2
tKCY3 tKCY3 tKCY3 tKCY3
1000
tKSO3
SB0, from from SB0, SB0, high-level width SB0, low-level width
tKSB tSBK tSBH tSBL
load resistors load capacitance output line.
µPD78011B, 78012B, 78013, 78014
mode (SCK. External clock output)
Parameter cycle time Symbol Test Conditions tKCY4 3200 high/low-level width tKH4 tKL4 SB0, setup time SCK) tSIK4 tKSI4 1600 MIN. TYP. MAX. Unit
SB0, hold time (from SCK) SB0, output delay time from
tKCY4/2
tKSO4 tKSB tSBK tSBH tSBL
tKCY4 tKCY4 tKCY4 tKCY4
1000
SB0, from from SB0, SB0, high-level width SB0, low-level width
rise, fall time
When external device expansion function used When external device expansion function used When 16-bit timer output function used When 16-bit timer output function used
1000
load resistors load capacitance output line. 2-wire serial mode (SCK. Internal clock output)
Parameter cycle time Symbol tKCY5 Test Conditions MIN. 1600 3800 high-level width low-level width SB0, setup time SCK) SB0, hold time (from SCK) SB0, output delay time from tKSO5 1000 tKH5 tKL5 tKCY5/2-50 tKCY5/2-50 TYP. MAX. Unit
tSIK5
tKSI5
load resistors load capacitance SCK0, output line.
µPD78011B, 78012B, 78013, 78014
2-wire serial mode (SCK. External clock input)
Parameter Symbol Test Conditions MIN. 1600 3800 TYP. MAX. Unit
cycle time tKCY6
high-level width low-level width SB0, setup time SCK) SB0, hold time (from SCK) SB0, output delay time from
tKH6 tKL6 tSIK6
tKSI6
tKCY6/2
tKSO6
1000
rise, fall time
When external device expansion function used When external device expansion function used When 16-bit timer output function used When 16-bit timer output function used
1000
load resistors load capacitance SCK0, output line.
µPD78011B, 78012B, 78013, 78014
3-wire serial mode with automatic transmit/receive function (SCK.Internal clock output)
Parameter cycle time
Symbol
Test Conditions
MIN. 3200
TYP.
MAX.
UNIT
tKCY7
high/low-level width
tKH7 tKL7
tKCY7/2-50 tKCY7/2-150
setup time SCK) tSIK7
hold time (from SCK) tKSI7
output delay time from tKSO7
1000
from Strobe signal high-level width
tSBD
tKCY7
tSBW
tKCY7-30
tKCY7+30
Busy signal setup time busy signal detection timing)
tBYS
Busy signal hold time (from busy signal detection timing) from busy inactive
tBYH
tSPS
2tKCY7
load capacitance output line.
µPD78011B, 78012B, 78013, 78014
3-wire serial mode with automatic transmit/receive function (SCK.External clock input)
Parameter cycle time
Symbol
Test Conditions
MIN. 3200
TYP.
MAX.
UNIT
tKCY8
high/low-level width
tKH8 tKL8
1600
setup time SCK) tSIK8
hold time (from SCK) tKSI8
output delay time from tKSO8
1000
rise, fall time
When external device expansion function function used When external device expansion function used
1000
load capacitance output line.
µPD78011B, 78012B, 78013, 78014
converter characteristics AVDD AVSS
Parameter Resolution Overall error* Conversion time Sampling time Analog input voltage Reference voltage AVREF current tCONV tSAMP VIAN AVREF AIREF 19.1 24/fx AVSS AVREF AVDD Symbol Test Conditions MIN. TYP. MAX. Unit
Overroll error excluding quantization error (±1/2 LSB). indicated ratio full-scale value.
µPD78011B, 78012B, 78013, 78014
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
0.4V
Input
1/fXT
tXTL
tXTH 0.4V
Input
Timing
1/fTI
tTIL TI0-TI2
tTIH
µPD78011B, 78012B, 78013, 78014
Read/Write Operation External fetch wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External fetch (Wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
µPD78011B, 78012B, 78013, 78014
External data access wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD tRDL2
tRDWD
tWDS tWDWR
tWDH tWRADH
tASTWR tWRL1
External data access (Wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD tRDL2 tRDWD tASTWR tWRL1 tWRADH tWDS tWDWR tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
µPD78011B, 78012B, 78013, 78014
Serial Transfer Timing 3-wire serial ode:
tKCY
tKL1,2
tKH1,2
tSIK1,2 tKSI1,2
tKSO1,2
Input Data
Output Data
mode (Bus release signal transfer):
tKCY3,4 tKL3,4 tKH3,4
tKSB tSBL tSBH tSBK tSIK3,4 tKSI3,4
SB0, tKSO3,4
Mode (command signal transfer):
tKCY3,4 tKL3,4 tKH3,4
tKSB tSBK tSIK3,4 tKSI3,4
SB0, tKSO3,4
µPD78011B, 78012B, 78013, 78014
2-wire serial mode:
tKCY5,6 tKL5,6 tSIK5,6 tKSO5,6 SB0, tKSI5,6 tKH5,6
3-wire serial mode with automatic transmit/receive function:
tSIK7,8 tKSO7,8
tKSI7,8 tKH7,8
tSBD tKL7,8 tKCY7,8 tSBW
3-wire serial mode with automatic transmit/receive function (busy processing):
tBYS
tBYH
10+n* tSPS
BUSY (Active High)
signal actually driven here; shown such indicate timing.
µPD78011B, 78012B, 78013, 78014
Data Memory Stop Mode Supply Voltage Data Retention Characteristics
Parameter Data retention supply voltage Data retention supply current IDDDR VDDDR Subsystem clock stop feed-back resister disconnected Release signal time Oscillation stabilization wait time Release interrupt tSREL tWAIT Release RESET 218/fx Symbol VDDDR Test Conditions MIN. TYP. MAX. Unit
combination with (OSTS0 OSTS2) oscillation stabilization time select register, selection 213/fx 215/fx 218/fx possible.
Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retension Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal STOP Mode Release Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retension Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78011B, 78012B, 78013, 78014
Interrupt Input Timing
tINTL INTP0-INTP2 tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
µ78011B, 78012B, 78013, 78014
CHARACTERISTIC CURVE (REFERENCE VALUES)
(Main System Clock: 8.38 MHz)
10.0
(Ta=25
PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT Oscillation, Oscillation)
Supply Current [mA]
PCC=B0H 0.05
HALT Stop, Oscillation) STOP Stop, Oscillation)
0.01
0.005
=4.19MHz XT=32.768kHz
0.001
Supply Voltage
µ78011B, 78012B, 78013, 78014
(Main System Clock: 4.19 MHz)
10.0
(Ta=25
PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT Oscillation, Oscillation)
Supply Current [mA]
PCC=B0H 0.05
HALT Stop, Oscillation) STOP Stop, Oscillation)
0.01
0.005
=4.19MHz XT=32.768kHz
0.001
Supply Voltage
µ78011B, 78012B, 78013, 78014
(VDD
Supply Current [mA]
HALT Oscillation)
Clock Oscillator Frequency [MHz]
(VDD
Supply Current [mA] HALT Oscillation)
Clock Oscillator Frequency [MHz]
µ78011B, 78012B, 78013, 78014
(Port P67)
(Ta=25 VDD=5 VDD=6 VDD=4 VDD=3
Output Current [mA]
Output Voltage
(Port
(Ta=25
Output Current [mA]
VDD=6 VDD=5 VDD=4
VDD=3
Output Voltage
µ78011B, 78012B, 78013, 78014
(P60 P63)
(Ta=25
VDD=6
VDD=5
VDD=4
Output Current [mA]
VDD=3
Output Voltage
(Port P67)
(Ta=25
Output Current High [mA]
VDD=5 VDD=4 VDD=6 VDD=3
Output Voltage High
µPD78011B, 78012B, 78013, 78014
PACKAGE INFORMATION
DRAWINGS MASS-PRODUCTION PRODUCT PACKAGES (1/2)
PLASTIC SHRINK (750 mil)
NOTE Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15°
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15° P64C-70-750A,C-1
Caution
Dimensions materials products different from those mass-production products. Refer DRAWINGS PRODUCT PACKAGES (1/2).
µPD78011B, 78012B, 78013, 78014
DRAWINGS MASS-PRODUCTION PRODUCT PACKAGES (2/2)
PLASTIC
detail lead
P64GC-80-AB8-3 ITEM MILLIMETERS 17.6 14.0 14.0 17.6 0.35 0.10 0.15 (T.P.) 0.15+0.10 -0.05 0.10 2.55 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Caution
Dimensions materials products different from those mass-production products. Refer DRAWINGS PRODUCT PACKAGES (2/2).
5°±5°
µPD78011B, 78012B, 78013, 78014
DRAWINGS PRODUCT PACKAGES (1/2)
64PIN CERAMIC SHRINK (SEAM WELD) (750 mil)
0~15°
P64D-70-750A1 NOTES Each lead centerline located within 0.25 (0.01 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel. ITEM MILLIMETERS 58.16 MAX. 1.521 MAX. 1.778 (T.P.) 0.46 0.05 MIN. 1.02 MIN. 3.14 5.08 MAX. 19.05 (T.P.) 18.8 0.25 0.05 0.25 INCHES 2.290 MAX. 0.060 MAX. 0.070 (T.P.) 0.018 0.002 0.031 MIN. 0.138 0.012 0.040 MIN. 0.124 0.200 MAX. 0.750 (T.P.) 0.740 0.010 -0.003 0.01
+0.002
µPD78011B, 78012B, 78013, 78014
DRAWINGS PRODUCT PACKAGES (2/2)
CERAMIC (FOR
(Bottom View)
X64B-80A-1 INCHES 0.866 0.016 0.551 0.551 0.866 0.016 0.039 0.039 0.013 0.031 (T.P.) 0.157+0.007 -0.006 0.01 0.119 MAX. 0.022 0.039 0.047
ITEM
MILLIMETERS 22.0 14.0 14.0 22.0 0.32 (T.P.) 0.15 0.25 MAX. 0.55
µPD78011B, 78012B, 78013, 78014
RECOMMENDED SOLDERING CONDITIONS
µPD78011B/78012B/78013/78014 should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (IE-1207). soldering methods conditions other than those recommended below, contact salespersonnel. Table 14-1 Surface Mounting Type Soldering Conditions 64-Pin Plastic 64-Pin Plastic
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Twice max. Points note Start second reflow after device temprature first reflow returns normal. Flux washing water after first reflow should avoided. Package peak temperature: 215°C, Duration: sec. max. 200°C above) Number times: Twice max. Points note Start second reflow after device temprature first reflow returns normal. Flux washing water after first reflow should avoided. temperature: 300°C max., Duration: sec. max. (per device side) Recommended Condition Symbol IR35-00-2
VP15-00-2
part heating
64-Pin Plastic
64-Pin Plastic
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Twice Points note Start second reflow after device temprature first reflow returns normal. Flux washing water after first reflow should avoided. Package peak temperature: 215°C, Duration: sec. max. 200°C above), Number times: Twice Points note Start second reflow after device temprature first reflow returns normal. Flux washing water after first reflow should avoided. Solder bath temperature: 260°C max. Duration: sec. max. Number times: Once Preliminary heat temperature: 120°C max. (Package surface temperature) temperature: 300°C max., Duration: sec. max. (per device side) Recommended Condition Symbol IR35-00-2
VP15-00-2
Wave soldering
WS60-00-1
part heating
Caution
more than soldering method should avoided (except case part heating).
µPD78011B, 78012B, 78013, 78014
Table 14-2 Insertion Type Soldering Conditions
Soldering Method Wave soldering (pin only) part heating
64-Pin Plastic Shrink (750 mil) 64-Pin Plastic Shrink (750 mil) 64-Pin Plastic Shrink (750 mil) 64-Pin Plastic Shrink (750 mil)
Soldering Conditions Solder bath temperature: 260°C max., Duration: sec. max. temperature: 300°C max., Duration: sec. max. (per pin)
Caution
Wave soldering only lead part order that solder contact with chip directly.
µPD78011B, 78012B, 78013, 78014
APPENDIX DEVEROPMENT TOOLS
following development tools available system development using µPD78011B, 78012B, 78013, 78014. Language Processing Software
RA78K/0*1, CC78K/0*1, DF78014*1, CC78K/0-L*1, 78K/0 series common assembler package 78K/0 series common compiler package
µPD78014 subseries device file
78K/0 series common compiler library source file
PROM Writting Tools
PG-1500 PA-78P014CW PA-78P014GC PG-1500 controller*1, PROM programmer Programmer adapter connected PG-1500
PG-1500 control program
Debugging Tool
IE-78000-R IE-78000-R-BK IE-78014-R-EM EP-78240CW-R EP-78240GC-R EV-9200GC-64 SD78K/0*1, SM78K/0*4, DF78014*1, Socket mounted user system board created 64-pin plastic IE-78000-R screen debugger 78K/0 series common system simulator 78K/0 series common in-circuit emulator 78K/0 series common break board
µPD78002/78014 subseries evaluation emulation board
Emulation probe common µPD78244 subseries
µPD78014 subseries device file
Real-Time
RX78K/0*1, MX78K/0*1, 78K/0 series common real-time 78K/0 series common
Fuzzy Inference Devleopment Support System
FE9000*1/FE9200*5 FT9080*1/FT9085*2 FI78K0*1, FD78K0*1, Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
PC-9800 series (MS-DOSTM) based PC/AT(PC DOSTM) based HP9000 series 300TM, HP9000 series 700(HP-UXTM) based, SPARCstationTM, (SunOSTM) based, EWS-4800 series (EWS-UX/V) based
µPD78011B, 78012B, 78013, 78014
PC-9800 series (MS-DOS WindowsTM) based PC/AT Windows) based Under development Remarks development tools manufactured third party, "78K/0 Series Selection Guide" (IF1185). RA78K/0, CC78K/0, SD78K/0, SM78K/0 used combination with DF78014.
µPD78011B, 78012B, 78013, 78014
APPENDIX RELATED DOCUMENTS Device Related Documents
Document Name User's Manual 78K/0 Series User's Manual Instruction Application Note Basic Basic Floating-Point Arithmetic Program Electronic Notebook Document (Japanese) IEU-780 IEU-849 IEA-715 IEA-740 IEA-718 IEA-744 Document (English) IEU-1314 IEU-1372 IEA-1288 IEA-1299 IEA-1289 IEA-1301
Development Tools Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller IE-78000-R IE-78000-R-BK IE-78014-R-EM SD78K/0 Screen Debugger Basic Reference Document (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-651 EEU-704 EEU-810 EEU-867 EEU-805 EEU-852 EEU-816 Document (English) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEU-1335 EEU-1291 EEU-1398 EEU-1427 EEU-1400 EEU-1414 EEU-1413
Caution
contents above related documents subject change without notice. documents should used design, etc.
latest
µPD78011B, 78012B, 78013, 78014
Embedded Software Documents (User's Manual)
Document Name Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator Document (Japanese) EEU-829 EEU-862 Document (English) EEU-1438 EEU-1444
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grade Semiconductor Devices Semiconductor Devices Quality Guarantee Guide Document (Japanese) IEI-635 IEI-616 IEI-620 MEI-603 Document (English) IEI-1213 IEI-1207 IEI-1209 MEI-1202
Caution
contents above related documents subject change without notice. documents should used design, etc.
latest
µPD78011B, 78012B, 78013, 78014
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after poweron devices having reset function.
µPD78011B, 78012B, 78013, 78014
[MEMO]
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. devices listed this document suitable aerospace equipment, submarine cables, nuclear reactor control systems life support systems. customers intend devices above applications they intend "Standard" quality grade devices applications intended NEC, please contact sales people advance. Application examples recommended Corporation Standard: Computer, Office equipment, Communication equipment, Test Measurement equipment, Machine tools, Industrial robots, Audio Visual equipment, Other consumer products, etc. Special: Automotive Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
92.6
registered trademark Corporation. IEBus trademark Corporation. MS-DOS Windows trademarks Microsoft Corporation. PC/AT trademarks Corporation. HP9000 Series 300, HP9000 series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation tradmark SPARC International, Inc. SunOS tradmark Microsystems, Inc.

µPD78011B, 78012B, 78013, 78014 8-BIT SINGLE-CHIP MICROCOMPUTER

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