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Digital Encoders Revision October 2002 Copyright Notice:


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VT1622 VT1622M
Digital Encoders
Revision October 2002
Copyright Notice:
Copyright 2002, Technologies Incorporated. Printed United States. RIGHTS RESERVED. part this document reproduced, transmitted, transcribed, stored retrieval system, translated into language, form means, electronic, mechanical, magnetic, optical, chemical, manual otherwise without prior written permission Technologies Incorporated. VT1622 VT1622M only used identify product Technologies, Inc. registered trademark Technologies, Incorporated.
Disclaimer Notice:
license granted, implied otherwise, under patent patent rights Technologies. Technologies makes warranties, implied otherwise, regard this document products described this document. information provided this document believed accurate reliable publication date this document. However, Technologies assumes responsibility errors this document. Furthermore, Technologies assumes responsibility misuse information this document patent infringements that arise from this document. information product specifications within this document subject change time, without notice without obligation notify person such change.
Offices:
Office: Mission Court Fremont, 94539 Tel: (510) 683-3300 Fax: (510) 683-3301 (510) 687-4654 Web: http://www.viatech.com Taipei Office: Floor, Chung-Cheng Road, Hsin-Tien Taipei, Taiwan Tel: (886-2) 2218-5452 Fax: (886-2) 2218-5453 Web: http://www.via.com.tw
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REVISION HISTORY
Document Release Date 9/16/02 10/4/02 Revision Initial Public Release Updated company logo cover page Fixed RESET resistor value description Initials
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TABLE CONTENTS
REVISION HISTORY.I TABLE CONTENTS. LIST FIGURES LIST TABLES PRODUCT FEATURES. OVERVIEW PINOUTS. DIAGRAM LIST DESCRIPTIONS REGISTERS. REGISTER OVERVIEW REGISTER DESCRIPTIONS FUNCTIONAL DESCRIPTION ARCHITECTURE DESCRIPTION. Data Capture. Color Space Converter. Scaler Deflicker Encoder. Serial Interface. CRTC. MASTER/SLAVE CLOCK MODE. Master Mode Slave Mode Digital Video Interface Video Standards. LUMINANCE CHROMINANCE FILTER OPTION COLOR TEST PATTERN GENERATOR Subcarrier Generation Burst Generation Power Down Mode Macrovision Anti-Copy Protection DISPLAY MODES Clock Frequency DESIGN GUIDELINES. BOARD LAYOUT CONSIDERATIONS Component Placement. Power Supply Decoupling General Controls Inputs Revision October 2002 -iiTable Contents
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Pixel Data Inputs Board Layout Example ELECTRICAL SPECIFICATIONS. ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS POWER SUPPLY CURRENT TOTAL POWER CONSUMPTION SPECIFICATIONS SPECIFICATIONS CHARACTERISTICS CHARACTERISTICS DISPLAY SIGNAL CHARACTERISTICS CHARACTERISTICS. PACKAGE MECHANICAL SPECIFICATIONS
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LIST FIGURES
FIGURE FUNCTIONAL BLOCK DIAGRAM FIGURE DIAGRAM (TOP VIEW). FIGURE ARCHITECTURAL DESCRIPTION BLOCK DIAGRAM FIGURE MASTER CLOCK MODE FIGURE MASTER CLOCK MODE FIGURE SLAVE CLOCK MODE FIGURE MULTIPLEXED INPUT INTERFACE PROTOCOL FIGURE NON-MULTIPLEXED INPUT INTERFACE PROTOCOL FIGURE INTERLACED 525-LINE (NTSC) VIDEO TIMING FIGURE INTERLACED 525-LINE (PAL-M) VIDEO TIMING. FIGURE INTERLACED 625-LINE (PAL-B, VIDEO TIMING (FIELDS 1-4) FIGURE INTERLACED 625-LINE (PAL-B, VIDEO TIMING (FIELDS 5-8) FIGURE INTERLACED 625-LINE (PAL-N) VIDEO TIMING (FIELDS 1-4) FIGURE INTERLACED 625-LINE (PAL-N) VIDEO TIMING (FIELDS 5-8) FIGURE NON-INTERLACED 262-LINE (NTSC) VIDEO TIMING FIGURE NON-INTERLACED 262-LINE (PAL-M) VIDEO TIMING. FIGURE NON-INTERLACED 312-LINE (PAL-B, VIDEO TIMING. FIGURE 525-LINE (NTSC/PAL-M) (LUMA) VIDEO TEST PATTERN WAVEFORM. FIGURE 625-LINE (PAL-B, (LUMA) TEST PATTERN WAVEFORM FIGURE 525-LINE (NTSC/PAL-M) (CHROMA) VIDEO TEST PATTERN WAVEFORM FIGURE 625-LINE (PAL-B, (CHROMA) VIDEO TEST PATTERN WAVEFORM FIGURE COMPOSITE 525-LINE (NTSC/PAL-M) VIDEO TEST PATTERN WAVEFORM FIGURE COMPOSITE 625-LINE (PAL-B, VIDEO TEST PATTERN WAVEFORM FIGURE 525-LINE PROGRESSIVE VIDEO TIMING FIGURE 625-LINE PROGRESSIVE VIDEO TIMING FIGURE LOW-PASS LUMA FILTER NTSC FIGURE LOW-PASS LUMA FILTER PAL. FIGURE NOTCH LUMA FILTER NTSC FIGURE WIDE BANDWIDTH LUMA FILTER FIGURE LOWPASS CHROMA FILTER FIGURE WIDE BANDWIDTH CHROMA FILTER. FIGURE INTERCONNECT WITH PM133 CHIPSET VT8605 NORTH BRIDGE FIGURE DECOUPLING CAPACITORS ARRANGEMENT FIGURE OUTPUT CONFIGURATION. FIGURE CRYSTAL CONFIGURATION. FIGURE LAYOUT EXAMPLE FIGURE MECHANICAL SPECIFICATION 64-PIN TQFP THIN QUAD FLAT PACK.
LIST TABLES
TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE LIST (ALPHABETICAL ORDER). DESCRIPTIONS. REGISTER SUMMARY INPUT DATA FORMAT. LUMINANCE FILTER CHROMINANCE FILTER DISPLAY MODES MASTER CLOCK MODE CLOCK SETTINGS
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VT1622 VT1622M
Digital Encoders
PRODUCT FEATURES
Input Format
Supports digital (15/16 24-bit) YCrCb (CCIR601 CCIR656) 4:2:2 input video data both interlaced non- interlaced formats
Output Format
S-Video, Composite, YCbCr SCART (RGB) with interlaced non-interlaced scan output YPbPr progressive scan output NTSC output SDTV output mode (525p 625p) compliant with EIA770-1 EIA770-2
High Quality 4x10-Bit Video
Simultaneous S-Video S-Video with composite outputs Simultaneous YCbCr component output with composite output progressive scan channel with YPbPr component output
Macrovision (VT1622M Only)
Macrovision anti-copy protection Macrovision copy protection with 525p progressive scan output
Other Features
Serial programming interface Graphics resolution 1024x768 Second edition ProScale engine support underscan overscan size Programmable power management Master slave video timing operation P:P2 clocking mode full screen Adaptive deflicker filter enhance image quality Automatic detection presence 64-pin TQFP package
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Product Features
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OVERVIEW
VT1622 VT1622M digital television encoders that accept various pixel data formats YCrCb (compatible with CCIR656 CCIR601) pixel data format from controller MPEG decoder. These encoder chips support input resolution from 320x200 1024x768 will will perform non-interlace interlace conversion generate high quality flicker-free composite video, S-video, component interlaced progressive scan output signals. Both VT1622 VT1622M newest ProScale® engine that provides most advanced vertical horizontal scaling technology. Using programmable CRTC scaling factor, these encoder chips zoom image size. These encoder chips uses adaptive deflicker filter that checks graphics pixel-by-pixel basis maintain flicker-free display. VT1622 VT1622M support various worldwide video standards, including NTSC-M (North America, Taiwan) NTSCJ (Japan), PAL-B, (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay) PAL-Nc (Argentina). Because there DACs, these encoder chips simultaneously output composite video, S-video, component YCbCr, signals output analog progressive scan signal YPbPr format. VT1622M output video with Macrovision anticopy video signal Macrovision copy protection with 525p progressive scan output. Macrovision anticopy process provides means deter unauthorized copying copy protected analog video signals onto videocassette. features software programmable through serial interface that provides read/write access registers.
Serial Interface Data Capture Color Space Converter FIFOs Scaler Deflicker
PD[15:0]
NTSC Encoder
CVBS CVBS
Horizontal Vertical Timing CRTC
Pixel Clock
HSYNC
VSYNC
XCLK
PCLK
Figure Functional Block Diagram
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Overview
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PINOUTS
Diagram
VCC25 (2.5V) PD13 PD12 PD11 PD10 VCC33 (3.3V)
PD14 PD15 ADDR TESTMODE CONF_XLT (3.3V) VCC33 (2.5V) VCC25 GNDPLL (2.5V) VCCPLL
VT1622/VT1622M Encoder
TQFP-64
VCC25 (2.5V) PCLK VCC33 (3.3V) XCLK HSYNC VSYNC RESET# VCC25 (2.5V)
Figure Diagram (Top View)
Revision October 2002
(2.5V) VCCOSC GNDOSC (2.5V) VCCBGAP COMP RSET GNDBGAP (2.5V) VCCDAC DACA GNDDAC DACB (2.5V) VCCDAC DACC GNDDAC DACD
Pinouts
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List
Table List (Alphabetical Order)
Name ADDR COMP CONF_XLT DACA DACB DACC DACD GNDBGAP GNDDAC GNDDAC GNDOSC GNDPLL HSYNC PCLK Name PD10 PD11 PD12 PD13 PD14 PD15 RESET# RSET TESTMODE VCC25 VCC25 VCC25 VCC25 VCC33 VCC33 VCC33 VCCBGAP VCCDAC VCCDAC VCCOSC VCCPLL VSYNC XCLK
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Descriptions
Table Descriptions
Pixel Data
Signal Name PD[15:0] Type Description Pixel Data These inputs accept multiplexed nonmultiplexed YcbCr format.
XCLK PCLK HSYNC VSYNC
Display Enable. rising edge this signal identifies first active pixel data each active line. Input Clock. Reference clock Pixel Data inputs. operate pixel clock. Pixel Clock Output. This provide operate pixel clock VGA. Horizontal Sync. When Rx1[2]=0, this accept horizontal sync input. When Rx1[2]=1, device will output horizontal sync pulse through this pin. Vertical Sync. When Rx1[3]=0, this accept vertical sync input. When Rx1[3]=1, device will output vertical sync pulse through this pin.
Output
Signal Name DACA DACB DACC DACD Type Description Vertical Sync. Composite Sync Horizontal Sync. Analog Output. Analog Output. Analog Output. Analog Output.
Serial Interface
Signal Name ADDR Type Description Serial Data. Serial Clock. Serial Address Select. 40h, High 42h.
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Descriptions
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Clock, Reset Test
Signal Name TESTMODE CONF_XLT Type Description Test Mode Enable. Pull down regular operation. Internal External Oscillator Select. Selects internal external oscillator. When pulled low, crystal must attached pins pulled high, stable 14.31818MHz external clock source must supplied Reset. When this low, device held power-on reset condition. Clock Out. Output providing 14.31818 clock other devices. Crystal 14.31818 crystal attached between oscillator also connected this pin. Crystal Out. 14.31818 crystal attached between external oscillator attached with this should connected ground. External Resistor. Used full scale range DACs. Typical value 4.64 (1%), attached between this ground. Compensation. Reserved Future Use. connect.
RESET# RSET COMP
Power Ground
Signal Name VCC33 VCC25 VCCPLL GNDPLL VCCDAC GNDDAC VCCBGAP GNDBGAP VCCOSC GNDOSC Type Description Power. 3.3V Core Power. 2.5V Digital Ground. Connect primary ground plane. Power. 2.5V Ground. Connect analog ground plane connect main digital ground plane through ferrite bead provide isolation from digital switching noise. Power. 2.5V Ground. Band Power. 2.5V Band Ground. Oscillator Power. 2.5V Oscillator Ground.
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REGISTERS
Register Overview
following tables summarize on-chip registers. These tables also document power-on default value ("Default") access type ("Acc") each register. Access type definitions used (Read/Write), (Read/Only), reserved (essentially same RO), just (Read Write Clear individual bits). Registers indicated have some read/only bits that always read back fixed value (usually unused); registers designated have some read-only read write bits (see individual register descriptions details). Detailed register descriptions provided following section this document. offset default values shown hexadecimal unless otherwise indicated.
Table Register Summary
Offset 25-49 Encoder Registers Input Frame Format Input Sync Format Output Select Luma Filter Output Mode Control Control Start Active Video Start Horizontal Position Start Vertical Position Amplitude Factor Black Level Luma Amplitude Factor Amplitude Factor Power Management Status Special Effect Special Effect Value Value Value Overflow Sub-carrier Value Sub-carrier Value Sub-carrier Value Sub-carrier Value Reserved Program) Version Overflow Test Test reserved Sync Step Burst Envelope Step Sub-carrier Phase Adjustment Blank Level Signal Overflow reserved Default Offset 6C-FF Encoder Registers Default Input Aperture Threshold Input Aperture Delta Coring Function Delay Control Delay Control Burst Maximum Amplitude Graphic Horizontal Total Pixels Graphic Horizontal Active Pixels Graphic Horizontal Overflow Graphic Vertical Total Lines Graphic Vertical Overflow Horizontal Total Pixels Horizontal Active Pixels Horizontal Sync Width Horizontal Overflow Burst Start Burst Video Start Video Video Overflow Vertical Scale Factor Horizontal Scale Factor Scaling Overflow Deflicker Threshold Deflicker Detection Length Scaling Horizontal Total Threshold Scaling Horizontal Total Pixel Overflow PY_G Amplitude Factor PB_B Amplitude Factor PR_R Amplitude Factor Auto Sub-carrier Value Auto Sub-carrier Value Auto Sub-carrier Value Auto Sub-carrier Value reserved
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Register Descriptions
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Register Descriptions
Offset Input Frame Format.RW Input Blurring .INBLUR_E Disable .default Enable Interlace Input Mode.ITL_IN Disable .default Enable Input Data Shift .YSH16 Disable .default Enable Input Data Shift .CSH128 Disable .default Enable Input Data Format.IDF 0000 16-bit non-multiplexed (16-bit color) input .default 0001 16-bit non-multiplexed YCrCb input 0010 16-bit multiplexed (24-bit color) input 0011 15-bit non-multiplexed (15-bit color) input 0100 12-bit multiplexed (24-bit color) input ("C" multiplex scheme) 0101 12-bit multiplexed (24-bit color) input ("I" multiplex scheme) 0110 8-bit multiplexed (24-bit color) input 0111 8-bit multiplexed (16-bit color) input 1000 8-bit multiplexed (15-bit color) input 1001 8-bit multiplexed YCrCb input multiplexed) 101x -reserved11xx -reservedOffset Input Sync Format Reserved always reads Field Signal Polarity. Active default Active High Input .DSEN Disable. default Enable identifies first active pixel data each active line Detect Embedded Sync .DES detect default Sync will detected from embedded codes pixel input stream Vertical Sync Direction. VSYO Input default Output Horizontal Sync Direction HSYO Input default Output Vertical Sync Polarity .VSP Active default Active High Horizontal Sync Polarity .HSP Active default Active High
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Offset Output Mode Polarity.VSOP Active default Active High Filter Bypass FIL_PASS Disable. default Enable PAL_Nc Mode .PAL_NC Disable. default Enable (bits must 00b) PAL_N Mode PAL_N Disable. default Enable (bits must 00b) Output Mode OUT_MODE Normal. default Non-Interlaced Progressive -reserved1 Output Line Selection LINE_SEL default Output Standard. default NTSC
Offset Output Select.RW Select CSO_EN Output .default Input Polarity .CSO_HSOP Active Low.default Active High Output Function CSO_HSO Output HSO.default Output Sync .SYNC_R_PR Disable .default Enable Sync .SYNC_G Disable .default Enable Sync SYNC_B_PB Disable .default Enable Select .DACSEL A/B/C/D CVBS CVBS default A/B/C/D A/B/C/D CVBS A/B/C/D CVBS Offset Luma Filter Control Luma Filter Adjust Lowpass (NTSC) Clock.default Lowpass (NTSC) Clock Lowpass (NTSC) Clock Notch (NTSC) Clock Lowpass (PAL) Clock Lowpass (PAL) Clock Lowpass (PAL) Clock Lowpass (All) Clock (see "Luminance Filter" Table page 34). Chroma Filter Adjust Lowpass Clk, B/W=0.6MHz .default Lowpass Clk, B/W=0.6MHz Lowpass Clk, B/W=0.6MHz -reserved100 -reserved101 -reserved110 -reserved111 Lowpass 26MHz Clk, B/W=4.43MHz (see "Chrominance Filter" Table page 34). Luma Channel Deflicker Adjust. Deflicker Filter .default 1:1:1 Deflicker Filter 1:2:1 Deflicker Filter -reserved-
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Offset Start Active Video Start Active Video Bits SAV[7:0] (see Rx1C[3] bit-8). default Sets delay from leading edge horizontal sync start active video. Offset -Start Horizontal Position. Start Horizontal Position Bits .HP[7:0] (see Rx1C[2] bit-8). default Used shift displayed image horizontal direction. Offset Start Vertical Position Start Vertical Position Bits 7-0. VP[7:0] (see Rx1C[1] bit-8). default Used shift displayed image vertical direction. Offset Amplitude Factor. Amplitude Factor. default Offset Black Level. Black Level default Offset Luma Amplitude Factor Luma Amplitude Factor default Offset Amplitude Factor Amplitude Factor default
Offset Control 1.RW Reserved always reads Master Slave Clock Mode Select .M_S Master Clock Mode.default Slave Clock Mode Reserved always reads FSCI Auto Adjust FCSI_ADJ_EN Disable (use FSCI value Rx19-16).default Enable (use 14.31818 calculate FSCI [31:0] which read Rx6B-68) FSCI Auto Fine Tune FSCI_FINE_TUNE Disable .default Enable PCLK Clock Polarity. PCLKP Normal .default Inverted PCLK Output Mode .PCM .default -reservedOffset Control 2.RW Color .CB_ENABLE Disable .default Enable XCLK Input Clock Mode. .default -reserved4 Edge Used Latch Input Data .MCP Normal clock input.default Inverted clock input Input Clock Adjust .DPA 0000 Shortest input clock delay .default 1111 Longest input clock delay Each increment this field gate delay
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Offset Status Macrovision Copy Protection. MACRV (RO) Disabled. default Enabled Reserved always reads Status. (RO) Disabled. default Enabled Status. (RO) Disabled. default Enabled Status. (RO) Disabled. default Enabled Status. (RO) Disabled. default Enabled
Offset Power Management Monitor Connection Status SENSE_ENB this from then back status monitor connections default Auto Sense .AUTOSENSE Disable .default Enable monitor connection status will automatically sensed once frame during vertical blanking interval Reserved always reads Power Down .PWRPLL_ENB Disable (PLL On).default Enable (PLL Off) Power Down PWRA_ENB Disable (DAC On).default Enable (DAC Off) Power Down .PWRB_ENB Disable (DAC On).default Enable (DAC Off) Power Down PWRC_ENB Disable (DAC .default Enable (DAC Off) Power Down. PWRD_ENB Disable (DAC On).default Enable (DAC Off)
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Register Descriptions
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Offset Sub-Carrier Value Sub-Carrier Value Bits 7:0. default Offset Sub-Carrier Value Sub-Carrier Value Bits 15:8 default Offset Sub-Carrier Value Sub-Carrier Value Bits 23:16 default Offset Sub-Carrier Value Sub-Carrier Value Bits 31:24 default Offset Version (03h) Version always reads Offset Overflow. Reserved always reads Start Active Video Bit-8.SAV[8] (see bits 0-7). default=0 Start Horizontal Position Bit-8 HP[8] (see bits 0-7). default=0 Start Vertical Position Bit-8 VP[8] (see bits 0-7). default=0 Frequency Conversion Parameter Bit-8. K0[8] (see Rx1A bits 0-7). default=0
Offset Special Effect 0.RW Adjust Bits 7-0. HUE_ADJ[7:0] (see Rx11[7-5] bits 10-8) .default Offset Special Effect 1.RW Reserved Program). default Crawl DOT_CRAWL Enable .default Disable Adjust Bits 10-8. HUE_ADJ[10:8] (see Rx10 bits 0-7) default 000b Refer Table Master Clock Mode Clock Settings, more information. Offset Value Resister Selection Bits .R[2:0] Programmed increments default 000b Second Post Divider Control. P2[4:0] Programmed increments 00000b Offset Value.RW Reserved always reads Pre-Divider Control.D[5:0] Programmed increments 000000b Offset Value.RW Output Division Factor Bits 7-0.N[7:0] (see Rx15[1:0] bits 9-8) .default N[9:8] defines division factor applied output. increments 1.0. Offset Overflow Reserved always reads First Post Divider Control. P[4:0] Programmed increments default 00000b Output Division Factor [9:8].N[9:8] (see Rx14 bits 0-7) default N[9:8] defines division factor applied output.
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Register Descriptions
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Offset Coring Function Coring Function COR_EN Disable. default Enable Coring Function Threshold .COR_TH default Offset Delay Control. Reserved. always reads Delay Depth. default Offset Delay Control Burst Amplitude Bit-8 BURST_AMP[8] (see Rx4F bits 7:0). default Delay Depth.U_DELAY Shortest input clock delay. default Longest input clock delay Each increment this field clock cycle Underflow Check .UF_CHK Disable. default Enable Delay Depth.V_DELAY Shortest input clock delay. default Longest input clock delay Each increment this field clock cycle Offset Burst Maximum Amplitude Burst Maximum Value. BURST_AMP[7:0] (see Rx4E[7] bit-8) default
Offset Sync Step.RW Sync Step .[7:0] (see Overflow Rx24[0] bit-8).default Step value control shape slope sync. Offset Burst Envelope Step Burst Envelope Step .[7:0] (see Overflow Rx24[1] bit-8).default Step value control shape slope burst. Offset Sub-Carrier Phase Adjust Sub-Carrier Phase Adjust .[7:0] (see Rx24[4-2] bits 10-8) .default Step value control shape slope burst. Offset Blank Level Blank Level .[7:0] (see Rx24[5] bit-8) .default Step value control base level blank signal. Offset Signal Overflow Reserved always reads Bit[8] Blank Level (Rx23). default Bit[10:8] Sub-Carrier Phase Adjust (Rx22) default Bit[8] Burst Envelope Step (Rx21)default Bit[8] Sync Step (Rx20) default
Offset Input Aperture Threshold.RW Input Data Threshold IN_APR_TH Threshold input data.default Offset Input Aperture Delta Input Data Adjustment Value. IN_APR_DLT Adjustment value input data.default
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Register Descriptions
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Offset Burst Start. Burst Start TBURST_START[7:0] (see Rx58[2-0] bits 10:8). default (start point relative analog HSYNC falling edge) Offset Burst End. Burst End. TBURST_END[7:0] (see Rx5D[6] default (end point relative analog HSYNC falling edge) Offset Video Start Point. Video Start.TVIDEO_START[7:0] (see Rx5D[4] default (number pixels between leading edge analog HSYNC active video) Offset Video Point Video TVIDEO_END[7:0] (see Rx5D[3-0] bits 11:8) default (number pixels between leading edge analog HSYNC video end) Offset Video Overflow Reserved. always reads Burst Overflow. TBURST_END[8] (see Rx5A bits 7:0) default Reserved. always reads Video Start Overflow.TVIDEO_START[8] (see Rx5B bits 7:0) default Video Overflow TVIDEO_END[11:8] (see Rx5C bits 7:0) default 0000b Offset Vertical Scale Factor Vertical Scale Factor. VSCALE_FAC[7:0] (see Rx60[3-0] bits 11:8). default Offset Horizontal Scale Factor. Horizontal Scale Factor .HSCALE_FAC[7:0] (see Rx60[6-4] bits 10:8). default Offset Scaling Overflow Reserved. always reads Scale Factor Overflow .HSCALEFAC[10:8] (see Rx5F bits 7:0). default 000b Scale Factor Overflow. VSCALE_FAC[11:8] (see Rx5E bits 7:0) default 0000b
Offset Graphic Horizontal Total Pixels.RW Graphic Horiz Total Pixels .GH_TOTAL[7:0] (see Rx52[2-0] bits 10:8) .default Offset Graphic Horizontal Active Pixels Graphic Horiz Active Pixels. GH_ACTIVE[7:0] (see Rx52[5-4] bits 9:8) .default Offset Graphic Horizontal Overflow.RW Reserved always reads Active Pixels Overflow. GH_ACTIVE[9:8] (see Rx51 bits 7:0) default Reserved always reads Total Pixels Overflow .GH_TOTAL[10:8] (see Rx50 bits 7:0) default 000b
Offset Graphic Vertical Total Lines Graphic Vert Total Pixels GV_TOTAL[7:0] (see Rx54[2-0] bits 10:8) .default Offset Graphic Vertical Overflow Reserved always reads Total Pixels Overflow. GV_TOTAL[10:8] (see Rx53 bits 7:0) default 000b Offset Horizontal Total Pixels Horiz Total Pixels TH_TOTAL[7:0] (see Rx58[2-0] bits 10:8) .default Offset Horizontal Active Pixels.RW Horiz Active Pixels .TH_ACTIVE[7:0] (see Rx58[5-4] bits 9:8) .default Offset Horizontal Sync Width Horiz Sync Width THSYNC_WIDTH [7:0] .default Offset Horizontal Overflow Reserved always reads Active Pixels Overflow .TH_ACTIVE[9:8] (see Rx56 bits 7:0) default Reserved always reads Total Pixels Overflow. TH_TOTAL[10:8] (see Rx55 bits 7:0) default 000b
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Offset PY_G Amplitude Factor. Amplitude Factor .PYGAF[7:0] default Offset PB_B Amplitude Factor Amplitude Factor. PBBAF[7:0] default Offset PR_R Amplitude Factor Amplitude Factor .PRRAF[7:0] default Offset Auto Sub-Carrier Value Auto Adjust FSCI Value Byte A_FSCI[7:0] byte 32-bit value Rx68-6B) default Offset Auto Sub-Carrier Value Auto Adjust FSCI Value Byte A_FSCI[15:8] byte 32-bit value Rx68-6B) default Offset Auto Sub-Carrier Value Auto Adjust FSCI Value Byte A_FSCI[23:16] byte 32-bit value Rx68-6B) default Offset Auto Sub-Carrier Value Auto Adjust FSCI Value Byte A_FSCI[31:24] byte 32-bit value Rx68-6B) default After reset, above registers read 00h, FSCI disabled, FSCI value Rx19-16 used. Rx5[3] enable "FSCI Auto Adjust", FSCI generated on-chip circuitry FSCI value read from registers Rx6B68 above this case, value Rx19-16 ignored).
Offset Deflicker Threshold Deflicker Threshold .DFK_THD[7:0] .default Offset Deflicker Detection Length Reserved always reads Deflicker Length DFKDT_LENGTH[1:0] detection .default pixels pixels pixels Offset Scaling Horizontal Total Pixels Scaling Total Pixels.SH_TOTAL[7:0] (see Rx64[3-0] bits 11:8) .default Offset Scaling Horizontal Total Pixels Overflow Reserved always reads Scaling Pixels Overflow .SH_TOTAL[11:8] (see Rx63 bits 7:0) default 0000b
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FUNCTIONAL DESCRIPTION
Architecture Description
Refer Figure below following module descriptions.
Serial Interface Data Capture Color Space Converter FIFOs Scaler Deflicker
PD[15:0]
NTSC Encoder
CVBS CVBS
Horizontal Vertical Timing CRTC
Pixel Clock
HSYNC
VSYNC
XCLK
PCLK
Figure Architectural Description Block Diagram
Data Capture 8-bit, 12-bit, 16-bit multiplexed 16-bit non-multiplexed input data captured this module transferred 24-bit data pixel. Color Space Converter data from Data Capture module YCrCb format. This module converts both formats format. Scaler Deflicker This module converts lines input pixel data appropriate number output lines producing full-screen image television receiver. image scaled 100% within viewable area screen. device perform vertical filtering reduce effects picture flicker interlacing output image. Because this process trades vertical resolution order reduce flicker, amount flicker filtering programmable allows process optimized specific image. This module generates YUV444 pixel data from interlaced image encoder module.
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Encoder This module accepts YUV444 pixel data converts standard baseband television signal that compatible with worldwide standards including NTSC data manipulated contrast control setup level added brightness control. data scaled achieve color saturation control. Also, signals modulated appropriate sub-carrier sine/cosine waveforms phase offset added onto color sub-carrier during active video allow adjustment. resulting signals added together make chrominance signal. luma chroma signals added together make composite video signal. Separated luma chroma signals make S-video signal. VT1622 VT1622M contain four 10-bit DACs. Each used convert digital composite, luma, chroma, RGB, YCbCr, YPbPr data analog signals individually powered required. addition, module auto-detection circuit, which provides sense connection Serial Interface VT1622 VT1622M contain standard serial control port through which control registers written read. serial address depending strapping ADDR pin. CRTC controller normally supplies horizontal vertical sync signals, however, they also selected generated VT1622 VT1622M. This module generates horizontal vertical sync signals. CCIR656 input mode, embedded sync also used. Both VT1622 VT1622M contain high accuracy, low-jitter phase-locked-loop create outstanding quality video. Normal operation requires encoding clock generated PLL. master clock mode, reference clock provided frequency 14.31818 MHz. slave clock mode, reference clock input XCLK pin.
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VT1622 VT1622M Digital Encoders
Master/Slave Clock Mode
Both VT1622 VT1622M configured either master slave clock mode. master clock mode, they provide pixel clock signal video source expect incoming data available when required. slave clock mode, encoder chips accept external pixel clock from video source. Master Mode master clock mode, VT1622 VT1622M work master video source device works slave. They provide clock signal through PCLK video source device video source device will this clock frequency reference. Then video source will generate clock signal into XCLK pin. encoders chips will this clock signal latch incoming data. PCLK clock signal also used input clock signal connected directly XCLK pin. HSYNC VSYNC signals programmed either input output encoder chips. master clock mode configured mode mode illustrated Figure Figure Slave Mode slave clock mode, VT1622 VT1622M work slave video source device works master. video source device will generate clock signal input XCLK pin. Through XCLK pin, they receive clock from video source device this clock latch incoming data. Moreover, this clock will reference clock encoder chips generating pixel clock. HSYNC VSYNC signals programmed either input output encoder chips. slave clock mode, both VT1622 VT1622M configured illustrated Figure
XCLK
VT1622 VT1622
XCLK
VT1622
Video Source Device
Hsync Vsync Pixel data PCLK
Video Source Device
Hsync Vsync Pixel data PCLK
VT1622M
Configuration
Configuration
XCLK
VT1622 VT1622
XCLK
VT1622
Video Source Device
Hsync Vsync Pixel data PCLK
Video Source Device
Hsync Vsync Pixel data PCLK
VT1622M
Configuration
Configuration
Figure Master Clock Mode
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Hsync
Hsync
Video Source Device
Vsync Pixel data XCLK
VT1622 VT1622M
VT1622
Video Source Device
Vsync Pixel data XCLK
VT1622
PCLK
PCLK
Configuration
Hsync
Configuration
Hsync
Video Source Device
Vsync Pixel data XCLK
VT1622 VT1622M
Video Source Device
Vsync Pixel data XCLK
VT1622 VT1622M
PCLK
PCLK
Configuration
Configuration
Figure Master Clock Mode
XCLK
VT1622
XCLK
VT1622
Video Source Device
Hsync Vsync Pixel data
VT1622
Video Source Device
Hsync Vsync Pixel data
VT1622M
Configuration
Configuration
XCLK
VT1622
XCLK
Video Source Device
Hsync Vsync Pixel data
VT1622
Video Source Device
Hsync Vsync Pixel data
VT1622 VT1622M
Configuration
Configuration
Figure Slave Clock Mode
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Digital Video Interface VT1622 VT1622M configured with 8-bit, 12-bit, 16-bit input data bus. They accept 16-bit, 15-bit, 24-bit YCrCb 16-bit (CCIR 656) data format. 8-bit Multiplexed Mode 15-bit: 5-5-5 over bytes 16-bit: 5-6-5 over bytes 24-bit: 8-8-8 over three bytes YCrCb 16-bit: .(CCIR656 style) 12-bit Multiplexed Mode 24-bit: 8-8-8 over words 16-bit Multiplexed Mode 24-bit: 8-8, over words 16-bit Non-multiplexed Mode 15-bit: 5-5-5 each word 16-bit: 5-6-5 each word YCrCb 16-bi CbY0, CrY1, .(CCIR656 style)
Table Input Data Format
16-bit 16-bit 24-bit 15-bit 24-bit YCrCb Pixel 24-bit 24-bit 16-bit 15-bit 16-bit YCrCb
PD15 PD14 PD13 PD12 PD11 PD10
Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0
Cr/Cb7 Cr/Cb6 Cr/Cb5 Cr/Cb4 Cr/Cb3 Cr/Cb2 Cr/Cb1 Cr/Cb0
denotes pixel number Each rising edge each rising falling edge) XCLK signal will latch data from video source device. nonmultiplexed multiplexed input data formats shown Figure Pixel Data represents 16-bit multiplexed 16-bit non-multiplexed data stream, which contains either YCrCb formatted data. settings input data rate pixel clock frequency, each 15/16-bit value will contain complete pixel encoded either 5-6-5, 5-5-5 YCrCb format. settings input data rate pixel clock frequency, each pair values (for example, P#B) will contain complete pixel, encoded shown Table above. When input data rate pixel clock frequency, each triplet values (for example, P#A, P#C) will contain complete pixel, encoded shown Table above. When input data YCrCb format, color-difference data will transmitted half data rate luminance data transmission sequence will When sync signals embedded into data stream embedded sync will similar CCIR656 convention. When sync signals embedded into data stream. this mode, embedded sync will follow CCIR656 convention, first byte "video timing reference code" will assumed occur when sample occurs video stream continuous.
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XCLK (2X) XCLK (1X) Hsync D[11:0] D[15:0]
Multiplexed Mode
XCLK (3X) Hsync
Multiplexed Mode
D[7:0]
Start Active Video (see Rx1C[3])
Figure Multiplexed Input Interface Protocol
Non-Multiplexed Mode
XCLK (1X) Hsync D[15:0]
Start Active Video (see Rx1C[3])
Figure Non-Multiplexed Input Interface Protocol
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Video Standards VT1622 VT1622M configured kinds output modes (interlaced, non-interlaced progressive), which selected OUT_MODE[1:0] register bits (Rx4[3:2]). addition, both encoders generate output video signals S-Video, composite, YCbCr, SCART (RGB), VGA-style interlaced non-interlaced output modes, YPbPr progressive output mode. While interlaced non-interlaced output mode, there several bits (VOS, LINE_SEL, PAL_N, PAL_Nc) that control generation various video standards. They allow generation NTSC video standards control specific encoding process parameters. Other registers also need modified meet video parameters particular video standard. difference between interlaced non-interlaced output mode that non-interlaced output mode always outputs field. NTSC, that lines frame frames second, PAL, lines frame frames second. Interlaced non-interlaced video timing diagrams illustrated from Figure Figure which summarize common video standards. Composite S-video outputs supported either NTSC format. Figure through Figure illustrate composite S-video output waveforms different color bars. While progressive output mode, LINE_SEL register controls whether output lines lines lines frame whether frame rate progressive analog component signal comprised three signals, analog YPbPr, which compliant with EIA770-1 EIA770-2. Progressive video timing diagrams illustrated from Figure Figure
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Figure Interlaced 525-Line (NTSC) Video Timing
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Figure Interlaced 525-Line (PAL-M) Video Timing
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Figure Interlaced 625-Line (PAL-B, Video Timing (Fields 1-4)
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Figure Interlaced 625-Line (PAL-B, Video Timing (Fields 5-8)
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Figure Interlaced 625-Line (PAL-N) Video Timing (Fields 1-4)
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Figure Interlaced 625-Line (PAL-N) Video Timing (Fields 5-8)
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Figure Non-interlaced 262-Line (NTSC) Video Timing
Figure Non-interlaced 262-Line (PAL-M) Video Timing
Figure Non-interlaced 312-Line (PAL-B, Video Timing
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Green Magenta
Yellow Cyan
White
26.67
1.000
Blue Black White Level Black Level Blank Level Sync Level
White Level Black Blank Level Sync Level
Functional Descriptions
9.08 7.63 0.340 0.286
0.00
0.000
Figure 525-Line (NTSC/PAL-M) (Luma) Video Test Pattern Waveform
Green Magenta
White Yellow Cyan
26.67
1.000
8.00
0.300
0.00
0.000
Figure 625-Line (PAL-B, (Luma) Test Pattern Waveform
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28.19
1.047
20.86 17.05 13.26
0.782 0.640 0.499
Black Blank Level
Cyan
Color Burst Cycles)
5.91
0.217
Figure 525-Line (NTSC/PAL-M) (Chroma) Video Test Pattern Waveform
Magenta
Yellow
White
Green
Blue
Magenta
Yellow
White
Green
Cyan
28.85
1.079
21.05 17.05 13.08
0.788 0.640 0.492
Color Burst (2.22
Blue
Black Blank Level
Functional Descriptions
5.25
0.195
Figure 625-Line (PAL-B, (Chroma) Video Test Pattern Waveform
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Magenta
Yellow
White
Cyan Green
28.85 26.67
1.079
1.000
Color Burst cycles)
11.44 9.08 7.63 3.84 0.00
0.428 0.340 0.286 0.145
0.000
Figure Composite 525-Line (NTSC/PAL-M) Video Test Pattern Waveform
Magenta
Yellow
White
Cyan Green
26.67
1.000
12.00 8.00 4.03 1.79 0.00
0.448 0.300 0.152 0.086 0.000
Color Burst (2.22
Figure Composite 625-Line (PAL-B, Video Test Pattern Waveform
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Blue Black White Level Black Blank Level Sync Level
Functional Descriptions
Blue Black White Level Black Level Blank Level Sync Level
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Figure 525-Line Progressive Video Timing
Figure 625-Line Progressive Video Timing
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Luminance Chrominance Filter Option
VT1622 VT1622M contain luminance chrominance filters provide controllable bandwidth output both composite S-video outputs. coefficients filter selected YBW[2:0] CBW[2:0] register bits. filter selection principle illustrated Table Table filter frequency response illustrated Figure through Figure
Table Luminance Filter
Filter Lowpass (NTSC) Lowpass (NTSC) Lowpass (NTSC) Notch (NTSC) Lowpass (PAL) Lowpass (PAL) Lowpass (PAL) Lowpass (ALL) Rx03[7:5] YBW[2:0] TVCLK (MHz) Bandwidth (MHz) 2.28 2.28 2.28 2.28/3.58/4.88 3.13 3.13 3.13 4.43
Table Chrominance Filter
Filter Lowpass Lowpass Lowpass Lowpass Rx03[4:2] CBW[2:0] TVCLK (MHz) Bandwidth (MHz) 4.43
Inphase Filter Frequency Response
Magnitude
Frequency
Figure Low-Pass Luma Filter NTSC
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Inphase Filter Frequency Response
Magnitude
Frequency
Figure Low-Pass Luma Filter
Inphase Filter Frequency Response
Magnitude
Frequency
Figure Notch Luma Filter NTSC
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Inphase Filter Frequency Response
Magnitude
Frequency
Figure Wide Bandwidth Luma Filter
Inphase Filter Frequency Response
Magnitude
-100 -120
Frequency
Figure Lowpass Chroma Filter
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Inphase Filter Frequency Response
Magnitude
Frequency
Figure Wide Bandwidth Chroma Filter
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Color Test Pattern Generator
VT1622 VT1622M have built-in color generator that generates amplitude 100% saturation colors NTSC standards. While color mode, input pixel data ignored. Subcarrier Generation VT1622 VT1622M 32-bit-word synthesize subcarrier. value sub-carrier increment required generate desired subcarrier frequency found with following equations: NTSC: FSCI[31:0] [455 H_Total)] -orFSCI[31:0] (int) (232 3.579545 Fclk) PAL: FSCI[31:0] [(1135/4 1/625) (H_Total)] -orFSCI[31:0] (int) (232 4.43361875 Fclk) where H_Total number output pixels line Fclk encoder clock frequency FSCI_ADJ_EN Fclk 14.31818 FSCI_ADJ_EN This allows generation desired subcarrier desired video standard. 32-bit subcarrier increment FSCI[31:0] must loaded serial interface before subcarrier enabled. order prevent residual errors from accumulating maintain correct phase, subcarrier reset every lines NTSC standard every field standard. Burst Generation Subcarrier burst generation function video standard (e.g. NTSC PAL), subcarrier frequency increment (FSCI), burst horizontal begin (TBURST_START) (TBURST_END) register settings. burst will automatically blanked during horizontal sync prevent invalid sync pulses from being generated. Burst blanking automatically controlled selected video format burst amplitude programmed BURST_AMP setting. Power Down Mode VT1622 VT1622M powered down programming their registers each DACs powered down independently used. register contents maintained when VT1622 VT1622M power down mode. Macrovision Anti-Copy Protection VT1622M implements Macrovision anti-copy protection process Macrovision copy protection with 525p progressive scan output. This process changes encoded output NTSC/PAL signals inhibit recording devices while affecting viewing parameters that control anti-copy protection process fully programmable documented this data sheet legal requirements Macrovision Corporation.
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Display Modes
VT1622 VT1622M designed accept input resolution from 320x200 1024x768 setting CRTC registers, scaling registers timing registers. CRTC registers include GH_TOTAL, GV_TOTAL, GH_ACTIVE, SH_TOTAL, TH_TOTAL, TH_ACTIVE register bits. These registers decide horizontal active total pixels, total lines input data, output horizontal active total pixels display after scaling. encoder chips scale down input images size from factors vertical horizontal directions setting VSCAL_FAC HSCAL_FAC register bits. encoder chips contain frame memory. Therefore, their output frame rate must synchronous input frame rate. accomplish this, input total, output total, scaling ratio, pixel frequency must proper values corresponding relationship. Because pixel frequency varies from every input resolution, further, timing fixed, must program different values timing registers every input resolution. timing registers include THSYNC_WIDTH, TBURST_START, TBURST_END, TVIDEO_START, TVIDEO_END register bits. Table lists display modes NTSC standards.
Table Display Modes
Mode Output Standard NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC Input Active Video 1024x768 1024x768 1024x768 1024x768 1024x768 1024x768 1024x768 1024x768 1024x768 1024x768 1024x768 1024x768 800x600 800x600 800x600 800x600 800x600 800x600 800x600 800x600 800x600 800x600 800x600 800x600 640x480 640x480 640x480 640x480 640x480 640x480 640x480 640x480 640x480 640x480 640x480 640x480 640x400 640x400 640x400 640x400 640x400 720x400 720x400 720x400 720x400 512x384 512x384 512x384 512x384 Input Total 1144x1050 1176x975 1160x945 1232x900 1200x840 1200x805 1160x1125 1200x1075 1400x1000 1200x925 1400x875 1200x825 1040x840 1080x805 1064x750 960x700 1080x665 920x630 960x875 1000x800 920x750 1000x700 1000x650 896x625 728x675 800x630 784x600 720x560 712x525 840x500 720x750 800x700 800x650 840x625 800x600 840x500 840x600 840x525 840x420 1008x625 1000x500 936x525 945x420 1116x625 1080x500 784x525 800x420 840x625 840x500 Scaling Ratio 7/13 7/12 15/23 25/43 25/37 25/33 15/23 7/10 15/19 25/32 25/28 25/26 15/16 21/20 25/28 25/26 25/24 Overscan Pixel Clock 72.000000 68.727272 65.706293 66.461538 60.419580 57.902097 65.250000 64.500000 70.000000 55.500000 61.250000 49.500000 52.363637 52.111888 47.832169 40.279720 43.048951 34.741258 42.000000 40.000000 34.500000 35.000000 32.500000 28.000000 29.454545 30.209790 28.195805 24.167832 22.405594 25.174825 27.000000 28.000000 26.000000 26.250000 24.000000 21.000000 30.209790 26.433566 21.146853 31.500000 25.000000 29.454545 23.790210 34.875000 27.000000 24.671329 20.139860 26.250000 21.000000
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Clock Frequency crystal must present between pins generating 14.31818 reference clock (Phase Lock Loop). master clock mode, uses this clock reference. slave clock mode, uses clock from XCLK reference clock. generates clocks: pixel clock output PCLK (for master mode only) other pixel clock used Encoder engine. frequency calculated using following formula: FCLK FREFCLK* (D*P) settings control registers listed Table programmed increments 0.5; programmed increments 1.0).
Table Master Clock Mode Clock Settings
Mode Pixel (MHz) 72.000000 68.727272 65.706293 66.461538 60.419580 57.902097 65.250000 64.500000 70.000000 55.500000 10x1 61.250000 11x1 49.500000 12x1 52.363637 13x1 52.111888 14x1 47.832169 15x1 40.279720 16x1 43.048951 17x1 34.741258 18x1 42.000000 19x1 40.000000 20x1 34.500000 21x1 35.000000 22x1 32.500000 23x1 28.000000 24x1 29.454545 25x1 30.209790 26x1 28.195805 27x1 24.167832 28x1 22.405594 29x1 25.174825 30x1 27.000000 31x1 28.000000 32x1 26.000000 33x1 26.250000 34x1 24.000000 35x1 21.000000 36x1 30.209790 37x1 26.433566 38x1 21.146853 39x1 31.500000 40x1 25.000000 41x1 29.454545 42x1 23.790210 43x1 34.875000 44x1 27.000000 45x1 24.671329 46x1 20.139860 47x1 26.250000 48x1 21.000000 13.5 25.5 26.5 17.5 17.5 21.5 21.5 17.5 10.5 22.5 17.5 12.5 22.5 Rx12 Rx13 Rx14 Rx15 (Bits 7:5=R, 4:0=P2) (Bits 6:2=P, 1:0=N[9:8])
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DESIGN GUIDELINES
Board Layout Considerations
This section focuses design considerations VT1622 VT1622M Encoder. using these chips, images easily displayed set. typical connection between VT1622/VT1622M VT8605 North Bridge chip shown Figure
VT8605 North Bridge TVD[11:0] TVCLKR TVCLK TVVS TVHS
VT1622 VT1622M
Encoder D[11:0] XCLK PCLK
Figure Interconnect with PM133 Chipset VT8605 North Bridge
Component Placement Components associated with VT1622 VT1622M encoder should placed close possible their respective pins. following discussion will describe guidelines connect critical pins well guidelines placement layout components associated with these pins.
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Power Supply Decoupling Optimum power supply decoupling accomplished placing 0.1uF ceramic capacitor next each power supply pins shown Figure These capacitors should connect close possible their respective power ground pins using short, wide traces minimize lead inductance. Whenever possible, physical connecting trace should connect ground pins decoupling capacitors VT1622 VT1622M ground pins, addition ground vias. Figure details.
VCC25 0.1u VGND VGND 0.1u 0.1u VGND VGND 0.1u VGND 0.1u VGND GNDDAC VCCDAC GNDDAC VCCDAC VCC25 0.1u GNDBGAP VGND VCCBGAP VCC25 0.1u GNDOSC VCCOSC VCC25 0.1u GNDPLL VCCPLL VCC25 0.1u VCC25
VT1622 VT1622M
VCC25 GND: Digital 2.5V VCCPLL GNDPLL: 2.5V VCCOSC GNDOSC: 2.5V VCCBGAP GNDBGAP: Bandgap 2.5V VCCDAC GNDDAC: 2.5V
Figure Decoupling Capacitors Arrangement
Ground Pins analog digital grounds VT1622 VT1622M should connect different ground planes provide impedance return paths with supply currents. Whenever possible, each VT1622 VT1622M ground pins should connect directly their respective decoupling capacitor ground lead, then connect ground plane through ground via. Short wide traces should used minimize lead inductance. Figure details. Power Pins Separate digital, analog, power planes recommended. Figure power supply assignments.
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General Controls Inputs RSET RSET (pin acts current reference source Output. 4.64 KOhm resister with precision should connected this through AGND. resister should placed close possible chip routing trace should component side with connection. quality issues, wide trace widths also recommended. Outputs There four output pins: DACA (pin 10), DACB (pin 12), DACC (pin 14), DACD (pin 16). components associated with these pins should placed close possible VT1622 VT1622M. output termination, output filter network, output connectors should located close possible VT1622 minimize noise pickup well possible reflections impedance mismatches. video output signals should overlay ground plane should routed away from digital lines that could introduce crosstalk. outputs should separated ground trace inductors ferrite beads series with these outputs should located next each other.
DACA 1.2uH 270p 1.2uH 330p 75_1% CVBS/Y
VGND VCCA2
VGND
VGND
VGND
C/R/Pr 1.2uH 270p 1.2uH 330p
DACB
75_1%
VGND VCCA2
VGND
VGND
VGND DACC 75_1%
1.2uH 270p
1.2uH 330p
VGND VCCA2
VGND
VGND
VGND DACD 75_1%
CVBS/C/B/Pb
1.2uH 270p
1.2uH 330p
VGND VCCA2
VGND
VGND
VGND
Figure Output Configuration
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Crystal Inputs 14.31818 (±50ppm NTSC systems, ±25ppm systems) crystal must placed close possible pins (pins with traces connected from point point, overlaying ground plane. Since crystal generates timing reference VT1622 VT1622M encoder, very important that noise should couple into these pins. Traces with fast edge rates should routed under adjacent these pins. addition, ground reference external capacitors connected crystal pins must connected close ground VT1622 VT1622M (see Figure 34). Reference Crystal Oscillator Both VT1622 VT1622M also include oscillator circuit, which allows inexpensive 14.31818 crystal connected directly. Alternatively, externally generated 14.31818 clock source supplied VT1622 VT1622M. external clock source used, should have CMOS level specifications. clock should connect pin, should tied ground, with pull resister KOhm CONF_XLT (pin 55). external source must exhibit ±50ppm better frequency tolerance, have jitter characteristics.
VT1622 VT1622M 14.31818 32pF
Figure Crystal Configuration
crystal used, designer should ensure that following conditions met: crystal specified 14.31818 MHz, ±50ppm, fundamental type, parallel resonant (NOT series resonant) crystal operated with load capacitance equal specified value External load capacitors have their ground connection very close VT1622 VT1622M. allow tunability, variable used from ground
Output VT1622 VT1622M output (pin reflect 14.31818 generated crystal inputs through PLL. operation work normally, capacitor 10pF connected ground recommended. External Clock Input external clock input, XCLK (pin 25), receives pixel clock from chipset north bridge chip.
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Pixel Data Inputs VT1622 VT1622M support bits data input support various input data formats. host interface supported VT8605 north bridge chip bits. this case, interconnect should started from least significant bits, i.e. connect TVD[11:0] VT8605 D[11:0] VT1622 VT1622M. Un-connected pins D[15:12] should connected ground prevent unexpected operation. Board Layout Example
Figure Layout Example
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ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Symbol Description
TSTG TAMB VESD TVPS Storage Temperature Junction Operating Temperature Ambient Operating Temperature Case Operating Temperature Analog Output Short Circuit Duration Input Voltage (all digital pins) Electrostatic Discharge (Human Body) Vapor Phase Soldering min.) 0.25 indefinite VCC+0.25
(desktop) (notebook)
Unit
Seconds
Recommended Operating Conditions Symbol
VCC33 VCC25 VCCPLL
Description
Voltage Digital Power Supply Voltage Power
3.15 2.25 2.25 2.25 2.25 2.25
37.5
3.45 2.75 2.75 2.75 2.75 2.75
Unit
VCCDAC Power VCCOSC Oscillator Power
VCCBGAP Band Power Output load outputs
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Power Supply Current Total Power Consumption Specifications Symbol Description
ID33 ID25 IPLL IOSC IBGON IBGOFF IDACON IDACOFF PTOTAL VCC33 (3.3V) VCC25 (2.5V) VCCPLL (2.5V) VCCOSC (2.5V) VCCBGAP (2.5V) Outputs Powered VCCBGAP (2.5V) Outputs Powered VCCDAC (2.5V) Outputs Powered VCCDAC (2.5V) Outputs Powered Total Power Consumption
Unit
Operating Conditions:
VCC25 VCCA VCCPLL VCCDAC VCCOSC VCCBGAP 2.5V, VCC33 3.3V, RSET 4.64
Specifications Symbol Parameter
VCC33 VIH5T COUT voltage Input voltage Input high voltage Input high voltage Output voltage Output high voltage Input leakage Input capacitance Output capacitance
-0.5
1.05
Unit Condition
Normal tolerant tolerant tolerant IOL= 3.2mA IOH= -200mA
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Characteristics Parameter
Full Scale Current Operating Temperature Operating Voltage Output Voltage Output Voltage Compliance SENSE Reference Voltage Band-Gap Reference Voltage RSET Resistor Output Load Resistor Output Loading Resolution Matching Gain Error 1.235 1.235 4.64 37.5 2.25
34.00 33.20 2.50 1.28
Unit
2.75
Bits
Characteristics Parameter
Frequency Output Rise Time Output Fall Time Output Full Scale Settling Time 21.5
Units
Note: VCCDAC 2.5V; 37.5; RSET 4.64 Temp 60oC, unless otherwise noted
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Display Signal Characteristics Symbol
Parameters
Pixel Clock Width Horizontal Sync Width Setup time from Pixel Data Pixel Clock Hold time from Pixel Clock Pixel Data
6.25
Unit
Characteristics Operating Conditions
Power Supply Clock Output Duty Cycle Note: Crystal Spec: 14.31818MHz ppm)
2.25
2.75
Unit
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PACKAGE MECHANICAL SPECIFICATIONS
0.05
VT1622/VT1622M
YYWWRR TAIWAN LLLLLLLLLL
Part Number Date Code, Chip Revision Country Assembly
SEATING PLANE
0.25mm
GAGE PLANE
NOTES DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL CAUSE LEAD WIDTH EXCEED MAXIMUM DIMENSION MORE THAN 0.08mm. DAMBAR LOCATED LOWER RADIUS FOOT. MINIMUM SPACE BETWEEN PROTRUSION ADJACENT LEAD 0.07mm.
CONTROL DIMENSIONS MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 1.20 0.047 0.05 0.15 0.002 0.006 0.95 1.00 1.05 0.037 0.039 0.041 12.00 BASIC 0.472 BASIC 12.00 BASIC 0.472 BASIC 10.00 BASIC 0.393 BASIC 10.00 BASIC 0.393 BASIC 7.50 BASIC 0.295 BASIC 7.50 BASIC 0.295 BASIC 0.08 0.003 0.08 0.20 0.003 0.008 0.09 0.20 0.004 0.008 0.45 0.60 0.75 0.018 0.024 0.030 1.00 0.039 0.20 0.008 0.17 0.20 0.27 0.007 0.008 0.011 0.50 BASIC 0.020 BASIC TOLERANCES FORM POSITION 0.20 0.008 0.20 0.008 0.08 0.003 0.08 0.003
Figure Mechanical Specification 64-Pin TQFP Thin Quad Flat Pack
Revision October 2002 -50Package Mechanical Specifications

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