AK4683 Asynchronous Multi-Channel Audio CODEC with DIR/T GEN

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AK4683 Asynchronous Multi-Channel Audio CODEC with DIR/T GEN

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[AK4683]
AK4683
Asynchronous Multi-Channel Audio CODEC with DIR/T
GENERAL DESCRIPTION AK4683 single chip CODEC that includes channels four channels DAC. outputs 24bit data accepts 24bit input data. Enhanced Dual architecture with wide dynamic range. introduces developed Advanced Multi-Bit architecture, achieves wider dynamic range lower outband noise. also digital audio receiver (DIR) transmitter (DIT) compatible with 192kHz, 24bits. automatically detect Non-PCM stream such Dolby Digital (AC-3)*. AK4683 dynamic range 100dB ADC, 106dB well suited digital home theater system. Dolby Digital (AC-3) trademark Dolby Laboratories. FEATURES ADC/DAC part Asynchronous ADC/DAC Operation Input Selector with Pre-amp 24bit Oversampling Sampling Rate 96kHz Linear Phase Digital Anti-Alias Filter Single-Ended Input S/(N+D): 90dB Dynamic Range, S/N: 100dB Digital Offset Cancellation Channel Independent Digital Volume (+24/-103dB, 0.5dB/step) Soft Mute Overflow Flag 24bit 128x Oversampling Sampling Rate 192kHz 24bit times Digital Filter Single-Ended Outputs S/(N+D): 90dB Dynamic Range, S/N: 106dB Channel Independent Digital Volume (+12/-115dB, 0.5dB/step) Soft Mute De-emphasis Filter (32kHz, 44.1kHz, 48kHz) Zero Detect Function Stereo Headphone with Volume 50mW 16ohm Click-noise free Power on/off High Jitter Tolerance
MS0427-E-00
2005/09
[AK4683]
DIR/DIT Part AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible jitter Analog Lock Range 32kHz 192kHz Clock Source: X'tal 4-channel Receiver input 1-channel Transmission output (Through output DIT) Auxiliary digital input De-emphasis 32kHz, 44.1kHz, 48kHz 96kHz Detection Functions Non-PCM Stream Detection DTS-CD Stream Detection Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) Unlock Parity Error Detection Validity Flag Detection 24bit Audio Data Format 40-bit Channel Status Buffer Burst Preamble Buffer Non-PCM stream Q-subcode Buffer stream Level Digital External Master Clock Input: 256fs, 384fs, 512fs (fs=32kHz 48kHz) 128fs, 192fs, 256fs (fs=64kHz 96kHz) 128fs (fs=120kHz 192kHz) Master Clock Output: 128fs/256fs/384fs/512fs Audio Serial (PORTA, PORTB) Master/Slave mode format PORTA: Left/Right(20/24 bit) justified, I2S, PORTB: Left/Right(20/24 bit) justified, 4-wire Serial mode setting Operating Voltage: 5.5V Power Supply output buffer: 5.5V 64pin LQFP Package (0.5mm pitch)
MS0427-E-00
2005/09
[AK4683]
Block Diagram
RMCLK LISEL LOPIN LIN1 LIN2 LIN3 LIN4 LIN5 LIN6 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 ROPIN RISEL
Through
Input Selector
Clock Recovery
DAIF Decoder
X'tal Oscillator
MCLK2 MCKO PORTB BICKB LRCKB
SDTIA1
IPS0/1, OPS0/1
LIN0/1/2, RIN0/1/2
HPF, DVOL
Audio
HPF, DVOL
SDOUT
SDTOB
SDTOB0/1 SDTIB
SDTIB SDTIA1 SDTIB SDTIA1 SDTIA2 SDTIA3 SDTIB SDTOA0/1
DIT0/1 LOUT1 ROUT1
DVOL DVOL DVOL DVOL
DAC1 Audio DAC2 Audio
CCLK CDTI CDTO
PORTA SDTOA OLRCKA BICKA ILRCKA SDTIA1 SDTIA2 SDTIA3
LOUT2 ROUT2
SDTIB SDTIA1 SDTIA2 SDTIA3
DAC10/11/12, DAC20/21/22
MS0427-E-00
2005/09
[AK4683]
Ordering Guide AK4683EQ AKD4683 +85°C 64pin LQFP (0.5mm pitch) Evaluation Board AK4683
Layout
AVDD1 PVSS AVSS1
RIN4
RIN3
RIN2
RIN6
RIN5
RIN1
LIN5
LIN4
LIN6
LIN3
PVDD VOUT CDTO LRCKB BICKB SDTOB OLRCKA ILRCKA BICKA SDTOA
LIN2
LIN1
RISEL ROPIN LOPIN LISEL AVSS2 AVDD2 VCOM ROUT2 LOUT2 ROUT2 LOUT2 MUTET HVSS HVDD
AK4683EQ
View
TVDD DVDD MCLK2 SDTIA1 SDTIA2 SDTIA3 MCKO SDTIB DVSS CCLK CDTI
Compatibility with AK4588
Functions DAC, Asynchronous operation HP-Amp Input selector AK4588 Available AK4683 Available
MS0427-E-00
2005/09
[AK4683]
PIN/FUNCTION
Name PVDD VOUT CDTO LRCKB BICKB SDTOB OLRCKA ILRCKA BICKA SDTOA MCKO TVDD DVSS DVDD MCLK2 CDTI CCLK TEST SDTIA1 SDTIA2 SDTIA3 SDTIB HVDD HVSS MUTET Function Power supply Pin, 4.5V5.5V Receiver Channel (Internal biased pin. Internally biased PVDD/2) Control Mode Select Pin. "L": 4-wire Serial, "H": Receiver Channel Receiver Channel Receiver Channel Interrupt V-bit Output Receiver Input Zero Input Detect When input data follow total 8192 LRCK cycles with input data, this goes "H". when RSTN1 "0", PWDA "0", this goes "H". Analog Input Overflow Detect This goes analog input overflows. Control Data Output Serial Mode "L". Channel Clock Audio Serial Data Clock Audio Serial Data Output Output Channel Clock Input Channel Clock Audio Serial Data Clock Audio Serial Data Output Master Clock Output Output Buffer Power Supply Pin, 2.7V5.5V Digital Ground Pin, Digital Power Supply Pin, 4.5V5.5V X'tal Input X'tal Output Transmit Channel Output When "0", RX0~3 Through. When "1", Internal Output. Master Clock Input Power-Down Mode Reset When "L", AK4683 powered-down, registers reset. then digital output pins "L". AK4683 must reset once upon power-up. Control Data Input Serial Mode "L". Control Data Serial Mode "H". Control Data Clock Serial Mode Control Data Clock Serial Mode Chip Select Serial Mode "L". This should connected DVSS Serial Mode "H". Audio Serial Data Input Audio Serial Data Input Audio Serial Data Input Audio Serial Data Input Power Supply Pin, 4.5V5.5V Ground Pin, Output Output Common Voltage Output capacitor should connected HVSS externally.
MS0427-E-00
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[AK4683]
Name LOUT2 ROUT2 LOUT1 ROUT1 VCOM AVDD2 AVSS2 LISEL LOPIN ROPIN RISEL AVSS1 AVDD1 LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 LIN4 RIN4 LIN5 RIN5 LIN6 RIN6 PVSS
Function DAC2 Positive Analog Output DAC2 Positive Analog Output DAC1 Positive Analog Output DAC1 Positive Analog Output DAC/ADC Common Voltage Output 2.2µF capacitor should connected AVSS2 externally. Power Supply Pin, 4.5V5.5V Ground Pin, Feedback Resistor Output Feedback Resistor Input Pin. AVDD1. Feedback Resistor Input Pin. AVDD1. Feedback Resistor Output Ground Pin, Power Supply Pin, 4.5V5.5V Input Input Input Input Input Input Input Input Input Input Input Input Ground External Resistor +/-1% resistor should connected PVSS externally.
Note: input pins except internal biased (RX0) analog input pins (LIN1-6, RIN1-6) should left floating.
Handling Unused
unused pins should processed appropriately below. Classification Analog Name RX0, LOUT1-2, ROUT1-2, LIN1-6, RIN1-6 INT, XTO, MCKO, VOUT/DZF/OVF, SDTOA-B, CDTO, RX1-3, CSN, CCLK, CDTI, XTI, MCLK2, OLRCKA, ILRCKA, BICKA, SDTIA1-3, LRCKB, BICKB, SDTIB Setting These pins should open. These pins should open. These pins should connected DVSS.
Digital
MS0427-E-00
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[AK4683]
ABSOLUTE MAXIMUM RATINGS (AVSS1, AVSS2, DVSS, PVSS, HVSS=0V; Note Parameter Symbol -0.3 Power Supplies Analog AVDD1 -0.3 Analog AVDD2 -0.3 Headphone Analog HVDD -0.3 Digital DVDD -0.3 PVDD -0.3 Output buffer TVDD |AVSS2-AVSS1| (Note GND1 |AVSS2-DVSS| (Note GND2 |AVSS2-PVSS| (Note GND3 |AVSS2-HVSS| (Note GND4
Input Current (any pins except supplies) Analog Input Voltage (LIN, pins) Digital Input Voltage Except ILRCKA, OLRCKA, LRCKB, BICKA-B, RX0, pins ILRCKA, OLRCKA, LRCKB, BICKA-B pins RX0, I2Cpins Ambient Temperature (power applied) Storage Temperature VINA VIND1 VIND2 VIND3 Tstg -0.3 -0.3 -0.3 -0.3
AVDD1+0.3 DVDD+0.3 TVDD+0.3 PVDD+0.3
Units
Notes: voltages with respect ground. 2.AVSS, DVSS PVSS must connected same analog ground plane. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, PVSS=0V; Note Parameter Symbol AVDD1 Power Supplies Analog AVDD2 (Note Analog AVDD2 HVDD Headphone Analog DVDD Digital PVDD TVDD Output buffer -0.3 |DVDD AVDD1| VDD1 -0.3 |DVDD AVDD2| VDD2 -0.3 |DVDD HVDD| VDD3 -0.3 |DVDD PVDD| VDD4 -0.1 |AVDD1 AVDD2| VDD5
DVDD +0.3 +0.3 +0.3 +0.3 +0.1
Units
Notes: voltages with respect ground. power sequences among AVDD1, AVDD2, DVDD, PVDD, HVDD TVDD critical. WARNING: assumes responsibility usage beyond conditions this datasheet.
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[AK4683]
ANALOG CHARACTERISTICS (Ta=25°C; AVDD1, AVDD2, HVDD, DVDD, PVDD, TVDD=5V; AVSS1, AVSS2, HVSS, DVSS, PVSS=0V; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz20kHz fs=48kHz, 20Hz~40kHz fs=96kHz; 20Hz~40kHz fs=192kHz, blocks synchronized, unless otherwise specified) Parameter Units Pre-Amp Characteristics: Feedback Resistance S/(N+D) (Note (A-weighted) (Note Load Capacitance Analog Input Characteristics (note Resolution Bits S/(N+D) (-0.5dBFS) fs=48kHz fs=96kHz (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted (Note fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted Interchannel Isolation (Note Interchannel Gain Mismatch Gain Drift ppm/°C Input Voltage (note AIN=1.22xAVDD1 Power Supply Rejection (Note Analog Output Characteristics Resolution Bits S/(N+D) fs=48kHz fs=96kHz fs=192kHz (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted fs=192kHz fs=192kHz, A-weighted (Note fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted fs=192kHz fs=192kHz, A-weighted Interchannel Isolation Interchannel Gain Mismatch Gain Drift ppm/°C Output Voltage AOUT=0.6xAVDD2 2.75 3.25 Load Resistance Load) Load Capacitance Power Supply Rejection (Note
MS0427-E-00
2005/09
[AK4683]
Analog Volume Characteristics (OPGA): Step Size: +0dB -16dB -16dB -38dB -38dB -50dB Headphone-Amp Characteristics: HPL/HPR pins, RL=16 Output Voltage (0.506xHVDD) 1.94 S/(N+D) (-3dBFS) (A-weighted) Interchannel Isolation Interchannel Gain Mismatch Load Resistance Figure Load Capacitance Figure Power Supplies Power Supply Current Normal Operation (PDN "H") (Note AVDD1+ AVDD2 fs=48kHz, fs=96kHz fs=192kHz HVDD PVDD DVDD+TVDD fs=48kHz (Note fs=96kHz fs=192kHz Power-down mode (PDN "L") (Note
HP-Amp
2.43
2.92
dBFS
HPL,
Figure Headphone Amplifier output circuit Notes: Measured LISEL/RISEL pins when input resistor=47kohm, feedback resistor=24kohm input level =2Vrms. Measured through Pre-Amp ADC. Input resistor=47kohm, feedback resistor=24kohm. measured CCIR-ARM 96dB(@fs=48kHz). This value interchannel isolation between channels LIN1-6 RIN1-6. applied AVDD, DVDD, PVDD TVDD with 1kHz, 50mVpp. measured CCIR-ARM 102dB(@fs=48kHz). CL=20pF, X'tal=24.576MHz, CM1-0="10", CM1-0="10", OCKS1-0="10"@48kHz,"00"@96kHz, "11"@192kHz. Headphone output. resister network attached pin. TVDD=6mA(typ@fs=48kHz), 7mA(typ@fs=96kHz), 10mA(typ@fs=192kHz). power-down mode. input open digital input pins including clock pins (MCLK2, BICKA, BICKB, ILRCKA, OLRCKA, BICKB pins) RX1-3 pins held DVSS.
MS0427-E-00
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[AK4683]
FILTER CHARACTERISTICS (Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.55.5V; TVDD=2.75.5V; fs=48kHz) Parameter Symbol Digital Filter (Decimation LPF): 18.9 Passband ±0.1dB 20.0 (Note -0.2dB 23.0 -3.0dB Stopband 28.0 Passband Ripple ±0.04 Stopband Attenuation Group Delay (Note Group Delay Distortion Digital Filter (HPF): Frequency Response (Note -3dB -0.1dB Digital Filter: Passband (Note -0.1dB 21.8 -6.0dB 24.0 Stopband 26.2 Passband Ripple ±0.02 Stopband Attenuation Group Delay (Note Digital Filter Analog Filter: ±0.2 Frequency Response: 20.0kHz 40.0kHz (Note ±0.3 80.0kHz (Note ±1.0
Units 1/fs 1/fs
Notes: passband stopband frequencies scale with example, 21.8kHz -0.1dB 0.454 (DAC). reference frequency these responses 1kHz. calculating delay time which occurred digital filtering. This time from setting input analog signal setting 24bit data both channels output register PORTA PORTB. DAC, this time from setting 20/24bit data both channels input register PORTA PORTB output analog signal. 40kHz@fs=96kHz, 80kHz@fs=192kHz
MS0427-E-00
2005/09
[AK4683]
CHARACTERISTICS (Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.55.5V; TVDD=2.75.5V) Parameter Symbol High-Level Input Voltage (Except pin) (XTI pin) 70%DVDD Low-Level Input Voltage (Except pin) (XTI pin) Input Voltage Coupling (XTI pin) (Note 40%DVDD High-Level Output Voltage (Except pins: Iout=-400µA) TVDD-0.4 pin: Iout=-400µA) DVDD-0.4 Low-Level Output Voltage (Iout=400µA) Input Leakage Current (Except pin) Notes: case connecting capacitance pin. S/PDIF RECEIVER CHARACTERISTICS (RX0) (Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.55.5V; TVDD=2.75.5V) Parameter Symbol Input Resistance Input Voltage (internally biased PVDD/2) Input Hysteresis Input Sample Frequency PVDD 20k(typ) 20k(typ) PVSS VCOM
30%DVDD
Units
Units mVpp
Internal biased Circuit
S/PDIF RECEIVER CHARACTERISTICS (RX1-3) (Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.5~5.5V;TVDD=2.7~5.5V) Parameter Symbol High-Level Input Voltage Low-Level Input Voltage Input Sample Frequency Input Leakage Current
Units
MS0427-E-00
2005/09
[AK4683]
SWITCHING CHARACTERISTICS (Ta=25°C; AVDD1, AVDD2, DVDD, PVDD, HVDD=4.55.5V; TVDD=2.75.5V; CL=20pF; Note Parameter Symbol Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 External Clock Frequency fECLK 4.096 24.576 Duty dECLK 24.576 4.096 fMCK MCKO Output Frequency dMCLK Duty (Note dMCK (Note Clock Recover Frequency (RX0-3) fpll Master Clock 12.288 8.192 fCLK 256fsn, 128fsd: tCLKL Pulse Width tCLKH Pulse Width High 18.432 12.288 fCLK 384fsn, 192fsd: tCLKL Pulse Width tCLKH Pulse Width High 24.576 16.384 fCLK 512fsn, 256fsd, 128fsq: tCLKL Pulse Width tCLKH Pulse Width High
LRCKA (LRCKB) Timing (Slave Mode) Normal mode Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle mode LRCKA frequency time time mode LRCKA frequency time time LRCKA (LRCKB) Timing (Master Mode) Normal mode Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle mode LRCKA frequency time (Note mode LRCKA frequency time (Note Power-down Reset Timing Pulse Width (Note SDTO valid (Note
Units
Duty tLRH tLRL tLRH tLRL
1/256fs 1/256fs 1/128fs 1/128fs
Duty tLRH tLRH tPDV
1/8fs 1/4fs
1/fs
Notes: SDTOA specified against OLRCKA, SDTIA1-3 measured against ILRCKA. When MCKO1-0 bits "01", "10" MCKO1-0 bits "00" CKSDT "0". When MCKO1-0 bits "00" CKSDT EXTCLK selected CM1-0 bits. Duty ("H" width) (clock cycle) time format AK4683 reset bringing upon power-up. These cycles number LRCKA (LRCKB) rising from rising. MS0427-E-00 2005/09
[AK4683]
Parameter Audio Interface Timing (Slave Mode) Normal mode BICKA (BICKB) Period BICKA (BICKB) Pulse Width Pulse Width High LRCKA (LRCKB) Edge BICKA (BICKB) (Note BICKA (BICKB) LRCKA (LRCKB) Edge (Note LRCKA (LRCKB) SDTOA, SDTOB (MSB) BICKA (BICKB) SDTOA, SDTOB SDTIA1-3, SDTIB Hold Time SDTIA1-3, SDTIB Setup Time mode BICKA Period BICKA Pulse Width Pulse Width High LRCKA Edge BICKA (Note BICKA LRCKA Edge (Note BICKA SDTOA SDTIA1 Hold Time SDTIA1 Setup Time mode BICKA Period BICKA Pulse Width Pulse Width High LRCKA Edge BICKA (Note BICKA LRCKA Edge (Note BICKA SDTOA SDTIA1-2 Hold Time SDTIA1-2 Setup Time Audio Interface Timing (Master Mode) Normal mode BICKA (BICKB) Frequency BICKA (BICKB) Duty BICKA (BICKB) LRCKA (LRCKB) Edge BICKA (BICKB)"" SDTO SDTIA1-3, Hold Time SDTIA1-3, Setup Time mode BICKA Frequency BICKA Duty (Note BICKA LRCKA Edge BICKA SDTOA SDTIA1 Hold Time SDTIA1 Setup Time mode BICKA Frequency BICKA Duty (Note BICKA LRCKA Edge BICKA SDTOA SDTIA1-2 Hold Time SDTIA1-2 Setup Time
Symbol
Units
tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS
fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS fBCK dBCK tMBLR tBSD tSDH tSDS
64fs 256fs 128fs
Notes: BICK rising edge must occur same time LRCK edge. When MCLK2/XTI 512fs, dBCK guaranteed. When 384fs 256fs, dBCK guaranteed. When MCLK2/XTI 256fs, dBCK guaranteed. When 128fs, dBCK guaranteed.
MS0427-E-00
2005/09
[AK4683]
Parameter Control Interface Timing (4-wire serial mode) CCLK Period CCLK Pulse Width Pulse Width High CDTI Setup Time CDTI Hold Time Time CCLK CCLK CDTO Delay CDTO Hi-Z Control Interface Timing (I2C mode) Clock Frequency Free Time Between Transmissions Start Condition Hold Time (prior first clock pulse) Clock Time Clock High Time Setup Time Repeated Start Condition Hold Time from Falling (Note Setup Time from Rising Rise Time Both Lines Fall Time Both Lines Setup Time Stop Condition Pulse Width Spike Noise Suppressed Input Filter Capacitive load
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO
Units
0.25
Notes: Data must held sufficient time bridge transition time SCL. registered trademark Philips Semiconductors.
MS0427-E-00
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[AK4683]
Timing Diagram
1/fCLK tCLKH tCLKL
MCLK
1/fsn, 1/fsd, 1/fsq
LRCK
tBCK tBCKH tBCKL
BICK
Clock Timing (Normal mode)
1/fCLK tCLKH tCLKL
MCLK
1/fsn, 1/fsd tLRH tLRL
LRCK
tBCK tBCKH tBCKL
BICK
Clock Timing (TDM mode, mode) LRCK= LRCKB, ILRCKA, OLRCKA, BICK= BICKA, BICKB, SDTI= SDTIA, SDTIB, SDTO= SDTOA, SDTOB.
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[AK4683]
LRCK tBLR tLRB
BICK
tLRS tBSD
SDTO tSDS
50%TVDD
tSDH
SDTI
Audio Interface Timing (Normal mode)
LRCK tBLR tLRB
BICK
tBSD
SDTO tSDS
50%TVDD
tSDH
SDTI
Audio Interface Timing (TDM mode, mode)
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[AK4683]
LRCK
50%TVDD
tMBLR BICK 50%TVDD
tBSD 50%TVDD
SDTO tDXS tDXH
SDTI
Audio Interface timing (Master Mode)
Power Down Reset Timing
MS0427-E-00
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[AK4683]
tCSS tCCK tCCKL tCCKH CCLK tCDH tCDS
CDTI
CDTO
Hi-Z
WRITE/READ Command Input Timing 4-wire serial mode ADC/DAC part doesn't support READ command.
tCSW tCSH
CCLK
CDTI
CDTO
Hi-Z
WRITE Data Input Timing 4-wire serial mode
CCLK
CDTI
tDCD
CDTO
Hi-Z
50%TVDD
READ Data Output Timing 4-wire serial mode ADC/DAC part doesn't support READ command.
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[AK4683]
tCSW tCSH CCLK
CDTI
tCCZ
CDTO
Hi-Z
50%TVDD
READ Data Input Timing 4-wire serial mode ADC/DAC part doesn't support READ command.
tBUF tLOW tHIGH tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
mode Timing ADC/DAC part doesn't support READ command.
tPDV
SDTO
50%TVDD
Power-down Reset Timing
MS0427-E-00
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[AK4683]
OPERATION OVERVIEW (General) Device Configuration System Clocks
AK4683 integrates stereo with input selector, with stereo amp, DIT. AK4683 serial audio interfaces (PORTA, input/output dataset (Figure Each block independently select operation clock from three clock sources (recovered clock from (RMCLK), X'tal clock (XTI) external clock (MCLK2)) also input data source/output data destination. using Clock loop-back such AD-DA operate even PORTA/B powered down.
MCLK2 MCKO0/1
MCKO
MCLK2
PORTA
Clock
MCLK2
X'tal Oscillator (XTI)
CLKB0/1 MCLK2 CLKA0/1
PORTB
Clock
MCLK2
MCLK2
MCLK2 CLKL0/1
Clock
Note
MCLK2
Figure System Clock Note: Each block must select same clock source each other when connected. operation will normal when clock sources same among connection. synchronized clock source that connected block uses. Even RMCLK selected, X'tal/MCLK2 chosen setting CM1-0bits. must synchronized when these blocks operates.
MS0427-E-00
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[AK4683]
X'tal Oscillator following circuits available feed clock AK4683. X'tal
25k(typ)
AK4683
Note: External capacitance depends crystal oscillator (Typ. 10-40pF) Figure X'tal mode
External clock Note: Input clock must exceed DVDD.
External Clock
External Clock
25k(typ)
25k(typ)
AK4683
AK4683
(Input: CMOS Level) Figure (5V). (a). External clock mode
(Input: 40%DVDD, C=0.1µF) Figure (3.3V). (b). External clock mode
XTI/XTO used
25k(typ)
AK4683
Figure mode
MS0427-E-00
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[AK4683]
Master Clock Output AK4683 master clock output pin. clock source selected from three clocks (recovered clock from (RMCLK), X'tal clock (XTI) external clock (MCLK2)). When powered-down unlocked state CM1/0 "10", CLKDT selects clock source. OCKS1/0 bits select clock speed. 512fs fs=96kHz, 256fs/512fs fs=192kHz available. UNLOCK Clock Source RMCLK EXTCLK RMCLK EXTCLK EXTCLK
Table Clock Mode Control CLKDT Clock Source MCLK2
Default
Table EXTCLK Control OCKS1 OCKS0 MCLKO(RMCLK) 256fs 256fs 512fs 128fs (max)
Table MCLKO Speed MCKO1 MCKO0 MCKO Clock Source X'tal(XTI) MCLK2 Reserved
default
Table MCKO Clock Source Control
OCKS1/0
RMCLK
EXTCLK x2/3 CKSDT CLKDT CM0/1
X'tal Oscillator (XTI)
MCLK2 MCKO0/1
MCKO
MCLK2
Figure MCKO Clock
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[AK4683]
Master/Slave Mode Change
bits control master/slave mode PORTA PORTB respectively. master mode, slave mode. AK4683 slave mode power-down (PDN "L"). change master mode, write MSA/MSB bit. ACKSAI, ACKSAO ACKSB bits ignored master mode. Until when writing MSA/MSB bit, ILRCKA, OLRCKA, BICKA, LRCKB BICKB input pins. Pull-up(or down) resistor with around 100kohm required prevent floating these input pins. MSA, Mode Slave Mode (default) Master Mode Table Select Master/Salve Mode
Other Detection Function
FUNC1-0 selects function VOUT pin. Mode FUNC1 FUNC0 Mode ("L") Overflow Detection Zero Detection output Table Detection Function Control
Default
Overflow Detection
AK4683 overflow detect function analog input. Overflow detect function enable OVFE "1". goes analog input overflows (more than -0.3dBFS). output overflowed analog input same group delay 19/fs 396µs @fs=48kHz). 522/fs (=10.9ms @fs=48kHz) after then overflow detection enabled. overflow detection applied data between digital DATT.
Zero Detection
AK4683 zero detect flag output. DZFM1-0 bits select channel grouping (Table goes when enabled channels continuously zeros 8192 LRCK cycles. immediately goes input data enabled channel zero after going "H". Mode DZFM1 DZFM0 AOUT Enable Enable Enable Enable
Enable Enable
Enable Enable
(default)
Table Zero Detection Control
Validity Detection
AK4683 Validity Detection function. decodes output pin. When unlocked, output.
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[AK4683]
OPERATION OVERVIEW (ADC/DAC/PORTA, part) System Clock
AK4683 audio serial interface (PORTA, operate these PORTs with asynchronous. each PORT, external clocks, which required operate AK4683, MCLK, LRCK BICK. MCLK should synchronized with LRCK phase critical. CLKA1-0, CLKB1-0bits select clock sources each PORT (Table Table bits select master/slave mode (Table Table 17). block that connected PORTA/B block that connected PORT indirectly operate same clock PORTA/B selects. When selects data while PORTB selects data also, operates same clock PORTB selects. block that isn't connected PORTA/B automatically connected Clock operates same clock Clock selects with CLKL1-0 bits (Table 10). master mode, CKSIA2-0, OLRA1-0, BICKAF, CKSB2-0 bits select clock frequency (Table Table Table Table 14). master mode, external clock (MCLK) should always supplied except power-down mode. AK4683 power-down mode until MCLK will supplied, when reset canceled Power-ON PORTA, input/output data independent LRCK (ILRCKA/OLRCKA) common BICK (BICKA). ILRCK OLRCK operate different sample rate synchronized each other (Table 12). slave mode, external clocks (MCLK, BICK, LRCK) should always present whenever AK4683 normal operation mode (PDN "H"). master clock (MCLK) should synchronized with LRCK phase critical. these clocks provided, AK4683 draw excess current because device utilizes dynamic refreshed logic internally. external clocks present, AK4683 should power-down mode (PDN "L") reset mode (RSTN1 "0"). After exiting reset power-up etc., AK4683 power-down mode until MCLK LRCK input. When block selects RMCLK clock source, sample rate PORT master mode ADC/DAC connecting Clock forced same rate DIR. DFSAD, DFSDA1-0 bits should controlled properly.
MS0427-E-00
2005/09
[AK4683]
CLKA1
CLKA0
PORTA Clock Source X'tal(XTI) MCLK2 Reserved
default)
Table PORTA Clock Source Control
CLKB1
CLKB0
PORTB Clock Source X'tal(XTI) MCLK2 Reserved
default)
Table PORTB Clock Source Control
CLKL1
CLKL0
Clock Clock Source X'tal (XTI) MCLK2 Reserved
(default)
Table Clock Clock Source Control
CKSAI2
CKSAI1
CKSAI0
Clock Speed 128fs 192fs 256fs 384fs 512fs Reserved Reserved Reserved
(default)
Table PORTA Input Data Clock Control (Master Mode)
OLRA1 OLRA0 OLRCKA Clock Freq ILRCKA ILRCKA ILRCKA Reserved Note: Select OLRA1-0 bits "00" mode. Table OLRCKA Clock Mode Control
(default)
MS0427-E-00
2005/09
[AK4683]
BCAF PORTA BICK Frequency Mode ILRCK (default) ILRCK x128 Note: ILRCK available when MCLK=ILRCK higher. BCAF ignored mode. Table PORTA BICK Control (Master Mode) CKSB2 CKSB1 CKSB0 Clock Speed 128fs 192fs 256fs 384fs 512fs Reserved Reserved Reserved
(default)
Table PORTB Data Clock Control (Master Mode)
CKSL2
CKSL1
CKSL0
Clock Speed 128fs 192fs 256fs 384fs 512fs Reserved Reserved Reserved
(default)
Table Clock Clock Control
master mode, LRCKA (LRCKB) pin, BICKA (BICKB) output pins. slave mode, these input pins (Table 18). PORTA Master/Slave Mode Slave Master Table PORTA Master/Slave Control
(default)
PORTB Master/Slave Mode Slave Master Table PORTB Master/Slave Control
(default)
MS0427-E-00
2005/09
[AK4683]
LRCKA BICKA (LRCKB) (BICKB) Slave Input Input Slave Input Input Master output output Slave Input Input Master Output Output (*): These input pins, input signals ignored internally. Table LRCKA (LRCKB) pin, BICKA (BICKB)
PWPOA(PWPOB)
Master/Slave
SDTOB1-0, SDTOA1-0 bits select output data source each PORT. SDTOB1 SDTOB0 SDTOB Source SDTIA1 (default)
Table SDTOB Source Control
SDTOA1
SDTOA0
SDTOA Source SDTIB (default)
Table SDTOA Source Control
MS0427-E-00
2005/09
[AK4683]
ADC, Control
There modes controlling sampling speed DAC. Manual Setting Mode using DFSAD1-0, DFSDA1-0 bits, other Auto Setting Mode. When block connects both PORTA PORTB, PORTA setting used. Manual Setting Mode When connected each PORT placed Manual Setting Mode, sampling speed selected DFSAD, DFSDA1-0 bits (Table Table 22). frequencies duties clocks (ILRCKA, OLRCKA, LRCKB, BICKA, BICKB) unstable moment when changing sampling speed mode. DFSAD0 Sampling Speed (fs) Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz
Default
Table 21.ADC sampling speed (Manual Setting Mode)
DFSDA1
DFSDA0
Sampling Speed (fs) Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz Quad Speed Mode 120kHz~192kHz Available
Default
Table 22.DAC sampling speed (Manual Setting Mode)
LRCKA (LRCKB) 32.0kHz 44.1kHz 48.0kHz
MCLK (MHz) 256fs 384fs 512fs 8.1920 12.2880 16.3840 11.2896 16.9344 22.5792 12.2880 18.4320 24.5760 (Normal Speed Mode @Manual Setting Mode) Table system clock example
BICKA (BICKB) (MHz) 64fs 2.0480 2.8224 3.0720
128fs 192fs 256fs 11.2896 16.9344 22.5792 12.2880 18.4320 24.5760 (Double Speed Mode @Manual Setting Mode) (Note: available 128fs 192fs Double Speed Mode (DFSAD="1")) Table system clock example
LRCKA (LRCKB) 88.2kHz 96.0kHz
MCLK (MHz)
BICKA (BICKB) (MHz) 64fs 5.6448 6.1440
MS0427-E-00
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[AK4683]
LRCKA (LRCKB) 176.4kHz 192.0kHz
MCLK (MHz)
128fs 192fs 256fs 22.5792 24.5760 (Quad Speed Mode @Manual Setting Mode) (Note: available Quad Speed Mode) Table system clock example
BICKA (BICKB) (MHz) 64fs 11.2896 12.2880
Auto Setting Mode (ACSKAD/ACSKDA "1") When DACs connected each PORT placed Auto Setting Mode, MCLK frequency detected automatically (Table internal master clock appropriate frequency (Table 27). this mode, setting DFSAD, DFSDA1-0 bits ignored.
MCLK 512fs 256fs 128fs
Sampling Speed Normal Double Quad
Table Sampling Speed (Auto Setting Mode) LRCKA (LRCKB) 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz MCLK (MHz) 128fs 22.5792 24.5760 256fs 22.5792 24.5760 512fs 16.3840 22.5792 24.5760 Sampling Speed Normal Double Quad
Table System clock example (Auto Setting Mode)
MS0427-E-00
2005/09
[AK4683]
DAC12-10, DAC22-20 bits select output data each DAC. DAC1 DAC2 must connected same PORT. DAC12 DAC11 DAC10 DAC1 Source SDTIA1 (default) SDTIA2 SDTIA3 Reserved Reserved
Table DAC1 Source Control
DAC22
DAC21
DAC20
DAC2 Source SDTIA1 SDTIA2 (default) SDTIA3 Reserved Reserved
Table DAC2 Source Control
MS0427-E-00
2005/09
[AK4683]
De-emphasis Filter
AK4683 includes digital de-emphasis filter (tc=50/15µs) filter. De-emphasis filter available Double Speed Mode Quad Speed Mode. This filter corresponds three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis each individually register. Mode Sampling Speed Normal Speed Normal Speed Normal Speed Normal Speed DEM1 DEM0 44.1kHz 48kHz 32kHz
Default
Table De-emphasis control
Digital High Pass Filter
digital high pass filter offset cancel. cut-off frequency 1.0Hz fs=48kHz scales with sampling rate (fs).
Audio Serial Interface Format
Each PORTA/B select independent audio interface format. TDMA1-0, DIFA1-0 bits control audio format PORTA support normal mode, TDM256 mode TDM128 mode. DIFB1-0 bits control audio format PORTB support only normal mode. default mode modes serial data MSB-first, complement format. SDTO pins clocked falling edge BICK pins SDTI pins latched rising edge BICK pins. Setting PORTA 1-1. Normal mode: TDMA1-0 "00" TDMA1-0 bits "00" AK4683 audio serial interface format normal mode. DIFB1-0 bits select following eight serial data format (Table 31). Mode Master /slave LRCKA BICKA Slave 24bit, 20bit, 48fs Slave 24bit, 24bit, 48fs Slave 24bit, 24bit, 48fs Slave 24bit, 24bit, 48fs Master 24bit, 20bit, 64fs Master 24bit, 24bit, 64fs Master 24bit, 24bit, 64fs Master 24bit, 24bit, 64fs Table Audio Interface Format (Normal mode, Left justified, Right justified.) DIFA1 DIFA0 SDTOA SDTIA1-3
default
MS0427-E-00
2005/09
[AK4683]
1-2. mode: TDMA1-0 "01" TDMA1-0 bits "01" AK4683 audio serial interface format mode. serial data SDTIA (1,2,3) input SDTIA1 pin. input data SDTIA2-3 pins ignored. BICKA should fixed 256fs. time time I/OLRCKA should 1/256fs least. DIFA1-0 bits select eight modes. Mode LRCKA BICKA Master DIFA1 DIFA0 SDTOA SDTIA1-3 /slave Slave 24bit, 20bit, 256fs Slave 24bit, 24bit, 256fs Slave 24bit, 24bit, 256fs Slave 24bit, 24bit, 256fs Master 24bit, 20bit, 256fs 256fs Master 24bit, 24bit, Master 24bit, 24bit, 256fs Master 24bit, 24bit, 256fs Table Audio Interface Format (TDM mode, Left justified, Right justified.)
default
1-3. mode: TDMA1-0 "11" TDMA1-0 bits "11" AK4683 audio serial interface format 1286 mode. four channel serial data (SDTIA1, input SDTIA1 pin. Other channel data (SDTIA3) input SDTIA2 pin. Mode LRCKA BICKA Master DIFA1 DIFA0 SDTOA SDTIA1-3 /slave Slave 24bit, 20bit, 128fs Slave 24bit, 24bit, 128fs Slave 24bit, 24bit, 128fs Slave 24bit, 24bit, 128fs Master 24bit, 20bit, 128fs Master 24bit, 24bit, 128fs Master 24bit, 24bit, 128fs Master 24bit, 24bit, 128fs Table Audio Interface Format (TDM mode, Left justified, Right justified.)
default
Setting PORTB 2-1: Normal mode: PORTB supports only normal mode. DIFB1-0 bits select following eight serial data format (Table 34). Mode Master /slave LRCKB BICKB Slave 24bit, 20bit, 48fs Slave 24bit, 24bit, 48fs Slave 24bit, 24bit, 48fs Slave 24bit, 24bit, 48fs Master 24bit, 20bit, 64fs Master 24bit, 24bit, 64fs Master 24bit, 24bit, 64fs Master 24bit, 24bit, 64fs Table Audio Interface Format (Normal mode, Left justified, Right justified.) DIFB1 DIFB0 SDTOB SDTIB
default
MS0427-E-00
2005/09
[AK4683]
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care
Don't Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Data
Data
Figure Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care 23:MSB, 0:LSB
Don't Care
Data
Data
Figure Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care
Don't Care
23:MSB, 0:LSB
Data
Data
Figure 10.Mode Timing
LRCK
BICK(64fs) SDTO(o) SDTI(i)
Don't Care
Don't Care
23:MSB, 0:LSB
Data
Data
Figure Mode Timing
MS0427-E-00
2005/09
[AK4683]
LRCKA LRCKA BICKA(256fs) SDTOA(o)
SDTIA1(i)
BICK
BICK BICK
Figure Mode Timing
LRCKA LRCKA BICKA(256fs) SDTOA(o)
SDTIA1(i)
BICK
BICK BICK
Figure Mode Timing
LRCKA LRCKA BICKA(256fs) SDTOA(o)
SDTIA1(i)
BICK
BICK BICK
Figure Mode Timinig
LRCKA LRCKA BICKA(256fs) SDTOA(o)
SDTIA1(i)
BICK
BICK BICK
Figure Mode Timing
MS0427-E-00
2005/09
[AK4683]
LRCKA LRCKA BICKA(128fs) SDTOA(o)
BICK
SDTIA1(i)
BICK
BICK
BICK
SDTIA2(i)
BICK
BICK
Figure Mode Timing
LRCKA LRCKA BICKA(128fs)
BICK
SDTIA1(i)
BICK
BICK
BICK
SDTIA2(i)
BICK
BICK
Figure Mode TIming
LRCKA LRCKA BICKA(128fs) SDTOA(o)
BICK
SDTIA1(i)
BICK
BICK
BICK
SDTIA2(i)
BICK
BICK BICK
Figure Mode Timing
MS0427-E-00
2005/09
[AK4683]
LRCKA LRCKA BICKA(128fs) SDTOA(o)
BICK
SDTIA1(i)
BICK
BICK
BICK
SDTIA2(i)
BICK
BICK
Figure Mode Timing
MS0427-E-00
2005/09
[AK4683]
Digital Volume Control
AK4683 channel-independent digital volume control (256 levels, 0.5dB step). ATTAD7-0 volume level each channel (Table 35), ATTDA7-0 each channel (Table 36). ATTAD7-0 Attenuation Level +24dB +23.5dB +22.0dB +0.5dB -0.5dB -103dB MUTE
(default)
Table 35.ADC Digital Volume
ATTDA7-0
Attenuation Level +12dB +11.5dB +11.0dB +0.5dB -0.5dB -115dB MUTE
(default)
Table 36.DAC Digital Volume Transition time between values ATTAD7-0 (ATTDA7-0) bits selected ATSAD (ATSDA) bits (Table Table 38). Transition between values soft transition. Therefore, switching noise does occur transition. Mode ATSAD speed 1061/fs 256/fs
(default)
Table Transition time between values ATTAD7-0 bits (ADC)
Mode
ATSDA
speed 1061/fs 256/fs
(default)
Table Transition time between values ATTDA7-0 bits (DAC) transition between values soft transition 1061 levels mode takes 1061/fs (24ms@fs=48kHz) from FFH(MUTE) mode goes "L", ATTAD7-0(ATTDA7-0) bits initialized 30H(18H). ATTs goes their default value when RSTN "0". When RSTN1 return "1", ATTs fade their current value.
MS0427-E-00
2005/09
[AK4683]
Soft mute operation
have soft mute function. soft mute operation performed digital domain. When SMAD/SMDA bits "1", output signal attenuated during transition time (Table from current level. When SMAD/SMDA bits returned "0", mute cancelled output attenuation gradually changes level during transition time. soft mute cancelled before attenuating after starting operation, attenuation discontinued returned level same cycle. soft mute effective changing signal source without stopping signal transmission.
SMAD/SMDA bits
Level Attenuation
AOUT 8192/fs
(for SMDA)
Notes: transition time (Table 16). example, Normal Speed Mode, this time 1061/fs cycles (1792/fs) ATT_DATA=00H. transition soft-mute from analog output corresponding digital input group delay, soft mute cancelled before attenuating after starting operation, attenuation discontinued returned level same cycle. When input data channels group continuously zeros 8192 cycles, each channel goes "H". immediately goes input data either channel group zero after going "H". Figure Soft mute zero detection
MS0427-E-00
2005/09
[AK4683]
Input Selector, Input Attenuator
AK4683 includes stereo input selectors (Figure 21). input selector selector. AIN2-0 bits input channel (Table 39). AIN2 AIN1 AIN0 Input Selector LIN1 RIN1 LIN2 RIN2 LIN3 RIN3 LIN4 RIN4 LIN5 RIN5 LIN5 RIN5 None None
Default
Table Input Selector input ATTs constructed adding input resistor (Ri) LIN1-6/RIN1-6 pins feedback resistor (Rf) between LOPIN (ROPIN) LOUT (ROUT) (Figure 21). voltage range LISEL(RISEL) should less than typ. 0.62 AVDD1 (Vpp). input voltage input selector exceeds typ. 0.62 AVDD, input voltage LISEL(RISEL) pins must attenuated typ. 0.62 AVDD1 (Vpp) input ATTs. Table shows example
Figure Input Input Range LISEL/R 1.02Vrms 4Vrms -11.86 (2.88Vpp) 1.02Vrms 2Vrms -5.84 (2.88Vpp) 1Vrms 1Vrms (2.82Vpp) Note: Input range internal 0.62 AVDD1 (5V) 3.1Vpp typ. Table Input example Gain [dB]
MS0427-E-00
2005/09
[AK4683]
[Input selector switching sequence] input selector should changed after soft mute avoid switching noise input selector (Figure 22). Enable soft mute before changing channel. Change channel. Disable soft mute.
Level Attenuation
hannel
Figure Input channel switching sequence example
period varies setting value DATT. takes 1028/fs mute when DATT value +24dB. When changing channels, input channel should changed during (2). period should around 200ms because there some difference between channels.
MS0427-E-00
2005/09
[AK4683]
Power ON/OFF Sequence
each block AK4683 placed power-down mode bringing both digital filters reset same time. also reset control registers their default values. power-down mode, analog outputs VCOM voltage SDTOA,B, DZF/OVF "L". This reset should always done after power-up. slave mode, after exiting reset power-up etc., AK4683 starts operate from rising edge LRCK after MLCK, then device power-down mode until MCLK LRCK input. slave mode Internal Loop Mode, AK4683 starts operate input MLCK after exiting reset. analog initialization cycle starts after exiting power-down mode. Therefore, output data, SDTO becomes available after 522/fs cycles LRCK clock. case DAC, analog initialization cycle starts after exiting power-down mode. analog outputs VCOM voltage during initialization. Figure hows sequences power-down power-up. DACs powered-down individually PWAD PWDA1-2 bits. These bits don't initialize internal register values. When PWAD selecting ADC, SDTOA(SDTOB) goes "L". When PWDA1-2 bits "0", analog outputs VCOM voltage DZF/OVF "H". Since some click noise occur, analog output should muted externally click noise influences system application.
Power
522/fs
Internal State Internal State (Analog) (Digital) (Digital)
"0"data
Init Cycle 516/fs
Normal Operation
Power-down
Normal Operation Power-down
Init Cycle
"0"data
"0"data
"0"data
(Analog) Clock
MCLK,LRCK,SCLK
Don't care
Don't care 1011/fs (10)
DZF1/DZF2
External Mute
Mute
Mute
Notes: analog part initialized after exiting power-down state. analog part initialized after exiting power-down state. Digital output corresponding analog input analog output corresponding digital input have group delay (GD). output data power-down state. Click noise occurs initialization analog part. Please mute digital output externally click noise influences system application. Click noise occurs falling edge 512/fs(DAC1) 512/fs +96ms(DAC2) after rising edge PDN. When external clocks (MCLK, BICKA (BICKB), LRCKA (LRCKB)) stopped, AK4683 should power-down mode. DZF/OVF power-down mode (PDN "L"). Please mute analog output externally click noise influences system application. (10) 1011/fs after PDN= Figure Power-down/up sequence example MS0427-E-00 2005/09
[AK4683]
Status analog output pins during power-down (PDN ="L")
status analog output pins follows. Name HPL/HPR LOUT1/ROUT1/LOUT2/ROUT2 LISEL/RISEL
HVSS VCOM Hi-Z
Reset Function
When RSTN1 "0", DACs powered-down internal register initialized. analog outputs VCOM voltage, DZF/OVF goes SDTOA/B pins "L". Because some click noise occurs, analog output should muted externally click noise influences system application. Figure shows power-up sequence.
RSTN
4~5/fs 1~2/fs
Internal RSTN
516/fs
Internal State Internal State (Analog) (Digital) (Digital)
Normal Operation
Digital Block Power-down
Init Cycle
Normal Operation
Normal Operation
Digital Block Power-down
Normal Operation
"0"data
"0"data
(Analog) Clock
MCLK,LRCK,SCLK
Don't care
45/fs
DZF1/DZF2
Notes: analog part initialized after exiting reset state. Digital output corresponding analog input analog output corresponding digital input have group delay (GD). output data power-down state. Click noise occurs when internal RSTN becomes "1". Please mute digital output externally click noise influences system application. When RSTN1 "0", analog outputs VCOM voltage. Click noise occurs 45/fs after RSTN1 becomes "0", occurs 12/fs after RSTN1 becomes "1". This noise output even data input. external clocks (MCLK, BICKA (BICKB), LRCKA (LRCKB)) stopped reset mode. When exiting reset mode, should written RSTN1 after external clocks (MCLK, BICKA (BICKB), LRCKA (LRCKB)) fed. pins when RSTN1 becomes "0", 6~7/fs after RSTN1 becomes "1". There delay, 4~5/fs from RSTN1 internal RSTN "0". Figure Reset sequence example MS0427-E-00 2005/09
[AK4683]
Headphone Output
Power supply voltage Headphone-Amp supplied from HVDD centered HVDD/2 voltage. When MUTEN "0", common voltage Headphone-Amp falls outputs (HPL pins) (HVSS). When MUTEN "1", common voltage rises HVDD/2. capacitor between MUTET ground reduces click noise power-up. Rise/Fall time constant proportional HVDD voltage capacitor MUTET pin. [Example]: capacitor between MUTET ground 1.0µF, HVDD=5V: Rise/fall time constant: 120ms(typ) When PWPD "0", Headphone-Amp powered-down, outputs (HPL pins) (HVSS).
PWHP
MUTEN pin,
Figure Power-up/Power-down Timing Headphone-Amp Headphone-Amp power-up (PWHP "1"). outputs still HVSS. Headphone-Amp common voltage rises (MUTEN "1"). Common voltage Headphone-Amp rising.
Start audio output after finishing setup common voltage prevent clipping.
Headphone-Amp common voltage falls down (MUTEN "0"). Common voltage Headphone-Amp falling. Headphone-Amp power-down (PWHP "0"). outputs HVSS. power supply switched Headphone-Amp powered-down before common voltage goes HVSS, some CLICK noise occurs. cut-off frequency (fc) Headphone-Amp depends external resistor capacitor. Table shows frequency output power various resistor/capacitor combinations. headphone impedance Output powers shown HVDD
HP-AMP
Headphone
AK4683
Figure External Circuit Example Headphone [µF] [Hz] Table External Circuit Example Output Power [mW]@0dBFS 12.5
MS0427-E-00
2005/09
[AK4683]
Output Analog Volume (OPGA)
Volume range output analog volume -50dB MUTE with zero crossing detection. OPGA operates with clock DAC. zero crossing detection worked independently. there zero-crossings, level will then change after timeout period (Table 10); timeout period scales with When "0", changed immediately without zero crossing detection. When writing OPGA4-0 bits continually, should take interval zero crossing timeout period more. OPGA4-0 bits changed before zero crossing. OPGA4-0 GAIN(dB) MUTE STEP LEVEL
(default)
Table Output Analog Volume Setting
When "1", Lch/Rch volume level changed independently zero crossing detection zero crossing timeout operation. count timer doubled when double speed mode, four times when quad speed mode. DAC2 Sampling Speed Normal Speed Mode Double Speed Mode Quad Speed Mode Zero crossing timeout 768/fs (16ms @fs=48kHz) 1536/fs (16ms @fs=96kHz) 3072/fs (16ms @fs=192kHz)
Table Zero crossing timeout OPGA enable PWDA PWDA2 "1". initializing OPGA starts when powered This initializing cycle 96ms(@fs=48kHz). Writing OPGA4-0 during initialization ignored. default volume value mute after power Initialization time 512/fs+96ms(@fs=48kHz) after "H". DAC2 Sampling Speed Normal Speed Mode Double Speed Mode Quad Speed Mode OPGA Initialization Time 4608/fs (96ms @fs=48kHz) 9216/fs (96ms @fs=96kHz) 18432/fs (96ms @fs=192kHz)
Table OPGA Initialization Time
MS0427-E-00
2005/09
[AK4683]
OPERATION OVERVIEW (DIR/DIT part)
192kHz Clock Recovery chip jitter wide lock range with 32kHz 192kHz lock time less than 20ms. AK4683 sampling frequency detect function. either clock comparison against X'tal oscillator using channel status, AK4683 detects sampling frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz 192kHz). loses lock when received sync interval incorrect.
Clock Operation Mode When selected. CM0/CM1 bits select clock source data source SDTO. Mode clock source automatically switched from XTI/MCLK2 when goes unlock state. Mode clock source fixed XTI/MCLK2, also operating recovered data such bits monitored. Mode recommended that frequency XTI/MCLK2 different from recovered frequency from PLL. Mode UNLOCK Clock source SDTO EXTCLK source EXTCLK source EXTCLK source Oscillation (Power-up), OFF: STOP (Power-down) Table Clock Operation Mode select
(default)
When 384fs XTI/MCLK2 supplied DIR/DIT, CKSDT should "1". CKSDT Clock Speed Table XTI/MCLK2 speed
(default)
MS0427-E-00
2005/09
ASAHI KASEI Sampling Frequency Pre-emphasis Detection AK4683 methods detecting sampling frequency follows. Clock comparison between recovered clock XTI/MCLK2 Sampling frequency information channel status Those could selected XTL1, bits. detected frequency reported FS3-0 bits. XTL1 XTL0 XTI/MCLK2 Frequency 11.2896MHz 12.288MHz 24.576MHz (Use channel status)
[AK4683]
default
Table Reference XTI/MCLK2 frequency XTL1,0= "1,1" Consumer Register output Professional mode mode Clock comparison (Note (Note Byte3 Byte0 Byte4 Bit3,2,1,0 Bit7,6 Bit6,5,4,3 44.1kHz 44.1kHz 0000 0000 Reserved Reserved 0001 (Others) 48kHz 48kHz 0010 0000 32kHz 32kHz 0011 0000 88.2kHz 88.2kHz (1000) 1010 96kHz 96kHz (1010) 0010 176.4kHz 176.4kHz (1100) 1011 192kHz 192kHz (1110) 0011 Note1: least range identified value Table case intermediate frequency those two, FS3-0 bits indicate nearer value. When frequency much bigger than 192kHz much smaller than 32kHz, FS3-0 bits indicate "0001". Note2: When consumer mode, Byte3 Bit3-0 copied FS3-0 bits. Table Information Except XTL1,0= "1,1"
pre-emphasis information detected reported bit. These information extracted from channel default. switched channel CS12 control register. Pre-emphasis Byte Bits 0X100 0X100
Table Consumer Mode Pre-emphasis Byte Bits
Table Professional Mode
MS0427-E-00
2005/09
ASAHI KASEI De-emphasis Filter Control
[AK4683]
AK4683 includes digital de-emphasis filter (tc=50/15µs) filter corresponding four sampling frequencies (32kHz, 44.1kHz, 48kHz 96kHz). When DEAU bit="1", de-emphasis filter enabled automatically sampling frequency pre-emphasis information channel status. AK4683 goes this mode default. Therefore, Parallel Mode, AK4683 always placed this mode status bits channel control de-emphasis filter. Serial Mode, DEM0/1 bits control de-emphasis filter when DEAU "0". internal de-emphasis filter bypassed recovered data output without change either pre-emphasis de-emphasis Mode OFF. (Others) Mode 44.1kHz 48kHz 32kHz 96kHz
Table De-emphasis Auto Control DEAU (default) DEM1 DEM0 Mode 44.1kHz 48kHz 32kHz 96kHz
(default)
Table De-emphasis Manual Control DEAU
System Reset Power-Down AK4683 power-down mode circuits partially powerd-down bit. RSTN2 initializes register resets internal timing. AK4683 should reset once bringing upon power-up. pin: analog digital circuit placed power-down reset mode bringing "L". registers initialized, clocks stopped. Reading/Witting register disabled. RSTN2 (Address 00H; D0): registers except RSTN2 bits initialized bringing RSTN2 "0". internal timings also initialized. When RSTN2 "0", clock output SDTO hold "L". Witting register available except RSTN2 bits. Reading register disabled. (Address 00H; D1): clock recovery part initialized bringing "0". this case, clocks from stopped. registers initialized mode settings kept. Writing Reading registers enabled.
MS0427-E-00
2005/09
ASAHI KASEI Biphase Input Through Output
[AK4683]
Eight receiver inputs (RX0-3) available Serial Control Mode. Only input includes amplifier corresponding unbalance mode accept signal 200mV more. IPS1-0 bits select receiver channel. output pin. IPS1 IPS0 Source
(default)
Table Recovery Data Select
1/4fs VOUT
C(R191)
V(L0)
V(R0)
V(L1)
V(L39)
V(R39) V(L40)
SDTO
R190
L191
R191
LRCK (except I2S) LRCK (I2S)
Figure output timings
MS0427-E-00
2005/09
ASAHI KASEI Biphase Output
[AK4683]
AK4683 output either through output (from transmitter output (DIT) pin. Those could selected bit. source through output from could selected among RX0-3 OPS0, bits. When output data, could controlled first bytes could controlled CT39-CT0 bits control registers. When bit0= "0"(consumer mode), bit20-23 (Audio channel) could controlled directly controlled CT20 bit. When CT20 "1", AK4683 outputs "1000" C20-23 left channel outputs "0100" C20-23 right channel automatically. When CT20 "0", AK4683 outputs "0000" "1000" frame "0100" frame bits fixed "0". OPS1 OPS0 Source
(default)
Table Source Control CLKDT selects clock source DIT. This clock must same clock clock sources PORT connecting DIT. UNLOCK Clock Source (default) EXTCLK EXTCLK EXTCLK Table Clock Mode Control CLKDT Clock Source MCLK2
Table EXTCLK Control CKSDT OCKS1 OCKS0 EXTCLK 256fs 256fs 512fs 128fs 384fs 384fs 768fs 192fs fs(max) 96kHz 96kHz 48kHz 192kHz 48kHz 48kHz 32kHz 96kHz
Table MCLKO Speed
MS0427-E-00
2005/09
ASAHI KASEI DITD1-0 bits control data source DIT. DITD1 DITD0 Source SDTIB SDTIA1(default)
[AK4683]
Table Source Control
Biphase signal input/output circuit (RX0,
0.1uF Coax
AK4683
Figure Consumer Input Circuit (Coaxial Input) Note: case coaxial input, coupling level this input from next input line pattern exceeds 50mV, there possibility occur incorrect operation. this case, possible lower coupling level adding this decoupling capacitor.
Optical Receiver Optical Fiber
RX0-3
AK4683
Figure Consumer Input Circuit (Optical Input) case coaxial input, input level line small, careful crosstalk among input lines. example, inserting shield pattern among them. AK4683 includes output buffer. output level meets combination 0.5V+/-20% using external resistor network. Figure transformer 1:1.
330±2% 100±2% DVSS cable
Figure External Resistor Network
MS0427-E-00
2005/09
ASAHI KASEI Q-subcode buffers
[AK4683]
AK4683 Q-subcode buffer application. AK4683 takes Q-subcode into registers following conditions. sync word (S0,S1) constructed least "0"s. start "1". Those 7bits follows start bit. distance between start bits 8-16 bits. QINT control register goes when Q-subcode differs from one, goes when QINT read.
number min=0; max=8. Figure Configuration U-bit(CD)
TRACK NUMBER INDEX
CTRL
ADRS
MINUTE SECOND FRAME ZERO ABSOLUTE MINUTE ABSOLUTE SECOND ABSOLUTE FRAME G(x)=x16+x12+x5+1
Figure Q-subcode Addr Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame
Figure Q-subcode register
MS0427-E-00
2005/09
ASAHI KASEI Error Handling
[AK4683]
There following eight events that make "H". show status following conditions. UNLOCK: when loses lock. AK4683 loses lock when distance between preambles correct when those preambles correct. PAR: when parity error biphase coding error detected, keeps until this register read. Updated every sub-frame cycle. Reading this register resets itself. AUTO: when Non-PCM bitstream detected. Updated every 4096 frames cycle. DTSCD: when DTS-CD bitstream detected. Updated every DTS-CD sync cycle. AUDION: when "AUDIO" recovered channel status indicates "1". Updated every block cycle. PEM: when "PEM" recovered channel status indicates "1". Updated every block cycle. QINT: when Q-subcode differ from one, keeps until this register read. Updated every sync code cycle Q-subcode. Reading this register resets itself. CINT: when received bits differ from one, keeps until this register read. Updated every block cycle. Reading this register resets itself. fixed when (CM1,0= "01"). Once goes "H", this holds 1024/fs cycles (this value changed EFH0/1 bits) after those events removed. mask those eight events individually. Once PAR, QINT CINT goes "1", those registers held until those registers read. While AK4683 loses lock, registers regarding C-bit U-bits initialized keep previous value.
outputs ORed signal among those eight events. However, each mask bits mask each event. When each masks those events, event does affect operation (those mask affect those registers (UNLOCK, PAR, etc.) themselves. Once goes "H", maintains 1024/fs cycles (this value changed EFH0-1 bits) after events removed. Once those PAR, QINT CINT goes "1", holds until reading those registers. While AK4683 loses lock, channel status Q-subcode bits updated holds previous data. initial state, outputs ORed signal between UNLOCK PAR. Event DTSCD AUDION QINT CINT SDTO* Previous Data Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Note: when selected.
UNLOCK
AUTO
Table Error Handling
MS0427-E-00
2005/09
[AK4683]
Error (UNLOCK, PAR,.) Register (PAR,CINT,QINT) Register (others) Command MCKO, BICK, LRCK (UNLOCK) note MCKO, BICK, LRCK (except UNLOCK) note SDTO (UNLOCK) note SDTO (PAR error) note SDTO (others) note Vpin (UNLOCK) note Vpin (except UNLOCK) note
(Error)
Hold Time (max: 4096/fs)
Hold
Reset
READ
Free (fs: around 20kHz)
Previous Data
Normal Operation
note: When selected source. Figure INT0/1 timing
MS0427-E-00
2005/09
[AK4683]
="L" Initialize Read
="H"
Release Muting
Mute output
Read
(Each Error Handling)
Read (Resets registers)
="H"
Figure Error Handling Sequence Example
MS0427-E-00
2005/09
[AK4683]
="L" Initialize Read
="H"
Read Detect QSUB=
(Read Q-buffer)
QCRC ="L" data valid
data invalid
Figure Error Handling Sequence Example (for Q/CINT)
MS0427-E-00
2005/09
[AK4683]
Non-PCM (AC-3, MPEG, etc.) DTS-CD Bitstream Detection AK4683 Non-PCM steam auto-detection function. When 32bit mode Non-PCM preamble based Dolby "AC-3 Data Stream IEC60958 Interface" detected, AUTO goes "1". 96bit sync code consists 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 0x4E1F. Detection this pattern will AUTO "1". Once AUTO "1", will remain until 4096 frames pass through chip without additional sync pattern being detected. When those preambles detected, burst preambles that follow those sync codes stored registers. AK4683 also DTS-CD bitstream auto-detection function. When AK4683 detects DTS-CD bitstreams, DTSCD goes "1". When next sync code does come within 4096 flames, DTSCD goes until when AK4683 detects stream again.
Burst Preambles non-PCM Bitstreams
sub-frame IEC958
preamble Aux.
bits bitstream
Burst_payload
stuffing
repetition time burst
Figure Data structure IEC60958 Preamble word Length field bits bits bits bits Contents sync word sync word Burst info Length code Value 0xF872 0x4E1F Table Numbers bits
Table Burst preamble words
MS0427-E-00
2005/09
[AK4683]
Bits
Value
Contents data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 data MPEG-2 without extension MPEG-2 data with extension MPEG-2 ADTS MPEG-2, Layer1 sample rate MPEG-2, Layer2 sample rate reserved type type type ATRAC ATRAC2/3 reserved reserved, shall error-flag indicating valid burst_payload error-flag indicating that burst_payload contain errors data type dependent info stream number, shall Table Fields burst info
Repetition time burst IEC60958 frames 4096 1536
16-31
1152 1152 1024 1152 1024 2048 1024
8-12 13-15
(Refer standards.)
MS0427-E-00
2005/09
[AK4683]
Non-PCM Bitstream timing When Non-PCM preamble coming within 4096 frames,
stream
Repetition time
>4096 frames
AUTO
Register
Register
Figure Timing example
When Non-PCM bitstream stops (when MULK0=0),
INT0 <20mS (Lock time) stream Stop Syncs (B,M AUTO <Repetition time INT0 hold time
Register
Register
Figure Timing example
MS0427-E-00
2005/09
[AK4683]
OPERATION OVERVIEW (ADC/DAC part, DIR/DIT part)
Serial Control Interface AK4683 registers, which ADC/DAC part DIR/DIT part. Each register chip address pin. (1). 4-wire serial control mode (I2C "L") internal registers either written read 4-wire interface pins: CSN, CCLK, CDTI CDTO. data this interface consists Chip address (2bits, C1-C0="10" ADC/DAC part, "00" DIR/DIT part), Read/Write (1bit), Register address (MSB first, 5bits) Control data (MSB first, 8bits). Address data clocked rising edge CCLK data clocked falling edge. write operations, data latched after 16th rising edge CCLK, after high-to-low transition CSN. read operations, CDTO output goes high impedance after low-to-high transition CSN. maximum speed CCLK 5MHz. resets registers their default values. When state changed, AK4683 should reset "L". Register ADC/DAC part read.
CCLK
CDTI WRITE CDTO CDTI READ CDTO
Hi-Z
Hi-Z
Hi-Z
C1-C0: R/W: A4-A0: D7-D0:
Chip Address: (Fixed "10" ADC/DAC part, "00" DIR/DIT part) READ/WRITE (0:READ, 1:WRITE) Register Address Control Data Figure 4-wire Serial Control Timing
MS0427-E-00
2005/09
[AK4683]
(2). control mode (I2C "H") AK4683 supports standard-mode I2C-bus (max 100kHz). Then AK4683 does support fast-mode I2C-bus system (max: 400kHz). (2)-1. Data transfer commands preceded START condition. After START condition, slave address sent. After AK4683 recognizes START condition, device interfaced waits slave address transmitted over line. transmitted slave address matches address devices, designated slave device pulls line (ACKNOWLEDGE). data transfer always terminated STOP condition generated master device. (2)-1-1. Data validity data line must stable during HIGH period clock. HIGH state data line only change when clock signal line except START STOP condition.
DATA LINE STABLE DATA VALID
CHANGE DATA ALLOWED
Figure Data transfer (2)-1-2. START STOP condition HIGH transition line while HIGH indicates START condition. sequences start from START condition. HIGH transition line while HIGH defines STOP condition. sequences STOP condition.
START CONDITION
STOP CONDITION
Figure START STOP conditions
MS0427-E-00
2005/09
[AK4683]
(2)-1-3. ACKNOWLEDGE ACKNOWLEDGE software convention used indicate successful data transfers. transmitting device will release line (HIGH) after transmitting eight bits. receiver must pull down line during acknowledge clock pulse that that remains stable during period this clock pulse. AK4683 will generates acknowledge after each byte been received. read mode, slave, AK4683 will transmit eight bits data, release line monitor line acknowledge. acknowledge detected STOP condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await STOP condition. register ADC/DAC part generate acknowledge READ operations.
Clock pulse acknowledge
FROM MASTER
DATA OUTPUT TRANSMITTER acknowledge DATA OUTPUT RECEIVER START CONDITION acknowledge
Figure Acknowledge I2C-bus (2)-1-4. FIRST BYTE first byte, which includes seven bits slave address bit, sent after START condition. transmitted slave address matches address device, receiver been addressed pulls down line. most significant five bits slave address fixed "00100". next bits CAD1 CAD0 (device address bits). These bits identify specific device bus. eighth (LSB) first byte (R/W bit) defines whether write read condition requested master. indicates that read operation executed. indicates that write operation executed.
CAD1
CAD0
(CAD1-CAD0 fixed "10" ADC/DAC part, "00" DIR/DIT part) Figure First Byte
MS0427-E-00
2005/09
[AK4683]
(2)-2. WRITE Operations WRITE operation AK4683. After receipt start condition first byte, AK4683 generates acknowledge, awaits second byte (register address). second byte consists address control registers AK4683. format first, those most significant 3-bits "Don't care".
Don't care) Figure Second Byte After receipt second byte, AK4683 generates acknowledge, awaits third byte. Those data after second byte contain control data. format first, 8bits.
Figure Byte structure after second byte AK4683 capable more than byte write operation sequence. After receipt third byte, AK4683 generates acknowledge, awaits next data again. master transmit more than words instead terminating write cycle after first data word transferred. After receipt each data, internal 5bits address counter incremented one, next data taken into next address automatically. address exceed prior generating stop condition, address counter will "roll over" previous data will overwritten.
Slave Address Register Address(n) Data(n+x)
Data(n)
Data(n+1)
Figure WRITE Operation
MS0427-E-00
2005/09
[AK4683]
(2)-3. READ Operations READ operation AK4683. After transmission data, master read next address's data generating acknowledge instead terminating write cycle after receipt first data word. After receipt each data, internal 5bits address counter incremented one, next data taken into next address automatically. address exceed prior generating stop condition, address counter will "roll over" previous data will overwritten. AK4683 supports basic read operations: CURRENT ADDRESS READ RANDOM READ. ADC/DAC part register read. (2)-3-1. CURRENT ADDRESS READ AK4683 contains internal address counter that maintains address last word accessed, incremented one. Therefore, last access (either read write) address next CURRENT READ operation would access data from address n+1. After receipt slave address with "1", AK4683 generates acknowledge, transmits 1byte data which address internal address counter increments internal address counter master does generate acknowledge data generate stop condition, AK4683 discontinues transmission
Slave Address Data(n+x)
Data(n)
Data(n+1)
Data(n+2)
Figure CURRENT ADDRESS READ (2)-3-2. RANDOM READ Random read operation allows master access memory location random. Prior issuing slave address with "1", master must first perform "dummy" write operation. master issues start condition, slave address(R/W="0") then register address read. After register address's acknowledge, master immediately reissues start condition slave address with "1". Then AK4683 generates acknowledge, 1byte data increments internal address counter master does generate acknowledge data generate stop condition, AK4683 discontinues transmission.
Slave Address
Word Address(n)
Slave Address
Data(n)
Data(n+1)
Data(n+x)
Figure RANDOM READ
MS0427-E-00
2005/09
[AK4683]
Register (ADC/DAC part)
Addr
Register Name Powerdown Powerdown Clock Select Clock Select Clock Select Clock Select Sampling Speed Data Source Select Data Source Select Analog Input Control Audio Data Format De-emphasis/ speed Volume Control Volume Control LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control Volume Control OVF/DZF/V Control
PWXTL PWPOB CKSL2 CKSAI2 DEM21
ATTAD7 ATTAD7 ATTDA7 ATTDA7 ATTDA7 ATTDA7
MUTEN PWPOA CKSL1 CKSAI1 XTL1
ACKSAI
PWVR PWDA CKSL0 CKSAI0 XTL0
ACKSAO
DAC22 DEM20
ATTAD6 ATTAD6 ATTDA6 ATTDA6 ATTDA6 ATTDA6
DITD1 DAC21 DIFB1 DEM11
ATTAD5 ATTAD5 ATTDA5 ATTDA5 ATTDA5 ATTDA5
PWHP PWAD CLKL1 CKSDT ACKSB DITD0 DAC20 DIFB0 DEM10
ATTAD4 ATTAD4 ATTDA4 ATTDA4 ATTDA4 ATTDA4
CLKB1 CLKL0 OLRA1 CKSB2
SDTOB1
SMAD CLKB0 MCKO1 OLRA0 CKSB1 DFSAD
SDTOB0
SMDA PWDA2 CLKA1 MCKO0 BCAF CKSB0
DFSDA1 SDTOA1
RSTN1 PWDA1 CLKA0 CLKDT
DFSDA0 SDTOA0
TDMA1
ATTAD3 ATTAD3 ATTDA3 ATTDA3 ATTDA3 ATTDA3
DAC12 AIN2 TDMA0 ATSAD
ATTAD2 ATTAD2 ATTDA2 ATTDA2 ATTDA2 ATTDA2
DAC11 AIN1 DIFA1
ATTAD1 ATTAD1 ATTDA1 ATTDA1 ATTDA1 ATTDA1
DAC10 AIN0 DIFA0 ATSDA
ATTAD0 ATTAD0 ATTDA0 ATTDA0 ATTDA0 ATTDA0
OPGA4
OPGA3 FUNC1
OPGA2 FUNC0
OPGA1 DZFM1
OPGA0 DZFM0
Note: addresses from14H 1FH, data must written. When goes "L", registers initialized their default values. When RSTN1 goes "0", internal timing reset goes "H", registers initialized their default values.
MS0427-E-00
2005/09
[AK4683]
Register Definitions
Addr
Register Name Powerdown Default
PWXTL
MUTEN
PWVR
PWHP
SMAD
SMDA
RSTN1
RSTN1: Internal timing reset Reset. "H", registers initialized. Normal operation (default) SMAD: Soft Mute Enable Normal operation (default) outputs soft-muted SMDA: Soft Mute Enable Normal operation (default) outputs soft-muted PWHP: Power management headphone amplifier Power (default) Power PWVR: Power management reference voltage Power Power (default) MUTEN: Bias voltage control headphone bias (default). Normal operation. Bias 0.45xHVDD(typ). PWXTL: Power management X'tal oscillator Power Power (default)
MS0427-E-00
2005/09
[AK4683]
Addr
Register Name Powerdown Default
PWPOB
PWPOA
PWDA
PWAD
PWDA2
PWDA1
PWDA1: Power-down control DAC1 Analog Power-down Normal operation (default) PWDA2: Power-down control DAC2 Analog Power-down Normal operation (default) PWAD: Power-down control Power-down Normal operation (default) PWDA: Full-Power-down control DAC1-2 Power-down Normal operation (default) PWPOA: Power-down control PORTA Power-down Normal operation (default) PWPOB: Power-down control PORTB Power-down Normal operation (default)
Addr Register Name Clock Select Default CLKB1 CLKB0 CLKA1 CLKA0
CLKA1-0: Clock source control PORTA X'tal(XTI) (default) MCLK2 (Reserved) CLKB1-0: Clock source control PORTB X'tal(XTI) (default) MCLK2 (Reserved)
MS0427-E-00
2005/09
[AK4683]
Addr
Register Name Clock Select Default
CKSL2
CKSL1
CKSL0
CLKL1
CLKL0
MCKO1
MCKO0
CLKDT
CLKDT: Clock source control Refer Table MCLKO1-0: Clock source control MCLKO Refer Table CLKL1-0: Clock source control Clock X'tal(XTI) (default) MCLK2 (Reserved) CLSL2-0: Clock control Clock Refer Table Addr Register Name Clock Select Default
CKSAI2
CKSAI1
CKSAI0
SELAO
OLRA1
OLRA0
BCAF
MSA: Master/Slave control input data PORTA. Refer Table BCAF: clock control PORTA Refer Table OLRA1-0: Clock control PORTA OLRCKA. Refer Table SELAO: Clock control DIR/DIT Except case "1". (default) Selects when frequency ILRCKA OLRCKA different, DIT[1:0]= "00" "01" both SDTOA[1:0] DIT[1:0] select same data source. CKSAI2-0: Clock control PORTA Input Data. Refer Table Addr Register Name Clock Select Default
XTL1
XTL0
CKSDT
CKSB2
CKSB1
CKSB0
MSB: Master/Slave control input data PORTB. Refer Table CKSB2-0: Clock control PORTB. Refer Table CKSDT: Clock control DIT. Refer Table XTL1-0: X'tal Frequency control 11.2896MHz (default) 12.288MHz 24.576MHz (channel status) MS0427-E-00 2005/09
[AK4683]
Addr
Register Name Sampling Speed Default
ACKSAI
ACKSAO
ACKSB
DFSAD
DFSDA1
DFSDA0
DFSDA1-0: sampling speed control These settings ignored Auto Setting Mode. Refer Table DFSAD: sampling speed control This setting ignored Auto Setting Mode. Refer Table ACSKB: Auto Setting Mode PORTB Disable, Manual Setting Mode (default) Enable, Auto Setting Mode Master clock frequency detected automatically ACKSB "1". this case, setting DFSAD, DFSDA1-0 bits block connecting this PORT ignored. When this "0", DFSAD, DFSDA1-0 bits sampling speed mode. ACSKAO: Auto Setting Mode PORTA Output Disable, Manual Setting Mode (default) Enable, Auto Setting Mode Master clock frequency detected automatically ACKSAO "1". this case, setting DFSAD, DFSDA1-0 bits block connecting this PORT ignored. When this "0", DFSAD, DFSDA1-0 bits sampling speed mode. ACSKAI: Auto Setting Mode PORTA Input Disable, Manual Setting Mode (default) Enable, Auto Setting Mode Master clock frequency detected automatically ACKSAI "1". this case, setting DFSAD, DFSDA1-0 bits block connecting this PORT ignored. When this "0", DFSAD, DFSDA1-0 bits sampling speed mode.
Addr
Register Name Data Source Select Default
DITD1
DITD0
SDTOB1
SDTOB0
SDTOA1
SDTOA0
SDTOA1-0: Data source control PORTA (default) SDTIB ("L" output) SDTOB1-0: Data source control PORTB (default) ("L" output) SDTIA1 DITD1-0: Data source control SDTIB SDTIA1 (default)
MS0427-E-00
2005/09
[AK4683]
Addr
Register Name Data Source Select Default
DAC22
DAC21
DAC20
DAC12
DAC11
DAC10
DAC12-10: Data source control DAC1 000: 001: 010: SDTIB 011: SDTIA1 (default) 100: SDTIA2 101: SDTIA3 DAC22-20: Data source control DAC2 000: 001: 010: SDTIB 011: SDTIA1 100: SDTIA2 (default) 101: SDTIA3
Addr
Register Name Analog Input Control Default
AIN2
AIN1
AIN0
AIN2-0: input selector control 000: LIN1/RIN1 (default) 001: LIN2/RIN2 010: LIN3/RIN3 011: LIN4/RIN4 100: LIN5/RIN5 101: LIN6/RIN6
Addr
Register Name Audio Data Format Default
DIFB1
DIFB0
TDMA1
TDMA0
DIFA1
DIFA0
DIFA1-0, TDMA1-0: Audio format control PORTA Refer Table Table Table DIFB1-0: Audio format control PORTB Refer Table Addr Register Name
De-emphasis/ speed
DEM21
DEM20
DEM11
DEM10
ATSAD
ATSDA
Default
ATSDA: digital Attenuator transition time control ATSAD: digital Attenuator transition time control Refer Table Table DEM11-10: DAC1 De-emphasis filter control DEM21-20: DAC2 De-emphasis filter control Refer Table
MS0427-E-00
2005/09
[AK4683]
Addr
Register Name Volume Control Volume Control Default
ATTAD7 ATTAD7
ATTAD6 ATTAD6
ATTAD5 ATTAD5
ATTAD4 ATTAD4
ATTAD3 ATTAD3
ATTAD2 ATTAD2
ATTAD1 ATTAD1
ATTAD0 ATTAD0
ATTAD7-0: Attenuation level control Refer Table Addr Register Name
LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control
ATTDA7 ATTDA7 ATTDA7 ATTDA7
ATTDA6 ATTDA6 ATTDA6 ATTDA6
ATTDA5 ATTDA5 ATTDA5 ATTDA5
ATTDA4 ATTDA4 ATTDA4 ATTDA4
ATTDA3 ATTDA3 ATTDA3 ATTDA3
ATTDA2 ATTDA2 ATTDA2 ATTDA2
ATTDA1 ATTDA1 ATTDA1 ATTDA1
ATTDA0 ATTDA0 ATTDA0 ATTDA0
Default
ATTDA7-0: Attenuation level control Refer Table Addr Register Name Volume Control Default
OPGA4
OPGA3
OPGA2
OPGA1
OPGA0
OPGA5-0: OPGA Attenuation level control Refer Table Addr Register Name OVF/DZF/V Control Default
FUNC1
FUNC0
DZFM1
DZFM0
DZFM1-0: mode setting Refer Table FUNC1-0: OVF/DZF/V mode control ("L" output. default) Overflow detection Zero data detection output VIN: control ="0" (default) ="1" ZCE: OPGA Zero-cross enable Disable Enable (default)
MS0427-E-00
2005/09
[AK4683]
Register (DIR/DIT part)
Addr Register Name
Power Down Control
CS12 EFH1 QINT CR15 CR23 CR31 CR39 CT15 CT23 CT31 CT39 PC15 PD15
EFH0 AUTO CR14 CR22 CR30 CR38 CT14 CT22 CT30 CT39 PC14 PD14
OPS1 MCIT0 CINT CR13 CR21 CR29 CR37 CT13 CT21 CT29 CT39 PC13 PD13
OPS0 CR12 CR20 CR28 CR36 CT12 CT20 CT28 CT39 PC12 PD12
OCKS1 DEAU CR11 CR19 CR27 CR35 CT11 CT19 CT27 CT39 PC11 PD11
OCKS0 DEM1 MPE0 CR10 CR18 CR26 CR34 CT10 CT18 CT26 CT39 PC10 PD10
DEM0 IPS1 MAUD0 AUDION QCRC CR17 CR25 CR33 CT17 CT25 CT39
RSTN2 IPS0 MPAR0 CCRC CR16 CR24 CR32 CT16 CT24 CT32
Format De-em Control Input/ Output Control Input/ Output Control MASK TEST Receiver status Receiver status Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second
MQIT0 MAUT0
MULK0 MDTS0 UNLCK DTSCD
Q-subcode Frame When goes "L", registers initialized their default values. When RSTN goes "0", internal timing reset registers initialized their default values. data written register even "0". register should written "0", register should written data.
MS0427-E-00
2005/09
[AK4683]
Register Definitions
Reset Initialize Addr Register Name Power Down Control Default CS12 OCKS1 OCKS0 RSTN2
RSTN2: Timing Reset Register Initialize Reset Initialize Normal Operation (default) PWN: Power Down Power Down Normal Operation (default) OCKS1-0: Master Clock Frequency Select Refer Table Table CM1-0: Master Clock Operation Mode Select Refer Table Table Table CS12: Channel Status Select Channel (default) Channel Selects which channel status used derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0, de-emphasis filter controlled channel Parallel Mode.
Format De-emphasis Control Addr Register Name Format De-em Control Default DFS: 96kHz De-emphasis Control Refer Table DEM1-0: 44.1, 48kHz De-emphasis Control Refer Table DEAU: De-emphasis Auto Detect Enable Disable Enable (default) DEAU DEM1 DEM0
MS0427-E-00
2005/09
[AK4683]
Input/Output Control Addr Register Name Input/ Output Control Default OPS1 OPS0
OPS1-0: Output Through Data Select Refer Table TXE: Output Enable Disable. outputs "L". Enable (default) Addr Register Name Input/ Output Control Default EFH1 EFH0 IPS1 IPS0
IPS1-0: Input Recovery Data Select Refer Table DIT: Through data/Transmit data select Through data data). Transmit data (DAUX2 data. default.). fixed "0") EFH1-0: Interrupt Hold Count Select LRCK2 1024 LRCK (default) 2048 LRCK 4096 LRCK
MS0427-E-00
2005/09
[AK4683]
Mask Control Addr Register Name MASK Default MPR0: MAN0: MPE0: MDTS0: MUL0: MCI0: MAT0: MQI0: MQI0 MAT0 MCI0 MUL0 MDTS0 MPE0 MAN0 MPR0
Mask Enable Mask Enable AUDN Mask Enable Mask Enable DTSCD Mask Enable UNLOCK Mask Enable CINT Mask Enable AUTO Mask Enable QINT Mask disable Mask enable
MS0427-E-00
2005/09
[AK4683]
Receiver Status Addr Register Name Receiver status Default QINT AUTO CINT UNLCK DTSCD AUDION
PAR: Parity Error Biphase Error Status Error Error Parity Error Biphase Error detected sub-frame. AUDION: Audio Output Audio Audio This made encoding channel status bits. PEM: Pre-emphasis Detect. This made encoding channel status bits. DTSCD: DTS-CD Auto Detect detect Detect UNLCK: Lock Status Locked Lock CINT: Channel Status Buffer Interrupt change Changed AUTO: Non-PCM Auto Detect detect Detect QINT: Q-subcode Buffer Interrupt change Changed QINT, CINT bits initialized when read. Receiver Status Addr Register Name Receiver status Default QCRC CCRC
CCRC: Cyclic Redundancy Check Channel Status 0:No Error 1:Error QCRC: Cyclic Redundancy Check Q-subcode 0:No Error 1:Error Validity channel status 0:Valid 1:Invalid FS3-0: Sampling Frequency detection (refer Table 48.)
MS0427-E-00
2005/09
[AK4683]
Receiver Channel Status Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CR15 CR23 CR31 CR39 CR14 CR22 CR30 CR38 CR13 CR21 CR29 CR37 CR12 CR20 CR28 CR36 CR11 CR19 CR27 CR35 CR10 CR18 CR26 CR34 CR17 CR25 CR33 CR16 CR24 CR32
initialized
CR39-0: Receiver Channel Status Byte
Transmitter Channel Status Addr Register Name Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Channel Status Byte Default CT15 CT23 CT31 CT39 CT14 CT22 CT30 CT38 CT13 CT21 CT29 CT37 CT12 CT11 CT20 CT19 CT28 CT27 CT36 CT35 CT10 CT18 CT26 CT34 CT17 CT25 CT335 CT16 CT24 CT32
CT39-0: Transmitter Channel Status Byte
Burst Preamble Pc/Pd non-PCM encoded Audio Bitstreams
Addr Register Name Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Burst Preamble Byte Default PC15 PD15 PC14 PD14 PC13 PD13 PC12 PD12 PC11 PD11 PC10 PD10
initialized
PC15-0: Burst Preamble Byte PD15-0: Burst Preamble Byte
MS0427-E-00
2005/09
[AK4683]
Q-subcode Buffer
Addr
Register Name Q-subcode Address Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode Minute Q-subcode Second Q-subcode Frame Default
initialized
MS0427-E-00
2005/09
[AK4683]
SYSTEM DESIGN
Figure shows system connection diagram. evaluation board available which demonstrates application circuits, optimum layout, power supply arrangements measurement results.
Analog
0.1u PVSS RIN6 LIN6 RIN5 LIN5 RIN4 LIN4 RIN3 LIN3 RIN2 LIN2 RIN1 LIN1
0.1u
AVDD1
PVDD
AVSS1 RISEL ROPIN LOPIN LISEL AVSS2 AVDD2 VCOM 0.1u 0.1u 2.2u MUTE MUTE MUTE MUTE 0.1u
S/PDIF sources
CDTO/TEST LRCKB
Analog
AK4683
ROUT2 LOUT2 ROUT2 LOUT2 MUTET CSN/TEST HVSS SDTIA3 SDTIA SDTIA SDTIB HVDD
Analog
Audio DSP2
BICKB SDTOB OLRCKA ILRCKA BICKA MCKO TVDD MCLK2 SDTOA DVDD DVSS
Headphone
Analog
X'tal 0.1u
3.3V Digital Audio DSP1 Digital
0.1u
Micro Controller
S/PDIF Digital Ground Analog Ground
Figure Typical Connection Diagram( serial control mode) Notes: depends crystal. AVSS, DVSS PVSS must connected same analog ground plane. Digital signals, especially clocks, should kept away from order avoid effect clock jitter performance. case coaxial input, ground connector terminator should connected PVSS AK4683 with impedance board.
MS0427-E-00
2005/09
[AK4683]
Grounding Power Supply Decoupling AK4683 requires careful attention power supply grounding arrangements. AVDD1, AVDD2, DVDD, PVDD HVDD usually supplied from analog supply system. AVDD1, AVDD2, DVDD, PVDD HVDD supplied separately, power sequence critical. AVSS1, AVSS2, DVSS PVSS HVSS AK4683 must connected analog ground plane. System analog ground digital ground should connected together near where supplies brought onto printed circuit board. Decoupling capacitors should near AK4683 possible, with small value ceramic capacitor being nearest. Voltage Reference Inputs voltage AVDD1, AVDD2 sets analog input/output range. VCOM signal ground this chip. electrolytic capacitor 2.2µF parallel with 0.1µF ceramic capacitor attached between VCOM AVSS1 eliminates effects high frequency noise. load current drawn from VCOM pin. signals, especially clocks, should kept away from AVDD1, AVDD2 VCOM pins order avoid unwanted coupling into AK4683. Analog Inputs AK4683 receives analog input through single-ended Pre-amp using external resistors. Adjust input level/gain Pre-amp match input range 1.22 AVDD1 (typ. fs=48kHz, =47kohm, 24kohm). Each input pins biased internally. output data format complement. internal digital removes offset. AK4683 samples analog inputs 64fs. digital filter rejects noise above stop band except multiples 64fs. AK4683 includes anti-aliasing filter filter) attenuate noise around 64fs. Analog Outputs analog outputs also single-ended centered around VCOM voltage. input signal range scales with supply voltage nominally AVDD2 Vpp. input data format complement. output voltage positive full scale 7FFFFFH(@24bit) negative full scale 800000H(@24bit). ideal output VCOM voltage 000000H(@24bit). internal analog filters remove most noise generated delta-sigma modulator beyond audio passband. offsets analog outputs eliminated coupling since outputs have offsets Attention Wiring LIN1-6 RIN1-6 pins summing nodes Pre-Amp. Attention should given avoid coupling with other signals those nodes. This accomplished making wire length input resistors short possible. same theory also applies LOPIN/ROPIN pins feedback resistors; keep wire length minimum. Unused input pins among LIN1-6 RIN1-6 pins should left open.
MS0427-E-00
2005/09
[AK4683]
PACKAGE
64pin LQFP(Unit:mm)
12.0±0.3 1.70max 0.10±0.10
10.0
1.40
12.0 ±0.3
0.17±0.05 0.10
0.21±0.05
~10°
0.45±0.2 0.10
Package Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Solder free) plate
MS0427-E-00
2005/09
[AK4683]
MARKING
AK4683EQ XXXXXXX
indication Asahi Kasei Logo Marking Code: AK4683EQ Date Code: XXXXXXX(7 digits)
Revision History
Date (YY/MM/DD) 05/09/30 Revision Reason First Edition Page Contents
MS0427-E-00
2005/09
[AK4683]
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
MS0427-E-00
2005/09

AK4683 Asynchronous Multi-Channel Audio CODEC with DIR/T GEN

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