JPEG Decoder 29C82 performs decompression still pictures accordan

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29C82
JPEG Decoder
29C82 performs decompression still pictures accordance with JPEG standard basic systems (pixels coded bits, sequential display, HUFFMAN coding, etc). 29C82 independently executes most following adaptive discrete cosine transform (ADCT) algorithm (HUFFMAN) decoding using tables created user contained JPEG image frame. tables tables loaded into 29C82. de-quantization using tables contained JPEG image frame. tables tables loaded into 29C82. inverse COSINE transform. 29C82 peripheral circuit which communicates with microprocessor over DATA [0.7] ADDRESS [0.3] busses. microprocessor performs decoding JPEG image frame header order extract markers, image parameters, quantization, tables. These tables parameters then used program 29C82. After decoding, pixels available pixels PIXEL[0.7] 29C82 DATA [0.7] system bus. 29C82 able provide pixels speed 1.25 MPixels/s PIXEL[0.7], with system clock (CLK) MHz.
Features
Decoding still images JPEG-8 Rev6 standard. Performs decoding, de-quantization inverse discrete cosine transform (IDCT). Maximum system clock frequency MHz. Maximum output rate 1.25 mega-pixels/s private bus. 8-bit microprocessor interface. Dedicated 8-bit pixel power supply. Package PLCC68
Figure
Application Block Diagram using 29C82
CCETT License This data sheet includes information obtained from CCETT
Rev. (20/05/94)
29C82
Architecture
Figure 2982 Block Diagram
29C82 peripheral circuit, system which compatible with demultiplexed address/data INTEL type. contains blocks which interconnected over internal (BUSDIF). internal "VLC decoder", "de-quantization operator" "DCT operator" blocks also interconnected over data path which enables passage coefficients between various blocks optimized, traffic internal BUSDIF reduced. After decompression over various stages mentioned previously, pixels then read system (over BUSDIF) PIXEL[7.0] private bus. 29C82 includes following blocks block decoder (see appendix tables, each containing bits. tables, each containing bits. sets registers (Nblock Mux)
de-quantization block de-quantization operator (see appendix de-quantization tables, each containing levels. programming register (PROGRAMQ) IDCT block inverse operator Duhamel-Guillemot type output FIFO with 64-byte pages working alternately each page accessed DATA[7.0] system PIXEL[7.0] (like single 64-bit FIFO). microprocessor interface interrupt monitor with status control registers. interface block allow connection microprocessor over DATA[7.0] bus, ADDR[3.0] bus, READY.
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29C82
Configuration
Figure 29C82 PLCC Package. View
NAME
(A1/A4) (A3) (A2) (B2) (B1) (A1) (A2) (A3/A4) (B1) (B2) RESET DATA[7.0] ADDR[3.0] READY
TYPE
supply supply supply supply supply supply supply supply supply supply core positive supply core positive supply core positive supply buffer positive supply buffer positive supply core negative supply (0V) core negative supply (0V) core negative supply (0V) buffer negative supply (0V) buffer negative supply (0V) reference clock
FUNCTION
hardware reset (active high) table contents changed reset system DATA system ADDRESS chip select active READ active WRITE active READY output signal active
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29C82
NAME
PIXEL[0.7] CTYPE[1.0] BLKRDY PIXOUT TEST1 TEST2
TYPE
interrupt signal active high pixel request used request from 29C82 block pixels pixel (active high) tristate pixel frequency) component type (tree state) user defined code cyan, green, block ready, indicates that pixel block available (active high) pixel flag, indicates that pixels present pixel (active high) TEST pin, should left floating normal mode TEST pin, should left floating normal mode
FUNCTION
Description Inputs Outputs
Initialization 29C82, loading blocks decoded into input FIFO (FIFE), pixel read after decoding, accomplished over microprocessor interface connected ADDR[3.0]/ DATA[7.0] demultiplexed bus. 29C82 peripheral circuit microprocessor, accessed 29C82 through 16-address window which corresponds registers, tables FIFOs. STATUS register, combined with INTerrupt register, informs detected change status errors. Figure 29C82 Read/Write Cycles PIXEL[7.0] bus, dedicated image memory interface, used read pixels after decompression. This able carry pixel blocks (line line) system clock frequency MHz. When used (pixel output system bus), PIXEL (7.0] CTYPE[1.0] high-impedance mode order allow connection several 29C82's parallel.
Rev. (20/05/94)
Figure Pixel Block Output Timing
29C82
Description Registers
microprocessor communicates with 29C82 over 8-bit data bits address bus, possible addresses). When these addresses corresponds FIFO table multiple register, read write access various parts FIFO, table register accomplished sequentially, keeping address ADDR[3.0] constant. depth 9-bit words, with (LSB) obtained address decoding. This forced leaf HUFFMAN tree, node tree. access write sequential mode.
Quantization Tables
29C82 contains quantization tables address depth 8-bit words access write sequential mode. threshold levels quantization tables written into following order
Tables
29C82 contains tables. coefficients coefficients. Each table contains HUFFMAN tree associated with decoding various coefficients. tables address T0_DC 00H. T1_DC 03H. depth 5-bit words centered LSB's byte written over microprocessor bus. Access write sequential mode. T0_DC/T1_DC selection performed NTAB register GENMUX register set. tables address T0_AC T1_AC
(Nodes) (leaves). (Nodes) (leaves).
selection accomplished using PROGRAMQ register.
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29C82
Registers
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FIFO's input FIFO FIFE address depth bytes access type sequential write pointer reset hardware software RESET Write access FIFE made through bus. Reading from FIFE done decoder. FIFE_MT status register used indicate that FIFE three-quarters empty bytes available FIFE). microprocessor responsible limiting number write into FIFO that capacity exceeded. When FIFO 100% empty, decoder does hold 29C82 operation. output FIFO MEMPIX address depth bytes access type sequential read pointer reset RESET
CONTROL START PIX_BUS address CL_FIFE RSC_ACK
29C82
Writing output Pixel FIFO (MEMPIX) achieved using operator. Read accomplished over PIXEL[7.0] PIX_BUS (CONTROL register) over DATA[7.0] PIX_BUS PIXELS FIFO splitted into pages bytes, accessed alternately operator. While operator calculating inverse block coefficients, second page bytes accessed over PIXEL[7.0] DATA[7.0] output results calculation preceding block. When output FIFO full BLK_RDY STATUS register goes interrupt (INT) activated this been enabled INT3_EN CONTROL register.
registers
Access type write INT3_EN BLK_RDY INT2_EN FIFE_MT RESET Hardware INT1_EN VLC_ERR RESET SOFT
START DECODING START. START=1 enables start image decoding. This reset clock period (CLK) after been written control register. PIX_BUS PIXEL PIX_BUS=0. Read access output FIFO, MEMPIX, occurs over microprocessor bus. PIXEL[7.0] CTYPE[1.0] outputs high-impedance state, PIXOUT=0, BLKRDY active inactive. PIX_BUS=1, read access output FIFO performed over PIXEL[7.0] private bus. CL_FIFE Input FIFO reset CL_FIFE=1 causes zero reset input FIFO, FIFE. This automatically reset period after been written CONTROL register.
Note JPEG standard specifies re-synchronisation markers order segment image. These markers alined byte borders. They used partial re-transmission images after detection errors.
Interrupts When INTx_EN enable interrupt request (INT) activated INT3_EN output FIFO, MEMPIX, contains full block 8x8pixels (bit BLK_RDY=1 STATUS register). Reading single pixel from MEMPIX causes reset interrupt request. INT2_EN input FIFO, FIFE, three-quarters empty (bit FIFE_MT=1 STATUS register). INT1_EN when decoding error detected (bit VLC_ERR=1 STATUS register). microprocessor must read STATUS register identify cause interrupt. interrupt process cycle allows output forced least
RSC_ACK DECODING RESYNCHRONISATION MARKERS. RSC_ACK=1 enables decoding RSC0(FFD0) RSC7(FFD7) markers.
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29C82
during cycle period) associated interrupt request de-activated following INT-1 (VLC error) read NBLOCK register. INT-2 INT-3 active, goes back after fully reading NBLOCK bytes). INT-2 (FIFE three-quarters empty) write FIFE used reset FIFE_MT STATUS register force output INT-1 INT-3 active, goes back after write cycle FIFE. Caution fact that more bytes Figure
have been written FIFE after INT-2 interrupt request does necessarily cause FIFO pointer value over (the empty level). such case, INT-2 interrupt occurs. INT-3 (block ready output FIFO) reading (one pixel only) from MEMPIX resets BLK_RDY (the status register) BLKROY/INT outputs "0". INT-1 INT-2 active, goes back after first read cycle from MEMPIX.
INT3_EN
"OUTPUT BLOCK READY" INTERRUPT ENABLE. INT3_EN=1 enables transmission INT-3 (BLOCK READY) interrupt request microprocessor. "FIFE EMPTY" INTERRUPT ENABLE. INT2_EN=1 enables transmission INT-2 (FIFE EMPTY) interrupt request microprocessor. "VLC ERROR" INTERRUPT ENABLE. INT1_EN=1 enables transmission INT-2
address CTYP BLK_RDY
(VLC ERROR) interrupt request microprocessor. RESET SOFTWARE RESET RESET=1 used re-initialise internal STATUS register also FIFO pointers without affecting contents tables CONTROL, PROGRAMQ, NBLOCK, MUXGEN registers. This automatically reset period after been written "1".
RESET SOFTWARE HARDWARE QZT_BSY VLC_BSY VLC_ERR FIFE_MT
INT2_EN
INT1_EN
STATUS CTYP
Access Type read DCT_BSY
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CTYP[1.0] COMPONENT TYPE. These bits used indicate image component which pixel block available MEMPIX belongs. CTYP[1.0] bits same state CTYPE[1.0] outputs. BLK_RDY PIXEL BLOCK READY. BLK_RDY goes when pixel block available MEMPIX. BLK_RDY same state BLKRDY output. DCT_BSY OPERATOR ACTIVE (FOR INFORMATION ONLY). DCT_BSY=1 indicates that reverse operator active. VLC_ERR=1, this re-defined RSC[2] (see description VLC_ERR bit). QZT_BSY DE-QUANTIZATION OPERATOR ACTIVE (FOR INFORMATION ONLY). QZT_BSY=1 indicates that de-quantization operator active. VLC_ERR=1, this re-defined RSC[1] (see description VLC_ERR bit). VLC_BSY DECODING OPERATOR ACTIVE (FOR INFORMATION ONLY). VLC_BSY=1 indicates that operator active. VLC_ERR=1, this re-defined RSC[0] (see description VLC_ERR bit). operator always active, even FIFE completely empty. VLC_BSY reset only after RESET before START been
PROGRAMQ QCT3 QCT3 address QCT2
29C82
VLC_ERR ERROR. VLC_ERR=1 indicates that decoding error been detected. This type error caused detection marker with content NBLOCK register different from detection code with length more than bits. coefficient pointer over this case, RSC[2.0] status register represent three LSB's last re-synchronisation marker detected before error. Output goes INT1_EN CONTROL register microprossor reads from NBLOCK number blocks remaining decoded (NBLOCK acts down-counter) order reset interrupt VLC_ERR case where there re-synchronisation, (APPLICATION) selects strategy used (re-transmission BLOCK, SCAN, FRAME, IMAGE, etc.) When more re-synchronisation markers exist, 29C82 waits next resynchronisation marker that continue decoding current image. FIFE_MT FIFE EMPTY. FIFE_MT=1 when input FIFO, FIFE, three-quarters empty bytes left When INT2_EN CONTROL register output goes this case, microprossor write bytes into FIFE.
Reset HARDWARE QCT1 QCT0 QCT0
Access type write QCT2 QCT1
QCT3[1.0] "QUANTIZATION TABLE" REFERENCE COMPONENT These bits code reference quantization table block which belongs type-3 image component. QCT2[1.0] "QUANTIZATION TABLE" REFERENCE COMPONENT These bits code reference quantization table block which belongs type-2 image component.
QCT1[1.0] "QUANTIZATION TABLE" REFERENCE COMPONENT These bits code reference quantization table block which belongs type-1 image component. QCT0[1.0] "QUANTIZATION TABLE" REFERENCE COMPONENT These bits code reference quantization table block which belongs type-0 image component.
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29C82
Multiple Registers
NBLOCK address depth bytes NBLK[22] NBLK[15] NBLK[07] NBLK[06] NBLK[14] NBLK[05] NBLK[13] NBLK[04] Access type sequential read/write RESET HARDWARE NBLK[21] NBLK[12] NBLK[03] NBLK[20] NBLK[11] NBLK[02] NBLK[19] NBLK[10] NBLK[18]
NBLK[23]
NBLK[17] NBLK[09] NBLK[01]
NBLK[16] NBLK[08] NBLK[00]
NBLK[23.0] NUMBER BLOCKS NBLK[23.0] contains number blocks decoded between markers (RSC_ACK=1) full image (RSC_ACK=0). 29C82 uses NBLOCK down-counter. MUXGEN address Access type sequential write depth bytes RESET HARDWARE
ADCT algorithm allows interlacing modes frame interlace mode, where each component coded separately transmitted sequentially complete image (e.g. press images, "yellow", "blue", "red", "black" transmission). block interlacing mode, where blocks interlaced accordance with repeating pattern (MDU) (e.g. Videotext transmission luminance blocks, "red" chrominance block, "blue" chrominance block,
MUXGEN contains registers
NTAB VLCT3 VLCT2 VLCT1 VLCT0
VLCT3
TABLE TYPE-3 IMAGE COMPONENT. This indicates which table will used block belonging type-3 component. ("0" T0_DC/ T0_AC T1_DC/T1_AC). TABLE TYPE-2 IMAGE COMPONENT. This indicates which table will used block belonging type-2 component. ("0" T0_DC/ T0_AC T1_DC/T1_AC).
VLCT1
TABLE TYPE-1 IMAGE COMPONENT. This indicates which table will used block belonging type-1 component. ("0" T0_DC/T0_AC T1_DC/T1_AC). TABLE TYPE-0 IMAGE COMPONENT. This indicates which table will used block belonging type-0 component. ("0" T0_DC/T0_AC T1_DC/ T1_AC).
VLCT2
VLCT0
NCOMP COMP[1] COMP[0]
COMP[1.0] NUMBER IMAGE COMPONENTS COMP[1.0] contains number image components decoded components
components components components
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ORDER 1_CT[1] 1_CT[0] 2_CT[1] 2_CT[0] 3_CT[1] 3_CT[0]
29C82
4_CT[1] 4_CT[0]
"quantization table", "VLC table"., data associated with each image component clearly specified JPEG header (see appendix ORDER register used associate indirectly component type with component JPEG frame. PROGRAMQ NTAB registers used associate quantization tables with each component type. 1_CT[1.0] TYPE FIRST COMPONENT. These bits code type first component processed.
BLOCK-0 BCT0[7] BCT0[6] BCT0[5] BCT0[4]
2_CT[1.0] TYPE FIRST COMPONENT. These bits code type second component processed. 3_CT[1.0] TYPE FIRST COMPONENT. These bits code type third component processed. 4_CT[1.0] TYPE FIRST COMPONENT. These bits code type fourth component processed.
BCT0[3]
BCT0[2]
BCT0[1]
BCT0[0]
BCT0[7.0] NUMBER SUCCESSIVE BLOCKS TYPE-0 COMPONENT.
BLOCK-1 BCT1[7] BCT1[6] BCT1[5] BCT1[4] BCT1[3]
BLOCK-0 register indicates bits) number successive blocks contained MDU.
BCT1[2]
BCT1[1]
BCT1[0]
BCT1[7.0] NUMBER SUCCESSIVE BLOCKS TYPE-1 COMPONENT.
BLOCK-2 BCT2[7] BCT2[6] BCT2[5] BCT2[4] BCT2[3]
BLOCK-1 register indicates bits) number successive blocks contained MDU.
BCT2[2]
BCT2[1]
BCT2[0]
BCT2[7.0] NUMBER SUCCESSIVE BLOCKS TYPE-2 COMPONENT.
BLOCK-3 BCT3[7] BCT3[6] BCT3[5] BCT3[4] BCT3[3]
BLOCK-2 register indicates bits) number successive blocks contained MDU.
BCT3[2]
BCT3[1]
BCT3[0]
BCT3[7.0] NUMBER SUCCESSIVE BLOCKS TYPE-3 COMPONENT.
BLOCK-3 register indicates bits) number successive blocks contained MDU.
Rev. (20/05/94)
29C82
Initialisation
Before used, 29C82 programmed microprocessor follows RESET CONTROL register partial reset, complete reset achieved forcing RESET order load NBLOCK register load MUXGEN register load table (example appendix load quantization tables (example appendix
write register PROGRAMQ write CONTROL register (START=0). START CONTROL register Load input FIFO (FIFE). This step programmed after setting CL_FIFE before setting START bits. After 29C82 started decoding, microprocessor able poll STATUS register state output discover state progress current decoded block.
Electrical Characteristics
Absolute Maximum Ratings
earth -0.5V Input/output voltage -0.3V 0.3V Storage temperature +150°C
Operating Characteristics
supply voltage 4.5V +5.5V Temperature 70°C Load capacity 50pF each output
Electrical Characteristics
PARAMETER
Input voltage Input voltage inputs except Test Test Input current leakage Test Test Output voltage, level Output voltage, level Dynamic consumption 6.4mA 6.4mA VCC=5V, 20MHz 120mA I=5µA I=5µA 2.2V 100µA 0.4V
CONDITIONS
0.8V
Rev. (20/05/94)
MATRA Timings
10%. Temperature 70°C load outputs
NAME
tphch tchpl tchqv tchqx tchqz tdvwh twhdx twhyh twlyl tchcl tclch trlyl trhyh trldv trldx trhdz tclk twlwh twhax tavw trlrh trhax tavr setup time hold time PIXEL_BUS data delay PIXEL_BUS floating PIXEL_BUS floating DATA[0.7] setup time DATA[0.7] hold time CS/WR high READY delay CS/WR READY delay minimum high pulse width minimum pulse width CS/RD READY CS/RD high READY high RD/CS DATA_BUS data delay RD/CS DATA_BUS floating RD/CS high DATA_BUS floating period write pulse width ADDR[3.0] hold time address hold time (write) pulse width ADDR[3.0] hold time address hold time (read) 1tclk 2tclk 3tclk 6tclk 1tclk 7tclk
29C82
DESCRIPTION
5tclk+30 5tclk+35 5tclk+5
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29C82
Timings
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29C82
Appendix
various stages ADCT
successive stages image de-compression basic JPEG system coding (Huffman) decoding, dequantization Inverse cosine transform.
two-dimensional Cosine Transform
image divided into pixel blocks then polled order shown figure case pixel image 4:2:2 example, image will Figure divided into blocks luminance blocks chrominance.
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29C82
Level transposition
Before applying Cosine Transform unsigned data (Y,Cr,Cb) level transposition performed subtracting (for 8-bit data).
Cosine Transform
each block, Cosine Transform used convert from space domain (the pixels) frequency domain (the coefficients), applying direct Cosine Transform (FDCT).
F(u, 4C(u) C(v)
F(i, cos(2i cos(2j
from frequency domain space domain using inverse Cosine Transform (IDCT).
F(i,
C(u) C(v)F(u, cos(2i cos(2j 1)vpi
Figure
Quantization
essential property Cosine Transform concentration energy coefficients between each block into component some 'low-frequency" components.
Rev. (20/05/94)
Since human very sensitive high-frequency components, these quantized coarser manner. Each coefficient quantized follows F(u,v)0 C(u,v) full division (F(u,v)+(Q(u,v)/2))/Q(u,v) F(u,v) C(u,v) full division (F(u,v) (Q(u,v)/2))/Q(u,v) F(u,v) coefficient before quantization C(u,v) coefficient after quantization Q(u,v) indicates quantization De-quantization performed similar fashion F'(u,v) C(u,v) Q(u,v) Example signal value
29C82
probability
classification probabilities decreasing order, grouping lowest probability values. .52, .25, .11, .11, .52, .25, .12, .11, .52, .25, .52, construction HUFFMAN tree
HUFFMAN coding
average number bits necessary code signal without loss information measured entropy signal. procedure used commonly construct associated variable-length code words known HUFFMAN coding. intuitively associates short code words frequent signal values longer code words less frequent values. association Code
SIGNAL VALUE
root (.52) (.25) (.11) (.11) (.01)
PROBABILITY
HUFFMAN CODE
1100 1101
CODE LENGTH
This technique used JPEG frame coding components after quantization. Each
block coefficients transmitted following order coefficient
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29C82
Appendix
Structure JPEG frame
JPEG image divided into signalling data segments. Each segment starts with FFxx marker notation. last byte marker identifies function Figure
S0F0 FFD8 FFFE FFD8 FFC4 FFC0 IMAGE START COMMENTS QUANTIZATION TABLES TABLES
segment. last data item segment ended with that FFxx aligned byte border.
FRAME Parameter definition sample precisio,n number line,s number samples lin,e number components fram,e vertical sampling factor horizontal sampling facto,r selection quantization table. SCAN Parameter definition number scan components, choice HUFFMAN matrix (AC, DC), choice mode (sequential, progressive). Coded data
FFDA
FFD9
IMAGE
Comments Example fffe 0020 432d 4355 4245 204d 6963 726f 7379 7374 656d 7320 496e 632e 2031 2e30 3000 marker Comment length usable bytes) MATRA Electronic APPLICATION 1992 JPEG image example
Quantization tables
quantization tables always included header frame component type). Example ffdb 007F marker Table length tables bits) Table luminance
Rev. (20/05/94)
table Chrominance (Cr/Cb)
29C82
HUFFMAN Tables Coding coefficients
Only coefficient first block transmitted form absolute value. following coefficients transmitted differentially relation this first block. value coefficient transmitted divided into categories coded bits, ssss, corresponds length delta code sent ssss delta -1,+1 -3,-2,2,3 -7.-4,4.7 -15.-8,8.15 -31.-16,16.31 -63.-32,32.63 -127.-64,64.127 -255.-128,128.255 -511.-256,256.511 -1023.-512,512.1023 -2047.-1024,1024.2047 -4095.-2048,2048.4095 -8191.-4096,4096.8191 -16383.-8192,8192.16383 -32767.-16384,16384.32767 HUF(ssss) HUFFMAN code associated with ssss HUFFMAN table (HUFCODE) associated with ssss transmitted directly JPEG image header. fact tables, [BITS] [HUFVAL], used this [BITS] bytes long contains number ssss values (categories) coded bit, bits, bits bits HUFFMAN table. [HUFVAL] contains list ssss values (categories) sorted into ascending order length HUFFMAN code bits). basic system, there maximum [BITS] [HUFVAL] pairs, transmitted coefficients.
coefficients coded following manner
HUF(ssss) coefficient
Example ffc4 01a2 0001 0501 0101 0101 00100 0000 0000 0000 0001 0203 0405 0607 0809 0a0b 0003 0101 0101 0101 0101 0100 0000 0000 0001 0203 0405 0607 0809 0a0b
marker Table length table BITS matrix HUFVAL matrix elements) table BITS matrix HUFVAL matrix elements)
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29C82
Creation matrices [EHUFCO] [EHUFSI] from [BITS] [HUFVAL] (JPEG standard)
following algorithm used create [HUFSIZE] table containing length HUFFMAN codes
associated with ssss function decreasing priority values
following algorithm used create [HUFCODE] table containing HUFFMAN codes
associated with ssss function decreasing priority values
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29C82
following algorithm used reorganise HUFSIZE HUFCODE function decreasing ssss (HUFVAL) values
Example ssss EHUHSI EHUFCO 111111110
reconstitution HUFFMAN decoding tree (see appendix accomplished using EHUFCO EHUFSI
Coding coefficients
coefficients transmitted divided into categories, coded bits, nnnnssss. nnnn gives number coefficients equal between non-zero coefficients, ssss gives amplitude category coefficients.
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29C82
00000000 represents which end-of-block indicator. ssss coefficient -1,+1 -3,-2,2,3 -7.-4,4.7 -15.-8,8.15 -31.-16,16.31 -63.-32,32.63 -127.-64,64.127 -255.-128,128.255 -511.-256,256.511 -1023.-512,512.1023 -2047.-1024,1024.2047 -4095.-2048,2048.4095 -8191.-4096,4096.8191 -16383.-8192,8192.16383 -32767.-16384,16384.32767 coefficients coded following manner Example 0002 0103 0302 0403 0605 0404 0000 017d 0102 0300 0411 0612 2131 4106 1351 6107 2271 1432 8191 a108 2342 b1c1 1552 d1f0 2433 6272 8209 0a16 1718 191a 2526 2728 292a 3435 3637 3839 3a43 4445 4647 4849 4a53 5455 5657 5859 5a63 6465 6667 6869 6a73 7475 7677 7879 7a83 8485 8687 8889 8a92 9394 9596 9798 999a a2a3 a4a5 a6a7 a8a9 aab2 b3b4 b5b6 b7b8 b9ba c2c3 c4c5 c6c7 c8c9 cad2 d3d4 d5d6 d7d8 d9da e1e2 e3e4 e5e6 e7e8 e9ea f1f2 f3f4 f5f6 f7f8 f9fa 0002 0102 0404 0304 0705 0404 0000 0277 0001 0203 1104 0521 3106 1241 5107 6171 1322 3281 0814 4291 a1b1 c109 2333 52f0 1562 72d1 0a16 2434 e125 f117 1819 1a26 2728 292a 3536 3738 393a 4344 4546 4748 494a 5354 5556 5758 595a 6364 6566 6768 696a 7374 7576 7778 797a 8283 8485 8687 8889 8a92 9394 9596 9798 999a a2a3 a4a5 a6a7 a8a9 aab2 b3b4 b5b6 b7b8 b9ba c2c3 c4c5 c6c7 c8c9 cad2 d3d4 d5d6 d7d8 d9da e2e3 e4e5 e6e7 e8e9 eaf2 f3f4 f5f6 f7f8 f9fa
table BITS matrix HUFVAL matrix (162 elements)
table BITS matrix HUFVAL matrix (289 elements)
HUF(nnnssss)
coefficient
HUF(nnnnssss) HUFFMAN code associated with nnnnssss HUFFMAN table (HUFCODE) associated with nnnnssss transmitted directly JPEG image header coefficients). fact tables, [BITS] [HUFVAL], used this. bytes, [BITS] contains number nnnnssss values (categories) coded bit, bits, bits bits HUFFMAN table. [HUFVAL] contains list nnnnssss values (categories) sorted into ascending order length HUFFMAN code bits). basic system, coefificients, there maximum [BITS] [HUFVAL] pairs.
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algorithms given paragraph dealing with coding DCcoefficients used create [EHUFSI] table containing length HUFFMAN codes associated with nnnnssss [EHUFCO] table containing HUFFMAN codes associated with nnnnssss.
29C82
single image component, interleavce mode, where single scan contains data components frame. Within frame, data transmitted form. non-interlace mode, block coefficients which correspond, example, (luminance) Cr/Cb (chrominance). interlace mode, interlacing blocks defined sampling factor Hi,Vi number components scan. following example, scan described three components, with respective sampling factors :1v, :1v, :1v. described following
Start frame (DCT basic mode)
number components frame limited (quadrichromy black, blue, yellow red). Each frame contain several successive scans, each corresponding component image. There scan modes non-interleave mode, where each scan contains
Data data sent with most significant byte leading most significant leading. Example 93fd 1639 9954 7c9e 5fda 653e 667e fe57 3cee 1cee 2df8 ff00 d476 96d1 cd74 e2df 7e0b 7ef3 f7ca bb63 c705 7e99 1c00 f418 ffds
when created during coding, byte added data
marker EOI, image
Example FFC0 0011 0100 0100 SOF0 marker fields length sample precision bits number lines number samples line number image components frame component horizontal sampling factor vertical sampling factor selection quantization table component horizontal sampling factor vertical sampling factor selection quantization table component horizontal sampling factor
Scanning ffda 000C 003F00
vertical sampling factor selection quantization table start scan marker length field usable bytes) number components scan selection scan component selection HUFFMAN table, selection HUFFMAN table, selection scan component selection HUFFMAN table, selection HUFFMAN table, selection scan component selection HUFFMAN table, selection HUFFMAN table, DCT/Sequential mode,
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29C82
Appendix
Operation Decoder (29C82)
contains HUFFMAN decoding tree (see appendix This tree obtained from [BITS] [HUFVAL] matrices contained frame header
(see appendix following example illustrates extraction parameters from data JPEG frame.
LOADING TABLES
Tables T0-DC T0-AC respectively programmed with
T0-DC
T0-AC
lines) lines) contains address next node leaf) HUFFMAN tree, shifted left, being forced Each word table containing leaf tree will forced number. this case contains ssss nnnnssss) shifted left, being forced
Each table divided into zones bytes tables bytes tables). last extracted from data stream indicated zone addressed. Conventions Each word table containing node HUFFMAN table forced even value. this case
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Figure
29C82
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29C82
DECODING DATA
extraction parameters Each table composed 5-bit words, with forced depending whether word corresponds node leaf tree. Extraction delta from block reading first data initial data stream (after header) extraction parameters
extraction coefficient from data stream data stream 0110011101100101000010000010. delta DC_bloc_0
Extraction delta from block reading fifth data initial data stream (after header) 0110011101100101000010000010. fifth calculation address node leaf) HUFFMAN tree address formed concatenating 8-bit register containing MSB's word corresponding preceding node HUFFMAN tree (after shifting right. (bit obtained address decoding). each coefficient, 8-bit register reset last extracted from data stream
0110011101100101000010000010.
first calculation address node leaf) HUFFMAN tree address formed concatenating 4-bit register containing MSB's word corresponding preceding node HUFFMAN tree (after shifting right). each coefficient, register reset last extracted from data stream
ADDRESS data (MSB) contents 4-bit register reading address table [@(00)] 02H. This memory point corresponds node line with conventions) right shift load into 4-bit register
ADDRESS data (MSB) contents 8-bit register reading address table
data contents 4-bit register reading data data stream 0110011101100101000010000010. concatenation with 4-bit register
[@(00)] 02H. This memory point corresponds node line with conventions) right shift load into 8-bit register data contents 8-bit register
reading data data stream 0110011101100101000010000010. concatenation with 8-bit register 101H
reading address [@(11H)] 05H. This memory point corresponds leaf line with conventions) right shift ssss coefficient block bits long.
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reading address 101H [@(101H)] 03H. This memory point corresponds leaf line with conventions) right shift nnnnssss 00000001 nnnn number zero coefficients ssss first coefficient block long. extraction coefficient from data stream data stream 0110011101100101000010000010. AC_1_bloc_0
29C82
Note nnnnssss corresponds detection end-of-block (EOB) character. nnnnssss corresponds detection escape character zero coefficients). this case following coefficients then resume decoding sequence re-initialising 8-bit register
Appendix
Example Program Creation Table
CONSTRUCTION TABLES TABLES void vlctable_dc (BITS, VALUE, HUFCODE, SIZE) BITS[17] VALUES[16] HUFCODE[16] PNTR SIZO[16] WORD unsigned CODE (I=0 I++) {SIZO[I] PNTR (I=1 I++) (J=1 J<=BITS[I] J++)
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{SIZO[PNTR] PNTR (I=0 I++) {HUFCODE[I] SIZE[I] WORD CODE SIZO[0] HUFCODE[VALUES[WORD]] CODE SIZE[VALUES[WORD]] HUFCODE[VALUES[WORD]] CODE SIZE[VALUES[WORD]] CODE++ WORD++ while (SIZO[WORD] (SIZO[WORD] {CODE (CODE ;}while (SIZO[WORD] else {break while (SIZO[WORD] return TABLES void vlctables_ac (BITS, VALUES, HUFCODE, SIZE) BITS[17] VALUES[256] HUFCODE[256] SIZE[256] PNTR SIZO[256] WORD unsigned CODE (I=0 I++) {SIZO[I] PNTR (I=1 I<17 I++) (J=1 J<=BITS[I] J++) {SIZO[PNTR] PNTR (I=0 I++) {HUFCODE[I] SIZE[I] WORD CODE SIZO[0] HUFCODE[VALUES[WORD]] CODE SIZE[VALUES[WORD]]
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HUFCODE[VALUES[WORD]] CODE SIZE[VALUES[WORD]] CODE++ WORD++ while (SIZO[WORD] (SIZO[WORD] {CODE (CODE }while (SIZO[WORD] else {break
29C82
while (SIZO[WORD] return CONSTRUCTION DECODING TREE CONSTRUCTION TREE void makecodar_dc (HUFCODE, SIZE, PARR) HUFCODE[16] SIZE[16] PARR[32] INDEX NEXT CODENO CODESIZE CODELO (I=0 I++) {PARR[I] NEXT (CODENO CODENO CODENO++) (SIZE[CODENO] INDEX CODESIZE SIZE[CODENO] CODELO HUFCODE[CODENO] CODELO (CODELO CODESIZE)) (I=1; CODESIZE I++) (CODELO INDEX (PARR[INDEX] INDEX PARR[INDEX] else NEXT PARR[INDEX] NEXT INDEX NEXT CODELO (CODELO (CODELO INDEX PARR[INDEX] (CODENO
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return CONSTRUCTION TREE void makecodar_ac (HUFCODE, SIZE, PARR) HUFCODE[256] SIZE[256] PARR[512] INDEX NEXT CODENO CODESIZE CODELO (I=0 I++) {PARR[I] NEXT (CODENO CODENO CODENO++) (SIZE[CODENO] INDEX CODESIZE SIZE[CODENO] CODELO HUFCODE[CODENO] CODELO (CODELO CODESIZE)) (I=1 CODESIZE I++) (CODELO INDEX (PARR[INDEX] INDEX PARR[INDEX] else NEXT PARR[INDEX] NEXT INDEX NEXT CODELO (CODELO (CODELO INDEX PARR[INDEX] (CODENO return
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Appendix
Decoupling Layout Precautions
recommended that ceramic capacitors type should used. order improve decoupling, compensate voltage peaks inductive origin, second capacitor placed parallel with each capacitor. This additional capacitor should placed close possible package.
Layout precautions
order reduce noise, recommended that card with levels metalling used, level which reserved earth plane second Vcc.
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Appendix
Application
HM67202 FIFO enables frequency accesses DATA reduced, thereby improving system flexibility. latch placed ADD[3.0] sampled
rising edge active). flag must re-synchronised signal clock) before injected into input.
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Appendix
29C82 Evaluation Board (8-bit)
Schematic EPLD equation
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C22V10
{29C82 Evaluation PC-Board} {82EPC.CYP} Board Logic DECODING} {Appli.Lab 13.11.92}
CONFIGURE
ICLK /RDF /EFF /HFF /C82 /WRF POUT OCLK (node (node (node (node (node 10), (node 11), (node NOREG), (node NOREG), {Input} (node NOREG), {Input} (node NOREG, NINV), (node NOREG, NINV), (node NOREG), (node NINV), (node NOREG), (node NOREG), {Input} (node NOREG, NINV), (node (node (node 13),
EQUATIONS
{Read Control FIFO Device. 310h 317h.} <oe> <som> {reading Empty Flag from FIFO. 318h 31Fh.} <oe> <sum> /EFF {Chip Select Control 29C82 Device. 300h 30Fh.} <oe> <sum> /A11*/A10*A9*A8*/A7*/A6*/A5*/A4 {Address Latch Enable Latch Device type 74LS373.} <oe> <sum> /A11*/A10*A9*A8*/A7*/A6*/A5*RD <sum> /A11*/A10*A9*A8*/A7*/A6*/A5*WR {Write Control FIFO Device.} <oe> <sum> /ICLK*POUT {Pixel request 29C82 synchronized Clock.} {Available only Half Full Flag from FIFO Present.} <oe> <sum> /HFF {Clock 29C82 synchronous with /WRF.} <oe> <sum> ICLK
OCLK
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Ordering Information
29C82
TEMPERATURE RANGE COMMERCIAL INDUSTRIAL
PACKAGE PLCC
Part number 29C82
information contained herein subject change without notice. responsibility assumed MATRA using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
Rev. (20/05/94)

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