5501/5502/5503 Overview SiS5501 SiS5502 SiS5503 PCI/ISA Cache Mem

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

5501/5502/5503 Overview SiS5501 SiS5502 SiS5503 PCI/ISA Cache Mem

Datasheet Thumbnail

Top Searches for this datasheet

Pentium/P54C PCI/ISA Chipset
5501/5502/5503 Overview
SiS5501 SiS5502 SiS5503 PCI/ISA Cache Memory Controller (PCMC) Local Data Buffer (PLDB) System (PSIO)
whole SiS5501, 5502, 5503 provides fully integrated support Pentium/P54C PCI/ISA system. chipset developed using very high level function integration system partitioning. With SiS5501, SiS5502, SiS5503 chipset, only TTLs (include DRAM address buffer) required implement cost, high performance, Pentium/P54C PCI/ISA system. Figure shows system block diagram.
SRAM
Pentium P54C
Address Data HOST
PCMC
5501 Address/Data
DRAM
PLDB
5502
PSIO
5503
Buffers
Drives
Local Device Device
Local Device Device
Address Data
Figure System Block Diagram
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
SiS5501
Features
Supports 510\60, 567\66, 735\90, 815\100 Pentium Processor Supports Other Pentium Compatible Supports Pipelined Address Mode Pentium P54C Processor Integrated Second Level Cache Controller Write Through Write Back Cache Modes bits bits with Direct Mapped Organization Supports Standard Burst SRAMs Supports KBytes MBytes Cache Sizes Cache Read/Write Cycle 3-2-2-2 4-2-2-2 Using Standard SRAMs Cache Read/Write Cycle 3-1-1-1 Using Burst SRAMs Integrated DRAM Controller Supports Banks SIMMs MBytes Cacheable Main Memory Supports Table- Free DRAM Configuration Concurrent Write Back CAS#-before-RAS# Transparent DRAM Refresh Supports 256K/512K/1M/2M/4M/16M 70ns Fast Page Mode DRAM Fastest Burst Cycle Speed 6-3-3-3 6-2-2-2 respectively Programmable CAS# driving Current Programmable DRAM Speed Programmable Non-Cacheable Regions Option Disable Local Memory Non-Cacheable Regions Shadow Increments KBytes Supports Pentium/P54C Mode Supports Stop Clock Provides High Performance Arbiter Supports Four Masters Supports Rotating Priority Mechanism Hidden Arbitration Scheme Minimizes Arbitration Overhead Integrated Bridge Translates Cycles into Cycles Provides CPU-to-PCI Read Assembly Write Disassembly Mechanism Translates Sequential CPU-to-PCI Memory Write Cycles into Burst Cycles Burst Write Pace X-2-2-2-. Burst Read Cache X-2-2-2-. Burst Read DRAM X-3-2-3-2-. Cache Snoop Filters Ensure Data Coherency Minimize Snoop Frequency Meet Specification Buffer Strength 208-Pin PQFP Package 0.6µm CMOS Technology
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller Functional Block Diagram
HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA HITM# A20M# KEN# EADS# CPURST INIT
INTERFACE
INTERFACE
C/BE[3:0]# AD[31:0] FRAME# IRDY# TRDY# DEVSEL# STOP# SERR# REQ[3:0]# GNT[3:0] PLOCK# PCICLKO PCICLKI PCIRST#
TAG[7:0] ALTWE# TAGWE# KA4X KA3/KA4Y KREX#/ COE0# KREY#/ COE1# KWEX# KWEY# CALE ADSC#/
FLUSH#
BUFFER CONTROL
CACHE CONTROL
HCR[1:0] ADLE# ADOE MDLE CMPSH CMPOP CPPSH CPPOP PRDLE HGDW PARITY# SMOUT WAKEUP[1:0] SMI# SMIACT# STPCLK# SIOREQ# SIOGNT# KBRST#/BREAK# TURBO# ACLK PWRGD
ADSV# KCE[7:0]#/ CWE[7:0] RAS[3:0]# CAS[7:0]# RAMW# MA[11:0] *RAS[7:4]# DRAM CONTROL
MISC.
SiS5501 Functional Block Diagram
Multi-function
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller General Description
SiS5501(PCMC) bridges between host local bus. SiS5501 (PCMC) monitors each cycle initiated CPU, forwards cycle does target local memory. local memory cycles, built-in Cache DRAM Controller assume control secondary cache, DRAMs, SiS5502 (PLDB). SiS5501 (PCMC) also guides SiS5502 (PLDB) correct data flow. Green functions provided.
Interface
SiS5501 designed support Pentium/P54C host interface 66.667/60/50 MHz. host data DRAM 64-bit wide. SiS5501 supports pipelined addressing mode Pentium/P54C issuing next address signal, NA#. only generated cases: burst read cache DRAM, single read DRAM. PCMC supports write back(WB) write through(WT) cache PCMC cache. cache snooped assertion EADS# when HOLD state. PCMC issues CPUHOLD Pentium/P54C response assertion master requests(REQ[3:0]#, SIOREQ#). Upon receiving CPUHLDA from CPU, does immediately assert GNT[3:0]# SIOGNT# until both posted write buffer Memory write buffer empty. During inquire cycles, CPUHOLD negated temporarily allow write back inquired modified line DRAM.
Cache Controller
built-in Cache Controller uses direct-mapped, scheme, which configured either write through write back mode. Both standard burst SRAMs supported. Table shows cache sizes that supported SiS5501, with corresponding sizes, data sizes, cacheable memory sizes. Tables summarize performance options when either standard SRAMs Burst SRAMs used.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Table Cache Size 128K 256K 512K 512K
Data 8Kx8x8 8Kx8x16 32Kx8x8 32Kx8x16 64Kx8x8 128Kx8x8 64Kx8x16 128Kx8x16
2Kx8 4Kx8 8Kx8 16Kx8 16Kx8 32Kx8 32Kx8 64Kx8
Alter 2Kx1 4Kx1 8Kx1 16Kx1 16Kx1 32Kx1 32Kx1 64Kx1
Cacheable Size 128M 128M 256M 256M 512M
Interleaved
PCMC also provides alternative save dirty SRAM chip. This accomplished sharing alter with address bits same 8-bit wide RAM. System uses this implementation supports address bits dirty bit. doing cacheable local memory sizes reduced half original sizes indicated Table reality, Cacheable DRAM Size determined Max. Cacheable Size described table Non-cacheable Area defined register 57h, 58h, Segment Cachability defined register 53h, 54h, 55h, 56h. But, Cacheable size only determined maximum DRAM size, i.e., 512M bytes. Thus, cycles with address ranging over Cacheable Size within 512M bytes also cacheable behavior KEN# ruled Cacheability. Note that only code segment cacheable L1/L2, data portion segment cacheable L1/L2. Table Burst SRAM Speed Setting Cycle type 66,60 Burst read 3/4-1-1-1 3/4-2-2-2 Burst write 3/4-1-1-1 3/4-2-2-2 Single read Single write
50MHz 3/4-1-1-1 3/4-2-2-2 3/4-1-1-1 3/4-2-2-2
Note burst SRAM speed 66/60 50MHz, X-Y-Y-Y recommended setting.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Table Asynchronous SRAM speed setting (apply read write cycle) 50MHz cache configuration Data Data 3-1-1-1 interleave -15ns 3-1-1-1 non-interleave -3-2-2-2 interleave 15ns 15ns 15ns 15ns 20ns 3-2-2-2 non-interleave 15ns 15ns 15ns 15ns 20ns 3-3-3-3 interleave 15ns 15ns 15ns 15ns 20ns 3-3-3-3 non-interleave 15ns 15ns 15ns 15ns 20ns 4-1-1-1 interleave 15ns 12ns 15ns 12ns 20ns 4-1-1-1 non-interleave -4-2-2-2 interleave 15ns 15ns 20ns 20ns 20ns 4-2-2-2 non-interleave 15ns 15ns 20ns 20ns 20ns 4-3-3-3 interleave 15ns 20ns 20ns 20ns 20ns 4-3-3-3 non-interleave 15ns 20ns 20ns 20ns 20ns 5-1-1-1 interleave 20ns 12ns 20ns 12ns 20ns 5-1-1-1 non-interleave -5-2-2-2 interleave 20ns 15ns 20ns 20ns 20ns 5-2-2-2 non-interleave 20ns 15ns 20ns 20ns 20ns 5-3-3-3 interleave 20ns 20ns 20ns 20ns 20ns 5-3-3-3 non-interleave 20ns 20ns 20ns 20ns 20ns
Data 15ns -20ns 20ns 20ns 20ns 15ns -20ns 20ns 20ns 20ns 15ns -20ns 20ns 20ns 20ns
DRAM Controller
5501 support rows DRAM, memory size from MBytes MBytes. Each populated bank could single double sided bits DRAM Extended Data Output) DRAM. also permissible DRAM bank DRAM bank without order. installed DRAM type 256K 512K SIMMs. However, since shares same signal Bank should excluded DRAM used. DRAM Boundary Register, register 77h~70h) used configure total amount memory. 7~0, corresponds host address 28~21 used compare against host address bank 7~0. Contents these registers reflect boundary address, that means value programmed last will DRAM size system. DBR0 Reg. Total amount memory Bank DBR1 Reg. Total amount memory Bank Bank DBR2 Reg. Total amount memory Bank Bank Bank DBR7 Reg. Total amount memory Bank Bank
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
following examples show registers used determine memory size. Example system memory populated banks single-sided DRAM, which located Bank This yields Bytes DRAM totally. registers programmed follows: DBR0 DBR1 DBR2 totally DBR3 DBR4 totally DBR5 totally DBR6 totally DBR7 totally Example system memory populated banks single-sided DRAM, which located from Bank This yields Byte DRAM totally. registers programmed follows: DBR0 DBR1 DBR2 DBR3 DBR4 totally DBR5 totally DBR6 totally DBR7 totally Bytes Bank Bytes Bank Bytes Bank Bytes Bank empty empty empty empty Bytes totally Bytes totally Bytes totally Bytes totally Bytes Bytes Bytes Bytes empty Bytes Bank empty Bytes Bank empty empty empty empty Byte totally Bytes totally Bytes Bytes totally Bytes Bytes Bytes Bytes
12-bit multiplexed row/column address MA[11:0] allows PCMC support 256K, 70ns fast page mode DRAMs. Table shows corresponding request address bits used column address address DRAM. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Table Generation Table
Body Type 256k 512k
improve write DRAMs performance, there level built-in CPU-to-Memory posted write buffer with deep (CTMPB). single writes burst writes buffered. read miss/line fill cycle, write-back data from cache also buffered into CTMPB. same time, PCMC starts reading from DRAMs. buffered data written DRAMs when read cycle completes. With this concurrent write back policy, many wait states eliminated. However, other cycle targeting DRAMs will suspended until CTMPB empty. Table outlines read write DRAM cycle performance based 70ns DRAMs. Table DRAM Performance Cycle type 66,60 read 6/9/12-3-3-3 7/10/13-4-4-4 (page hit/row miss /page miss) 6/9/12-2-2-2 7/10/13-2-2-2 posted write 3/4/5-1-1-1 (CPU Buffer) 3/4/5-2-2-2 3/4/5-3-3-3 write retire rate 3/4/5 (Buffer DRAM) Note: X-Y-Y-Y recommended setting.
50MHz 6/9/12-3-3-3 7/10/13-4-4-4 6/9/12-2-2-2 7/10/13-2-2-2 3/4/5-1-1-1 3/4/5-2-2-2 3/4/5-3-3-3 3/4/5
DRAM Type standard page mode standard page mode standard page mode, standard page mode, standard page mode, standard page mode
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Table DRAM speed setting based 70ns DRAMs (apply read write cycle) Register 66MHz 60MHz 50MHz read pulse width write pulse width precharge time 1T/2T 1T/2T precharge time delay time refresh active time DRAM write push delay DRAM pulse width 1T/2T 1T/2T DRAM precharge time 1T/2T 1T/2T
Note: burst DRAM read cycle 6-3-3-3 when precharge time precharge time burst DRAM read cycle increased 7-4-4-4. When type DRAMs installed register bits[1:0] "11" (1T), burst DRAM read cycle 6-2-2-2. standard Fast Page mode DRAM timing applied, register bits[1:0] "00". fact, 5501 detect type DRAM applies optimal timing automatically.
Arbiter
SiS5501 contains high performance hidden arbitration scheme that allows efficient sharing among five Masters CPU. Note that master reserved PSIO chip. SiS5501 employs priority rotation scheme that done different layers. first layer shared between PSIO four Masters group. second layer consists four masters with equal priority. Arbitration done both layers. winner arbitration among four masters arbitrates against PSIO. Fair rotation scheme applies only layer level. arbitration scheme assures that master channels (represented PSIO) access with minimal latency. PSIO given high level priority assure compatibility with traditional expansion boards that require short latency. This implementation together with Programmable Bursting Address Counter guarantees device will starved during master long bursting cycle. example, When maximum bursting length bytes, maximum arbitration latency PSIO, master about 12us, 40us respectively. following figures detail rotation arbitration structure corresponding timing diagram.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Rotation Arbitration Scheme:
GRANT PRIORITY
G0123
Notation: SW1: switch path from node G0123 GRANT PRIORITY SW2: switch path from node node G0123 SW3: switch path from node node SW4: switch path from node node G01, G23, G0123: intermediate nodes request from PSIO requests from device device device device respectively. Initial Path Parking: GRANT PRIORITY-G4 G0123-G01 G01-G0 G23-G2 Rule Rotating Priority Arbitration: GRANT PRIORITY will choose path whenever encounters optional path. will granted Daisy Chain Path switches will toggled from GRANT PRIORITY request node (G4, them have been utilized Example: Initial Priority: G01, PSIO(G4) Request SIOGNT# asserted toggled G0123 (since been utilized) Priority change Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
PSIO, REQ3, REQ2, REQ1, REQ0 requesting GNT0# asserted SW1, toggled respectively (since they have been utilized) Priority change REQ3, REQ2, REQ1, REQ0 active GNT2# asserted SW2, toggled respectively (since they have been utilized) Priority change REQ3, REQ2, REQ1, REQ0 active GNT1# asserted SW2, toggled respectively (since they have been utilized) Priority change REQ3, REQ2, REQ1, REQ0 active GNT3# asserted SW2, toggled respectively (since they have been utilized) Priority change During there request comes from PSIO, Arbiter will grant PSIO.
Arbiter Rotation Arbitration scheme CPUCLK PCICLK REQ[3:0]# SIOREQ# GNT[3:0]# SIOGNT# HOLD CPUHOLD CPUHLDA HLDA FRAME# IRDY# 501arbi Note HOLD internal signal
master burst long target source/sink data, other agent requests bus. However, specifies mechanisms that master's tenure presence other requests, that predictable acquisition latency achieved. Master Latency Timer(LT) that implemented into PCMC, other Target Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Initiated Termination. SiS5501, Programmable Bursting Address Counter(PBAC) implemented disconnect master during long bursting cycle. this way, high throughput maintained, latency still kept reasonably small. Note that bursting length naturally applied master local memory accessing. When master accesses non-local memory target, master target should together have responsibility maintaining reasonable latency, system arbiter does. arbiter asserts only GNT# time. 5501 also implemented time-out counter prevent faulty device hugging bus. granted device currently idle, clocks limitation that device should assert FRAME# during period time. time-out occurs, arbiter will mask request line, therefore desserts GNT#. When this happens, devices start arbitration again. Note that PSIO free this constraint. 5501 master will also mask PSIO request arbiter LOCK# asserted keep master channels target latency within specification. 5501 arbiter also allowed force system back each time after SIOREQ# serviced. This function disabled default, enabled register PCMC Configuration space.
Bridge
2.8.1 Master Controller Master Controller forwards cycles targeting local memory bus. case 64-bit request misaligned 32-bit request, PCMC assumes read assembly write disassembly control. level posted write buffer (CTPPB) implemented improve memory write performance. Except on-board memory write cycles, cycles forwarded will suspended until CTPPB empty. memory write cycles, data pushed into CTPPB full. pushed data are, later time, written bus. consecutive written data incremental sequence, they will transferred burst manner. burst transfer rate always X-2-2-2-. until exhausted. master interface read data from write data utmost speed wait state. This fact that PCMC drives address PLDB drives data. That necessitates turn around cycle between address data phases. PCMC provides mechanism converting standard cycles Configuration cycles bus. Configuration Mechanism Specification page used cycle conversion. PCMC always intercepts first interrupt acknowledge cycle from bus, forwards second interrupt acknowledge cycle onto bus.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
2.8.2 Slave Controller SiS5501 operates slave whenever master requests access SiS5501 resource such Cache, DRAM SiS5501 Internal registers. Note that internal registers only accessed SiS5501 itself when cycle. SiS550x PCI/ISA system, placed HOLD state before granting master. following figure shows behavior CPUHOLD/CPUHLDA response masters requests. Only linear ordered cycles supported PCMC slave interface.
CPUCLK PCICLK REQ# HOLD CPUHOLD CPUHLDA HLDA GNT# FRAME# IRDY# CIP# park Note HOLD,CIP# (current progress) internal signal drives master drives park
501req
master local memory access conducted until snoop cycle completed. snoop cycle used inquire first level cache maintain coherency between first level second level caches main memory. Snoop cycles performed driving master address onto asserting EADS#. Depending status HITM# clocks after assertion EADS#, PCMC conducts master cycles table outlines.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Table Master Read Cycle Miss Unmodified) Miss Unmodified) HitM
Miss (Dirty !Dirty) Miss
HitM
(Dirty !Dirty)
Data Transfer Data transfer from DRAM Data transfer from Data first written back from DRAM. Then, master gets data from DRAM. Data first written back from Then, master gets data from line marked dirty Data Transfer Data transfer from DRAM Data transfer from DRAM Dirty changed. Data first written back from DRAM. Then, master writes data DRAM. Data first written back from Then, master writes data DRAM. Line marked dirty
Master write Cycle Miss Unmodified) Miss Miss Unmodified) (Dirty !Dirty) HitM Miss
HitM
(Dirty !Dirty)
snoop filter implemented prevent need multiple inquires same line line inquired previously. support snoop filter, Snoop Address Latch (SAL) Line Comparator implemented. line comparator used determine Address (NA) same content SAL. not, loaded into SAL, snoop cycle issued. addition, Valid association with used ensure snoop filtering effective only when HLDA asserted. simplified filter algorithm Write Back Mode NA=SAL master write cycle, PCMC only issues EADS#. does wait status HITM#. NA=SAL master read cycle, snoop cycle EADS# issued. NASAL master cycle, PCMC issues snoop cycle EADS#, then monitors status HITM#. During burst transaction, PCMC automatically generates snoop cycle when address advances across line. Write Through Mode following cases, PCMC only generates EADS#. ignores logic HITM#. NA=SAL master write cycle, During burst transaction, address advances across line. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
SiS550x, signal P54C should connected W/R# that driven SiS5501 master cycle. this way, SiS5501 invalidate line that currently inquired assertion EADS# master write cycles. PCMC slave interface supports burst transfers. burst transfer will disconnected (retry) transfer goes across bytes(or KBytes selected Register 5Dh, address boundary. This fact that address generator, support burst transfer, only address bytes. this way, most cache lines uninterruptedly transferred they state cache. Another reason constraint that page miss occur only once during entire bursting transaction since maximum bursting length always within page size used DRAM master writes buffered deep Memory posted write buffer (PTMPB). PCMC always packs aligned write data into write buffer, then retires into DRAM array cache. master write performance, utmost, X-2-2-2- master reads through read buffer with which burst transfers perform pace X-2-2-2-. (from cache), X-3-2-3-2-. (from DRAMs). Concurrent refresh will still performed when into Hold state. DRAM idle, refresh conducted time. refresh request occurs same time that master wants access DRAM, arbitration scheme employed resolve conflict. refresh request thus service while master accessing suspended until refresh cycle completed. Although refresh DRAM bus, most refresh cycle conducted each individual transaction, i.e. each Frame# initiating. other hand, refresh also deferred until DRAM idle. SiS550x system, refresh postponed more than worst case when master reading whole lines through burst transaction. 2.8.3 Speed Setting following settings apply system environment, even though system running 66MHz while running 33MHz.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Table setting latency from ADS# monitor local memory status CAS# pulse width master write cycle latency from disarming "full" assertion BRDY# pending write cycle latency from reading L2/DRAM assertion TRDY# master read cycles latency from packing Qword into PTMPB assertion CAS#(or KWE#) latency from TRDY# BRDY# read/write slave cycles Register Setting Unit CPUCLK PCICLK CPUCLK
PCICLK PCICLK CPUCLK
Green Function
following paragraphs Power Management Unit features description: 2.9.1 Power States provides different power management states, which described following sections. Monitor Standby State Monitor will blanked external devices turned through SMOUT when Monitor standby timer expires. Monitor Standby monitors following events: 1-15 HOLD Each sets mask bits, wake mask, other standby mask. HOLD includes local masters master request. Each event maskable. event happens during monitored period timer expires, generated monitor enters standby state. Once Monitor standby state, event from IRQ1-15, HOLD will cause which brings Monitor back normal state. time slot Monitor standby timer programmable 6.6sec, 0.84sec, 13.3ms, 1.6ms. (ii) System Standby State
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
system standby timer expires, generated system enter system standby state. following events happen: STPCLK# asserted stop clock hard disk drives spindle motors turned serial, parallel ports programmable port turned Once STPCLK# asserted, events from IRQ1-15, NMI, HOLD, INIT will cause STPCLK# de-asserted. Hard disk motors, serial, parallel programmable ports were turned off, they will back normal state only when they accessed. System Standby monitored events (each event maskable) Programmable ports (one 10-bit port, another a16-bit port) 1-15 (each sets mask bits Monitor Standby State) HOLD Hard Disk ports 1F0-1F7h, 3F6-3F7h, 170-17Fh, 320-32Fh) Serial ports 2F8-2FFh, 3F8-3FFh, 2E8-2EFh, 3E8-3EFh) Parallel ports 278-27Fh, 378-37Fh, 3BC-3BEh) A0000-AFFFFh B0000-BFFFFh Address trap (Video RAM) C0000-C7FFFh Address trap (Video BIOS) 3Bx-3Dxh (Video port) time slot System standby timer programmable sec, sec, 70ms, 8.85ms. (iii) Throttling state throttling state, STPCLK# asserted de-asserted periodically. This function maskable. throttling timer (Registers 62h) programmable time slot 35us. 2.9.2 Break Switch Whenever break switch pressed, caused enter leave power saving state. signal from break switch level trigger signal which lasts more than clocks. 2.9.3 Software software enable written Register 60h, SMI# generated software service routine invoked. Register should cleared handler. 2.9.4 Shadow Register order support "suspend HDD" function, necessary shadow registers implemented into 5503. more detailed information, please refer "5503 Register Description" Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
2.10 Configuration Registers
There sets registers PCMC, mapped registers configuration space registers. 2.10.1 Mapped Registers SiS5501 uses configuration space access mechanism This mechanism defines registers, CONFIG_ADDRESS (CF8h) register CONFIG_DATA (CFCh) register. Both CONFIG_ADDRESS CONFIG_DATA read/write registers, length DWORD. mechanism write value into CONFIG_ADDRESS first, then read write CONFIG_DATA. write CONFIG_ADDRESS specifies bus, device that bus, configuration register that device being accessed. read write CONFIG_DATA will cause host bridge translate CONFIG_ADDRESS value requested configuration cycle. definition CONFIG_ADDRESS register described below: Register 0CF8h CONFIG_ADDRESS Register Device Function Register Number Reserved Number Number Number Enable ('1' enabled, disabled) Bits 30:24 Bits 23:16 Bits 15:11 Bits 10:8 Bits Bits enable flag determining accesses CONFIG_DATA should translated configuration cycles bus. Reserved, read only, must return when read. Choose specific system. Choose specific device bus. Choose specific function device. Choose DWORD device's configuration space. read only must return when read.
full Dword write address 0CF8h, host bridge will load data into CONFIG_ADDRESS register. Also, full Dword read 0CF8h, host bridge gets data from CONFIG_ADDRESS register. non-Dword writes reads 0CF8h treated normal cycles. When host bridge SiS5501 sees access that falls inside Dword beginning CONFIG_DATA address, checks enable CONFIG_ADDRESS register. CONFIG_ADDRESS register cycle translated into configuration cycle.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
There types configuration cycle determined number. Number zero, configuration cycle will Type Number non-zero, configuration cycle will Type Type configuration cycle, AD[1:0] driven "00" during address phase cycle. host bridge decodes device number CONFIG_ADDRESS assert only AD[31:11] copies bits [10:2] CONFIG_ADDRESS AD[10:2] directly. instance, when accessing configuration registers SiS5501, because 5501 considered device AD11 will high, bits[10:2] CONFIG_ADDRESS copied AD[10:2] directly. Never AD11 IDSEL line other target device since reserved PCMC. 5501 responds configuration asserting DEVSEL#. type configuration cycle, AD[1:0] driven "01" bits[31:2] CONFIG_ADDRESS copied AD[31:2] directly during address phase cycle. byte-enables data phase both types type configuration cycles copied from HBE[7:4]# directly. following programming sequences example writing register PCMC reading register 5Ch, 5Dh, PCMC. write 51h: EAX, 80000050h 0CF8h, DATA 0CFDh, read 5Ch, 5Dh, 5Fh: EAX, 8000005Ch 0CF8h, 0CFCh Register 0CF9h Turbo Reset Control Register Bits Reserved INIT Enable When this ,the PCMC drives INIT during software reset. When this cleared PCMC drives CPURST during software reset, INIT inactive. BIST Enable. When this well enabled, subsequent initiation hard reset through this register enables Built
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Self Test(BIST) mode CPU. PCMC also drives INIT during hard reset. Reset CPU. There types resets CPU: hard reset using CPURST signal soft reset using INIT signal. this register transitions from PCMC initiates hard reset. hard reset through this register thus requires write operations this register: first write operation writes second write operation writes When this register transitions from PCMC initiates soft reset. sequence initiate soft reset through this register identical that hard reset except written first write operation. Enable System Hard Reset. When this transitions from PCMC initiates hard reset When this transitions from PCMC initiates soft reset CPU. Select Turbo /DeTurbo Mode There ways enter Deturbo mode. through software; another hardware. Software Deturbo: Reg. Reg. Reg. pull GNT#3 high, then Reg. CF9h Hardware Deturbo: Reg. Reg. Reg. pull GNT#3 high, then press deturbo switch. 2.10.2 Configuration Space Mapped Registers Register Bits Register Bits Register Bits Register Bits Register Preliminary V2.0 Vendor byte Vendor high byte Device byte Device high byte Command byte Reserved April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Respond parity. This always since PCMC does support parity checking Bits Reserved Enable special cycle. This always since PCMC does issue special cycle. Enable master. This always allowing PCMC serve master. Enable response memory access. Disables master's accesses local memory Enables master's accesses local memory Enable response access. This always since PCMC does respond cycles. PCMC only responds initiated cycles. Command high byte Reserved Status byte Reserved Status high byte Detected parity error. This always since PCMC does support parity checking bus. Signaled system error. This when PCMC asserts SERR#. This cleared writing Received master abort. This PCMC whenever terminates transaction with master abort. This cleared writing Received target abort. This when transaction terminated with target abort. This cleared writing Signaled target abort. This always since PCMC will terminate transaction with target abort.
Register Bits Register Bits Register
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Bits DEVSEL# Timing DEVT. bits define timing assert DEVSEL#. PCMC asserts DEVSEL# signal within three clocks after assertion FRAME#. default value DEVT=10. fact, PCMC always asserts DEVSEL# medium timing except writes port 60h. Reserved Revision Identification. 00h.
Register Bits
Register 0B~09h Class Code Bits 23:0 060000h
Register Header Type Bits Register Bits DRAM Read Pulse Width Reserved DRAM Write Pulse Width Timing Setting Normal operation. changed CAS# rising edge.) Advance than normal operation. When using DRAM, this must Reserved Cache Toggle /Linear burst mode selection Toggle mode Linear burst mode Bits DRAM type selection 256k Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Register Cache Exist Exist Exist Cache Enable Disable Enable SRAM type Standard Burst Standard SRAM Burst SRAM Cache WT/WB Policy Write-Through mode Write-Back mode Bits Cache Size 64KB 128KB 256KB 512KB Reserved Cache Write-Back Enable Disable Enable Register Bits Standard SRAM Cache speed (Read/Write) 5-x-x-x Slower 4-x-x-x Faster 3-x-x-x Fastest Reserved Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Bits Standard/Burst SRAM Setting (Burst Read/Write cycle Cache Interleave Enable Disable Enable Burst SRAM Cache Burst Cycle 4-x-x-x 3-x-x-x Cache Sizing Enable Normal Operation Always Cache enable Cache Sizing BIOS Refresh Active time Register DRAM precharge time Shadow Read Enable Disable Enable When this enabled, segment shadowed default. Before shadowing, BIOS should turn that reading segment always forwarded bus. Shadow Write Protection Enable Disable Enable After porting shadowed segment into DRAM, this that corresponding shadowed segment writable. Under such circumstances, cycle which intends write segment treated non-local memory cycle, forwarded bus. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Shadow Enable Master Accesses Disable Enable F0000h FFFFFh Shadow Cacheable Non-Cacheable Cacheable Note that only code cacheable L2/L1 when this set. delay time precharge time Enable host CTMPB push rate X-1-1-1 Enable Disable. When this disabled, push rate defined [5:4] register 52h. Register Register Preliminary V2.0 Segment Setting E0000h E3FFFh Shadow Enable E4000h E7FFFh Shadow Enable E8000h EBFFFh Shadow Enable EC000h EFFFFh Shadow Enable E0000h E3FFFh Shadow Cacheable E4000h E7FFFh Shadow Cacheable E8000h EBFFFh Shadow Cacheable EC000h EFFFFh Shadow Cacheable Segment Setting D0000h D3FFFh Shadow Enable D4000h D7FFFh Shadow Enable D8000h DBFFFh Shadow Enable April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Register Register Allocation Non-cacheable Area Local DRAM Bus. local DRAM disabled. Non-cacheable Area Enable Disable Enable Bits Size Non-Cacheable Area (within MBytes) 64KB 128KB 256KB 512KB Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation DC000h DFFFFh Shadow Enable D0000h D3FFFh Shadow Cacheable D4000h D7FFFh Shadow Cacheable D8000h DBFFFh Shadow Cacheable DC000h DFFFFh Shadow Cacheable Segment Setting C0000h C3FFFh Shadow Enable C4000h C7FFFh Shadow Enable C8000h CBFFFh Shadow Enable CC000h CFFFFh Shadow Enable C0000h C3FFFh Shadow Cacheable C4000h C7FFFh Shadow Cacheable C8000h CBFFFh Shadow Cacheable CC000h CFFFFh Shadow Cacheable
SiS5501 PCI/ISA Cache Memory Controller
Bits Register Bits Register Allocation Non-cacheable Area Local DRAM Bus. local DRAM disabled. Non-cacheable Area Enable Disable Enable Bits Size Non-Cacheable Area (within MBytes) 64KB 128KB 256KB 512KB Bits Register Bits Register Fast Gate Emulation Enable Disable Enable sequence generate A20M# write port followed write port with data 00h. When this enabled, SiS5501 responds cycle asserting DEVSEL# slowest timing. Otherwise, cycle subtractively decoded 5503, then passed 8042 bus. Fast Reset Emulation Enable Non-Cacheable Area (within MBytes) Non-Cacheable Area (within MBytes) Non-Cacheable Area (within MBytes) Non-Cacheable Area (within MBytes)
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Disable Enable Fast reset command write port with data 1111XXX0b. After command issued, assertion INIT CPURST delayed which programmed held CPUCLK. Fast Reset Latency Control Slow Refresh Enable (1:4) Normal Refresh Slow Refresh DRAM Write Push delay De-turbo Hold time Hold Hold (Every De-turbo Switch Enable Always turbo, ignore status De-turbo Switch De-turbo Switch Enable Register Latency from ADS# Monitor Local Memory Status Depending setting this bit, master bridge SiS5501 monitor local memory status from inside local memory decoder either initiates cycle, determined converted side from this point. Specifically, BRDY# always returned CPUCLK later CTPPB full, post memory write cycles. Thus, this also affects Post write speed. When Post write rate each double word. When rate double word. Qword memory write, post write rate 7T(bit7=1), 8T(bit7=0). Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation Driving Current Control Please refer Reg. details)
SiS5501 PCI/ISA Cache Memory Controller
Enable Refresh Cycle when hold Disable Enable Enable Snoop Filter Disable Enable CAS# Pulse Width master write cycle Latency from disarming "Full" assertion BRDY# pending write cycle Selection KWE# synchronization KWE# synchronized with ACLK (Recommended) KWE# synchronized with CPUCLK Length bits bits Memory Parity Enable/Disable Enable parity error detection (default value) Disable parity error detection Register Control Register Bits Clock Frequency Selection PCICLK=CPUCLK/2 PCICLK=CPUCLK/1.5 Reserved PCICLK=14MHz Maximum Burstable Address Range master cycles Bytes KBytes This defines maximum bursting length each FRAME# asserting.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Latency from Reading L2/DRAM assertion TRDY# master read cycles Latency from Packing Qword into PTMPB assertion CAS#(or KWE#) This latency reserved Post write data propagating onto bus, also parity generation that minimum time data CAS# will violated. Latency from TRDY# BRDY# read/write slave cycles CPUCLKs CPUCLKs CPU-to-PCI burst memory write Enable Disable Enable CPU-to-PCI post memory write Enable Disable Enable Register This register mainly defines enable bits events monitored System Standby timer. monitored event occurs during programmed time, System standby timer will reloaded starts count down again. Programmable 10-bit port When set, access address will cause timer reloaded. address defined Registers 67h. Programmable 16-bit port When set, access address will cause timer reloaded. address defined Registers 6Eh. Hard Disk port When set, access Hard Disk ports 1F0-1F7h 3F6h) will cause timer reloaded. Serial port
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
When set, access Serial Ports 2F8-2FFh, 3F8-3FFh, 2E8-2EFh 3E8-3EFh) will cause timer reloaded. Parallel port When set, access Parallel ports 278-27Fh, 378-37Fh 3BC3BEh) will cause timer reloaded. HOLD When set, event from master Local Master will cause timer reloaded. IRQ1-15, When set, event from IRQ1-15 will cause timer reloaded. Driving Current Control Register used control driving current. Register Register Bits Bits Define events monitored Monitor standby timer Define events break Monitor System standby state. 1-15, When set, event from IRQ1-15 will cause Monitor standby timer reloaded. HOLD When set, event from master local master will cause Monitor standby timer reloaded. 1-15, When enabled, event from IRQ1-15 will bring Monitor back Normal state from Standby state. HOLD Register Minimum Current (default) 12mA
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
When enabled, event from master local master will bring Monitor back Normal state from Standby state. 1-15, When enabled, event from IRQ1-15 will de-assert STPCLK#. HOLD When enabled, event from master local master will deassert STPCLK#. INIT When enabled, event from INIT will de-assert STPCLK#. Register Reserved. should written with Reserved. should written with STPCLK# Enable When set, writing Register will cause STPCLK# become active. This cleared. Throttling Enable When set, writing Register will cause STPCLK# throttling state become active. throttling function disabled clearing this bit. STPCLK# Control When this set, STPCLK# will asserted Throttling function will enabled depending bits both bits enabled, system will throttling function. Break SW., Keyboard reset selection (pin 138) KBRST BREAK# Break disable function done programming register "0". When Register enabled, written this bit, generated. used software controlled function like APM. This should cleared handler. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation Reserved (must '0')
SiS5501 PCI/ISA Cache Memory Controller
Register Bits Bits define period STPCLK# assertion time when STPCLK# enable set. timer will start count until Stop Grant Special Cycle received. timer slot Register Bits Bits define period STPCLK# de-assertion time when STPCLK# enable set. timer starts count when STPCLK# assertion timer expires. When these registers read, current values returned. STPCLK# De-assertion Timer Reserved. STPCLK# Assertion Timer
Register Bits
System Standby Timer register defines duration System Standby Timer. When System Standby Timer expires, system enters System Standby State. non-masked event occurs before timer expires, timer reloaded with programmed number timer starts counting down again.
Register Bits
SMRAM mapping address. Correspond Host address A[27:20].
This register together with register define SMRAM location. SMRAM location either non-shadow, non-cacheable location selecting segment defined register implemented through logical address remap scheme. Logical address remap done through comparing upper bits access address with address bits defined register 65h. addresses compared equal SRAM area selection been either segment, then access remapped into segment access. SMRAM mapping address should BIOS during POST process service routine also moved into SMRAM area during this process. When system mode SMRAM access control enabled, access SMRAM area will redirected defined these registers. Note: SMRAM mapping address defines granularity logical address must first memory area.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Register Bits SMRAM area selection E0000h-E7FFFh A0000h-A7FFFh A0000h-AFFFFh B0000h-B7FFFh B0000h-BFFFFh others reserved SMRAM area non-cacheable, non-shadowed. E0000h-E7FFFh physical logical address space. other selections used relocate SMRAM from pre-defined area defined registers 65h) during SMM. SMRAM access control When set, SMRAM area used. This whenever necessary access SMRAM area. cleared after access finished. SMRAM area only accessed during handler. FLUSH# (De-turbo mode), ADSC# selection (pin ADSC# FLUSH# (De-turbo mode) Bits Register Bits Reserved (must '0') Define time slot Monitor Standby timer seconds 0.84 seconds 13.3 milli-seconds milli-seconds Bits Programmable 10-bit port address mask bits mask masked A1-A0 masked A2-A0 masked A3-A0 masked Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation Bits correspond Host Address A[30:28].
SiS5501 PCI/ISA Cache Memory Controller
A4-A0 masked A5-A0 masked A6-A0 masked Bits Programmable 10-bit port address bits Bits correspond address bits Register Bits Bits define programmable 10-bit port address bits A[9:2]. Register This register defines enable status devices SMM. bits when devices standby state cleared when respective devices normal state. System Standby enable When non-masked event occurs during programmed duration system standby timer, timer expires. this enabled, SMI# generated system enters System Standby state. Programmable 10-bit port wake enable When set, access this port will monitored generate SMI# wake this port from standby state Normal state. This enabled only when port Standby state. Programmable 16-bit port wake enable When set, access this port will monitored generate SMI# wake this port from standby state Normal state. This enabled only when port Standby state. Serial ports wake enable When set, access serial ports will monitored generate SMI# wake serial ports from standby state Normal state. This enabled only when serial ports Standby state. Parallel ports wake enable When set, access parallel ports will monitored generate SMI# wake parallel ports from standby state Normal state. This enabled only when parallel ports Standby state. Hard Disk port enable
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
When set, access hard disk port will monitored generate SMI# wake hard disk from standby state Normal state. This enabled only when hard disk port Standby state. Break Switch enable When set, break switch pressed generate SMI# system enter Standby state. Software enable When set, write register will generate SMI. Register This register defines request status. respective enable set, each specific event will cause respective set. asserted should cleared handler. System standby request This when system standby timer expires. Programmable 10-bit port wake request This when there access port. Programmable 16-bit port wake request This when there access port. Serial ports wake request This when serial ports accessed. Parallel ports wake request This when parallel ports accessed. Hard Disk port wake request This when hard disk port accessed. Break Switch request This when break switch pressed. Software request This when write register 60h. Register Monitor Standby enable Disable Enable Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
When there access from IRQ1-15, HOLD during programmed time Monitor Standby Timer, timer expires. this set, generated bring Monitor standby state. Monitor Standby request This when Monitor Standby Timer expires. This should cleared handler. Monitor wake enable When set, event from IRQ1-15, HOLD will monitored generate SMI# wake monitor from standby state normal state. Monitor wake request This when there event from IRQ1-15, HOLD NMI, Monitor standby state. Throttling wake request This when there unmasked event from NMI, INIT, IRQ1-15, HOLD when system throttling state. Throttling wake enable When set, unmasked event from NMI, INIT, IRQ1-15, HOLD will cause generated bring system back Normal state from throttling state. System wake enable When set, unmasked event from NMI, INIT, IRQ1-15, HOLD will cause generated bring system back Normal state from standby state. System wake request This when there unmasked event from NMI, INIT, IRQ1-15, HOLD when system standby state. Register Monitor Standby timer byte Bits Bits define byte Monitor standby timer. count-down timer time slot programmable 6.6s, 0.84s, 13.3 1.6ms. value programmed this register loaded when timer enabled timer starts counting down. timer reloaded when event from IRQ1-15, HOLD occurs before timer expires. When this register read, current value returned.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Register Monitor Standby timer High byte Bits Bits define high byte Monitor standby timer.
Register Programmable 16-bit port byte Bits Bits define byte Programmable 16-bit port.
Register Programmable 16-bit port High byte Bits Register This register except mainly defines events monitored System Standby timer. unmasked event occurs before timer expires, System Standby Timer will reloaded timer starts count down again. Return after SIOREQ# Serviced Disable Enable SMOUT reserved application circuit. A0000h AFFFFh B0000 BFFFFh Address trap When set, memory access address range will cause timer reloaded. C0000h C7FFFh Address trap When set, memory access address range will cause timer reloaded. 3B0-3BFh, 3C0-3CFh, 3D0-3DFh Address trap When set, access addresses will cause timer reloaded. Secondary Drive port When set, access secondary drive port (170-17Fh, 320-32Fh, 3F7h) will reload system standby timer. Bits System Standby Timer Slot 8.85 milli seconds milli seconds seconds seconds Bits define high byte Programmable 16-bit port.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Register DRAM Boundary
Each register records accumulated DRAM size including present previous banks. Bits DRAM Bank Boundary Address A[28:21] 00h: 0Mbyte 01h: 2Mbyte 02h: 4Mbyte 04h: 8Mbyte Note: Please refer "2.6 DRAM Controller" detailed information. Register Bits BRDY# Timing Selection 00,10: DRAM BRDY# type timing (6-2-2-2) BRDY# type timing (7-2-2-2) Bits MDLE 5502 Timing Selection 00,10: DRAM MDLE type timing (6-2-2-2) MDLE type timing (7-2-2-2) ADSV#, RAS6# Selection (pin Select ADSV# Select RAS6# ADSC#/FLUSH#, RAS7# Selection (pin Select ADSC#/FLUSH# Select RAS7# NA#, RAS4# selection (pin 193) Select Select RAS4# MA11, RAS5# selection (pin Select MA11 Select RAS5# Note: function chosen Register bits hardware trap. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Register Bits Register SMAC access must whenever CCR1 cleared CCR1 cleared. MMAC access set, access address within space conducted main memory instead area. must whenever CCR1 cleared CCR1 cleared. M1's specification, SMIACT will de-asserted when MMAC re-asserted after cleared. This allows service routine access normal memory area instead memory area. should current Toggle Mode Enable Break without toggle mode Break with toggle mode Flush Function Block Mode suggested block FLUSH Deturbo Mode) when STPCLK asserted. Un-block Block Reserved Control Register Disable register 7Dh. Enable register 7Dh. When register zero, parity checking function 5501 enabled. When register "1", parity check each bank controlled register 7Dh. Register AD[31:0] output current selection Reserved DRAM Bank Boundary Address Corresponds Bank
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
50mA/2.2V (default value) 95mA/2.2V FRAME#, IRDY#, TRDY#, DEVSEL#, C/BE[3:0]# output current selection 50mA/2.2V (default value) 95mA/2.2V GNT[3:0]#, PAR, SERR# output current selection 50mA/2.2V (default value) 95mA/2.2V Bits Register CMPOP Synchronous CAS# CMPOP active after CAS# active CMPOP CAS# active same time. DRAM Write CAS# Pulse Width Control Disable register Enable register MDLE Control Write Access According bits register 78h. MDLE CAS# active same time. DRAM Write CAS# pulse Width data sheet Rev. 1.0, register used CAS# pulse width DRAM read write cycle. From 5501 REV. register only used define CAS# pulse width read cycle while register used define CAS# pulse width write cycle. MDLE Always High This only testing purpose. Disable Enable Standard SRAM First Cache Read/Write Cycle Setting read write Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation Reserved
SiS5501 PCI/ISA Cache Memory Controller
read write original design, bits register used define first cycle time cache burst read write cycle when using standard SRAM. When bits register "10", first cycle time both read write cycle. When register "1", first cycle time redefined read cycle write cycle. This only valid when first cycle time defined register 52h. Access DRAM CAS# pulse width Access DRAM CAS# pre-charge time Note: recommended that CAS# pulse width pre-charge time when DRAM used. Register Banks Parity Disable Control This register valid when register set. Bits Bank Parity Disable Control Enable parity check. Disable parity check. Register Setting Bank Standard/EDO type DRAM Standard DRAM type DRAM Setting Bank Standard/EDO type DRAM Standard DRAM type DRAM Setting Bank Standard/EDO type DRAM Standard DRAM type DRAM Setting Bank Standard/EDO type DRAM Standard DRAM type DRAM Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Setting Bank Standard/EDO type DRAM Standard DRAM type DRAM Setting Bank Standard/EDO type DRAM Standard DRAM type DRAM Setting Bank Standard/EDO type DRAM Standard DRAM type DRAM Setting Bank Standard/EDO type DRAM Standard DRAM type DRAM
2.11 Assignment Description
2.11.1 Hardware Trap 5501 will strobe status GNT[3:0]# rising edge PWRGD determine function 193. definition described below: Function condition RAS6# GNT2# pulled ohms resistor RAS7# GNT3# pulled ohms resistor RAS5# GNT1# pulled ohms resistor RAS4# GNT0# pulled ohms resistor ADSV# GNT2# pulled high ohms resistor ADSC#/FLUSH# GNT3# pulled high ohms resistor MA11 GNT1# pulled high ohms resistor GNT0# pulled high ohms resistor restriction, 5501 shared ADSC#, FLUSH#, RAS7#. hardware trap only distinguish ADSC#/FLUSH# RAS7#. order distinguish ADSC# FLUSH#, register implemented. definition register described below: Register
ADSC# FLUSH#
Beside hardware method, software method also provided define multi-function pins. following method hardware trap register define multi-function pins. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Hardware trap: bits[3:0] register Select function through GNT[3:0]# Software: Pull GNT[3:0]# logic "high" Select function through bits[3:0] register 2.11.2 Assignment
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
HA10 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 CPURST HBE7# HBE6# HBE5# HBE4# HBE3# HBE2# HBE1# HBE0# A20M# W/R# HITM# EADS# D/C# ADS# CPUHLDA SMIACT# CPUHOLD NA#/RAS4# BRDY# KEN# CACHE# M/IO# VDD3 KCE0#/CW KCE1/CWE2# KCE2#/CW KCE3#/CWE3# KCE4#/CWE4# KCE5#/CWE5# KCE6#/CWE6# KCE7#/CWE7#
HA11
5501
Silicon Integrated Systems Corporation
Preliminary V2.0
April 1995
SiS5501 PCI/ISA Cache Memory Controller
2.11.3 Listing means active low)
1=CALE 2=KA3/KA4Y 3=KA4X 4=KWY1# 5=KWY0# 6=VSS 7=KWX1# 8=KWX0# 9=KREY#/COE1# 10=KREX#/COE0# 11=VSS 12=ADSV#/RAS6# 13=ADSC#/FLUSH #/RAS7# 14=VDD3 15=TA0 16=TA1 17=TA2 18=TA3 19=TA4 20=TA5 21=TA6 22=TA7 23=ALTWE# 24=ALT 25=TAGWE# 26=CAS0# 27=CAS1# 28=CAS2# 29=CAS3# 30=CPUCLK 31=VSS 32=CAS4# 33=CAS5# 34=CAS6# 35=CAS7# 36=ACLK 37=VSS 38=RAS0# 39=RAS1# 40=VDD 41=RAS2# 42=RAS3# 43=VSS 44=RAMW# 45=MA0 46=MA1 47=MA2 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 48=MA3 49=MA4 50=MA5 51=MA6 52=MA7 53=MA8 54=MA9 55=MA10 56=MA11/RAS5# 57=HGDW 58=ADLE# 59=CPPOP 60=CPPSH 61=CMPOP 62=CMPSH 63=MDLE 64=PRDLE 65=ADOE 66=PARITY# 67=HCR0 68=VSS 69=HCR1 70=HLDA 71=PCICLKO 72=AD0 73=AD1 74=AD2 75=AD3 76=AD4 77=AD5 78=AD6 79=AD7 80=VDD 81=AD8 82=AD9 83=PWRGD 84=VSS 85=AD10 86=AD11 87=AD12 88=AD13 89=AD14 90=AD15 91=AD16 92=AD17 93=AD18 94=AD19 95=AD20 96=AD21 97=AD22 98=AD23 99=AD24 100=AD25 101=AD26 102=AD27 103=AD28 104=AD29 105=AD30 106=AD31 107=C/BE0# 108=C/BE1# 109=VSS 110=C/BE2# 111=C/BE3# 112=REQ0# 113=REQ1# 114=REQ2# 115=REQ3# 116=GNT0# 117=GNT1# 118=GNT2# 119=GNT3# 120=STOP# 121=DEVSEL# 122=TRDY# 123=IRDY# 124=FRAME# 125=PLOCK# 126=PAR 127=SERR# 128=VSS 129=PCICLKI 130=SIOGNT# 131=SIOREQ# 132=PCIRST# 133=SMOUT 134=WAKEUP1 135=WAKEUP0 136=VDD 137=TURBO 138=KBRST#/BREAK# 139=VSS 140=OSC 141=VDD3 5V/3.3V
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
142=STPCLK# 143=INIT 144=SMI# 145=HA23 146=HA21 147=HA24 148=HA22 149=HA27 150=HA26 151=HA25 152=HA28 153=HA31 154=HA29 155=HA30 156=HA3 157=HA4 158=HA6 159=HA7 160=HA8 161=HA10 162=HA5 163=HA11 164=HA9 165=HA12 166=HA13 167=HA14 168=HA15 169=HA16 170=HA17 171=HA18 172=HA19 173=HA20 174=CPURST 175=HBE7#
5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V
176=HBE6# 177=HBE5# 178=HBE4# 179=HBE3# 180=HBE2# 181=HBE1# 182=HBE0# 183=VSS 184=A20M# 185=W/R# 186=HITM# 187=EADS# 188=D/C# 189=ADS# 190=CPUHLDA 191=SMIACT# 192=CPUHOLD 193=NA#/RAS4# 194=BRDY# 195=VSS 196=KEN# 197=CACHE# 198=M/IO# 199=VDD3 200=KCE0#/CWE0# 201=KCE1#/CWE1# 202=KCE2#/CWE2# 203=KCE3#/CWE3# 204=VSS 205=KCE4#/CWE4# 206=KCE5#/CWE5# 207=KCE6#/CWE6# 208=KCE7#/CWE7#
5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
2.11.4 Description Host Interface 145-173 Symbol HA[31:3] Type Function Address driven during cycles. 5501 forwards either DRAM depending address range. address driven 5501 during master cycles. Byte Enables indicate which byte lanes data carry valid data during current cycle. HBE7# indicates that most significant byte data valid while HBE0# indicates that least significant byte data valid. Address Status driven indicate start cycle. Memory definition input indicate cycle when low, memory cycle when high. Write/Read from indicates whether current cycle write read access. output during master cycles. Data/Code used indicate whether current cycle data code access. Burst Ready indicates that data presented valid during burst cycle. Hold Request used request control bus. CPUHLDA will asserted after completing current cycle. Hold Acknowledge comes from response CPUHOLD request. active high remains driven during hold period. CPUHLDA indicates that given another master. Modified indicates snoop cycle hits modified line cache CPU. Mask fast A20GATE output CPU. remains high during power reset period. forces when active.
175-182
HBE[7:0]#
ADS# M/IO#
W/R#
D/C# BRDY# CPUHOLD
CPUHLDA
HITM# A20M#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
KEN# Cache Enable used when current cycle cacheable cache CPU. active signal asserted 5501 during cacheable cycles. Cache indicates internally cacheable read cycle burst write-back cycle. this driven inactive during read cycle, will cache returned data, regardless state KEN# pin. EADS# driven indicate that valid external address been driven address pins used inquire cycle. Reset active high output reset CPU. Initialization output forces begin execution known state. state after INIT same state after CPURST except that internal caches, model specific registers, floating point registers retain values they prior INIT. System Management Interrupt used indicate occurrence system management events. connected directly SMI# input. SMIACT# used acknowledgment input from indicate that being acknowledged processor operating System Management Mode(SMM). Stop Clock indicates stop clock request CPU.
CACHE#
EADS#
CPURST INIT
SMI#
SMIACT#
STPCLK#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Cache DRAM Interface 22-15 Symbol TA[7:0] KA4X KA3/KA4Y KREX#/COE0# Type Function data lines. indicates particular line level cache contains modified data. Cache address even bank interleaved cache configuration. Cache address bank, Cache address non-interleaved mode. Cache Read Enable even bank standard SRAM, Cache Output Enable burst SRAM. Cache Read Enable bank standard SRAM, Cache Output Enable burst SRAM. When used COE1#, copy COE0# loading consideration. Cache Write Enable standard SRAM, even bank. Cache Write Enable standard SRAM, bank. ALTWE# write strobe RAM. This signal active when cache read miss cache write occurs. used update bit. write enable output. Cache Enable pins standard SRAM indicate that corresponding byte accessed. Cache Write Enable pins burst SRAM allow cache data update byte-by-byte basis. CALE controls external latch between host address lines cache address lines. When high, allows address lines propagate through external latches onto cache address lines. When low, used latch cache address lines. RAS[3:0]# used latch address bus. Each RAS[3:0]# corresponds DRAM row.
KREY#/COE1#
KWX0/1# KWY0/1# ALTWE#
208-205 203-200
TAGWE# KCE[7:0]# CWE[7:0]#
CALE
42,41 39,38
RAS[3:0]#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
35-32 29-26
CAS[7:0]#
55-45
RAMW# MA[10:0]
CAS[7:0]# used latch column address bus. Each CAS[7:0]# corresponds byte eight-byte wide array. Write active output signal enable local DRAM writes. MA[10:0] provide column address DRAM.
Interface 111,110 108,107 Symbol C/BE[3:0]# Type Function Command Byte Enables define command during address phase cycle, byte enables during data phases. C/BE[3:0]# outputs when 5501 master inputs when slave. Address /Data address phase: When 5501 master, AD[31:0] output signals. When 5501 target, AD[31:0] input signals. data phase: When 5501 master memory read/write cycle, AD[31:0] floating. When 5501 master configuration cycle, AD[31:0] input signals read cycle, output signals write cycle. When 5501 target memory read/write cycle, AD[31:0] floating. When 5501 target configuration cycle, AD[31:0] output signals read cycle, input signals write cycle. FRAME# output when 5501 master. 5501 drives FRAME# indicate beginning duration access. When 5501 slave, FRAME# input signal.
106-85 82,81 79-72
AD[31:0]
FRAME#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
IRDY# IRDY# output when 5501 master. assertion IRDY# indicates current master's ability complete current data phase transaction. read cycle, IRDY# indicates that master prepared accept read data following rising edge clock. write cycle, IRDY# indicates that master driven valid data bus. When 5501 slave, IRDY# input. TRDY# output when 5501 slave. assertion TRDY# indicates target agent's ability complete current data phase transaction. read cycle, TRDY# indicates that target driven valid data onto bus. write cycle, TRDY# indicates that target prepared accept data from bus. When 5501 master, input. 5501 drives DEVSEL# based DRAM address range being accessed master current configuration cycle 5501. input indicates device responded current cycle initiated 5501. STOP# indicates that master must start terminating current cycle next clock edge release control bus. STOP# used disconnect, retry, targetabort sequences bus. Parity even parity generated across AD[31:0] C/BE[3:0]#. System error open drain output reporting errors. Request used indicate arbiter that agent requires bus. Grant indicates agent that access been granted.
TRDY#
DEVSEL#
STOP#
115-112
SERR# REQ[3:0]#
119-116
GNT[3:0]#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
PLOCK# Lock indicates exclusive operation that require multiple transactions complete. When PLOCK# sampled asserted beginning cycle, 5501 considers itself locked resource remains locked state until PLOCK# sampled negated cycle. PCICLKO provides clock 5501/5502/5503 devices system. PCICLKI input provides fundamental timing internal operating frequency 5501. runs same frequency skew local bus. should generated from PCICLKO signal through clock distribution buffer. Reset forces devices known state.
PCICLKO PCICLKI
PCIRST#
Data Buffer Control Interface 69,67 Symbol HCR[1:0] Type Function Host Data Controls. These signals driven 5501 used control 5502 HD[63:0] bus. They defined 5502 floats 5502 drives FFFFFFFF 5502 drives data from 5502 drives data from Data Latch Enable. This signal following functions: Latch data into read buffer (PRMB) Latch data into read buffer rising edge PCICLKI. Latch data into posted write buffer (PTMPB) rising edge PCICLKI. Output Enable. This signal used enable 5502 drive bus. asserted writes master reads local memory cycles. Memory Data Read Latch Enable. This signal latches data when negated.
ADLE#
ADOE
MDLE
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
CPPSH Push Posted Write Data into 5502. data latched into 5502 Posted Write Buffer CPPSH rising edge. edge also increases write pointer next available loading entry buffer. rising edge CPPOP, read pointer changed address next available reading location. When this signal asserted, data written into memory posted write buffer (CTMPB) rising edge CPUCLK, write pointer also changed address next available location. Memory Posted Write Buffer Data. When this signal asserted, read pointer Memory Posted Write Buffer increased rising edge CPUCLK. This signal latches current output entry Posted Write Buffer into prelatch 5502. output prelatch driven onto bus. master cycle, PRDLE asserted when master reading data from secondary cache, when master writing data local memory. High Double Word Indicator. signal driven high when: high from written into Posted Write Buffer, reads high from bus, master writes high local memory, master reads high from local memory. Parity Bit, from 5502.
CPPOP
CMPSH
CMPOP
PRDLE
HGDW
PARITY#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Multi-function Pins Symbol NA#/RAS4# Type Function This that used RAS4# depends BIOS programming hardware trap selection. Next Address driven clock indicate that memory system ready accept cycle. Although data transfer current cycle completed, drive internally pending cycle address clocks after asserted. RAS4# used latch address bus. This that used MA11 RAS5# depends BIOS programming hardware trap selection. MA11 provides column address DRAM. RAS5# used latch address bus. This that used ADSV# RAS6# depends BIOS programming hardware trap selection. Cache Advance driven burst SRAM advance internal two-bit address counter next address burst sequence. RAS6# used latch address bus. This that used ADSC#, FLUSH#, RAS7# depends BIOS programming hardware trap selection. Cache Address Strobe Control causes burst SRAM latch cache address. FLUSH# asserted during deturbo mode. used force writeback modified lines data cache invalidate internal cache. RAS7# used latch address bus.
MA11/RAS5#
ADSV#/RAS6#
ADSC#/FLUSH# /RAS7#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Others Symbol HLDA SMOUT SIOREQ# SIOGNT# Type Function Hold Acknowledge. System Management Output control pin. used control peripheral's power, clock.etc. Request from 5503 request bus. Grant. When asserted, SIOGNT# indicates that arbiter granted 5503. When break switch enable set, KBRST# will disabled. signal from break switch will cause system enters standby state. pulse width BREAK# must greater than CPUCLK. Turbo input pin. system De-turbo mode when this low. When this input activated, 5501 will reload system standby timer. inactive system standby timer expires, system will enter system standby state. During system standby state, this input becomes active, system will wake from standby state return back normal state. When this input activated, 5501 will reload monitor standby timer. inactive monitor standby timer expires, system will enter monitor standby state. During monitor standby state, this input becomes active, system will wake from standby state return back normal state. clock input timer controller. 14.318MHz generated external oscillator. Advanced clock should lead CPUCLK provide clock 5501 internal cache control logic. clock input runs frequency skew equal those clock. Power Good power reset push button reset input. power +3.3V power system power system
KBRST#/BREA
TURBO WAKEUP1
WAKEUP0
ACLK
40,80,136 14,141
CPUCLK PWRGD VDD3
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
6,11,31,37 43,68,84 109,128 139,183 195,204 Ground
2.12 Timing Diagram
Cache Burst Read Cycle 3-1-1-1 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr1 Cache Burst Read Cycle 4-2-2-2 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr2 Cache Burst Read Cycle 5-3-3-3 CPUCLK ADS# BRDY# KA4X KA4Y KREX# KREY# 501cbr3
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Cache Burst Write Cycle 3-1-1-1 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw1 Cache Burst Write Cycle 4-2-2-2 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw2 Cache Burst Write Cycle 5-3-3-3 CPUCLK ADS# BRDY# KA4X KA4Y KWEX# KWEY# 501cbw3
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Cache Miss Update Cycle Only Dirty=0, DRAM:7-4-4-4 CPUCLK ADS# CAS# RAS# BRDY# MA[11:0] CALE KWEX# KWEY# KA4X KA4Y 5501cmu1 Cache Miss Update Cycle Only Dirty=0, DRAM:6-3-3-3 CPUCLK ADS# CAS# RAS# BRDY# MA[11:0] CALE KWEX# KWEY# KA4X KA4Y 5501cmu2
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Cache Miss,Concurrent Write Back Cycle Cache:4-2-2-2 DRAM:7-4-4-4 CPUCLK ADS# CAS# RAS# BRDY# CMPSH MA[11:0] CMPOP CALE KWEX# KWEY# KA4X KA4Y RAMW# KREX# KREY# 5501cmwb
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
DRAM Burst Read Miss 10-3-3-3 (Cache 3/4-x-x-x) CPUCLK ADS# CAS# RAS# BRDY# MDLE MA[11:0] CALE KWEX# KA4X 5501dbr1 DRAM Burst Read Miss 11-4-4-4 (Cache 3/4-x-x-x) CPUCLK ADS# CAS# RAS# BRDY# MDLE MA[11:0] CALE KWEX# KA4X 5501DBR2
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
DRAM Burst Read Miss 9-3-3-3 (Cache 3/4-x-x-x) CPUCLK ADS# CAS# RAS# BRDY# MDLE MA[11:0] CALE KWEX# KA4X 5501dbr3
DRAM Burst Read Miss 10-4-4-4 (Cache 3/4-x-x-x) CPUCLK ADS# CAS# RAS# BRDY# MDLE MA[11:0] CALE KWEX# KA4X 5501DBR4
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
DRAM Posted Write 4-2-2-2 cache Write-Through CPUCLK ADS# CAS# RAS# BRDY# CMPSH MA[11:0] CMPOP KWEX# KA4X 5501dbw1
Burst Read (7-2-2-2)
CPUCLK ADS# RAS# CAS# Physical Timing Assume delay delay Logic Timing
CAS# MDLE BRDY#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Burst Write (Posted Write 4-2-2-2)
CPUCLK ADS# Logic Timing CAS# Physical Timing Assume delay 10ns delay
CAS# CMPOP BRDY#
5501 Configuration Register Read Cycle CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW PCICLK FRAME# IRDY# DEVSEL# TRDY# PRDLE ADOE ADLE# 0CF8 0CFC
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
5501 Configuration Register Write Cycle CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW PCICLK FRAME# IRDY# DEVSEL# TRDY# PRDLE ADOE ADLE# 501crw 0CF8 0CFC
Read Slave CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW PCICLK AD[31:0] C/BE[3:0]# FRAME# IRDY# DEVSEL# TRDY# PRDLE ADLE# HCR[1:0] 501crp addr. data addr. data read read high
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Psoted Write Cycle CPUCLK HA[31:3] HBE[7:0]# ADS# BRDY# HGDW PCICLK AD[31:0] C/BE[3:0]# FRAME# IRDY# DEVSEL# TRDY# ADOE CPPSH CPPOP PRDLE 501ctpp master Reads High from L2,NA=SAL PCICLK FRAME# IRDY# DEVSEL# KRE# TRDY# HGDW ADOE ADLE# 501prl2 wait state XXX800 DATA XXXXX800 XXXXX808
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
master Writes L2/DRAM, NA=SAL, Page CPUCLK PCICLK FRAME# IRDY# DEVSEL# EADS# KWE#/CAS# TRDY# HGDW HCR[1:0] ADLE# CALE PRDLE RAMW# 501prl2d
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Snoop Modified line miss Master Writes Last Line Boundary, Disconnect CPUCLK PCICLK FRAME# IRDY# DEVSEL# TRDY# STOP# EADS# HITM# CPUHOLD CPUHLDA ADS# BRDY# RAS# CAS# RAMW# PRDLE ADLE# HGDW CALE
501snp2 address column addr
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Snoop Modified line Master Read Line from CPUCLK PCICLK FRAME# IRDY# DEVSEL# TRDY# EADS# HITM# CPUHOLD CPUHLDA HA[31:3] ADS# BRDY# KWE# KRE# ADOE PRDLE ADLE# HGDW
501snp1 00100000 drive 00100000 00100000 00100008 00100010 00100018
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller 2.13 Electrical Characteristics
2.13.1 Absolute Maximum Ratings Parameter Ambient operating temperature Storage temperature Input voltage Output voltage Power Dissipation -0.3 -0.5 Unit
Note: Stress above these listed cause permanent damage device. Functional operation this device should restricted conditions described under operating conditions. 2.13.2 Characteristics VDD=5V+5%, VDD3=3.3V+5% Symbol VIL1 VIH1 VIL2 VIH2 VT1VT1+ VOL1 VOH1 VOL2 VOH2 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 IOL5 IOH5 Parameter Input voltage Input High Voltage Input voltage Input high voltage Schmitt Trigger Threshold Voltage Falling Edge Schmitt Trigger Threshold Voltage Rising Edge Hysteresis Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Current Output High Current Output Current Output High Current Output Current Output High Current Output Current Output High Current Output Current Output High Current Input Leakage Current April 1995 -0.3 -0.3 VDD3+0.3V VDD+0.3 Unit Condition Note VDD3=3.3V Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note Note
VDD3 0.45
Preliminary V2.0
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
COUT CI/O ICC3 Note: VIL1 VIH1 applicable HA[31:3], W/R#, HBE[7:0]#, HITM#, D/C#, ADS#, CPUHLDA, SMIACT#, CACHE#, M/IO# VIL2 VIH2 applicable TA[7:0], ALT, CPUCLK, ACLK, PARITY#, AD[31:0], C/BE[3:0]#, REQ[3:0]#, STOP#, DEVSEL#, TRDY#, IRDY#, FRAME#, LOCK#, PCICLKI, SIOGNT#, SIOREQ#, WAKEUP[1:0], TURBO, KBRST#, VT1-,VT1+ applicable PWRGD VOL1 VOH1 applicable TA[7:0], ALTWE#, ALT, TAGWE#, CAS[7:0]#, RAS[3:0]#, RAMW#, MA11/RAS5#, MA[10:0], HGDW, ADLE#, CPPOP, CPPSH, CMPOP, CMPSH, MDLE, PRDLE, ADOE, HCR[1:0], HLDA, PCICLKO, AD[31:0], GNT[3:0]#, STOP#, DEVSEL#, TRDY#, FRAME#, PAR, SERR#, PCIRST#, SMOUT VOL2 VOH2 applicable CALE, KA4Y, KA4X, KWY[1:0]#, KWX[1:0]#, KREX#, KREY#, ADSC#/FLUSH#/RAS7#, ADSV#/RAS6#, STPCLK#, INIT, SMI#, HA[31:3], CPURST, W/R#, A20M#, EADS#, CPUHOLD, NA#/RAS4#, BRDY#, KEN#, KCE[7:0]# IOL1 IOH1 applicable TA[7:0], ALTWE#, ALT, TAGWE#, RAMW#, MA11/RAS5#, MA[10:0], HGDW, ADLE#, CPPOP, CPPSH, CMPOP, CMPSH, MDLE, PRDLE, ADOE, HCR[1:0], HLDA, PCICLKO, AD[31:0], C/BE[3:0]#, GNT[3:0]#, PAR, SERR#, PCIRST#, SMOUT, WAKEUP[1:0] IOL2 IOH2 applicable FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#. IOL3 IOH3 applicable CAS[7:0]# IOL4 IOH4 applicable KA4X, KA4Y, KWY[1:0]#, KWX[1:0]#, ADSV#/RAS6#, ADSC#/FLUSH#/RAS7#, RAS[3:0]# IOL5 IOH5 applicable CALE, KREY#, KREX#, STPCLK#, INIT, SMI#, HA[31:3], W/R#, EADS#, CPUHOLD, NA#/RAS4#, BRDY#, KEN#, KCE[7:0]#, CPURST, A20M# IOH5 system, when system, IOH5 4mA. driving current CAS# some signals programmable. Please refer Register Description. Input Leakage Current Input Capacitance Output Capacitance Capacitance Power Supply Current VDD3 Fc=1 Fc=1 Fc=1 3.3V, 66MHz
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
2.13.3 Characteristics
Symbol Parameter BRDY# Active delay from CPUCLK BRDY# Inactive delay from CPUCLK KEN# Active delay from CPUCLK KEN# Inactive delay from CPUCLK Active delay from CPUCLK Inactive delay from CPUCLK EADS# Active delay from CPUCLK EADS# Inactive delay from CPUCLK CPUHOLD Active delay from CPUCLK CPUHOLD Inactive delay from CPUCLK CPURST Inactive delay from CPUCLK CPURST High Pulse Width KREX#,KREY# Active delay from ACLK KREX#,KREY# Inactive delay from ACLK KWX[0:1]#,KWY[0:1]# Active delay from ACLK KWX[0:1]#,KWY[0:1]# Inactive delay from ACLK KWX[0:1]#,KWY[0:1]# Active delay from CPUCLK KWX[0:1]#,KWY[0:1]# Inactive delay from CPUCLK KCE[7:0]# Active delay from ADS# falling edge KCE[7:0]# Inactive delay from CPUCLK MDLE High Active delay from CPUCLK MDLE High Inactive delay from CPUCLK KA4X,KA4Y Valid delay from ACLK KA4X,KA4Y High Valid delay from ACLK KA4X,KA4Y Valid delay from CPUCLK Update Cycle Write cycle KA4X,KA4Y High Valid delay from CPUCLK Update Cycle Write cycle Output Valid delay from CPUCLK Update Cycle RAS[7:0]# Active delay from CPUCLK RAS[7:0]# Inactive delay from CPUCLK CAS[7:0]# Active delay from CPUCLK CAS[7:0]# Inactive delay from CPUCLK MA[11:0] Valid delay from CPUCLK MA[11:0] High Valid delay from CPUCLK MA[11:0] Propagation delay from A[27:3] Output Valid delay from CPUCLK ALTWE#,TAGWE# Active delay from CPUCLK ALTWE#,TAGWE# Inactive delay from CPUCLK A20M# Active delay from CPUCLK A20M# Inactive delay from CPUCLK AD[31:0],C/BE[3:0]# Output valid delay from PCICLKI PRDLE Active delay from PCICLKI Active delay from PCICLKI Inactive delay from PCICLKI Unit cpuclk 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 100pf 100pf 100pf 100pf 100pf 100pf 35pf 35pf 35pf 35pf 100pf 100pf 100pf 100pf 35pf 250pf 250pf 120pf 120pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 35pf 50pf 50pf
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
Active delay from PCICLKI Inactive delay from PCICLKI HA[31:3] Drive Output Valid delay from PCICLKI HCR[1:0],HGDW Active delay from CPUCLK HLDA Active delay from CPUCLK HLDA Inactive delay from CPUCLK INIT# Active delay from CPUCLK INIT# Inactive delay from CPUCLK MDLE Active delay from CPUCLK MDLE Inactive delay from CPUCLK PCICLKO,PCIRST Active delay from CPUCLK RAMW# Active delay from CPUCLK RAMW# Inactive delay from CPUCLK SMOUT Active delay from CPUCLK ADSC# Active delay from CPUCLK ADSC# Inactive delay from CPUCLK ADSV# Active delay from CPUCLK ADSV# Inactive delay from CPUCLK CPPSH Active delay from CPUCLK CPPOP Active delay from PCICLK CPPSH Inactive delay from CPUCLK CPPOP Inactive delay from PCICLK ADOE Active delay from PCICLK ADOE Inactive delay from PCICLK ADLE# Active delay from PCICLK ADLE# Inactive delay from PCICLK PCICLKO high time (Divided PCICLKO time (Divided PCICLKO high time (Divided 1.5) PCICLKO time (Divided 1.5) PCICLKO rise time (Divided PCICLKO fall time (Divided PCICLKO rise time (Divided 1.5) PCICLKO fall time (Divided 1.5) HCR[1:0] fall time CPUCLK rising HCR[1:0] rise time CPUCLK rising CALE# Active delay from CPUCLK CALE# Inactive delay from CPUCLK SMI# rise time CPUCLK rising SMI# fall time CPUCLK rising 15.2 12.6 12.5 15.8 1.16 0.66 1.06 50pf 50pf 50pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 35pf 35pf 50pf 90pf 90pf 150pf 150pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 35pf 50pf 50pf 50pf 50pf 50pf 50pf 50pf 50pf 35pf 35pf 35pf 35pf 35pf 35pf
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
CPUCLK SIGNAL1
T10, T11, T17, T22, T23, T25, T27, T28, T30, T32, T36, T38, T49, T50, T53, T55, T58, T60, T64, T78, T80, T18, T20, T21, T24, T26, T27, T29, T31, T33, T35, T37, T39, T47, T48, T51, T52, T54, T56, T57, T59, T61, T62, T79, T81, SIGNAL1 BRDY#, KEN#, NA#, EADS#, CPUHOLD, CPURST, KWX[0:1]#, KWY[0:1]#, KCE[7:0]#, MDLE, CALE, KA4X, KA4Y, TA[7:0], RAS[7:0]#, CAS[7:0]#, MA[11:0], ALT, ALTWE#, TAGWE#, A20M#, HLDA, INIT#, PCICLKO, PCIRST, RAMW#, SMOUT, ADSC#, ADSV#, GNT[3:0]#, PAR, SERR#, SIOGNT#, STPCLK#, CPPSH
ACLK SIGNAL2
T13, T15, T14, T16, SIGNAL2 KREX#, KREY#, KWX[0:1]#, KWY[0:1]#, KA4X, KA4Y
PCICLKI SIGNAL3
T40, T41,T42, T46, T44, T65, T67, T40, T41, T43, T46, T45, T63, T66, SIGNAL3 AD[31:0], C/BE[3:0], ADLE#, ADOE, PRDLE, DEVSEL#, FRAME#, IRDY#,STOP#, TRDY#, HA[31:3], CPPOP, ADOE, ADLE
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5501 PCI/ISA Cache Memory Controller
ADS# KCE[7:0]#
CPURST
HA[27:3] MA[11:0]
PCICLKO
T70,T72 T71, T74, T75,
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
SiS5502
Features
Supports Full 64-bit Pentium Processor Data Provides 64-Bit Interface DRAM Memory Provides 32-bit Interface Three Integrated Posted Write Buffers Read Buffers Increase System
Performance level CPU-to-Memory Posted Write Buffer (CTMPB) with QuadWords (QWs) Deep level CPU-to-PCI Posted Write Buffer (CTPPB) with DoubleWords (DWs) Deep level PCI-to-Memory Posted Write Buffer (PTMPB) with Deep level Memory-to-CPU Read Buffer (CRMB) with Deep level Memory-to-PCI Read Buffer (PRMB) with Deep Near Zero Wait State Performance CPU-to-Memory CPU-to-PCI writes Operates Synchronously 66.7 33.3 Clocks Provides Parity Generation Memory Writes 208-Pin PQFP CMOS Technology
General Description
SiS5502 Local Data Buffer(PLDB) provides bi-directional data buffering among 64-bit Host Data Bus, 64-bit Memory Data Bus, 32-bit Address/Data Bus. PLDB incorporates three Posted Write Buffers Read Buffers along bridges CPU, Memory buses. This buffering scheme smoothes differences access latencies bandwidths among three buses, therefore improves overall system performance. four level/4DWs deep write buffer (CTPPB) provides buffering write bus. level/4QWs deep write buffer (CTMPB) used buffering write data from Memory. level/1QW deep write buffer (PTMPB) used buffer write Memory data. Read Buffer (CRMB) used latch read Memory data Read Buffer (PRMB) used latch data master read from Cache DRAM cycle. During operation between Host, Memory, PLDB receives control signals from PCMC, performs functions such latching data, forwarding data destination bus, data assemble disassemble. Figure shows PLDB block diagram.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
MDLE
MD[63:0]
CTMPB QWS)
PRDLE
PARITY# P.CK.
HD[63:0] PD[7:0]
P.G.
LATCH PTMPB
HCR[1:0]
LATCH DISASSEMBLE AD[31:0]
PRDLE
ADLE#
HGDW
DISASSEMBLE
CTPPB DWS)
HGDW PRDLE
(1DW)
Figure PLDB Block Diagram
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer Functional Description
3.3.1 Data Flow Between Data flows from when writes local memory PCMC writes back dirty line from cache local memory read miss/line fill cycle. data written memory first pushed into CPMPB. data then popped from buffer written Memory.
During read local memory cycle, data read first latched 64-bit read buffer (CRMB) order provide enough hold time cache. PLDB also checks parity read data.
3.3.2 Data Flow Between
This path used following cases. first case writes slave cycle. second case master read cycle that hits modified data local cache which implemented using write-back policy. data sent memory slave first pushed into CTPPB. data then popped onto later time when busy. further write suspended CTPPB full. writes posted, still exploit CTPPB write buffer.
path master read from cache implemented through PRMB, built-in 64-bit read memory buffer. Since read each time, PCMC always sustains wait state reading second This path exercised cases. first case during reads slave second case during master write cycles. reads cycle stalled until CTPPB empty. When reads slave, data latched assembled PTMPB before they transmitted bus. During master writes local memory, data first posted PTMPB. They then transferred local memory host master write also hits cache. 3.3.3 Data Flow Between
Write data from master buffered PTMPB before transferred local memory. Parity generated memory write data. masters receive data from local memory through this path. PRMB, 64-bit read Memory buffer implemented this path. read parity ignored inside PLDB.
Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
3.3.4 Address Flow Data Flow Basic Cycles Cycles CPU/R/PCI CPU/W/PCI CPU/R/ISA Address Flow HA5501AD HA5501AD HA5501AD5503 LA,SA CPU/W/ISA HA5501AD5503 LA,SA CPU/R/DRAM HA5501MA CPU/W/DRAM HA5501MA CPU/R/L2 Independent CPU/W/L2 Independent CPU/R/PCI(master abort) HA5501AD PCI/R/L2 AD5501HA PCI/W/L2 AD5501HA PCI/R/DRAM AD5501HA PCI/W/DRAM AD5501HA ISA/R/L2 LA,SA5503AD5501 ISA/W/L2 LA,SA5503AD5501 DMA/R/L2 5503AD5501HA, 5503LA,SA DMA/W/L2 5503AD5501HA, 5503LA,SA ISA/R/DRAM LA,SA5503AD5501 ISA/W/DRAM LA,SA5503AD5501 DMA/R/DRAM 5503AD5501MA, 5503LA,SA DMA/W/DRAM 5503AD5501MA, 5503LA,SA Refresh 5503SA Data Flow AD5502HD HD5502AD SD5503AD5502 HD5502AD5503 MD5502HD HD5502MD Independent Independent 5502HD HD5502AD AD5502HD MD5502AD AD5502MD HD5502AD5503 SD5503AD5502 HD5502AD5503 SD5503AD5502 MD5502AD5503 SD5503AD5502 MD5502AD5503 SD5503AD5502
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
Assignment Description
3.4.1 Assignment
VDD3 MD63 MD62 MD61 MD60 MD59 MD58 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32
5502
HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 VDD3 CPURST RAMW HGDW ADLE# CPPOP CPPSH CMPOP CMPSH MDLE PRDLE ADOE PARITY# HCR0 HCR1 HLDA CPUCLK AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
3.4.2 Listing means active low)
1=HD9 2=HD8 3=HD7 4=HD6 5=HD5 6=HD4 7=HD3 8=HD2 9=VSS 10=HD1 11=HD0 12=VDD3 13=MD63 14=MD62 15=MD61 16=MD60 17=MD59 18=MD58 19=MD57 20=MD56 21=MD55 22=VSS 23=MD54 24=MD53 25=MD52 26=VDD 27=MD51 28=VSS 29=MD50 30=MD49 31=MD48 32=MD47 33=MD46 34=MD45 35=MD44 36=MD43 37=MD42 38=MD41 39=MD40 40=MD39 41=MD38 42=MD37 43=MD36 44=MD35 45=VSS 46=MD34 47=MD33 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 48=MD32 49=PD7 50=PD6 51=PD5 52=PD4 53=MD31 54=MD30 55=MD29 56=MD28 57=MD27 58=MD26 59=VDD 60=MD25 61=MD24 62=MD23 63=VSS 64=MD22 65=MD21 66=MD20 67=MD19 68=MD18 69=MD17 70=MD16 71=MD15 72=MD14 73=MD13 74=MD12 75=MD11 76=MD10 77=MD9 78=MD8 79=MD7 80=VSS 81=MD6 82=MD5 83=MD4 84=MD3 85=MD2 86=MD1 87=MD0 88=PD3 89=PD2 90=VDD 91=PD1 92=PD0 93=AD31 94=AD30
95=AD29 96=AD28 97=AD27 98=PCICLK 99=VSS 100=AD26 101=AD25 102=AD24 103=AD23 104=AD22 105=AD21 106=AD21 107=AD19 108=AD18 109=AD17 110=AD16 111=AD15 112=AD14 113=AD13 114=AD12 115=AD11 116=VSS 117=AD10 118=AD9 119=AD8 120=AD7 121=AD6 122=AD5 123=AD4 124=VDD 125=AD3 126=AD2 127=AD1 128=AD0 129=VSS 130=CPUCLK 131=HLDA 132=HCR1 133=HCR0 134=PARITY# 135=ADOE 136=PRDLE 137=MDLE 138=CMPSH 139=CMPOP 140=CPPSH 141=CPPOP
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
142=ADLE# 143=HGDW 144=RAMW# 145=CPURST 146=VDD3 147=HD63 148=HD62 149=VSS 150=HD61 151=HD60 152=HD59 153=HD58 154=HD57 155=HD56 156=HD55 157=HD54 158=HD53 159=HD52 160=VSS 161=HD51 162=HD50 163=HD49 164=HD48 165=HD47 166=HD46 167=HD45 168=HD44 169=VDD3 170=HD43 171=HD42 172=VSS 173=HD41 174=HD40 175=HD39
5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V
176=HD38 177=HD37 178=HD36 179=HD35 180=HD34 181=HD33 182=HD32 183=VSS 184=HD31 185=HD30 186=HD29 187=HD28 188=HD27 189=HD26 190=HD25 191=HD24 192=HD23 193=HD22 194=VSS 195=HD21 196=HD20 197=HD19 198=VDD3 199=HD18 200=HD17 201=HD16 202=HD15 203=HD14 204=HD13 205=HD12 206=VSS 207=HD11 208=HD10
5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
3.4.3 Description 147,148 150-159 161-168 170,171 173-182 184-193 195-197 199-205 207,208 1-8,10,11 13-21,2325, 27,2944,46-48, 53-58 60-62,6479, 81-87 93-97, 100-115, 117-123 125-128 91,92,4952, 88,89 Symbol HD[63:0] Type Function data bus.
MD[63:0]
Memory data bus.
AD[31:0]
address/data bus.
PD[7:0] PARITY# ADOE
Parity bus. Parity Error signal. Drive bus. This signal used enable 5502 drive bus. asserted writes master reads local memory cycles. Hold Acknowledge asserted response assertion CPUHLDA. Memory data Read Latch Enable. This signal latches data when negated. Data Latch Enable. This signal following functions: Latch data into read buffer (PRMB) Latch data into read buffer rising edge PCICLKI. Latch data into posted write buffer (PTMPB) rising edge PCICLKI.
HLDA MDLE ADLE#
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
CPPSH Push Post Write Data into CTPPB 5502. data latched into CTPPB CPPSH rising edge. edge also increases write pointer next available loading entry buffer. rising edge CPPOP, read pointer changed address next available reading location. When this signal asserted, data written into memory posted write buffer (CTMPB) rising edge CPUCLK, write pointer also changed address next available location. When this signal asserted, read pointer CTMPB increased rising edge CPUCLK. This signal latches current output entry CTPPB, post write buffer, into prelatch 5502. output prelatch driven bus. master cycles, PRDLE also asserted when master reading data from secondary cache, when master writing data local memory. High Double Word Indicator. signal driven high 5501 when high from written into Posted Write Buffer, reads high from bus, master writes high local memory, master reads high from local memory. Host Data Control. These signals driven 5501 they used control 5502 HD[63:0] bus. They defined 5502 floats 5502 drives FFFFFFFF 5502 drives data from 5502 drives data from DRAM Write Enable. Reset. Clock. Clock. power
CPPOP
CMPSH
CMPOP
PRDLE
HGDW
132,133
HCR[1:0]
26,59,90,
RAMW# CPURST CPUCLK PCICLK
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
146, VDD3 169, 9,22,28,45 ,63,80,99, 116,129, 149,160 172,183, 194,206 +3.3V power system power system Ground
Electrical Characteristics
3.5.1 Absolute Maximum Ratings Parameter Ambient operating temperature Storage temperature Input voltage Output voltage Power Dissipation -0.3 -0.5 Unit
Note: Stress above these listed cause permanent damage device. Functional operation this device should restricted conditions described under operating conditions. 3.5.2 Characteristics VDD=5V+5%, VDD3=3.3V+5% Symbol Parameter Unit Condition VIL1 Input Voltage -0.3 Note VDD3=3.3V VIH1 Input High Voltage VDD3+0.3V Note VIL2 Input Voltage -0.3 Note VIH2 Input High Voltage VDD+0.3 Note VOL1 Output Voltage 0.45 Note VOH1 Output High Voltage Note VOL2 Output Voltage Note VOH2 Output High Voltage VDD3 Note IOL1 Output Current Note IOH1 Output High Current Note Input Leakage Current Input Leakage Current Input Capacitance Fc=1 COUT Output Capacitance Fc=1 CI/O Capacitance Fc=1 ICC3 Power Supply Current 3.3V, 66MHz VDD3 Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
Note: VIL1 VIH1 applicable HD[63:0]. VIL2 VIH2 applicable MD[63:0], AD[31:0], CPURST, PD[7:0], CPUCLK, ADOE, HLDA, HCR[1:0], PRDLE, MDLE, CMPSH, CMPOP, CPPSH, CPPOP, ADLE#, HGDW, RAMW#. VOL1 VOH1 applicable MD[63:0], AD[31:0], PD[7:0], PARITY#. VOL2 VOH2 applicable HD[31:0]. IOL1 IOH1 applicable HD[63:0], MD[63:0], AD[31:0], PD[7:0], PARITY#. 3.5.3 Characteristics Symbol Preliminary V2.0 Parameter Data Setup Time MDLE falling Data Hold Time MDLE falling Data Valid Delay from data valid ADLE# Setup Time PCICLK rising ADLE# Hold Time PCICLK rising HGDW Setup Time PCICLK rising HGDW Hold Time PCICLK rising Data Setup Time PCICLK rising Data Hold Time PCICLK rising Data Valid Delay from PCICLK rising CMPSH Setup Time CPUCLK rising CMPSH Hold Time CPUCLK rising CMPOP Setup Time CPUCLK rising CMPOP Hold Time CPUCLK rising Data Setup Time CPPSH rising Data Hold Time CPPSH rising Data Valid Delay from CPUCLK rising Data Valid Delay from CPUCLK rising RAMW# Setup Time MDLE rising RAMW# Hold Time MDLE falling PARITY# Active Delay from MDLE falling Data Valid from PRDLE rising Data Valid from data valid HGDW Setup Time CPPSH rising HGDW Hold Time CPPSH rising Data Valid Delay from PCICLK rising Data Valid Delay from PCICLK rising Data Setup Time ADLE# falling Data Hold Time ADLE# falling Data Valid Delay from data valid Output Delay from RAMW# asserted April 1995 3.2, 3.2, 3.3,3.8 3.3,3.8 3.3,3.8 3.3,3.8 3.3,3.8 3.3,3.8 3.3,3.8 3.4,3.5 3.4,3.5 3.10 3.11
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
Output Float Delay from RAMW# inactive Output Delay from ADOE asserted Output Float Delay from ADOE inactive Output Delay from asserted Output Float Delay from inactive 3.11 3.12 3.12 3.13 3.13 Unit
3.5.4 Timing Diagram MDLE
Figure Read DRAM Cycle PCICLK ADLE# HGDW
T5,T7 T4,T6
Figure Read Slave Cycle CPUCLK CMPSH CMPOP
T11,T13 T12,T14
Figure Write DRAM Cycle CPPSH HGDW
Figure Write Post Write Buffer
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
PRDLE
Figure Write Posted Data onto MDLE RAMW# PARITY#
Figure PARITY# Generation Reading DRAM Cycle PCICLK ADLE# HGDW
T5,T7 T4,T6
Figure Read Slave Cycle ADLE#
Figure Master Read Secondary Cache MDLE ADLE#
Figure 3.10 Master Read DRAM
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5502 Local Data Buffer
RAMW#
Figure 3.11 Write DRAM Cycle
ADOE
Figure 3.12 Write Posted Data onto
Figure 3.13 Read DRAM Cycle
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5503 System
SiS5503
Features
Integrated Bridge Between Translates Cycles into Cycles Translates Master Cycles into Cycles Provides PCI-to-ISA Memory DoubleWord Posted Write Buffer Integrated Compatible Logic Controller Arbiter Master, Devices, Refresh Built-in 8237 Compatible Controllers Built-in 8259A Compatible Interrupt Controllers Built-in 8254 Timer Supports Reroutibilty four Interrupts Unused Interrupt Supports Flash Built-in with Bytes Extended CMOS SRAM Built-in Fully Compatible with Local Specification V2.0. Accommodates Bits, Bits, Bits Data Transfer. Supports Burst Read/Write Operation. Supports Read Ahead Posted Write Buffers Concurrent System Operation. Controls Channels Max. Connects Drives. Supports Mode Timing Specification. Programmable Command Recovery Timing Reads Writes Channel. Auto Channel Speed Setting with Software Driver. Hardware Software Chip Disable Capability Supports Power Down Feature Meet Specification Buffer Strength 160-Pin PQFP CMOS Technology
Functional Description
SiS5503 highly integrated PCI/ISA system (PSIO) device that integrates necessary system control logic used PCI/ISA specific applications. SiS5503 consists bridge that translates cycles onto bus, master/DMA device cycles onto bus; seven-channel programmable Controller, sixteen-level programmable interrupt controller, programmable timer with three counters, built-in with bytes extended CMOS SRAM, built-in IDE. Since 5503 includes bridge IDE, naturally becomes multifunction device. PCI/ISA bridge defined function device while function device. following examples describe write register bridge configuration space register configuration space. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5503 System
Example EAX, 800010XXh 0CF8h, data 0CFDh, Example EAX, 800011YYh 0CF8h, data 0CFDh, 4.2.1. Bridge SiS5503 interface provides interface between PSIO bus. contains both master slave bridge bus. When SIOGNT# asserted, master bridge translates master cycles onto based decoding status from address decoder. When SIOGNT# negated, slave bridge accepts these cycles initiated targeted PSIO internal registers bus, then forwards cycles Interface that further translates them onto Bus. address decoder provides information which slave bridge depends respond process cycle initiated Masters. Slave Bridge slave, PSIO responds both memory transfers. PSIO always targetterminates after first data phase bursting cycle. SiS5503 always converts single interrupt acknowledge cycle (from 5501) into cycles that internal 8259 pair respond PSIO assigned subtractive decoder PCI/ISA system accepting accesses positively decoded some other agent. reality, PSIO only subtractively responds memory accesses. PSIO also positively decodes addresses internal registers, BIOS memory space asserting DEVSEL# medium timing. Master Bridge long SIOGNT# asserted, master bridge behalf devices Masters starts drive bus, C/BE[3:0]# signal. When MRDC# MWTC# asserted, PSIO will generate FRAME#, IRDY# targeted memory side. valid address command driven during address phase, asserted clock after that phase. PSIO always activated FRAME# PCLKs because does conduct bursting cycle.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5503 System
address decoder used determine destination master devices. This decoder provides following options they defined configuration registers Memory: 0-512K Memory: 512K-640K Memory: 640K-768K(video buffer) Memory: 768K-896K eight sections(Expansion ROM) Memory: 896K-960K(lower BIOS area) Memory: 1M-XM-16M within which hole opened. Access hole forwarded bus. Memory:>16Mb automatically forwards PCI. 4.2.2 Controller SiS5503 Interface accepts those cycles from interface then translates them onto bus. also requests master bridge generate cycle behalf master. interface thus contains standard Controller Data Buffering logic. provides control, such command generation, recovery control, wait-state insertion, data buffer steering. to/from address data bufferings also integrated SiS5503. SiS5503 directly support slots without external data address buffering. Standard refresh requested Counter then performed IBC. generates pertinent command refreshes address bus. Since refresh transparent cycle, arbiter employed resolve possible conflicts among cycles, refresh cycles, cycles. 4.2.3 Controller SiS5503 contains seven-channel controller. channel 8-bit devices while channel 16-bit devices. channels also programmed four transfer modes, which include single, demand, block, cascade. Except cascade mode, each three active transfer modes perform three different types transfers, which include read, write, verify. address generation circuitry SiS5503 only support 24-bit address devices. 4.2.4 Interrupt Controller SiS5503 provides compatible interrupt controller that incorporates functionality 82C59 interrupt controllers. controllers cascaded that external internal interrupts supported. master interrupt controller provides IRQ<7:0> slave provides IRQ<15:8>. internal interrupt used internal functions only available externally. IRQ2 used cascade controllers together IRQ0 used system timer interrupt tied interval Counter remaining interrupt lines available external system interrupts. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5503 System
Priority 3-10 Label IRQ0 IRQ1 IRQ2 IRQ8# IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Controller Typical Interrupt Source Timer/Counter Keyboard Interrupt from Controller Real Time Clock Expansion Expansion Expansion Expansion Coprocessor Error Ferr# Fixed Disk Drive Controller Expansion Expansion Serial port Expansion Serial port Expansion Parallel Port Expansion Diskette Controller, Expansion Parallel Port, Expansion
addition features, ability interrupt sharing included. registers(ECLR) located 4D0h 4D1h defined allow edge level sense selection made individual channel channel basis instead complete bank channels. Note that default IRQ0, IRQ1, IRQ2, IRQ8# IRQ13 edge sensitive, programmed. Also, each Interrupt(INTx#) programmed independently route eleven compatible interrupts(IRQ<7:3>, IRQ<15:14>, IRQ<12:9>) through configuration registers 44h. 4.2.5 Timer/Counter SiS5503 contains channel counter/timer that equivalent those found 82C54 programmable interval timer. counters division 14.31818MHz input clock source. outputs timers directed system functions. Counter connected interrupt controller IRQ0 provides system timer interrupt time-ofday, diskette time-out, other system timing function. Counter generates refreshrequest signal Counter generates tone speaker. 4.2.6 Built-in 5503 incorporates real-time clock system configuration memory. combines: complete time-of-day clock with alarm year calendar Programmable periodic interrupt bytes clock control registers bytes lower power general purpose SRAM Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5503 System
method accessing upper bytes CMOS SRAM write port then setting port 23h. 4.2.7 Built-in internal contains five blocks. They interface decode, system configuration control, interface ckt, read ahead buffers, posted write buffers. Interface Decode internal operates slave device. decodes interprets cycles generate signals start terminate cycles. This block responds only cycles that belong address space. supports both 16bit 32-bit data transfer address 1F0/170. other registers 8-bit only. System Configuration Control Configuration This block contains configuration header registers meet specifications. internal supports type configuration cycles configuration mechanism Interface Proper cycle timing generated speed different mode drive. cycle timing controlled software programming. Posted Write Buffers Read Ahead Buffers internal kinds buffers, posted write buffers read ahead buffers. They enabled disabled independently. posted write buffers enhance transfer rate interface interface write operation decoupling wait-states effect from slower side faster side. read ahead buffers eliminate idle cycle side improve read operation.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5503 System Functional Block Diagram
SD[15:8] SA[16:0] LA[23:17] IO16# M16# SBE# MR16# MRDC# MWTC# CHRDY IOCHK# BCLK BALE IORC# IOWC# SMRDC# SMWTC# ZWS# RTCALE RTCRD RTCWR REF# ROMKBCS# SDIR IGNNE# XD[7:0]
PCICLK PCIRST# AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# STOP# LOCK# DEVSEL# SERR# A-D# SIOREQ# SIOGNT#
DATA
INTERFACE
BUFFER
DECODER
DECODER
INTERFACE
IRQ(15,14, 12:9,7:3,1) FERR# IRQ8 WAKEUP0 WAPEUP1
INTERRUPT
CONTROLLER
SPKR
TIMERs/COUNTERs
CONTROLLER
DRQ[7:5,3:0] DAK[2:0]
*RTCVDD *OSCI *PSRSTB# *PWRGD
*ID[15:0] *IDECS[3:0]#
Multi-function
Figure SiS5503 Functional Block Diagram
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5503 System Configuration Registers
Registers 00h, Bits 15:0 Vendor Identification Register
1039h (Read Only) Device Identification Register
Registers 02h, Bits 15:0
0008h (Read Only) Command Register
Registers 04h, Bits 15:4
Reserved. Read (Special Cycle Enable) (Bus Master Enable) (Memory Space Enable) IOSE (I/O Space Enable) Device Status Register
Registers 07h-06h Bits 15:14
Reserved. Read (Master-Abort Status). When 5503 generates master-abort, Software clears writing this location.
(Received Target-Abort Status). When 5503 receives target-abort, Software clears writing this location.
Bits 10:9
Reserved. Read DEVT (SIO DEVSEL# Timing Status). 5503 always generates DEVSEL# with medium timing, DEVT=01
Bits Register Bits
Reserved. Read 0's. Revision Identification Register (Read Only)
Register 0B-09h Class Code Bits 23:0 060100h (Read Only)
Register Header Type
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5503 System
Bits Register When MASTER retries, Arbiter deasserts SIOGNT#. This defaults Posted Write Buffer Enable default value (disabled). Bits [3:0] determine 5503 responds segment, segment, extended segment (FFF80000-FFFDFFFF) accesses. 5503 will positively respond extended segment access when set. combining with bits [3:2], enables 5503 respond segment access. bits [3:2] Positive Decode Upper BYTE BIOS Enable. BIOS Subtractive Decode Enable. segment segment 5503 positively responds segment access. 5503 subtractively responds segment access. 5503 positively responds segment access. 5503 positively responds segment access. comment BIOSCON BIOS Control Register Reserved. Read Reserved. Read
enabled set. Lower BIOS Enable. Register
Extended BIOS Enable. (FFF80000~FFFDFFFF) INTA# Remapping Control Register Remapping Control When enabled, INTA#, remapped compatible interrupt signal specified remapping table. This after reset. Enable Disable Reserved. Read 0's. April 1995 Silicon Integrated Systems Corporation
Bits Preliminary V2.0
SiS5503 System
Bits IRQx Remapping table. Bits 0000 0001 0010 0011 0100 Register Bits Bits Register Bits Bits Register Bits Bits IRQx# reserved reserved reserved IRQ3 IRQ4 Bits 0101 0110 0111 1000 1001 IRQx# IRQ5 IRQ6 IRQ7 reserved IRQ9 Bits 1010 1011 1100 1101 1110 IRQx# IRQ10 IRQ11 IRQ12 reserved IRQ14 Bits 1111 IRQx# IRQ15
INTB# Remapping Control Register Remapping Control Reserved. Read 0's. Remapping table. INTC# Remapping Control Register Remapping Control Reserved. Read 0's. Remapping table. INTD# Remapping Control Register Remapping Control Reserved. Read 0's. Remapping table. Note: difference INT[A:D]# remapped same signal, this signal should level sensitive.
Register
Master/DMA Memory Cycle Control Register master memory access cycles will forwarded when address fall within programmable region defined bits[7:4]. base address programmable region 1Mbyte, addresses programmed 1MByte increments from 1MByte 16MByte. memory cycles will forwarded besides cycle fall within memory hole defined register 4Bh.
Bits Bits Preliminary V2.0 Memory MByte Silicon Integrated Systems Corporation
April 1995
SiS5503 System
MByte MByte MByte MByte MByte MByte MByte MByte MByte MByte MByte MByte MByte MByte MByte master memory cycles following memory regions will forwarded they enabled. F0000h~EFFFFh Memory Region Disable Enable, cycle forwarded bus. A0000h~BFFFFh memory Region Disable Enable, cycle forwarded bus. 80000h~9FFFFh Memory Region Disable Enable cycle forwarded bus. 00000h~7FFFFh Memory Region Disable Enable cycle forwarded bus. Register Master/DMA Memory Cycle Control Register master memory cycles following memory regions will forwarded they enabled. DC000h-DFFFFh Memory region Disable Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5503 System
Enable D8000h-DBFFFh Memory Region Disable Enable D4000h-D7FFFh Memory Region Disable Enable D0000h-D3FFFh Memory Region Disable Enable CC000h-CFFFFh Memory Region Disable Enable C8000h-CBFFFh Memory Region Disable Enable C4000h-C7FFFh Memory Region Disable Enable C0000h-C3FFFh Memory Region Disable Enable Register Master/DMA Memory Cycle Control Register Register register used define address hole. address hole located between 1Mbyte 16MByte, sized 64KByte increments. master memory cycles fall within this hole will forwarded bus. Register used define bottom address hole respectively. hole located between bottom address, bottom address must above 1MByte. bottom address greater than address, address hole disabled. Preliminary V2.0 April 1995 Silicon Integrated Systems Corporation
SiS5503 System
Register Master/DMA Memory Cycle Control Register This register used define address Address hole.
Registers 4Ch-4Fh Bits ICW1 ICW4 built-in interrupt controller (master) read from 4Fh.
Registers 50h-53h Bits ICW1 ICW4 built-in interrupt controller (slave) read from 53h.
Registers 54h-55h Bits OCW2 OCW3 built-in interrupt controller (master) read from 55h.
Registers 56h-57h Bits Register Bits byte initial count number Counter built-in read from 58h. OCW2 OCW3 built-in interrupt controller (slave) read from 57h.
Preliminary V2.0
April 1995
Silicon Integrated Systems Corporation
SiS5503 System
Register Bits Register Bits Register Bits Register Bits Register Bits Register Bits Register Bits indicates status whether read written when Read/Write word function been processed corresponding counter. Control word (43h) built-in read from 5Eh. High byte initial count number Counter built-in read from 5Dh. byte initial count number Counter built-in read from 5Ch. High byte initial count number Counter built-in read from 5Bh. byte initial count number Counter built-in read from 5Ah. High byte initial count number Counter built-in read from 59h.
Non-Configuration Registers
Registers These registers accessed from bus. Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h Attribute Register Name DMA1 Base Current Address Register DMA1 Base Current Count Register DMA1 Base Current Address Register DMA1 Base Current Count Register DMA1 Base Current Address Register DMA1 Base Current Count Register DMA1 Base Current Address Register DMA1 Base Current Count Register DMA1 Status(r) Command(w) Register Silicon Integrated Systems Corporation
Preliminary V2.0
April 1995
SiS5503 System
0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 00C0h 00C2h 00C4h 00C6h 00C8h 00CAh 00CCh 00CEh 00D0h 00D2h 00D4h 00D6h 00D8h 00DAh 00DCh 00DEh DMA1 Request Register DMA1 Write Single Mask DMA1 Mode Register DMA1 Clear Byte Pointer DMA1 Master Clear DMA1 Clear Mask Register DMA1 Write Mask Bits(w) Mask Status Register(r) DMA2 Base Current Address Register DMA2 Base Current Count Register DMA2 Base Current Address Register DMA2 Base Current Count Register DMA2 Base Current Address Register DMA2 Base Current Count Register DMA2 Base Current Address Register DMA2 Base Current Count Register DMA2 Status(r) Command(w) Register DMA2 Request Register DMA2 Write Single Mask Register DMA2 Mode Register DMA2 Clear Byte Pointer DMA2 Master Clear DMA2 Clear Mask Register DMA2 Write Mask Bits(w) Mask Status Register(r)
These registers accessed from bus. Address 0080h 0081h 0082h 0083h 0084h 0085h 0

5501/5502/5503 Overview SiS5501 SiS5502 SiS5503 PCI/ISA Cache Mem

Top Searches for this datasheet

Other recent searches