HM62V864 Series 65536-word 8-bit Voltage Operation CMOS Static
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ADE-203-316A
HM62V864 Series
65536-word 8-bit Voltage Operation CMOS Static
Rev. Nov. 1994
Hitachi HM62V864 CMOS static organized 64-kword 8-bit. realizes higher density, higher performance power consumption employing Hi-CMOS process technology. offers power standby power dissipation; therefore, suitable battery back-up systems. device, packaged 525-mil (460-mil body SOP) TSOP with thickness available high density mounting. TSOP package suitable cards.
Ordering Information
Type HM62V864LFP-8 Access time Package 525-mil 32-pin plastic (FP-32D) 32-pin TSOP (normal type) (TFP-32D)
HM62V864LT-8
Features
voltage operation SRAM Single supply High speed Fast access time: (max) power Standby: 1.32 (typ) Completely static memory clock timing strobe required Equal access cycle times Common data input output Three state output Directly LVTTL compatible inputs outputs Capability battery back operation (Lversion) chip selection battery back
HM62V864 Series
Arrangement
HM62V864LFP Series HM62V864LT Series
I/O0 I/O1 I/O2
(Top view)
I/O7 I/O6 I/O5 I/O4 I/O3
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
(Top view)
Description
name I/O0 I/O7 Function Address Input/output Chip select Chip select Write enable Output enable connection Power supply Ground
HM62V864 Series
Block Diagram
(MSB) (LSB) Decoder
Memory Matrix 1,024
I/O0 Input Data Control I/O7
Column Column Decoder
(MSB)
(LSB)
Timing Pulse Generator Read/Write Control
Function Table
Note: Mode selected selected Output disable Read Write Write current ISB, ISB1 ISB, ISB1 High-Z High-Z High-Z Dout Ref. cycle Read cycle Write cycle Write cycle
HM62V864 Series
Absolute Maximum Ratings
Parameter Power supply voltage*1
Symbol Topr Tstg Tbias
Value -0.5 +4.6 -0.5 +125
Unit 0.3*3
Terminal voltage
Power dissipation Operating temperature Storage temperature Storage temperature under bias Note:
Relative min: -3.0 pulse half-width Maximum voltage
Recommended Operating Conditions +70°C)
Parameter Supply voltage Symbol Input high (logic voltage Input (logic voltage Note: 0.7VCC -0.3
0.2VCC
Unit
min: -3.0 pulse half-width
HM62V864 Series
Characteristics +70°C,
Parameter Input leakage current Output leakage current Symbol |ILI| |ILO| Typ*1 Unit Test conditions VIL, VI/O VIL, VIH, Others VIH/VIL, II/O cycle, duty 100%, VIL, VIH, Others VIH/VIL, II/O Cycle time duty 100%, II/O VIH,
Operating power supply current Average operating power supply current
ICC1
ICC2
Standby power supply current
ISB1
Output voltage Output high voltage Note:
Typical values +25°C guaranteed.
Capacitance 25°C, MHz)*1
Parameter Input capacitance Input/output capacitance Note: Symbol CI/O Unit Test conditions VI/O
This parameter sampled 100% tested.
HM62V864 Series
Characteristics +70°C, unless otherwise noted.)
Test Conditions Input pulse levels: Input rise fall times: Input timing reference level: Output timing reference level:
Output Load
Dout
pF*1
Note Including scope
Read Cycle
HM62V864-8 Parameter Read cycle time Address access time Chip selection output valid Symbol tCO1 tCO2 Output enable output valid Chip selection output low-Z tLZ1 tLZ2 Output enable output low-Z Chip deselection output high-Z tOLZ tHZ1 tHZ2 Output disable output high-Z Output hold from address change tOHZ Unit Notes
HM62V864 Series
Read Timing Waveform
Address
Valid Address
Dout High Impedance Valid data
Notes: tOHZ defined time which outputs achieve open circuit conditions referred output voltage levels. This parameter sampled 100% tested. high read cycle.
HM62V864 Series
Write Cycle
HM62V864-8 Parameter Write cycle time Chip selection write Address setup time Address valid write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time Output active from write Symbol tWHZ Unit Notes
HM62V864 Series
Write Timing Waveform Clock)
Address
Valid Address
WR*4
High Impedance Dout
Valid data
HM62V864 Series
Write Timing Waveform Fixed)*12
Address
Valid Address
WR*4
*5*11
Dout High Impedance Valid data
Notes: write occurs during overlap CS1, high CS2, write begins latest transition among going low, going high, going low. write ends earliest transition among going high, going low, going high. measured from beginning write write. measured from later going going high write. measured from address valid beginning write. measured from earliest going high going write cycle. During this period, pins output state; therefore, input signals opposite phase outputs must applied. goes simultaneously with going after going low, outputs remain high impedance state. Dout same phase latest written data this write cycle. Dout read data next address. high during this period, pins output state. Therefore, input signals opposite phase outputs must applied them. This parameter sampled 100% tested. tOHZ tWHZ defined time which output achieve open circuit conditions referred output voltage levels.
HM62V864 Series
write cycle with fixed, must satisfy following equation avoid problem data contention, tWHZ min.
Data Retention Characteristics +70°C)
Parameter data retention Symbol Unit Test conditions*2 retention waveform
Data retention current
ICCDR
27*1
Chip deselect data retention time Operation recovery time
tCDR
tRC*4
Data Retention Timing Waveform (CS1 Controlled)
Data retention mode
Data Retention Timing Waveform (CS2 Controlled)
Data retention mode
HM62V864 Series
Notes: 40°C. controls address buffer, buffer, buffer, buffer, buffer. controls data retention mode, levels (address, CS1, I/O) high impedance state. controls data retention mode, must other input levels (address, I/O) high impedance state. Typical values 25°C guaranteed. Read cycle time.
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