PD161606 OUTPUTS TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR
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INTEGRATED CIRCUIT
PD161606
OUTPUTS TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR
DESCRIPTION
PD161606 TFT-LCD source driver that includes display RAM. This driver outputs, display capacity 115,200 bits (240 pixels bits lines rendering flag) partial display RAM.
FEATURES
TFT-LCD driver with on-chip display Logic power supply voltage: (Generating inside chip also possible from power supply interface power supply) CPU/RGB interface power supply voltage: Gate driver power supply voltage: Driver power supply voltage: Display RAM: bits Driver outputs: outputs interface: Three types interfaces selectable 6-bit/16-bit/18-bit interface i80/M68 parallel interface (selectable from 8-bit) 8-bit serial interface (SPI correspondence) Colors: 262,144 colors/pixel On-chip timing generator On-chip oscillator
ORDERING INFORMATION
Part Number Package Chip
PD161606P
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information contained this document being issued advance production cycle product. parameters product change before final production Electronics Corporation, discretion, withdraw product prior production. products and/or types availabe every country. Please check with Electronics sales representative availability additional information.
Document S16789EJ2V0PM00 (2nd edition) Date Published March 2004 CP(K) Printed Japan
mark shows major revised points.
2003
PD161606
CONTENTS
BLOCK DIAGRAM.4 CONFIGURATION (Pad Layout) FUNCTIONS.9
Power Supply System Pins Logic System Pins Driver Pins Pins Gate Control Interface Power Supply.
PROM Control Pins
Test Other Pins
CIRCUITS RECOMMENDED CONNECTION UNUSED PINS.15 DESCRIPTION FUNCTIONS
Interface 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Selection interface type interface. i80/M68 Parallel interface. Serial interface Chip select Access display data internal registers
PD161645 control serial interface
address circuit. address circuit. Arbitrary address area access (window access mode (WAS)).
Partial Display 5.2.1 5.2.2 5.2.3
Oscillator. Display Timing Generator. Curve Correction Circuit 5.5.1 5.5.2 5.5.3 5.5.4 Amplitude adjustment with internal amplifier Amplitude adjustment bulit-in resistance Inclination adjustment Fine tuning adjustment.
Partial Display Function Stand-by.
Preliminary Product Information S16789EJ2V0PM
PD161606
5.7.1 5.7.2 Stand-by mode Stand-by mode
POWER SUPPLY INJECTION/INTERCEPTION
PD161606 Power Supply Injection Setting Sequence Example PD161606 Power Supply Interception Setting Sequence Example
E2PROM INTERFACE.62
PD161606 E2PROM Connection Each Operation.
RESET.68 COMMAND.71
Command List
ELECTRICAL SPECIFICATIONS.80 EXAMPLE PD161606 CONNECTION
Preliminary Product Information S16789EJ2V0PM
PD161606
BLOCK DIAGRAM
T.B.D. Remark T.B.D.: determined.
Preliminary Product Information S16789EJ2V0PM
PD161606
CONFIGURATION (Pad Layout)
Chip size: 19.5 Bump size (output, including long side short side): Bump size (input):
Alignment mark (mark center, unit:
1025 1025 9575 -9575
Alignment mark size
Preliminary Product Information S16789EJ2V0PM
PD161606
Table 2-1. Coordinate (1/3)
NAME DUMMY GSTB GCLK VCOUT GOE2 GOE1 GSCLK DCCLK GRESET DUMMY DUMMY DUMMY VCC3 VCC3 VCC3 VCC3 VCOM VCOM VCOM VCOM CVNH1 CVNH2 CVPH1 CVPH2 CVNL1 CVNL2 CVPL1 CVPL2 DVSS BWS1 DVCC2 BWS0 DVSS DVCC2 SSEL DVSS DVCC2 CSEG DVSS SCLEG1 DVCC2 SCLEG0 DVSS RSEL DVCC2 DVSS /RD(E) /WR(R,/W) DVSS RGB25 RGB24 RGB23 RGB22 RGB21 RGB20 RGB15 RGB14 RGB13 RGB12 RGB11 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 9330.00 9220.00 9110.00 9000.00 8890.00 8780.00 8670.00 8560.00 8450.00 8340.00 8230.00 8120.00 8010.00 7900.00 7790.00 7680.00 7570.00 7460.00 7350.00 7240.00 7130.00 7020.00 6910.00 6800.00 6690.00 6580.00 6470.00 6360.00 6250.00 6140.00 6030.00 5920.00 5810.00 5700.00 5590.00 5480.00 5370.00 5260.00 5150.00 5040.00 4930.00 4820.00 4710.00 4600.00 4490.00 4380.00 4270.00 4160.00 4050.00 3940.00 3830.00 3720.00 3610.00 3500.00 3390.00 3280.00 3170.00 3060.00 2950.00 2840.00 2730.00 2620.00 2510.00 2400.00 2290.00 2180.00 2070.00 1960.00 1850.00 1740.00 1630.00 1520.00 1410.00 1300.00 1190.00 1080.00 970.00 860.00 750.00 640.00 530.00 420.00 310.00 200.00 90.00 -20.00 -130.00 -240.00 -350.00 -460.00 -570.00 -680.00 -790.00 -900.00 -1010.00 -1120.00 -1230.00 -1340.00 -1450.00 -1560.00 NAME RGB10 RGB05 RGB04 RGB03 RGB02 RGB01 RGB00 HSYNC VSYNC DOTCLK /RESET TIN2 TIN1 TIN0 TESTO17 TESTO16 TESTO15 TESTO14 TESTO13 TESTO12 TESTO11 TESTO10 TESTO9 TESTO8 TESTO7 TESTO6 TESTO5 TESTO4 TESTO3 TESTO2 TESTO1 TESTO0 TOSC1SEL TOSC1IN DVCC2 DVSS OSC2SEL OSC2IN OSC2OUT VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC3 VCC4 VCC2 VCC2 VCC2 VCC2 VSTBY DVSS DUMMY DUMMY DUMMY -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -1038.26 -675.30 -630.30 -585.30 -540.30 -495.30 -450.30 -405.30 -360.30 -315.30 -270.30 -225.30 -180.30 -135.30 -90.30 -45.30 -0.30 44.70 89.70 134.70 179.70 224.70 269.70 314.70 359.70 404.70 449.70 494.70 539.70 -1670.00 -1780.00 -1890.00 -2000.00 -2110.00 -2220.00 -2330.00 -2440.00 -2550.00 -2660.00 -2770.00 -2880.00 -2990.00 -3100.00 -3210.00 -3320.00 -3430.00 -3540.00 -3650.00 -3760.00 -3870.00 -3980.00 -4090.00 -4200.00 -4310.00 -4420.00 -4530.00 -4640.00 -4750.00 -4860.00 -4970.00 -5080.00 -5190.00 -5300.00 -5410.00 -5520.00 -5630.00 -5740.00 -5850.00 -5960.00 -6070.00 -6180.00 -6290.00 -6400.00 -6510.00 -6620.00 -6730.00 -6840.00 -6950.00 -7060.00 -7170.00 -7280.00 -7390.00 -7500.00 -7610.00 -7720.00 -7830.00 -7940.00 -8050.00 -8160.00 -8270.00 -8380.00 -8490.00 -8600.00 -8710.00 -8820.00 -8930.00 -9040.00 -9150.00 -9260.00 -9370.00 -9480.00 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9461.26 NAME DUMMY DUMMY S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 584.70 629.70 674.70 719.70 764.70 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 -9596.26 -9461.26 -9596.26 -9461.26 -9596.26 -9254.00 -9226.00 -9198.00 -9170.00 -9142.00 -9114.00 -9086.00 -9058.00 -9030.00 -9002.00 -8974.00 -8946.00 -8918.00 -8890.00 -8862.00 -8834.00 -8806.00 -8778.00 -8750.00 -8722.00 -8694.00 -8666.00 -8638.00 -8610.00 -8582.00 -8554.00 -8526.00 -8498.00 -8470.00 -8442.00 -8414.00 -8386.00 -8358.00 -8330.00 -8302.00 -8274.00 -8246.00 -8218.00 -8190.00 -8162.00 -8134.00 -8106.00 -8078.00 -8050.00 -8022.00 -7994.00 -7966.00 -7938.00 -7910.00 -7882.00 -7854.00 -7826.00 -7798.00 -7770.00 -7742.00 -7714.00 -7686.00 -7658.00 -7630.00 -7602.00 -7574.00 -7546.00 -7518.00 -7490.00 -7462.00 -7434.00 -7406.00 -7378.00 -7350.00 -7322.00 -7294.00 -7266.00 -7238.00 -7210.00 -7182.00 -7154.00 -7126.00 -7098.00 -7070.00 -7042.00 -7014.00 -6986.00 -6958.00 -6930.00 -6902.00 -6874.00 -6846.00 -6818.00 -6790.00 -6762.00 -6734.00 -6706.00 -6678.00 -6650.00 -6622.00
Preliminary Product Information S16789EJ2V0PM
PD161606
Table 2-1. Coordinate (2/3)
NAME S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S159 S160 S161 S162 S163 S164 S165 S166 S167 S168 S169 S170 S171 S172 S173 S174 S175 S176 S177 S178 S179 S180 S181 S182 S183 S184 S185 S186 S187 S188 S189 S190 S191 S192 S193 S194 S195 S196 S197 S198 S199 S200 S201 S202 S203 S204 S205 S206 S207 S208 S209 S210 S211 S212 S213 S214 S215 S216 S217 S218 S219 S220 S221 S222 S223 S224 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 -6594.00 -6566.00 -6538.00 -6510.00 -6482.00 -6454.00 -6426.00 -6398.00 -6370.00 -6342.00 -6314.00 -6286.00 -6258.00 -6230.00 -6202.00 -6174.00 -6146.00 -6118.00 -6090.00 -6062.00 -6034.00 -6006.00 -5978.00 -5950.00 -5922.00 -5894.00 -5866.00 -5838.00 -5810.00 -5782.00 -5754.00 -5726.00 -5698.00 -5670.00 -5642.00 -5614.00 -5586.00 -5558.00 -5530.00 -5502.00 -5474.00 -5446.00 -5418.00 -5390.00 -5362.00 -5334.00 -5306.00 -5278.00 -5250.00 -5222.00 -5194.00 -5166.00 -5138.00 -5110.00 -5082.00 -5054.00 -5026.00 -4998.00 -4970.00 -4942.00 -4914.00 -4886.00 -4858.00 -4830.00 -4802.00 -4774.00 -4746.00 -4718.00 -4690.00 -4662.00 -4634.00 -4606.00 -4578.00 -4550.00 -4522.00 -4494.00 -4466.00 -4438.00 -4410.00 -4382.00 -4354.00 -4326.00 -4298.00 -4270.00 -4242.00 -4214.00 -4186.00 -4158.00 -4130.00 -4102.00 -4074.00 -4046.00 -4018.00 -3990.00 -3962.00 -3934.00 -3906.00 -3878.00 -3850.00 -3822.00 NAME S225 S226 S227 S228 S229 S230 S231 S232 S233 S234 S235 S236 S237 S238 S239 S240 S241 S242 S243 S244 S245 S246 S247 S248 S249 S250 S251 S252 S253 S254 S255 S256 S257 S258 S259 S260 S261 S262 S263 S264 S265 S266 S267 S268 S269 S270 S271 S272 S273 S274 S275 S276 S277 S278 S279 S280 S281 S282 S283 S284 S285 S286 S287 S288 S289 S290 S291 S292 S293 S294 S295 S296 S297 S298 S299 S300 S301 S302 S303 S304 S305 S306 S307 S308 S309 S310 S311 S312 S313 S314 S315 S316 S317 S318 S319 S320 S321 S322 S323 S324 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 -3794.00 -3766.00 -3738.00 -3710.00 -3682.00 -3654.00 -3626.00 -3598.00 -3570.00 -3542.00 -3514.00 -3486.00 -3458.00 -3430.00 -3402.00 -3374.00 -3346.00 -3318.00 -3290.00 -3262.00 -3234.00 -3206.00 -3178.00 -3150.00 -3122.00 -3094.00 -3066.00 -3038.00 -3010.00 -2982.00 -2954.00 -2926.00 -2898.00 -2870.00 -2842.00 -2814.00 -2786.00 -2758.00 -2730.00 -2702.00 -2674.00 -2646.00 -2618.00 -2590.00 -2562.00 -2534.00 -2506.00 -2478.00 -2450.00 -2422.00 -2394.00 -2366.00 -2338.00 -2310.00 -2282.00 -2254.00 -2226.00 -2198.00 -2170.00 -2142.00 -2114.00 -2086.00 -2058.00 -2030.00 -2002.00 -1974.00 -1946.00 -1918.00 -1890.00 -1862.00 -1834.00 -1806.00 -1778.00 -1750.00 -1722.00 -1694.00 -1666.00 -1638.00 -1610.00 -1582.00 -1554.00 -1526.00 -1498.00 -1470.00 -1442.00 -1414.00 -1386.00 -1358.00 -1330.00 -1302.00 -1274.00 -1246.00 -1218.00 -1190.00 -1162.00 -1134.00 -1106.00 -1078.00 -1050.00 -1022.00 NAME S325 S326 S327 S328 S329 S330 S331 S332 S333 S334 S335 S336 S337 S338 S339 S340 S341 S342 S343 S344 S345 S346 S347 S348 S349 S350 S351 S352 S353 S354 S355 S356 S357 S358 S359 S360 S361 S362 S363 S364 S365 S366 S367 S368 S369 S370 S371 S372 S373 S374 S375 S376 S377 S378 S379 S380 S381 S382 S383 S384 S385 S386 S387 S388 S389 S390 S391 S392 S393 S394 S395 S396 S397 S398 S399 S400 S401 S402 S403 S404 S405 S406 S407 S408 S409 S410 S411 S412 S413 S414 S415 S416 S417 S418 S419 S420 S421 S422 S423 S424 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 -994.00 -966.00 -938.00 -910.00 -882.00 -854.00 -826.00 -798.00 -770.00 -742.00 -714.00 -686.00 -658.00 -630.00 -602.00 -574.00 -546.00 -518.00 -490.00 -462.00 -434.00 -406.00 -378.00 -350.00 -322.00 -294.00 -266.00 -238.00 -210.00 -182.00 -154.00 -126.00 -98.00 -70.00 -42.00 -14.00 14.00 42.00 70.00 98.00 126.00 154.00 182.00 210.00 238.00 266.00 294.00 322.00 350.00 378.00 406.00 434.00 462.00 490.00 518.00 546.00 574.00 602.00 630.00 658.00 686.00 714.00 742.00 770.00 798.00 826.00 854.00 882.00 910.00 938.00 966.00 994.00 1022.00 1050.00 1078.00 1106.00 1134.00 1162.00 1190.00 1218.00 1246.00 1274.00 1302.00 1330.00 1358.00 1386.00 1414.00 1442.00 1470.00 1498.00 1526.00 1554.00 1582.00 1610.00 1638.00 1666.00 1694.00 1722.00 1750.00 1778.00
Preliminary Product Information S16789EJ2V0PM
PD161606
Table 2-1. Coordinate (3/3)
NAME S425 S426 S427 S428 S429 S430 S431 S432 S433 S434 S435 S436 S437 S438 S439 S440 S441 S442 S443 S444 S445 S446 S447 S448 S449 S450 S451 S452 S453 S454 S455 S456 S457 S458 S459 S460 S461 S462 S463 S464 S465 S466 S467 S468 S469 S470 S471 S472 S473 S474 S475 S476 S477 S478 S479 S480 S481 S482 S483 S484 S485 S486 S487 S488 S489 S490 S491 S492 S493 S494 S495 S496 S497 S498 S499 S500 S501 S502 S503 S504 S505 S506 S507 S508 S509 S510 S511 S512 S513 S514 S515 S516 S517 S518 S519 S520 S521 S522 S523 S524 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 1806.00 1834.00 1862.00 1890.00 1918.00 1946.00 1974.00 2002.00 2030.00 2058.00 2086.00 2114.00 2142.00 2170.00 2198.00 2226.00 2254.00 2282.00 2310.00 2338.00 2366.00 2394.00 2422.00 2450.00 2478.00 2506.00 2534.00 2562.00 2590.00 2618.00 2646.00 2674.00 2702.00 2730.00 2758.00 2786.00 2814.00 2842.00 2870.00 2898.00 2926.00 2954.00 2982.00 3010.00 3038.00 3066.00 3094.00 3122.00 3150.00 3178.00 3206.00 3234.00 3262.00 3290.00 3318.00 3346.00 3374.00 3402.00 3430.00 3458.00 3486.00 3514.00 3542.00 3570.00 3598.00 3626.00 3654.00 3682.00 3710.00 3738.00 3766.00 3794.00 3822.00 3850.00 3878.00 3906.00 3934.00 3962.00 3990.00 4018.00 4046.00 4074.00 4102.00 4130.00 4158.00 4186.00 4214.00 4242.00 4270.00 4298.00 4326.00 4354.00 4382.00 4410.00 4438.00 4466.00 4494.00 4522.00 4550.00 4578.00 NAME S525 S526 S527 S528 S529 S530 S531 S532 S533 S534 S535 S536 S537 S538 S539 S540 S541 S542 S543 S544 S545 S546 S547 S548 S549 S550 S551 S552 S553 S554 S555 S556 S557 S558 S559 S560 S561 S562 S563 S564 S565 S566 S567 S568 S569 S570 S571 S572 S573 S574 S575 S576 S577 S578 S579 S580 S581 S582 S583 S584 S585 S586 S587 S588 S589 S590 S591 S592 S593 S594 S595 S596 S597 S598 S599 S600 S601 S602 S603 S604 S605 S606 S607 S608 S609 S610 S611 S612 S613 S614 S615 S616 S617 S618 S619 S620 S621 S622 S623 S624 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 4606.00 4634.00 4662.00 4690.00 4718.00 4746.00 4774.00 4802.00 4830.00 4858.00 4886.00 4914.00 4942.00 4970.00 4998.00 5026.00 5054.00 5082.00 5110.00 5138.00 5166.00 5194.00 5222.00 5250.00 5278.00 5306.00 5334.00 5362.00 5390.00 5418.00 5446.00 5474.00 5502.00 5530.00 5558.00 5586.00 5614.00 5642.00 5670.00 5698.00 5726.00 5754.00 5782.00 5810.00 5838.00 5866.00 5894.00 5922.00 5950.00 5978.00 6006.00 6034.00 6062.00 6090.00 6118.00 6146.00 6174.00 6202.00 6230.00 6258.00 6286.00 6314.00 6342.00 6370.00 6398.00 6426.00 6454.00 6482.00 6510.00 6538.00 6566.00 6594.00 6622.00 6650.00 6678.00 6706.00 6734.00 6762.00 6790.00 6818.00 6846.00 6874.00 6902.00 6930.00 6958.00 6986.00 7014.00 7042.00 7070.00 7098.00 7126.00 7154.00 7182.00 7210.00 7238.00 7266.00 7294.00 7322.00 7350.00 7378.00 NAME S625 S626 S627 S628 S629 S630 S631 S632 S633 S634 S635 S636 S637 S638 S639 S640 S641 S642 S643 S644 S645 S646 S647 S648 S649 S650 S651 S652 S653 S654 S655 S656 S657 S658 S659 S660 S661 S662 S663 S664 S665 S666 S667 S668 S669 S670 S671 S672 S673 S674 S675 S676 S677 S678 S679 S680 S681 S682 S683 S684 S685 S686 S687 S688 S689 S690 DUMMY DUMMY DUMMY S691 S692 S693 S694 S695 S696 S697 S698 S699 S700 S701 S702 S703 S704 S705 S706 S707 S708 S709 S710 S711 S712 S713 S714 S715 S716 S717 S718 S719 S720 DUMMY DUMMY 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 911.26 1046.26 764.70 719.70 674.70 629.70 584.70 539.70 494.70 449.70 404.70 359.70 314.70 269.70 224.70 179.70 134.70 89.70 44.70 -0.30 -45.30 -90.30 -135.30 -180.30 -225.30 -270.30 -315.30 -360.30 -405.30 -450.30 -495.30 -540.30 -585.30 -630.30 -675.30 7406.00 7434.00 7462.00 7490.00 7518.00 7546.00 7574.00 7602.00 7630.00 7658.00 7686.00 7714.00 7742.00 7770.00 7798.00 7826.00 7854.00 7882.00 7910.00 7938.00 7966.00 7994.00 8022.00 8050.00 8078.00 8106.00 8134.00 8162.00 8190.00 8218.00 8246.00 8274.00 8302.00 8330.00 8358.00 8386.00 8414.00 8442.00 8470.00 8498.00 8526.00 8554.00 8582.00 8610.00 8638.00 8666.00 8694.00 8722.00 8750.00 8778.00 8806.00 8834.00 8862.00 8890.00 8918.00 8946.00 8974.00 9002.00 9030.00 9058.00 9086.00 9114.00 9142.00 9170.00 9198.00 9226.00 9254.00 9282.00 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26 9461.26 9596.26
Preliminary Product Information S16789EJ2V0PM
PD161606
FUNCTIONS
Power Supply System Pins
Symbol VCC1 Name Logic power supply Function This power supply logic circuit. When VSTBY power supply voltage input from this directly used power supply voltage internal logic circuit. When VSTBY voltage output SF_VCC1 used logic power supply voltage, connect this SF_VCC1 pin. details, refer Figure 3-1. VCC2 VCC3 CPU/RGB interface power supply Gate interface power supply Driver power supply 143, 155, SF_VCC1 Internal logic power supply generation amplifier output VSTBY Logic power supply generation control Input Output When VSTBY connect capacitor between this VSS. details, refer Figure 3-1. Select existence voltage supply power supply logic circuits. VSTBY With voltage supply necessity VCC1 VSTBY VCC1 needs voltage supplied DVSS Mode setting 136, DVCC2 Mode setting Pull-up power supply mode setting. Pull-down power supply mode setting. This power supply gate driver interface. This power supply driver circuit. This power supply circuit. This ground logic circuit, logic interface circuit, source driver circuit, gate control circuit, power supply control circuit. This power supply CPU/RGB interface.
power supply
Ground
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 3-1. Supplies Power Supply
[When using regulator logic circuit] Usage conditions: VCC2 VCC3
VCC3
VCC2
On-chip power supply gate interface circuit
CPU/RGB Interface circuit VCC1 SF_VCC1 VSTBY 2.35 internal logic circuit power supply
Regulator
[When using regulator logic circuit] Usage conditions: VCC1 VCC2 VCC3 VCC1VCC2
VCC3 On-chip power supply gate interface circuit VCC2 CPU/RGB Interface circuit Open VCC1 SF_VCC1 VSTBY internal logic circuit power supply
Regulator
Preliminary Product Information S16789EJ2V0PM
PD161606
Logic System Pins
Symbol BWS0, BWS1 Name interface width selection Input Function This selects width interface. BWS1 Input BWS0 interface width bits bits bits Setting prohibited
(1/2)
interface mode selection
This selects mode interface. Parallel interface Serial interface
Chip select
Input
This used chip select signals. When active level, chip active perform data operations including command data I/O.
CSEG
Chip select polarity selection
Input
This selects active level chip select (/CS). CSEG level CSEG High level
/RESET
Reset
Input
When /RESET internal reset performed. reset operation executed /RESET signal level. sure perform reset this power application.
RSEL
Reset switch
Input
Switches effective range hard reset registers. Hard reset Don't perform reset registers. Perform reset registers. Command reset Perform reset registers. Perform reset registers.
Read (Enable)
Input
When series parallel data transfer (/RD) been selected, signal this used enable read operations. Data output data only when this low. When series parallel data transfer been selected, signal this used enable read/write operations.
Write (Read/write)
Input
When series parallel data transfer (/WR) been selected, signal this used enable write operations. When series parallel data transfer (R,/W) been selected, this used determine direction data transfer. Write Read
Select interface
Input
This used switch between interface modes (i80 series series CPU). Selects series mode Selects series mode
Data Serial input Serial output Serial clock
Input Output Input
These pins comprise 8-bit bi-directional data. When chip selected, high impedance mode. This data input serial interface. This data output serial interface. This clock input serial interface.
Remark /xxx indicates active signal.
Preliminary Product Information S16789EJ2V0PM
PD161606
(2/2)
Symbol SCLEG0 SCLEG1 select polarity select Input Name data edge Input details, refer Table 5-5. Selects active level serial clock (SCL) serial interface. SCLEG1 level (high-level start) SCLEG1 High level (low-level start) SSEL Serial interface mode select Input Selects serial interface mode. SSEL Serial interface SSEL Serial interface Input This used serial interface When parallel data transfer been selected, this usually connected least significant standard address used distinguish between data from display data commands. Indicates that data from commands. Indicates that data from display data. HSYNC Horizontal sync signal Input This horizontal sync signal interface. Function Selects serial clock edge data serial interface.
Data/command select
VSYNC
Vertical sync signal
Input
This vertical sync signal interface.
DOTCLK
clock
Input
This clock signal interface.
RGB00 RGB05, Data RGB10 RGB15, RGB20 RGB25 OSC2SEL
102,
Input
These pins interface data signal.
Oscillation signal select
Input
This oscillation signal selection pin. Selects internal oscillator. Selects external resistor connected oscillator.
OSC2IN OSC2OUT
Oscillation signal
Input Output
These oscillation signal pins. OSCEL Connect resistor between OSCIN OSCOUT pin. resistance values used guide, refer electrical characteristics. OSCEL Leave OSCIN OSCOUT open.
Preliminary Product Information S16789EJ2V0PM
PD161606
Driver Pins
Symbol S720 Name Source output 204, 866,
CVPH1, CVPH2, CVPL1, CVPL2, CVNH1, CVNH2, CVNL1, CVNL2
Output
Function These pins source output pins.
Reference power supply correction power supply
Operational amplifier output pins -correction. Normally capacitor greater connected these pins. Leave these pins open when using amplifier correction.
Pins Gate Driver Control Internal Power Supply
Symbol GCLK GSTB GOE1 GOE2 VCOUT Name Gate driver output Gate driver output Gate driver output Gate driver output Square wave signal output Function
Output This output gate driver. Output Connect this STVR gate driver. Output This output gate driver. Output This output gate driver. Output Outputs square wave signal common modulation VP-P voltage VCC3.
Chip select gate driver interface
Output This chip select gate driver serial interface.
GSCLK
Serial clock gate driver interface
Output This serial clock gate driver serial interface.
Serial data output gate driver interface
Output This serial data output gate driver serial interface.
GRESET
Reset output gate driver interface
Output This reset output gate driver serial interface.
DCCLK
VCOM_EQ1 VCOM_EQ4
Boost clock output Equalize control VCOM equalize control
Output Outputs DC/DC converter boost clock. Output Equalize control pin. Input used equalize control.
Preliminary Product Information S16789EJ2V0PM
PD161606
E2PROM Control Pins
Symbol
Name Chip select PROM interface
Output
Function This chip select PROM interface. PROM made active outputting following which data transmission performed. Connect this (chip select pin) PROM.
Serial clock PROM interface
Output
This PROM interface. Data output from PROM rising edge ESK. Connect this (shift clock pin) PROM
Serial data input PROM interface
Input
This data input PROM interface. This used PROM data read. Connect this DOUT (data pin) PROM
Serial data output PROM interface
Output
This data output PROM. Data output PROM. Connect this (data pin) PROM.
Test Other Pins
Symbol TOUT0 TOUT17 TIN0 TIN2 TOSC1IN TOSC1SEL DUMMY Name Test output Test input Test input Test input Dummy 112, 174, 205, 206, 869, 900, Normally, leave open. Input Input Input This input when test mode. Normally, leave open connected VSS. This input when test mode. Normally, leave open connected VSS. This input when test mode. Normally, leave open connected VSS. Dummy Function Output This output when test mode.
Preliminary Product Information S16789EJ2V0PM
PD161606
CIRCUITS RECOMMENDED CONNECTION UNUSED PINS
circuit types each recommended connection unused pins described below. (1/2)
Name BWS0, BWS1 Input Type Schmitt trigger Schmitt trigger Schmitt trigger Input Input Input
Power Supply
Recommended Connection Unused Pins Parallel Interface Mode setting Mode setting Connect this VCC2 when CSEG CSEG respectively. Serial Interface
Note
VCC2 VCC2 VCC2
CSEG /RESET RSEL (R,/W) SCLEG0, SCLEG1 SSEL HSYNC VSYNC DOTCLK RGB00 RGB05, RGB10 RGB15, RGB20 RGB25
Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger
Input Input Input Input Input Input Input Output Input Input Input Input Input Input Input
VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2
Mode setting Always reset power application Mode setting Mode setting Connect VCC2 Leave open Connect VCC2 Connect VCC2 Register setting Connect VCC2 Connect VCC2 Connect VCC2 Leave this open. unused pins follows. pins case 6-bit interface: RGB10 RGB15, RGB20 RGB25 pins case 16-bit interface: RGB00, RGB20 Mode setting Mode setting Connect VCC2 Leave open Connect VCC2
OSC2IN OSC2OUT OSC2SEL
Schmitt trigger
Input Output Input
VCC2 VCC2 VCC2
Leave open Leave open Connect
Note Connect VCC2 VSS, depending mode selected.
Preliminary Product Information S16789EJ2V0PM
PD161606
(2/2)
Name GCLK GSTB GOE1 GOE2 VCOUT GSCLK GRESET DCCLK VCOM_EQ S720 VSTBY TOUT0 TOUT17 TIN0 TIN2 TOSC1IN TOSC1SEL Input Type Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Schmitt trigger Output Output Output Output Output Output Output Output Output Output Output Input Output Output Input Output Output Input Output Input Input Input Power Supply VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 Recommended Connection Unused Pins Parallel Interface Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Mode setting Leave open Leave open Connect Leave open Connect Leave open Connect Serial Interface Note
Note Connect VCC2 VSS, depending mode selected.
Preliminary Product Information S16789EJ2V0PM
PD161606
DESCRIPTION FUNCTIONS
Interface 5.1.1 Selection interface type µPD161606 transfer data using interface (18/16/6-bit), i80/M68 parallel interface (8-bit), serial interface (8-bit), serial interface (8-bit). modes listed following table selected setting PSX, BWS0, BWS1, SSEL pins. i80/M68 parallel interface allows writing reading to/from both data registers. serial interface allows writing both display data registers, reading registers. interface allows display data input. Table 5-1.
SSEL BWS0 BWS1 Mode 18-bit 8-bit parallel 6-bit 18-bit 8-bit Serial1 6-bit 18-bit 8-bit Serial2 6-bit Setting prohibited 16-bit
Note1 Note1 Note1 Note1
(R,/W)
SCLK
RGB00 RGB25 RGB00 RGB25 RGB00 RGB25
16-bit
(R,/W)
(RGB00, RGB20
Note1 Note1
open) RGB00 RGB05 (RGB10 RGB15, RGB20 RGB25 open)
RGB00 RGB25 RGB00 RGB25
Note1
16-bit
R,/W
Note1
Hi-Z
Note2
(RGB00, RGB20 open) RGB00 RGB05 (RGB10 RGB15, RGB20 RGB25 open) RGB00 RGB25 RGB00 RGB25
Hi-Z
Note2
(RGB00, RGB20 open) RGB00 RGB05 (RGB10 RGB15, RGB20 RGB25 open)
Other above
Notes1. Connect VCC2 VSS. Hi-Z: High impedance. Leave open.
Preliminary Product Information S16789EJ2V0PM
PD161606
5.1.2 interface PD161606 inputs display data from DOTCLK, HSYNC, VSYNC, RGB00 RGB05, RGB10 RGB15, RGB20 RGB25 pins. horizontal interval back porch with R75, vertical interval back porch with R76. 6-bit, 16-bit, 18-bit data width interface. Selection performed with BWS0 BWS1 pins. When 6-bit width selected, back porch, HSYNC width, etc., must controlled units DOTCLK. Table 5-2. Data Width Selection
BWS1 BWS0 Data Width 18-bit 16-bit 6-bit
operation sequence follows (when DCKEG HSEG VSEG Figure shows timing chart when 16-bit 18-bit width selected. Start VSYNC HSYNC Vertical back porch count reset, line count reset VSYNC HSYNC Vertical back porch count value Vertical back porch counter subtracted from value (tVBP) back porch Vertical period. tVBP Vertical back porch count number HSYNC DOTCLK Horizontal back porch count reset HSYNC DOTCLK Horizontal back porch count+1 value horizontal back porch counter subtracted from value (tHBP) back porch horizontal period. tHBP horizontal back porch count number taking about first data rising edge next DOTCLK. Data taken clocks (data disregarded after clocks). data taken HSYNC latched output stage. VSYNC
Remark active DOTCLK, VSYNC HSYNC latch data rising edge.
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-1. Interface Timing Chart (DCKEG HSEG VSEG
VSYNC tVSS tVSH
line period
HSYNC
Invalid
line Last line
Invalid
Invalid
pixel pixel Last pixel
Invalid
HSYNC
tHSS
tHSH
pixel period
Invalid
pixel Last pixel
Invalid
vertical back porch period horizontal back porch period
Preliminary Product Information S16789EJ2V0PM
PD161606
relationships between input data various source output pins each width follows. Figure 5-2. Relationship between Input Data Source Output (16-/18-bit Width) [16-/18-bit width] <ADC
Source output Data Receiving order S715 RGB20 RGB25
Note2
RGB20 RGB25
Note2
RGB10 RGB15 pixel
RGB00 RGB05
Note1
RGB20 RGB25
Note2
RGB10 RGB15 pixel
RGB00 RGB05
Note1
RGB20 RGB25
Note2
RGB10 RGB15
pixel
S716 RGB10 RGB15 239th pixel
S717 RGB00 RGB05
Note1
S718 RGB20 RGB25
Note2
S718 RGB10 RGB15 240th pixel
S720 RGB00 RGB05
Note1
<ADC
Source output Data Receiving order S715 RGB00 RGB05
Note1
RGB00 RGB05
Note1
RGB10 RGB15 240th pixel
RGB20 RGB25
Note2
RGB00 RGB05
Note1
RGB10 RGB15 239th pixel
RGB20 RGB25
Note2
RGB00 RGB05
Note1
RGB10 RGB15
238th pixel
S716 RGB10 RGB15 pixel
S717 RGB20 RGB25
Note2
S718 RGB00 RGB05
Note1
S718 RGB10 RGB15 pixel
S720 RGB20 RGB25
Note2
Notes When 16-bit width selected, RGB01 RGB05 used. When 16-bit width selected, data input RGB00 need performed, output performed data input RGB05, because this regarded data input. When 16-bit width selected, RGB21 RGB25 used. When 16-bit width selected, data input RGB20 need performed, output performed data input RGB25, because this regarded data input.
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-3. Relationship between Input Data Source Output (6-bit width) [6-bit width] <ADC
Source output Data Receiving order RGB00 RGB05 RGB00 RGB05 pixel RGB00 RGB05 RGB00 RGB05 RGB00 RGB05 pixel RGB00 RGB05 RGB00 RGB05 RGB00 RGB05
pixel
S715 RGB00 RGB05
S716 RGB00 RGB05 239th pixel
S717 RGB00 RGB05
S718 RGB00 RGB05
S718 RGB00 RGB05 240th pixel
S720 RGB00 RGB05
<ADC
Source output Data Receiving order RGB00 RGB05 RGB00 RGB05 240th pixel RGB00 RGB05 RGB00 RGB05 RGB00 RGB05 239th pixel RGB00 RGB05 RGB00 RGB05 RGB00 RGB05
238th pixel
S715 RGB00 RGB05
S716 RGB00 RGB05 pixel
S717 RGB00 RGB05
S718 RGB00 RGB05
S718 RGB00 RGB05 pixel
S720 RGB00 RGB05
PD161606 contains on-chip partial (3-bit/1-pixel). addition data input form interface, partial area specified registers also displayed, setting register,
Preliminary Product Information S16789EJ2V0PM
PD161606
[Example when using Interface]
interface input data
Partial display data
[TUE] 10:35
R15: Partial display area start address R16: Partial display area line count R19: Partial display area start address R20: Partial display area line count
Actually display screen
[TUE] 10:35
Display data area
i80/M68 interface rewrites serial interface
interface start line (Setting register)
interface through display mode access area
interface line (Setting register)
<Cautions regarding interface> sure input data each frame data input from interface. When switching partial mode, input least frame's worth data after issuing mode switching command. When switching stand-by mode, input frame's worth data case stand-by mode1, input frame's worth data case stand-by mode Mode transition flows
Normal display mode partial display mode (display clock: internal oscillation) Wait time Partial display mode Normal display mode (display clock: DOTCLK) Data input start Normal display mode stand-by mode Stand-by mode normal display mode (stand-by release) Data input start STBY
STBY Wait time (STBSEL Wait time (STBSEL (stand-by mode transition) Data input stop "Stand-by mode"
(partial display mode transition) Data input stop "Normal display mode"
"Normal display mode"
"Normal display mode"
Wait time Please secure sufficient time equal frame more. Wait time Please secure sufficient time equal frames more.
Preliminary Product Information S16789EJ2V0PM
PD161606
5.1.3 i80/M68 parallel interface When parallel interface been selected, setting either enables direct connection series series (Refer following table). Table 5-3.
Mode series series
data signal identified according combination (E), signals. Table 5-4.
Common series series Function Read display data Write display data Read command Write command
Preliminary Product Information S16789EJ2V0PM
PD161606
series parallel interface When series parallel data transfer been selected, data written PD161606 period signal. data output data when signal Figure 5-4. Series Interface Data Status
(CSEG
Valid data
Data write
Data read
series parallel interface When series parallel data transfer been selected, data written period signal when R,/W signal data read operation, data output rising edge signal period when R,/W signal data released (Hi-Z) falling edge signal. Figure 5-5. Series Interface Data Status
(CSEG
R,/W
Valid data
Data write
Data read
Preliminary Product Information S16789EJ2V0PM
PD161606
5.1.4 Serial interface serial interface selected from serial interface mode serial interface mode through serial mode selection (SSEL). These mode described sections 5.1.4 5.1.4 (2). This serial interface supports SPI. settings described section 5.1.4 (3). Serial interface mode serial interface mode data input specified either "register number/register data" "display data (RAM data)" through input pin. concrete details follows. register number register data input sequences, refer Figure 5-9.
Input Level Low-level High-level
Data Input from Serial Interface Register number/register data Display data
Serial interface mode serial interface mode byte transfer sets serial interface operation specification registers byte transfer, specifies whether transfer data byte "register number", "register data", "display data (RAM data)". During byte transfer, data specified with byte transferred. serial interface operation specification registers follows. Table5-5. Serial Interface Operation Specification Registers
Number Register/RAM data select name This sets whether data data PD161606's registers RAM. data PD161606's registers. data PD161606's RAM. Read/write select This selects whether data transfer read operation write operation. However, read operation possible only µPD161606's registers. read operation timing chart, refer Write operation Read operation Command/data select This selects whether data data specifying register number command register, setting data command register. register number register setting value Function
Preliminary Product Information S16789EJ2V0PM
PD161606
Therefore, shown following timing chart, serial interface mode after chip select signal becomes active, access serial interface operation specification register always performed. Figure 5-6. Serial Interface Mode Timing Chart
Serial interface operation specification transfer Register setting setting selection Read write selection Register number value register data value
Command data transfer Register numbaer value transfer Register data value transfer Display data (RAM data) transfer
Therefore, perform write register, example, 2-byte transfer performed until series settings have been completed. Also note that during 4-byte transfer performing access register, during 2-byte transfer performing display data (RAM) write, chip select must kept active. Figure 5-7. When Performing Register Setting Serial Interface Mode
byte
byte
Serial interface operation specification transfer Specification transfer register number value next transfer
Command data transfer Register number value transger
byte
byte
Serial interface operation specification transfer Specification transfer register data value next transfer
Command data transfer Register data value transger
Preliminary Product Information S16789EJ2V0PM
PD161606
When serial interface selected, serial data input (SI) serial clock input (SCL) accepted chip active status, relationship between data valid edges serial clock this time, active level serial clock with SCLEG0 SCLEG1 pins. Table 5-6. Relationship between Serial Clock Data
name SCLEG1 SCLEG0 Low-level Low-level High-level High-level Rising edge serial clock Falling edge serial clock Falling edge serial clock Rising edge serial clock Falling edge serial clock Rising edge serial clock Rising edge serial clock Falling edge serial clock Active level serial clock Serial data load timing Serial data output timing
operation example when active level serial clock level, data output falling edge serial clock, data input rising edge serial clock, described below. Serial data read sequence first, then synchronization with rising edge serial clock from serial input pin. This data converted into parallel data processed synchronization with rising edge serial clock. Whether serial input data display data register setting judged from input case serial interface mode data display data, register number/register data. case serial interface mode this judged from data operation specification bit. data display data, register number/register data. Next, serial interface signal chart shown. Figure 5-8. Serial Interface Signal Chart
(SCLEG1 (SCLEG1 (SCLEG0 (SCLEG0
above figure indications data read timing.
Remarks chip active, shift register counter reset their initial settings. Display data read possible. When using wiring, take care concerning possible effects terminating reflection noise from external sources. recommends checking operation with actual device.
Preliminary Product Information S16789EJ2V0PM
PD161606
5.1.5 Chip select PD161606 chip select (/CS). parallel interface serial interface used only when When chip select inactive, high impedance (invalid) input /RD, active. Therefore, keep chip select active cycle period data transfer (until read/write operation been completed once parallel interface mode). necessary keep chip select signal active when successively transferring data. non-active between data transfer operations. However, note that necessary continue making chip selection active during register specification register value setup" transmission "higher rank 8-bit+ rank 8-bit RAM" 16-bit case serial interface. 5.1.6 Access display data internal registers Figures 5-13 show write accesses display data read/write accesses internal registers 8-bit parallel interface modes serial interface mode. When accessed PD161606, only satisfy standard requirement cycle time (tCYC) transfer data high speeds. Usually, necessary take WAIT time into consideration.
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-9. Read/Write 8-Bit Parallel Interface Mode
<8-bit Parallel Interface> Write Display data
D7-D0
Display data Display data Display data
Invalid data, D4-bit RAM, D3-bit RAM, D2-bit RAM, D1-bit RAM, D0-bit
Read Display data
D7-D0
Display data Display data Display data
Invalid data, D4-bit RAM, D3-bit RAM, D2-bit RAM, D1-bit RAM, D0-bit
Write Register
D7-D0
Command
Data
Register Register
Read Register
D7-D0
Command
Data
Register Register
Cautions While setting writing register, fixed input level pin. register write interval "register number specification" "register value setting" interval. While setting writing display data RAM, fixed input high level pin. display data write interval "1-pixel data transfer interval"
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-10. Read/Write 8-bit Serial Interface (Serial Interface Mode1)
<8-bit Serial interface mode1> Write display data (SCLEG0 SCLEG1
R,/W
Display data
Display data
(SCLEG0 SCLEG1
R,/W
Display data
Display data
(SCLEG0 SCLEG1
R,/W
Display data
Display data
(SCLEG0 SCLEG1
R,/W
Display data
Display data
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-11. Read/Write 8-bit Serial Interface (Serial Interface Mode1)
Write Register (SCLEG0 SCLEG1
R,/W
Command (SCLEG0 SCLEG1
R,/W
Data
Command (SCLEG0 SCLEG1
R,/W
Data
Command (SCLEG0 SCLEG1
R,/W
Data
Command
Data
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-12. Read/Write 8-bit Serial Interface (Serial Interface Mode1)
Read Register (SCLEG0 SCLEG1
R,/W
Command
(SCLEG0 SCLEG1
R,/W
Data
Command
(SCLEG0 SCLEG1
R,/W
Data
Command
(SCLEG0 SCLEG1
R,/W
Data
Command
Data
Cautions During 16-bit transfer "register number specification register value setting", chip select must maintained active. When performing register write, keep output level during "register number specification register value setting" interval. When performing display data write, keep output high level during 1-pixel data transfer interval.
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-13. Read/Write 8-bit Serial Interface (Serial Interface Mode2)
<8-bit Serial interface mode2> Write Register (SCLEG0 SCLEG1
Serial interface operatoin specification transfer Command data transfer
(SCLEG0 SCLEG1
Serial interface operatoin specification transfer Command data transfer
(SCLEG0 SCLEG1
Serial interface operatoin specification transfer Command data transfer
(SCLEG0 SCLEG1
Serial interface operatoin specification transfer Command data transfer
Read Register (SCLEG0 SCLEG1
Serial interface operatoin specification transfer
Data
(SCLEG0 SCLEG1
Serial interface operatoin specification transfer
Data
(SCLEG0 SCLEG1
Serial interface operatoin specification transfer
Data
(SCLEG0 SCLEG1
Serial interface operatoin specification transfer
Data
Caution During 16-bit transfer "serial interface operation specification transfer command data transfer", chip select must maintained active.
Preliminary Product Information S16789EJ2V0PM
PD161606
5.1.7 PD161645 control serial interface This 16-bit serial interface performing control PD161645. transfer operation follows. <Transfer operation> This interface performs batch transfer 16-bit data. data format PD161645 consists command first byte transfer data, data second byte. Transfer performed first. transfer start trigger data write control registers PD161645. When data written control registers, GCS, GS0, GSCLK output automatically starts. Following input reset command, PD161645 checks data bytes transferred against command, checks data even bytes against data command. Perform write shift register following completion transfer. Thus secure interval least between write operations registers PD161645. Transfer data when performing data write during transfer cannot guranteed. Figure 5-14. µPD161645 Control Serial Interface Timing Chart
GSCLK
Command (first 8-bit data)
Data command (2nd byte data)
Preliminary Product Information S16789EJ2V0PM
PD161606
Partial Display holding dots display configuration 115,200bits (240 bits) bits. pixel accessed specifying address address. Figure 5-15 shows configuration display data RAM. partial display 5-bit configuration, bits display data bits. Bits used function, enabled when this function selected. Figure 5-16 shows operation when function enabled. Figure 5-15. Display RAM/Bit Configuration
Function
Display data
data Pixel pixel
data
data
panel
Pixel Pixel
Pixel Pixel
Pixel Pixel
Pixel Pixel
Pixel Pixel
Pixel Pixel
Pixel Pixel
Pixel Pixel
Figure 5-16. Transmittance when Blending Function Selected
function Invalid Valid Valid Valid Valid Display data transmittance Transmittance (base image 100%) Transmittance (base image 100%) Transmittance (base image 50%) Transmittance (base image 25%) Transmittance 100% (base image
Remark Don't care 5.2.1 address circuit address display data specified using address register (R6) shown Figure 5-18. specified address incremented each time display data written read. address increment mode, address incremented EFH. more display data written read, address incremented, address returns 00H. relationship between address source output inverted flag control register shown Figure 5-18. After switched ADX, input data rotated degrees displayed changing function address increment direction between
Preliminary Product Information S16789EJ2V0PM
PD161606
5.2.2 address circuit address display data specified using address register (R7) shown Figure 5-18. address incremented each when each time display written read address incremented last address. When address been incremented address final address, further display data read written, addresses return 00H. shown Figure 5-18, relationship between address gate output inverted flag control register. data written display rotated degrees output changing function address increment direction between Table 5-7. Data Access Control (R5) Settings
Setting During data access, addresses continuously incremented direction. During data access, addresses continuously incremented direction.
Figure 5-17. Example 90-degree Rotation
address increment (INC address increment (INC
Display image
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-18. µPD161606 Addressing
ADX=0 ADC=0 Source output ADC=1 X-address Column address S720 000H Y-address ADY=0 ADY=1 Display area S719 000H 001H Pixel 002H 003H S718 S717 S716 001H 004H Pixel 005H S715 -2CAH S715 S716 2CBH 239th Pixel 2CCH 2CDH S717 S718 S719 2CEH 240th Pixel 2CFH S720
ADX=1 ADC=0 Source output ADC=1 X-address Column address S720 2CFH Y-address ADY=0 ADY=1 Display area S719 2CEH 240th Pixel 2CDH 2CCH S718 S717 S716 2CBH 239th Pixel 2CAH S715 -005H S715 S716 001H 004H Pixel 003H 002H S717 S718 S719 000H 001H Pixel 000H S720
Preliminary Product Information S16789EJ2V0PM
PD161606
5.2.3 Arbitrary address area access (window access mode (WAS)) With PD161606, area display selected MIN., address registers R10) MAX., address registers R11) accessed. First, select area accessed using address registers address registers. When data access control register (R5) window access mode then selected. address scanning setting also valid this mode, same manner when data normally written display RAM. addition, data written from address specifying address register (R6) address register (R7). Figure 5-19. Example Incrementing Address when Window Access Mode
MIN. address Start point MAX. address
MIN. address
MAX. address point
Cautions When using window access mode, relationship between start point point shown table below must established.
Item address address Address Relationship address address (R6) address address address (R7) address
invalid address data MIN./MAX. address, operation guarateed.
Preliminary Product Information S16789EJ2V0PM
PD161606
Example Sequence Window Access Mode settings MIN. address register (R8), MIN. address register (R10), MAX. address register (R9), MAX. address register (R11) performed order.
Start
MIN. address register (R8) Sets start point. MIN. address register (R10)
MAX. address register (R9) Sets point. MAX. address register (R11)
Data access control register (R5) (WAS
Sets window access mode.
address register (R6) address register (R7) Write display data
Data
Writing complete?
Preliminary Product Information S16789EJ2V0PM
PD161606
Oscillator PD161606 allows selection on-chip oscillator (OSC2SEL on-chip type) external oscillator (OSC2SEL external) oscillator generating display clock setting OSC2SEL pin. Moreover, on-chip oscillator contains oscillation circuits. these oscillation circuits (OSC2) used generate liquid crystal display output timing, while other oscillation circuit (OSC1) used when executing frame frequency calibration. (OSC1OFF) (OSC2OFF) WAIT time: T.B.D. (Oscillation stabilization time wait) (OC) (OC) (OSC1OFF) Calibration start WAIT about time line frame frequency Calibration stop WAIT time: T.B.D. µs(Calibration processing time) Oscillation circuit stop calibrations Internal oscillation start
Since oscillation circuit calibrations comes unnecessary after calibration execution, order lower power consumption, suspend oscillation ("1" OSC1OFF R1). addition, when calibration again once performing calibration, start oscillation operation again. Moreover, frame frequency which calibration carried eliminated command reset. Therefore, when command reset input, calibration again. When selecting external oscillator (OSCSEL connect T.B.D. resistor OSCIN OSCOUT pin. When internal oscillator selected, leave both pins unconnected. Cautions DIVSL (R46), HCKSL (R46), LNSEL (R50) changed from their initial values, calibration prohibited. When external oscillator selected, calibration prohibited.
Preliminary Product Information S16789EJ2V0PM
PD161606
Display Timing Generator display timing generator generates timing signals internal timing source driver gate driver. Horizontal interval timing following signals controlled register setting. drive period addition, timing chart shown next page.
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-20. Display Driving Signal Timing Chart (RGB interface: 16/18-bit batch transfer, line inversion)
18-bit Mode display timing chart <line inversion, output, VSYNC width non-dummy line>
HSYNC unit (Horizon period back porch (R75)
*VSEG HSEG DCKEG *Display address value turns into value which counted DOTCLK. *When puts more period, added after display address(Hcnt) value address. tHSW (MIN. DOTCLK) (MIN. DOTCLK)
HSYNC
DOTCLK
tHBP (MIN. DOTCLK)
Data
Invalid
12345 6789
Invalid
Hcnt
1234567
GCED[7:0]
GCLK
Polarity reversal possible GSTB-GCLK (MIN. DOTCLK)
GSTB
GOST[7:0] GOED[7:0]
GOE1
time display changes with time standby, 59DR1 (GOE2ON) commands.
GOE2
EQST[7:0] EQED[7:0]
APST[7:0] APED[7:0]
Equalize drive period
Amplifier drive period r-resistance direct drive period
S720
Hi-Z
Hi-Z
VCOUT
Gn+1
MIN. value EQST, APST, GOST MIN. value GCED When position standup falling same, output serves fixation.
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-21. Display Driving Signal Timing Chart (RGB interface: 6-bit batch transfer, line inversion)
Mode display timing chart <line inversion, output, VSYNC width non-dummy line>
VSYNC HSYNC operate every DOTCLK time 6bit Mode.
HSYNC unit (Horizon period back porch (R75)
VSEG HSEG DCKEG *Display address value (Hcnt) turns into value which counted DOTCLK. tHSW (MIN. DOTCLK) (MIN. DOTCLK)
HSYNC
DOTCLK
tHBP (MIN. Dotclk)
(Internal CLK)
Invalid
Data
Invalid
Hcnt
GCED[5:0]
GCLK
Polarity reversal possible
GSTB
GOST[5:0] GOED[5:0]
GOE1
time display changes with time standby, 59DR1 (GOE2ON) commands.
GOE2
EQST[5:0] EQED[5:0]
APST[5:0] APED[5:0]
Equalize drive period
Amplifier drive period
r-resistance direct drive period
S720
Hi-Z
Hi-Z
VCOUT
Gn+1
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-22. Display Driving Signal Timing Chart (partial display, line inversion)
Display timing chart (Partial display)
HCNT unit *Display address value (Hcnt) turns into value which counted DOTCLK. Horizontal, perpendicular address: MIN. setup
Hcnt
PGCED[7:0]
GCLK
Polarity reversal possible
GSTB
PGOST[7:0] PGOED[7:0]
GOE1
time display changes with time stand-by, 59DR1 (GOE2ON) commands.
GOE2
PEQST[7:0] PEQED[7:0]
PAPST[7:0] PAPED[7:0]
Equalize drive period
Amplifier drive period
r-resistance direct drive period
S720
Hi-Z
Hi-Z
VCOUT
Gn+1
MIN. value EQST, APST, GOST MIN. value GCED When position standup falling same, output serves fixation.
Preliminary Product Information S16789EJ2V0PM
PD161606
Curve Correction Circuit PD161606 on-chip curve correction power supply circuit. internal curve correction matches characteristics, external parts required. This circuit incorporates curve correction resistor adjusts Inclination amplitude switching between positive negative polarity according register settings. Figure 5-23. Curve Correction Circuit
Amplitude adjustment (fixed) Amplitude adjustment (fixed)
Amplitude adjustment
-register switch
Inclination adjustment
Fine tunig adjustment
gray-scale
Inclination adjustment
Amplitude adjustment (fixed) Amplitude adjustment (fixed)
-register switch
Amplitude adjustment
Preliminary Product Information S16789EJ2V0PM
PD161606
5.5.1 Amplitude adjustment with internal amplifier Amplitude adjustment select ways, method adjusting with internal amplifier, method adjusting internal resistance. Each register R101 (GPH [5:0]), R102 (GNH [5:0]), R103 (GPL [5:0]), R104 (GNL [5:0]) performs adjustment with amplifier. Refer Figure 5-24. Figure 5-24. Amplitude Adjustment (This figure circuit side positive-polarity. reading GNH, GNL, VNH, negative-polarity side's reading)
[5:0]
VD127 VD64
VD63
[5:0]
VSS1 VSS1
Figure 5-25. Relationship Drive Voltage (Normally White)
Black
VSS1 Positive polarity Negative polarity
White
Drive Level Positive polarity, black Negative polarity, white Negative polarity, white Positive polarity, black
Setting Register Contrast value setting register Contrast value setting register Contrast value setting register Contrast value setting register R101 R102 R103 R104
Preliminary Product Information S16789EJ2V0PM
PD161606
value each amplifier output expressed follows value shown Table using contrast value registers (R101, R102, R103, R104) VNL, VPL, VNH, 129) Caution usable range which each output level VPH, VNH, VPL, depends curve. Table 5-8. Contrast Value Setting Electronic Volume Register Setting (VPH, VNL)
R101 R102 VPH5 VNH5 VPH4 VNH4 VPH3 VNH3 VPH2 VNH2 VPH1 VNH1 VPH0 VNH0 value Setting Status Setting
Table 5-9. Contrast Value Setting Electronic Volume Register Setting (VPL, VNL)
R103 R104 VPL5 VNL5 VPL4 VNL4 VPL3 VNL3 VPL2 VNL2 VPL1 VNL1 VPL0 VNL0 value Setting Statement Setting
Preliminary Product Information S16789EJ2V0PM
PD161606
5.5.2 Amplitude adjustment built-in resistance 4-bit data registers R105 R109 sets amplitude adjustment built-in resistance. Refer Figure 5-26. Figure 5-26. Amplitude Adjustment
V0RP[3:0] (V0RP[3:0])
VDRP
V0RN[3:0] (V0RN[3:0])
VDNP
VSS1 Scale Data
Preliminary Product Information S16789EJ2V0PM
Voltage
PD161606
5.5.3 Inclination adjustment Internal resistance also adjusts inclination adjustment. R106 R110 register adjustment. Refer Figure 5-27. Figure 5-27. Inclination Adjustment
VGR4
VGR5
VHRP[3:0] (VLRP[3:0])
VHRP
VHRN[3:0] (VLRN[3:0])
VHRN
V0R4P[2:0] (V0R7P[2:0])
VDR4(7)P
V0R4N[2:0] (V0R7N[2:0])
VDR4(7)N
VGR6
V0R5P[2:0] (V0R6P[2:0])
VDR5(6)P
V0R5N[2:0] (V0R6N[2:0])
VDR5(6)N
VGR7
Voltage
Scale Data
Preliminary Product Information S16789EJ2V0PM
PD161606
5.5.4 Fine tuning adjustment Internal resistance also sets fine tuning. Please adjust R107, R108, R111, R112 register. Refer Figure 5-28. Figure 5-28. Fine Tuning
Default VGR0 VGR1 R2:VGR2 VGR3 R:R' VGR0 VGR1 VGR2 VGR3
VGRnP[2:0] VGR0P VGR1P VGR2P VGR3P VGRnN[2:0] VGR0N VGR1N VGR2N VGR3N
Default:
Preliminary Product Information S16789EJ2V0PM
PD161606
Partial Display Function PD161606 contains partial display function. When this function used, display control clock becomes internal oscillation clock, display image shows only data written partial display RAM. Moreover, partial non-display area displays partial non-display area color with register. Refer Figure 5-29. Table5-10 shows comparison regular operation partial display operation. Table 5-10. Comparison Regular Operation Partial Display Operation
Regular Operation Display control clock Partial display function DOTCLK, HDYNC, VSYNC Displayed only when function enabled Enabled. settings enabled. Partial Display Operation Internal oscillation clock Always displayed. Disabled. Regardless settings, data written partial always enabled. Display outside partial Input data displayed interface Partial non-display area color with displayed.
display
Figure 5-29. Partial Display
interface input data
Partial display data [TUE] R15: Partial display area start address R16: Partial display area line count R19: Partial display area start address R20: Partial display area line count
"Invalid"
Actually display screen Partial non-display area Color
Data display area i80/M68 interface rewtite serial interface
[TUE]
R17, R18: Partial display area display start line
R21, R22: Partial display area display start line
Preliminary Product Information S16789EJ2V0PM
PD161606
Stand-by PD161606 stand-by function that allows types operation stand-by operation, either which selected. 5.7.1 Stand-by mode Stand-by mode selected setting STBSEL (R0, setting control register (R0): STBY white display performed, during frame dummy line interval, gate outputs panel charge discharged. setting control register (R24): DCON after gate outputs have become regulator DC/DC converter executed, setting OSC2OFF full stand-by mode entered after internal oscillator stops. <Stand-by sequence> STBY (WAIT frame period) DCON R24= OSC2OFF transition from stand-by mode regular mode opposite sequence from stand-by sequence, executed order OSC2OFF DCON STBY Figure 5-30. Outline Operation during Stand-by Mode Execution
Operation stand-by command execution
Stand-by command exectuion (STBY Sourse output level output start (white level when VCOUT VCOUTn level output
After one-frame
GOE2 output level output Source output level output
Remark stand-by mode (STBY display data access, display data hold, register access possible even during DC/DC converter internal oscillation stop, long power supplied VCC1, VCC2, VCC3 (including when power supplied VCC1 from SF_VCC1).
Preliminary Product Information S16789EJ2V0PM
PD161606
5.7.2 Stand-by mode Stand-by mode selected setting STVSEL (R0, setting control register (R0): STBY white display starts. After white output been performed until next frame after STBY been set, GO21 executed frames. Then source output becomes level. After source output becomes level, setting control register (R24): DCON regulator DC/DC converter executed, setting OSC2OFF, full stand-by mode entered after internal oscillator stops. <Stand-by sequence> STBY (WAIT four frame period) DCON R24= OSC2OFF transition from stand-by mode regular mode opposite sequence from stand-by sequence, executed order OSC2OFF DCON STBY outline operation during stand-by mode execution shown next page.
Preliminary Product Information S16789EJ2V0PM
PD161606
Figure 5-31. Outline Operation during Stand-by Mode Execution
frame
Stand-by command execution (STBY Source output level output start (White display) VCOUTn Inverted operation
frame
White output
frame
GOE1 output
frame Source output level VCOUT level
Remark stand-by mode (STBY display data access, display data hold, register access possible even during DC/DC converter internal oscillation stop, long power supplied VCC1, VCC2, VCC3 (including when power supplied VCC1 from SF_VCC1).
Preliminary Product Information S16789EJ2V0PM
PD161606
Stand-by sequence power supply control, example sequence time performing internal sequence shown.
µPD161606 stand-by
electric charge panel discharge. will become white display normally white panel. frame time wait case stand-by mode stand-by mode frames time wait)
µPD161606 stand-by mode
Register)
accordance with usage conditions.
µPD161645 power supply setting
(R24 Register)
accordance with usage conditions. Power completed T.B.D. MIN. wait
µPD161606 internal oscillation setting
Register)
accordance with usage conditions. Oscillation stop (Stand-by status)
Preliminary Product Information S16789EJ2V0PM
PD161606
Stand-by release sequence power supply control, example sequence time performing internal sequence shown.
PD161606 stand-by mode release
Oscillation start
PD161606 internal oscillation setting
Register)
accordance with usage conditions.
PD161645 power supply setting
(R24 Register)
accordance with usage conditions. Power after time PUPT0/PUPT1 register lapsed! T.B.D. MIN. wait
PD161606 stand-by mode release
Register)
accordance with usage conditions. Complete return regular mode!
Preliminary Product Information S16789EJ2V0PM
PD161606
POWER SUPPLY INJECTION/INTERCEPTION
example powering injection/interception chip TFT-LCD panel driving using PD161606 shown below. PD161606 Power Supply Injection Setting Sequence Example
Hard reset PD161606 register. Reset PD161606 register
PD161606 command reset
register)
Start PD161606 internal oscillation
PD161606 internal oscillation setting
register)
accordance with usage conditions.
Oscillation start Reset PD161645 register
PD161645 command reset
(R34 register)
accordance with usage conditions.
PD161606
T.B.D. MIN. wait setting order order
(Perform this setting required.)
PD161606 setting
accordance with usage conditions.
PD161606 horizontal interval timing
setting order order
PD161606 horizontal interval timing setting
accordance with usage conditions.
Preliminary Product Information S16789EJ2V0PM
PD161606
Calibration
PD161606 power supply setting
(R45 register)
accordance with usage conditions.
PD161606 calibration internal oscillation
setting register)
accordance with usage conditions.
Power supply setting
PD161645 power supply setting
(R25 register)
accordance with usage conditions. T.B.D. MIN. wait
PD161645 power supply setting
(R26 register)
accordance with usage conditions. T.B.D. MIN. wait
PD161645 power supply setting
(R27 register)
accordance with usage conditions. T.B.D. MIN. wait
PD161645 power supply setting
(R28 register)
accordance with usage conditions. T.B.D. MIN. wait
Preliminary Product Information S16789EJ2V0PM
PD161606
Power after time PUPT0/PUPT1 register lapsed!
µPD161645 power supply setting
(R29 register)
accordance with usage conditions. T.B.D. MIN. wait
PD161645 power supply setting
(R30 register)
accordance with usage conditions. T.B.D. MIN. wait
PD161645 power supply setting
(R31 register)
accordance with usage conditions. T.B.D. MIN. wait
PD161645 power supply setting
(R32 register)
accordance with usage conditions. T.B.D. MIN. wait
PD161645 power supply setting
(R33 register)
accordance with usage conditions. T.B.D. MIN. wait
PD161645 power supply setting
(R24 register)
accordance with usage conditions. T.B.D. MIN. wait
Preliminary Product Information S16789EJ2V0PM
PD161606
Display data input start
Data input start interface
Display start setting
PD161606 GOE1, GOE2 signal setting
(R59 register)
After 1-frame time, whites blacks displayed.
PD161606 display setting
register)
accordance with usage conditions. data display start Regular data display through DISP1, DISP0 cancellation
Preliminary Product Information S16789EJ2V0PM
PD161606
µPD161606 Power Supply Interception Setting Sequence Example
µPD161606 stand-by mode
µPD161606 stand-by mode setting
register)
accordance with usage conditions. Discharge electric charge panel carried out. will become white display normally white panel. frame time wait stand-by mode frames times wait)
µPD161645 power supply setting
(R24 register)
accordance with usage conditions. T.B.D. MIN. wait
µPD161606 power supply setting
register)
accordance with usage conditions. Oscillation stop (Stand-by status)
Preliminary Product Information S16789EJ2V0PM
PD161606
E2PROM INTERFACE
PD161606 builds interface function PROM corresponding micro-wire interface. However, capacity PROM corresponds 4k-bit article.
PD161606 E2PROM Connection Connection with E2PROM made shown following figure.
Controller/ Driver
DOUT Microwire E2PROM
controller side signal
Chip select signal over PROM. With outputting PROM made into active state data transmitted after that. connects with (chip select pin) PROM. Clock signal over PROM. falling ESK, data outputted from PROM. connects with (shift clock pin) PROM. Data output pin. Data outputted PROM. connects with (data pin) PROM Data input pin. used reading data PROM. connects with DOUT (data pin) PROM.
Function
Preliminary Product Information S16789EJ2V0PM
PD161606
Each Operation PD161606 perform writing register data, reading register date elimination E2PROM data
PROM. Selection each operation performed using R118 register.
R118 Register E2OPC2 E2OPC1 E2OPC0 Setting prohibited
PROM Command
EPSAVE: Writing PROM MASKON: Permission writing elimination PROM MASKOF: Prohibition writing elimination PROM EPCLR: area elimination PROM EPWALL: written area PROM EPREAD: Reading from PROM Setting prohibited
addition, explain each operation below.
PROM read command: Reading from PROM]
From "E2PROM address" "the E2PROM reading start address register (R124)", reads order "index"
register value" total bits) register data stored PROM saved applicable index
PD161606. addition, reading operation continuously performed until reads reading (FFFFH 7FFFH).
When FFFFH 7FFFH read, reading operation stopped reading exceeds times.
R124: Setting reading start address R118: PROM read execution (06H)
Command input PROM read Writing register Register data reading repeated until reads FFFF Completion Completion processing
Preliminary Product Information S16789EJ2V0PM
PD161606
[EPSAVE command: Writing data E2PROM] register data PD161606, data written E2PROM address based R119 (E2PROM address) R120 data).
Elimination/writing permission command input EWEN issue PROM writing address specification Writing index specification PROM data transmission command input PROM Wait Completion Elimination/writing protected command input EWDS Completion processing passes elimination/writing protected. About data PROM, they elimination disposal making rewrite carelessly.
R118: Elimination/writing permission carry (MASKON command 02H)
elimination/writing permission state
writes R119 specification address. Remark Since increment carried out, required. index which wants write R120 data index, register value PD161606 written in.) R118: Data transmission execution PROM (EPSAVE command 01H)
wait time order write ROM. needed. Insert wait time after confirming specification PROM used.
R118: Elimination/writing protected execution (03H)
Preliminary Product Information S16789EJ2V0PM
PD161606
[MASKON command: Writing/elimination permission E2PROM] Elimination/writing E2PROM permitted.
Command input EWEN <Erase write enable> Completion processing elimination/writing permission state R118
[MASKOF: Writing protected E2PROM] Elimination/writing E2PROM protected (Reading data possible).
Command input EWDS <Erase write disable> Completion processing passes elimination/writing protected. R118
Preliminary Product Information S16789EJ2V0PM
PD161606
[EPCLR command: E2PROM elimination] data E2PROM initialized.
Elimination/writing permission command input EWEN ERAL <Erase All> PROM elimination command input Wait Completion processing Elimination/write-protected command input EWDS Completion processing passes elimination/write-protected. R118 After command input order access ROM, ERAL needed wait time like data write. Insert wait time after confirming specification PROM used.
R118
elimination/writing permission state
data elimination PROM
R118
Preliminary Product Information S16789EJ2V0PM
PD161606
[EPWALL] "Index 7FH"+ "Data FFH" written data E2PROM.
time PROM initialization, reads PROM data, command (R127) written infinite loop
reading noise etc. prevented.
Elimination/writing permission command input EWEN EPWALL command input WRAL <Erase All> After command input order access ROM, WRAL Wait Elimination/write-protected command input EWDS Completion processing passes elimination/write-protected. R118 needed wait time like data write. Insert wait time after confirming specification PROM used.
R118
elimination/writing permission state
R118
"Index (R127) "Data FFH" written data PROM.
Preliminary Product Information S16789EJ2V0PM
PD161606
RESET
/RESET input becomes reset command input, internal timing generator initialized. reset command will also initialize each register default value. These default values listed table below. When RSEL High-level, initialization performed reset command range setting /RESET input Lowlevel. (1/3)
Register Control register Control register interface register Command reset register Output amplitude power supply setup register 8-color display register Data access control register address register address register MIN. address register MAX. address register MIN. address register MAX. address register Partial display area start address register Partial display area line count register Partial data display area start line register Partial data display area start line register Partial display area start address register Partial display area line count register Partial data display area start line register Partial data display area start line register Partial area color register Power supply control register Power supply control register Power supply control register Power supply control register Power supply control register Gate scan setting register Common setting register Common amplitude setting register Common center voltage setting register Power supply rising select register Power supply command reset register /RESET
Note
Reset Command
Default Value
Remark Default value set, Default value Note case reset /RESET pin, only internal counters initialized. power application, sure perform reset /RESET pin.
Preliminary Product Information S16789EJ2V0PM
PD161606
(2/3)
Register Calibration register Partial display/horizontal interval clock setting register Gate scan line count select register Line count specify during line inversion register Partial display area gate scan cycle register GOE1 output control register DCCLK frequency register Horizontal back porch register Vertical back porch register Dummy line control select register GCLK, GSTB polarity select register GCLK inversion timing register Equalize interval start position register Equalize interval position register Amplifier drive start position register Amplifier drive position register GOE1 start position register GOE1 position register Partial mode GCLK inversion timing register Partial mode equalize interval start position register Partial mode equalize interval position register Partial mode amplifier drive start position register Partial mode amplifier drive position register Partial mode GOE1 start position register Partial mode GOE1 position register Bias adjustment register Bias adjustment register R100 R101 R102 R103 R104 R105 /RESET
Note
Reset Command
Default Value
adjustment register adjustment register adjustment register adjustment register adjustment register adjustment register
Remark Default value set, Default value Note case reset /RESET pin, only internal counters initialized. power application, sure perform reset /RESET pin.
Preliminary Product Information S16789EJ2V0PM
PD161606
(3/3)
Register /RESET R106 R107 R108 R109 R110 R111 R112 R113 R114 R115 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127
Note
Reset Command
Default Value
adjustment register adjustment register adjustment register adjustment register adjustment register adjustment register adjustment register adjustment register adjustment register adjustment register adjustment register
NW/NB polarity select register PROM setting PROM writing address specification PROM writing register address specification PROM products information register PROM products information register PROM products information register PROM reading address specification PROM divide register
PD161645 divide register
PROM read stop register
Remark Default value set, Default value Note case reset /RESET pin, only internal counters initialized. power application, sure perform reset /RESET pin. Cautions Whether reset performed /RESET reset command, contents display held. However, contents undefined immediately following power application. Calibration setting time tcal following value using reset command. tcal 1/fOSC
Preliminary Product Information S16789EJ2V0PM
PD161606
COMMAND
Command List (1/9)
Register Symbol DISP1 Function This command performs same output when data independently internal data (white display case normally white). This command executed, after been transferred, when next line output. Normal operation Ignores data outputs data DISP1 takes precedence over DISP0. When DISP1 DISP0 ignored. This command performs same output when data independently internal data (black display case normally white). This command executed, after been transferred, when next line output. Normal operation Ignores data outputs data This command selects line reversal function frame reversal function. Execution mode this command from timing which gate scan time command execution ends lines, following scan starts. Line inversion frame inversion Selects partial function. Execution mode selected with this command starts after gate scan during command execution completes lines next scan starts. Normal display mode Partial display mode This selects stand-by function. When stand-by function selected, display operation executed, amplifiers, oscillator each output stage stopped. After executing stand-by function using this bit, regulator gate power supply Block DC/DC converter OFF. sequence, refer preliminary product information machine. Note that when releasing stand-by, perform opposite operation, i.e., after setting DC/DC converter setting regulators this execute normal operation command. Normal operation Stand-by function Stand-by mode chosen from kinds operation (Stand-by mode Stand-by mode Refer Stand-by details operation. Stand-by mode Stand-by mode Selects function. Execution mode selected with this command starts after gate scan during command execution completes lines next scan starts. This command becomes invalid time partial display mode. Normal display mode display mode Sets output gate scanning signal during partial display. this gate scan lines partial non-display area carries every frame cycle register. Normal mode Gate scanning partial non-display area determined with setting value setting value
DISP0
STBY
STBSEL
Preliminary Product Information S16789EJ2V0PM
PD161606
(2/9)
Register Symbol
OSC1OFF
Function Addressing address inverted. more details, refer Figure 5-18. Addressing address inverted. more details, refer Figure 5-18. direction column address. direction sauce driver output select. more details, refer Figure 5-16. This oscillator circuit stop calibration. This command stop when stand-by mode. Oscillator operation Oscillator stop This oscillator circuit stop display. Regardless setup this bit, oscillation display stop time stand-by. Oscillator operation Oscillator stop Switches 260K color mode colors mode. Execution mode selected with this command starts after gate scan during command execution completes lines next scan starts. 262,144 colors colors Selects time calibration. calibration function adjusts frame frequency setting time line. This command select time aline form following. 1-line time tcal 1-line time tcal (tcal: Calibration time Frame frequency Number displayed lines) addition changing sequence data during write, switches relationship between data input from interface data source output. (The data switched.) Normal operation Source output Data RGB25 RGB20 Sn+1 RGB15 RGB10 Sn+2 RGB05 RGB00
OSC2OFF
COLOR
Switch data perform write. Source output Data DCKEG RGB05 RGB00 Sn+1 RGB15 RGB10 Sn+2 RGB25 RGB20
VSEG
HSEG
Selects DOTCLK active level. High active active Selects VSYNC active level. High active active Selects HSYNC active level. High active active
Preliminary Product Information S16789EJ2V0PM
PD161606
(3/9)
Register Symbol Function Command reset function. sure execute this after power Command reset automatically clears this following execution (CRES Therefore, necessary (select normal operation) again software. Moreover, since time required value this change following command reset execution extremely short, necessary secure time until command following command reset setting. Normal operation Command reset When colors mode selected, sets positive side black data drive method. Inverter drive Amplifier drive When colors mode selected, sets positive side black data drive method. Inverter drive Amplifier drive When colors mode selected, sets positive side black data drive method. Inverter drive Amplifier drive When colors mode selected, sets positive side black data drive method. Inverter drive Amplifier drive Window access mode setting When window access mode set, address incremented/decremented only range MIN. address setting register (R8), MAX. address setting register (R9), MIN. address setting register (R10), MAX. address setting register (R11). Normal operation Window access mode This selects direction which address incremented. Increments address Increments address This register sets address display RAM. value between EFH. This register sets address display RAM. value between 5FH. Sets minimum value address window access mode. address incremented maximum value MAX. address register (R9), then initialized address value this command. this register EFH. Sets maximum value address window access mode. address incremented maximum value MIN. address register (R8), then initialized address value this command. this register EFH. Sets minimum value address window access mode. address incremented maximum value MAX. address register (R11), then initialized address value this command. 5FH. Sets maximum value address window access mode. address incremented address value this command, then initialized minimum address value MIN. address register (R10). 5FH.
DSELPH
DSELNH
DESLPL
DSELNL
XMINn
XMAXn
YMINn
YMAXn
Preliminary Product Information S16789EJ2V0PM
PD161606
(4/9)
Register Symbol P1SLn Function This start address register (00H 5FH) partial data display area During partial display display, data display area extends line with this command line count register (R16) partial data display area This line count register (00H 60H) partial data display area During partial display display, data display area from line with this command start address register (R15) partial data display area Sets display start line partial data display area (00H 168H). display start line area specified with R18. Start line Setting prohibited line 359th line 360th line
P1AWn
P1DLn
Perform settings preserve following relationship. R17.R18+R16R21.R22 P1DLn P2STn Sets display start line partial display area This start address register (00H 5FH) partial data display area During partial display display, data display area extends line with this command line count register (R20) partial data display area This line count register (00H 60H) partial data display area During partial display display, data display area from line with this command start address register (R19) partial data display area Sets display start line partial data display area (00H 168H). display start line area specified with R22. Start line Setting prohibited line 359th line 360th line
P2AWn
P2DLn
Perform settings preserve following relationship. R17.R18+R16R21.R22 P2DLn PGR, PGC, Sets display start line partial display area Partial display color register Sets screen color areas other than partial display area, during partial display (R0: color selected from among colors each color. relationships between each color data this register's bits follows. These relationships depend value. Following transfer, this command executed from timing which next line data output. PGR: PGG: PGB:
Preliminary Product Information S16789EJ2V0PM
PD161606
When registers written serial interface PD161645 control started data transfer starts. (5/9)
Register Symbol RGONR VS4ON VS3ON VS2ON VD2ON VD1ON DCON VRSEL2 VRSEL1 VRSEL0 VCD2 CLS1 CLS0 ACS1 ACS0 EXRV VSEL2 VSEL1 VSEL0 RGON LACS1 LACS0 LFS3 LFS2 LFS1 LFS0 0E2SEL 0E1SEL STVSEL SCN2 SCN1 SCN0 COMHI COMSEL COMON CDAn PONM DUPF1 DUPF0 PUPT1 PUPT0 Function details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information. details, refer PD161645 preliminary products information.
Preliminary Product Information S16789EJ2V0PM
PD161606
(6/9)
Register Symbol This used calibration. time from calibration start command execution until calibration stop command execution becomes time line. Calibration stop Calibration start DIVSLn Selects horizontal interval clock division ratio. DIVSL1 HCKSLn DIVSL0 Division ratio Setting prohibited Horizontal interval time HCKSLn setting value HCKSLn setting value HCKSLn setting value Function
Selects horizontal interval clock count during partial mode. Horizontal interval clock HCKSLn setting value)] clock HCKSL3 HCKSL2 HCKSL1 HCKSL0 Horizontal interval clock count Setting prohibited Horizontal interval time
DIVSLn setting value DIVSLn setting value DIVSLn setting value DIVSLn setting value
LNSELn
Selects gate scan line count. LNSEL5 LNSEL4 LNSEL3 LNSEL2 LNSEL1 LNSEL0 Line count lines lines lines lines
Settings other than above prohibited
NLINE1 NLINE0
Selects line inversion line count. NLINE1 NLINE0 line inversion line count
GSMLN1 GSMLN0
Selects partial non-display area gate scan operation. GSMLN1 GSMLN0 Partial non-display area gate scan Gate scan stop Gate scan during frames interval Gate scan during frames interval Setting prohibited
Preliminary Product Information S16789EJ2V0PM
PD161606
(7/9)
Register Symbol GOE2ON Function Controls GOE2 output. Normal operation GOE2 output fixed Low-level. (All gates Selects gate scan ON/OFF based GOE1 output. Gate scan (GOE1 fixed Low-level) Normal operation Selects DCCLK frequency. DCSEL1 HBPn DCSEL0 Output frequency Output stop fOSC/30 fOSC/20 fOSC/10
GOE1ON
DCSELn
VBPn
DMSEL
GSSEL
GCSEL
GCEDn EQSTn EQEDn APSTn APEDn GOSTn GOEDn PGCEDn PEQSTn PEQEDn PAPSTn PAPEDn PGOSTn PGOEDn
Sets horizontal direction back porch interval interface. Horizontal back port interval Setting value DOTCLK unit horizontal back porch interval higher. Sets vertical direction back porch interval interface. Vertical back porch interval Setting value HSYNC unit horizontal back porch interval higher. Sets whether perform dummy output first line frame. Dummy line dummy line Inverts GSTB signal polarity. active High active Inverts GCLK signal's polarity. When HSYNC active level input, GCLK High results changes timing R79. When HSYNC active level input, GCLK results changes High timing R79. Sets GCLK inversion timing during normal operation. Sets equalize interval start position horizontal interval during normal operation. Sets equalize interval position horizontal during normal operation. Sets start position amplifier driver interval horizontal interval during normal operation. Sets position amplifier driver interval horizontal interval during normal operation. Sets start position (rising edge position) GOE1 signal horizontal interval during normal operation Sets stop position (falling edge position) GOE1 signal horizontal interval during normal operation Sets GCLK inversion timing partial display mode. Sets start position equalize interval horizontal interval partial display mode. Sets stop position equalize interval horizontal interval partial display mode. Sets start position amplifier drive interval horizontal interval partial display mode. Sets stop position amplifier drive interval horizontal interval partial display mode. Sets start position (rising edge position) GOE1 signal horizontal interval during partial display mode. Sets stop position (falling edge position) GOE1 signal horizontal interval during partial display mode.
Preliminary Product Information S16789EJ2V0PM
PD161606
(8/9)
Register R100 Symbol RBIASn BBIASn ABIASn OPADJn GSELPH Function Adjust bias operational amplifier. Adjust bias operational amplifier bias circuit. Adjust bias output operational amplifier. Adjust capacity output operational amplifier. Sets output source power supply black data positive side compensation resistor. Sets power supply voltage. (Outputs potential) Uses internal output adjustment circuit. (Uses VPH, VNH, VPL, outputs) Sets output source power supply white data negative side compensation resistor. Sets power supply voltage. (Outputs potential) Uses internal output adjustment circuit. (Uses VPH, VNH, VPL, outputs) Sets output source power supply white data positive side compensation resistor. Sets power supply voltage. (Outputs potential) Uses internal output adjustment circuit. (Uses VPH, VNH, VPL, outputs) Sets output source power supply black data negative side compensation resistor. Sets power supply voltage. (Outputs potential) Uses internal output adjustment circuit. (Uses VPH, VNH, VPL, outputs) Positive-polarity amplitude adjustment register. Refer 5.5.1 Amplitude adjustment with internal amplifier. Negative-polarity amplitude adjustment register. Refer 5.5.1 Amplitude adjustment with internal amplifier. Positive-polarity amplitude adjustment register. Refer 5.5.1 Amplitude adjustment with internal amplifier. Negative-polarity amplitude adjustment register. Refer 5.5.1 Amplitude adjustment with internal amplifier. Positive-polarity amplitude adjustment register. Refer 5.5.2 Amplitude adjustment built-in resistance. Positive-polarity amplitude adjustment register. Refer 5.5.2 Amplitude adjustment built-in resistance. Positive-polarity tilt adjustment register. Refer 5.5.3 Inclination adjustment. Positive-polarity tilt adjustment register. Refer 5.5.3 Inclination adjustment. Positive-polarity fine adjustment register. Refer 5.5.4 Fine tunig adjustment. Positive-polarity fine adjustment register. Refer 5.5.4 Fine tunig adjustment. Positive-polarity fine adjustment register. Refer 5.5.4 Fine tunig adjustment. Positive-polarity fine adjustment register. Refer 5.5.4 Inclination adjustment. Positive-polarity tilt adjustment register. Refer 5.5.3 Inclination adjustment. Positive-polarity tilt adjustment register. Refer 5.5.3 Inclination adjustment. Positive-polarity tilt adjustment register. Refer 5.5.3 Inclination adjustment. Positive-polarity tilt adjustment register. Refer 5.5.3 Inclination adjustment. Negative-polarity amplitude adjustment register. Refer 5.5.2 Amplitude adjustment built-in resistance. Negative-polarity amplitude adjustment register. Refer 5.5.2 Amplitude adjustment built-in resistance. Negative-polarity inclination adjustment register. Refer 5.5.3 Inclination adjustment. Negative-polarity inclination adjustment register. Refer 5.5.3 Inclination adjustment. Negative-polarity fine adjustment register. Refer 5.5.4 Fine tunig adjustment. Negative-polarity fine adjustment register. Refer 5.5.4 Inclination adjustment.
GSELNH
GSELPL
GSELNL
R101 R102 R103 R104 R105
GPHn GNHn GPLn GNLn VDRPn VSRPn VLRPn VHRPn VGR1Pn VGR0Pn VGR3Pn VGR2Pn VGR5Pn VGR4Pn VGR7Pn VGR6Pn VDRNn VSRNn VLRNn VHRNn VGR1Nn VGR0Nn
R106 R107 R108 R109 R110 R111
R112 R113
Preliminary Product Information S16789EJ2V0PM
PD161606
(9/9)
Register R114 R115 R116 R117 Symbol VGR3Nn VGR2Nn VGR5Nn VGR4Nn VGR7Nn VGR6Nn NWBSL Function Negative-polarity fine adjustment register. Refer 5.5.4 Fine tuningadjustment. Negative-polarity fine adjustment register. Refer 5.5.4 Fine tuning adjustment. Negative-polarity inclination adjustment register. Refer 5.5.3 Inclination adjustment. Negative-polarity inclination adjustment register. Refer 5.5.3 Inclination adjustment. Negative-polarity inclination adjustment register. Refer 5.5.3 Inclination adjustment. Negative-polarity inclination adjustment register. Refer 5.5.3 Inclination adjustment. Switches normally white normally black. Normally white Normally black R118 R119 R120 R121 R122 R123 R124 R125 PROM PROM write address specify PROM write register address specify PROM fabrication information register PROM fabrication information register PROM fabrication information register PROM read start address specify PROM divide register Selects serial clock frequency PROM interface. R126 PROM interface serial clock frequency Interface oscillation frequency/2 Interface oscillation frequency/4 Interface oscillation frequency/8 Interface oscillation frequency/16
PD161645 divide register
Selects serial clock frequency PD161645 interface.
E2PROM interface serial clock frequency PD161645 interface serial clock frequency
Interface oscillation frequency/1 frequency/2 Interface oscillation frequency/2 frequency/4 Interface oscillation frequency/4 frequency/8 Interface oscillation frequency/6 Interface oscillation frequency/16
R127
PROM read stop register
Preliminary Product Information S16789EJ2V0PM
PD161606
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C,
Parameter Power supply voltage Power supply voltage Power supply voltage Power supply voltage Power supply voltage Input voltage Input voltage Input current Output current Operating ambient temperature Storage temperature Symbol VCC1 VCC2 VCC3 Tstg
Note1 Note2
Ratings -0.5 +3.0 -0.5 +6.0 -0.5 +6.0 -0.5 +6.0 -0.5 +6.0 -0.5 VCC2 -0.5 +125
Unit
Notes Power supply system VCC2. Power supply system Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Recommended Operating Conditions +85°C,
Parameter Power supply voltage Power supply voltage Power supply voltage Power supply voltage Power supply voltage Input voltage Input voltage Symbol VCC1 VCC2 VCC3
Note1 Note2
MIN. 1.65 1.65 1.65
TYP.
MAX.
Unit
VCC2
Notes Power supply system VCC2. Power supply system
Preliminary Product Information S16789EJ2V0PM
PD161606
Electrical Specifications (Unless Otherwise Specified, +85°C, VCC1 VCC2 VCC3
Parameter Input leakage High level input voltage level input voltage High level output voltage level output voltage High level input current level input current SF_VCC1 output voltage SF_VCC1 output resistor Source driver output voltage range Source driver output current IVOH IVOL Source driver output bias Source driver output delay time Current consumption tPHLSI tPLHSI ICC1 ICC2 ICC3 ISTBY T.B.D. T.B.D. VCC1 (when non-access CPU) VCC2 (when non-access CPU) VCC3 (when non-access CPU) VCC1 (stand-by mode) VCC2 (stand-by mode) VCC3 (stand-by mode) (stand-by mode) (stand-by mode)
Note
Symbol VOH1 VOH2 VOL1 VOL2 SF_VCC1 RSFVCC1 VP-P VCC2 VCC2
Condition
MIN.
TYP.
Note1
MAX.
Unit
VCC2 VCC2 VCC2 VCC3 VCC2 VCC3 1.65 T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D.
VCC2, IOUT -100 VCC3, IOUT -100 VCC2, IOUT -100 VCC3, IOUT -100 VCC2 VCC2 ISFVCC1
VOUT 0.1, VOUT VOUT 0.1, VOUT
Notes TYP. values reference values when 25°C VSTBY
Preliminary Product Information S16789EJ2V0PM
PD161606
Characteristics (Unless Otherwise Specified, +85°C, VCC1 VCC2 VCC3 18-/16-bit interface
Horizontal system tCLK DOTCLK tHBP RGB00 RGB25 HSYNC VSYNC tVSS Vertiacal system HSYNC tVBP RGB00 RGB25 tHSS tHSH tHSW pixel pixel
Last Data
VSYNC line line tVSW Last line
Parameter clock cycle time clock high level pulse width clock level pulse width Data setup time Data hold time HSYNC pulse width HSYNC setup time HSTNC hold time Horizon period back porch time VSYNC pulse width VSYNC setup time Vertical period back porch time
Symbol tCLK tCLKH tCLKL tHSW tHSS tHSH tHBP tVSW tVSS tVBP
Condition
MIN.
TYP.
MAX.
Unit DOTCLK DOTCLK
Remarks input signal's rise/fall times rated less. timing rated based VCC1. minimum number DOTCLK clocks that should input horizontal interval follows. DOTCLK count horizontal interval (DOTCLK count HSYNC interval) (horizontal back porch interval) (pixel display interval times) number HSYNC that should input frame interval follows. HSYNC frame interval (HSYNC count during VSYNC interval) (vertical back porch interval) (pixel display interval)
Preliminary Product Information S16789EJ2V0PM
PD161606
6-bit interface
Horizontal system
tCLK
DOTCLK ENABLE RGB20 RGB25 tHSS HSYNC VSYNC
tVSS tHSH tHSW tHBP
Data Data Data
Last data
Vertical system
HSYNC
tVBP
RGB20 RGB25 VSYNC
line tVSW Last line
Parameter clock cycle time clock high level pulse width clock level pulse width Data setup time Data hold time HSYNC pulse width HSYNC setup time HSTNC hold time Horizon period back porch time VSYNC pulse width VSYNC setup time Vertical period back porch time
Symbol tCLK tCLKH tCLKL tHSW tHSS tHSH tHBP tVSW tVSS tVBP
Condition
MIN.
TYP.
MAX.
Unit DOTCLK DOTCLK
Remarks input signal's rise/fall times rated less. timing rated based VCC1. minimum number DOTCLK clocks that should input horizontal interval follows. DOTCLK count horizontal interval (DOTCLK count HSYNC interval) (horizontal back porch interval) (pixel display interval times number HSYNC that should input frame interval follows. HSYNC frame interval (HSYNC count during VSYNC interval) (vertical back porch interval) (pixel display interval)
Preliminary Product Information S16789EJ2V0PM
PD161606
interface
tAS8 tAH8
tCYC8 tCCLW, tCCLR
/WR, tCCHR, tCCHW tDS8 (Write) tACC8 (Read) tOH8 tDH8
(Unless Otherwise Specified, +85°C, VCC1 VCC2 VCC3
Parameter Address hold time Address setup time System cycle time Symbol tAH8 tAS8 tCYC8 Read (Register) Read (RAM) Write Control low-level pulse width (/WR) Control low-level pulse width (/RD) Control high-level pulse width (/WR) Control high-level pulse width (/RD) Write Read time Data setup time Data hold time access time (Register) access time (RAM) Output disable time tOH8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 (Register) (RAM) (Register) (RAM) (RAM), (RAM) Condition MIN. T.B.D. TYP. MAX. Unit
Remarks input signal's rise/fall times rated less. timing rated based VCC2.
Preliminary Product Information S16789EJ2V0PM
PD161606
interface
R,/W tAS6 tAH6
tCYC6 tEWHR, tEWHW
tEWLR, tEWLW tDS6 tDH6
(Write) tACC6 (Read) tOH6
(Unless Otherwise Specified, +85°C, VCC1 VCC2 VCC3
Parameter Address hold time Address setup time System cycle time Symbol tAH6 tAS6 tCYC6 Read (Register) Read (RAM) Write Data setup time Data hold time Access time (Register) Access time (RAM) Write Read time Output disable time Enable high pulse width Read Write Enable pulse width Read Write tOH6 tEWHR tEWHW tEWLR tEWLW (RAM), (RAM) (Register) (RAM) (Register) (RAM) T.B.D. tDS6 tDH6 tACC6 Condition MIN. TYP. MAX. Unit
Remarks input signal's rise/fall times rated less. timing rated based VCC2.
Preliminary Product Information S16789EJ2V0PM
PD161606
Serial interface
tCSS tCSH
tSAS tSAH
tSWRS R,/W
tSWRH
tSCYC tSLW tSDS tACCS tOHS tSHW tSDH
(Unless Otherwise Specified, +85°C, VCC1 VCC2 VCC3
Parameter Serial clock cycle high level pulse width level pulse width time hold time time hold time R,/W time R,/W hold time Data time Data hold time Access time Output disable time Symbol tSCYC tSHW tSLW tCSS tCSH tSAS tSAH tSWRS tSWRH tSDS tSDH tACCS tOHS Read Write Read Write Read Write R,/W R,/W Condition MIN. TYP. MAX. Unit
Remarks rise fall times input signals rated less. timing rated based VCC2.
Preliminary Product Information S16789EJ2V0PM
PD161606
Common
Parameter Calibration setting time (frame frequency) Frame frequency Frame frequency Frame frequency Oscillation frequency Symbol tcal (fFRAME0) fFRAME2 fFRAME3 fFRAME4 fOSC1 fOSC2 Calibrated Calibrated
Note3 Note4
Condition Note2, fFRAME
MIN.
TYP.
Note1
MAX.
Unit
44.3 (60) T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. 1745
(Hz)
Before calibration, OSCSEL OSCSEL VCC1 OSCSEL T.B.D.
Note5
External oscillation frequency Reset pulse width time power supply injection Reset pulse width Reset time
fOSCIN /RESET interface operation VSTBY SF_VCC1
Notes TYP. values reference values when 25°C. relationship between frame frequency calibration setting time follows. tcal 1/(fFRAME (360 16)) Measured +85°C, after calibration frame frequency 25°C exactly. Measured ±5°C, after calibration frame frequency exactly. Since oscillation frequency changed with parasitism capacity value external resistance, please refer standard.
Preliminary Product Information S16789EJ2V0PM
PD161606
EXAMPLE PD161606 CONNECTION
Examples PD161606 connection shown below. example below, control para
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