#7#&026#4XDG&$6 89#70# )HDWXUHV Organization: 4,194,304 words bit
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#7#&026#4XDG&$6 89#70# )HDWXUHV
Organization: 4,194,304 words bits High speed 50/60 access time 25/30 column address access time 12/15 access time power consumption Active: Standby: max, CMOS Fast page mode Refresh 4096 refresh cycles, refresh interval 4C4M4FOQ 2048 refresh cycles, refresh interval AS4C4M4F1Q RAS-only CAS-before-RAS refresh self-refresh TTL-compatible, three-state separate pins allow separate operation JEDEC standard package mil, 28-pin mil, 28-pin TSOP Latch-up current protection 2000
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I/O0 I/O1 *NC/A11 CAS0 CAS1 I/O3 I/O2 CAS3 CAS2 I/O0 I/O1 *NC/A11 CAS0 CAS1
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TSOP
I/O3 I/O2 CAS3 CAS2
Pin(s) CAS0 CAS3 I/O0 I/O3
Description Address inputs address strobe Column address strobe Write enable Input/output Output enable Power Ground
AS4C4M4F0Q/F1Q
refresh version; refresh version
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Symbol Maximum access time Maximum column address access time Maximum access time Maximum output enable (OE) access time Minimum read write cycle time Minimum fast page mode cycle time Maximum operating current Maximum CMOS standby current tRAC tCAA tCAC tOEA ICC1 ICC5 4C4M4FOQ-50 AS4C4M4F1Q-50 4C4M4FOQ-60 AS4C4M4F1Q-60 Unit
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Copyright ©1999 Alliance Semiconductor. rights reserved.
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4C4M4FOQ AS4C4M4F1Q high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) devices organized 4,194,304 words bits. devices fabricated using advanced CMOS technology innovative design techniques resulting high speed, extremely power wide operating margins component system levels. Alliance 16Mb DRAM family optimized main memory workstation, router switch applications. These devices feature high speed page mode operation where read write operations within single page) exec uted very high speed toggling column addresses within that row. column addresses alternately latched into input buffers using falling edge inputs respectively. Four individual pins allow separate operation which enables devices operate parity mode. Also, used make column address latch transparent, enabling application column addresses prior assertion. Refresh 4096 address combinations must performed every using: RAS-only refresh: asserted while held high. Each 4096 rows must strobed. Outputs remain high impedence. Hidden refresh: held while toggled. Refresh address generated internally. Outputs remain impedence with previous valid data. CAS-before-RAS refresh (CBR): asserted prior RAS. Refresh address generated internally. Outputs high-impedence don't care). Normal read write cycles refresh being accessed. Self-refresh cycles Refresh 2048 address combinations must performed every using: RAS-only refresh: asserted while held high. Each 2048 rows must strobed. Outputs remain high impedence. Hidden refresh: held while toggled. Refresh address generated internally. Outputs remain impedence with previous valid data. CAS-before-RAS refresh (CBR): asserted prior RAS. Refresh address generated internally. Outputs high-impedence don't care). Normal read write cycles refresh being accessed. Self-refresh cycles 4C4M4FOQ AS4C4M4F1Q available standard 28-pin plastic 28-pin plastic TSOP packages. 4C4M4FOQ AS4C4M4F1Q operate with single power supply 0.5V provide compatible inputs outputs.
Refresh controller Column decoder Sense Data buffers
I/O0 I/O3
clock generator
clock generator
clock generator
Address buffers decoder 4,194,304 Array (16,777,216)
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Refresh controller Column decoder Sense Data buffers
I/O0 I/O3
clock generator
clock generator
clock generator
Address buffers decoder 4,194,304 Array (16,777,216) Substrate bias generator
Parameter Supply voltage Input voltage Ambient operating temperature
Symbol
-0.5
Nominal
Unit
-3.0V pulse widths less than Recommended operating conditions apply throughout this document unlesss otherwise specified.
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Parameter Input voltage Input voltage (DQs) Power supply voltage Storage temperature (plastic) Soldering temperature time Power dissipation Short circuit output current Symbol TSTG TSOLDER Iout -1.0 -1.0 -1.0 +7.0 +7.0 +150 Unit
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Parameter Symbol Test conditions +5.5V, Pins under test DOUT disabled, Vout +5.5V RAS, Address cycling; tRC=min cycling, VIH, after XCAS low. VIL, CAS, address cycling: tHPC 0.2V IOUT -5.0 IOUT RAS, cycling, UCAS LCAS 0.2V, 0.2V, other inputs 0.2V 0.2V Unit Notes
Input leakage current Output leakage current Operating power supply current standby power supply current ICC1 ICC2
Average power supply current, refresh ICC3 mode Fast page mode average power supply ICC4 current CMOS standby power ICC5 supply current Output voltage before refresh current ICC6
Self refresh current
ICC7
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Symbol Parameter tRAS tCAS tRCD tRAD tRSH tCSH tCRP tASR tRAH tREF tRAL tASC tCAH Random read write cycle time precharge time pulse width pulse width delay time column address delay time hold time hold time precharge time address setup time address hold time Transition time (rise fall) Refresh period precharge time Column address lead time Column address setup time Column address hold time 32/64 32/64 Unit 17/16 Notes
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Symbol Parameter tRAC tCAC tRCS tRCH tRRH Access time from Access time from Access time from address Read command setup time Read command hold time Read command hold time Unit Notes 6,13 7,13
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Symbol Parameter tWCS tWCH tRWL tCWL Write command setup time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time Unit Notes
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Symbol Parameter tRWC tRWD tCWD tAWD Read-write cycle time delay time delay time Column address delay time Unit Notes
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Symbol Parameter tCSR tCHR tRPC tCPT setup time (CAS-before-RAS) hold time (CAS-before-RAS) precharge hold time precharge time (CBR counter test) Unit Notes
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Symbol tCPA tRASP tPCM tCRW Parameter Access time from precharge
pulse width
100K 100K Unit Notes
Read-write cycle time
precharge time (fast page)
Fast page mode cycle Page mode pulse width (RMW)
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Symbol tCLZ tROH tOEA tOED tOEZ tOEH tOLZ tOFF Parameter output hold time referenced access time data delay Output buffer turnoff delay from command hold time output Output buffer turn-off time Unit 8,10 Notes
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Symbol tRASS tRPS tCHS Parameter
pulse width (CBR self refresh) precharge time (CBR self refresh) hold time (CBR self refresh)
Unit Notes
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ICC1, ICC3, ICC4, ICC6 dependent frequency. ICC1 ICC4 depend output loading. Specified values obtained with output open. initial pause required after power-up followed cycles before proper device operation achieved. case internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. initialization cycles required after extended periods bias without clocks (greater than ms). Characteristics assume parameters measured with load equivalent loads (min) (max) VCC. (min) (max) reference levels measuring timing input signals. Transition times measured between VIL. Operation within tRCD (max) limit insures that tRAC (max) met. tRCD (max) specified reference point only. greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation within tRAD (max) limit insures that (max) met. tRAD (max) specified reference point only. tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. Assumes three state test load Thevenin equivalent). Either tRCH must satisfied read cycle. tOFF (max) defines time which output achieves open circuit condition; referenced output voltage levels. tOFF referenced from rising edge CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD tAWD restrictive operating parameters. They included datasheet electrical characteristics only. (min) (min), cycle early write cycle data pins will remain open circuit, high impedance, throughout cycle. tRWD tRWD (min), tCWD tCWD (min) tAWD tAWD (min), cycle read-write cycle data will contain data read from selected cell. neither above conditions satisfied, condition data access time indeterminate. These parameters referenced leading edge early write cycles leading edge read-write cycles. Access time determined longest tCAA tCAC tCPA tASC achieve (min) tCPA (max) values. These parameters sampled 100% tested. These characteristics apply 4C4M4FOQ devices. These characteristics apply AS4C4M4F1Q devices.
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Access times measured with output reference levels 2.4V 0.4V, 2.4V 0.8V Input rise fall times:
Dout
*including scope capacitance
+3.3V Dout
*including scope capacitance
Figure Equivalent output load (AS4C4M4F0/AS4C4M4F1)
Figure Equivalent output load (AS4C4M4F0/AS4C4M4F1)
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Rising input Falling input Undefined output/don't care
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tRAS tRCD tRSH
tCSH tCRP tASC tRCS tCAH tCAS
tRAD tASR tRAH Column address tRRH tRCH tRAL
Address
address
tROH tROH
tWEZ
tRAC tOEA tCAC tCLZ tREZ Data tOLZ tOEZ tOFF (see note
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tRAS
tCSH tRSH tCRP tRCD tRAD tASC tASR tRAH tCAH Column address tCWL tRWL tWCS tWCH tCAS tRAL
Address
address
Data
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tRAS
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tCSH tCRP tRCD tRSH tCAS tRAL tRAD tRAH tASC tCAH Column address tRWL tCWL
tASR
Address
address
tOEH
tOED
Data
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tRWC tRAS tCAS tCRP tRCD tCSH tRSH
tRAD tASR tRAH address
tRAL tASC tCAH Column address tRWD tAWD tRCS tCWD tOEA tOEZ tOED tCWL tRWL
Address
tRAC
tCAC tCLZ Data
tOLZ
Data
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tRASP
tCSH tCRP tRCD tCAS tRSH
tRAD tASR tRAH tASC tRAL tCAH
Address
Column
tRCS tRCH tOEA
Column
tRCS
Column
tRCH tOEA tRRH
tRAC tCLZ tOEZ tCAP tOFF tCAC
Data
Data
Data
tRASP
tPCM tCSH tRCD tCAS tCRP
tASR
tRAD tRAH tCAH tCAH tRAL tCAH
Address
tRCS
Column
tRWD tCWD tAWD
Column
tCWL tCWD
Column
tRWL tCWD tAWD tCWL
tOEA tOEZ tRAC tCLZ tCAC tCLZ tCAC tCAP tCLZ tCAC tOED tOEA
Data Data
Data Data
Data Data
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tRASP tRAH tRWL tRCD tCSH tCAS tASC tWCS tRAL tRSH tCAH
tCRP
tASR tRAD
Address
Column
Column
Column
tCWL tWCH tOEH
tHDR tOED
Data
Data
Data
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tRAS
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tRPC tCSR tCHR
OPEN
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tRAS tRPC
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tCRP
tASR tRAH address
Address
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tRAS tCHR tRCD tRSH tCRP tRAS
tCRP
tRAD tRAH tASR tASC tRCS address tRRH tOEA tCAH
Address
tRAC tCAC tCLZ tOEZ Data tOFF
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tRAS tCHR
tCRP tRCD tRSH
tRAD tRAH tASR tASC address tWCR tWCS tWCH address tRWL tRAL tCAH
Address
tDHR Data
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tRAS tRSH
tCSR tCHR tCPT tCAS
tASC tCAH
tRAL
Address
address tCAC tCLZ tOFF tOEZ Data tRCS tRRH tRCH
Read cycle
tROH tOEA
tRWL tCWL tWCH tWCS
Write cycle
Data
tRCS tCWD tAWD
tRWL tCWL
Read-Write cycle
tOEA tOED
tCLZ tCAC tOEZ Data Data
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tRASS tRPS
tRPC tCSR tCHS tRPC
UCAS, LCAS
tCEZ
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Parameter Input capacitance capacitance Symbol CIN1 CIN2 Signals RAS, UCAS, LCAS, DQ15
#4#0+]/#7D# #5RRP#WHPSHUDWXUH Test conditions Vout Unit
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Package access time Plastic SOJ, mil, 24/26-pin Plastic TSOP, mil, 24/26-pin 3.3V 4C4M4FOQ-50JC 4C4M4FOQ-50TC 4C4M4FOQ-60JC 4C4M4FOQ-60TC
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Package access time Plastic SOJ, mil, 24/26-pin Plastic TSOP, mil, 24/26-pin 3.3V AS4C4M4F1Q-50JC AS4C4M4F1Q-50TC AS4C4M4F1Q-60JC AS4C4M4F1Q-60TC
DRAM prefix E0=4K refresh E1=2K refresh access time CMOS 3.3V CMOS Package: Commercial temperature mil, 24/26 range, TSOP mil, 24/26
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