SST34HF162x SST34HF164x Preliminary Specifications FEATURES: Flas
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Mbit Concurrent SuperFlash Mbit Mbit SRAM
SST34HF162x SST34HF164x
Preliminary Specifications FEATURES: Flash Organization: Dual-Bank Architecture Concurrent Read/Write Operation Mbit Bottom Sector Protection Devices SST34HF1621: 12Mbit Mbit SST34HF1641: 12Mbit Mbit Mbit Sector Protection Devices SST34HF1622: Mbit Mbit SST34HF1642: Mbit Mbit SRAM Organization: Mbit: 256K 128K Mbit: 512K 256K Single 2.7-3.3V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Auto Power Mode: (typical) Hardware Sector Protection/WP# Input Protects outer most sectors KWord) larger bank holding unprotects holding high Hardware Reset (RST#) Resets internal state machine reading data array PRODUCT DESCRIPTION SST34HF162x/164x ComboMemory devices integrate CMOS flash memory bank with 256K 128K 512K 256K CMOS SRAM memory bank Multi-Chip Package (MCP). These devices fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST34HF162x/164x devices ideal applications such cellular phones, GPSs, PDAs other portable electronic devices power small form factor system. SST34HF162x/164x features dual flash memory bank architecture allowing concurrent operations between flash memory banks SRAM. devices read data from either bank while Erase Program operation progress opposite bank. flash memory banks partitioned into Megabits Megabits with bottom sector protection options storing boot code, program code, configuration/parameter data user data.
2001 Silicon Storage Technology, Inc. 523-2 1/01 S71172
Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Read Access Time Flash: SRAM: Latched Address Data Fast Erase Word-Program: Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Word-Program Time: (typical) Chip Rewrite Time: seconds (typical) Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Ready/Busy# CMOS Compatibility JEDEC Standard Command Conforms Common Flash Memory Interface (CFI) Packages Available 56-Ball LFBGA (8mm 10mm) SuperFlash technology provides fixed Erase Program times, independent number Erase/ Program cycles that have occurred. Therefore, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST34HF162x/164x devices offer guaranteed endurance 10,000 cycles. Data retention rated greater than years. With high performance Word-Program, flash memory banks provide typical Word-Program time µsec. entire flash memory bank erased programmed word-by-word typically seconds SST34HF162x/164x, when using interface features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent flash write, SST34HF162x/164x devices contain on-chip hardware software data protection schemes. flash SRAM operate independent memory banks with respective bank enable signals. memory bank selection done bank enable signals.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory Concurrent SuperFlash trademarks Silicon Storage Technology, Inc.These specifications subject change without notice.
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications SRAM bank enable signal, BES1# BES2, selects SRAM bank. flash memory bank enable signal, BEF#, used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. memory banks superimposed same memory address space where they share common address lines, data lines, which minimize power consumption area. contention eliminated device will recognize both bank enables being simultaneously active. Designed, manufactured, tested applications requiring power small form factor, SST34HF162x/164x offered both commercial extended temperatures small footprint micro ball grid array (µBGA) package meet board space constraint requirements. Device Operation SST34HF162x/164x uses BES1#, BES2 BEF# control operation either flash SRAM memory bank. When BEF# low, flash bank activated Read, Program Erase operation. When BES1# low, BES2 high SRAM activated Read Write operation. BEF# BES1# cannot level, BES2 cannot high level same time. bank enable signals asserted, contention will result device suffer permanent damage. address, data, control lines shared flash SRAM memory banks which minimizes power consumption loading. device goes into standby when BEF# BES1# bank enables raised VIHC (Logic High) when BEF# high BES2 low. SST34HF162x/164x also have Auto Power mode which puts flash memory near standby mode after data been accessed with valid Read operation. This reduces active read current typically device exits Auto Power mode with address transition control signal transition used initiate another read cycle, with access time penalty. Concurrent Read/Write Operation Dual bank architecture SST34HF162x/164x devices allows Concurrent Read/Write operation whereby user read from bank while program erase other bank. This operation used when user needs read system code bank while updating data other bank. Figures Dual-Bank Memory Organization. CONCURRENT READ/WRITE STATE TABLE Flash Bank Bank Read Write Write Operation Write Operation Write Read Operation Write Operation Write
SRAM Operation Operation Read Read Write Write
Note: purposes this table, write means Block-, Sector, Chip-Erase, Word-Program applicable appropriate bank.
Flash Read Read operation SST34HF162x/164x controlled BEF# OE#, both have system obtain data from outputs. BEF# used device selection. When BEF# high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either BEF# high. Refer Read cycle timing diagram further details (Figure Flash Word-Program Operation SST34HF162x/164x programmed word-byword basis. Program operation consists three steps. first step three-byte load sequence Software Data Protection. second step load word address word data. During Word-Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored. Flash Sector/Block-Erase Operation Sector/Block-Erase operation allows system erase device sector-by-sector block-by-block basis. SST34HF162x/164x offer both Sector-Erase Block-Erase mode. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. SectorErase operation initiated executing six-byte com2
S71172 523-2 1/01
2001 Silicon Storage Technology, Inc.
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications mand sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Figures timing waveforms. commands issued during Sector- Block-Erase operation ignored. Flash Chip-Erase Operation SST34HF162x/164x provide Chip-Erase operation, which allows user erase unprotected sectors/ blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth BEF#, whichever occurs first. During Erase operation, only valid read Toggle Bits Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored. Flash Write Operation Status Detection SST34HF162x/164x provide hardware software means detect completion Write (Program Erase) cycle, order optimize system write cycle time. hardware detection uses Ready/Busy# (RY/BY#) pin. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-ofWrite detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Ready/Busy# (RY/ BY#), Data# Polling (DQ7) Toggle (DQ6) read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed write cycle, otherwise rejection valid. Ready/Busy# (RY/BY#) SST34HF162x/164x includes Ready/Busy# (RYBY#) output signal. During initiated operation, e.g., Erase, Program, Read operation, RY/BY#
2001 Silicon Storage Technology, Inc.
actively pulled low, indicating controlled operation Progress. status RY/BY# valid after rising edge fourth CE#) pulse Program operation. Sector-, Block- Bank-Erase, valid after rising edge sixth (CE#) pulse. RY/BY# open drain output that allows several devices tied parallel external pull resistor. Ready/Busy# high impedance whenever high RST# low. Flash Data# Polling (DQ7) When SST34HF162x/164x internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. device then ready next operation. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling (DQ7) valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block- Chip-Erase, Data# Polling (DQ7) valid after rising edge sixth BEF#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart. Flash Toggle Bits (DQ6 DQ2) During internal Program Erase operation, consecutive attempts read will produce alternating 0's, i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. Toggle (DQ6) valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block- Chip-Erase, Toggle (DQ6) valid after rising edge sixth BEF#) pulse. Figure Toggle timing diagram Figure flowchart. Data Protection SST34HF162x/164x provide both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: BEF# pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications Hardware Block Protection SST34HF162x/164x provide hardware block protection which protects outermost KWords larger bank.The block protected when held low. Figures Block-Protection location. user disable block protection driving high thus allowing erase program data into protected sectors. must held high prior issuing write command remain stable until after entire Write operation completed. Hardware Reset (RST#) When RST# input held least TRP, progress operation will terminate device will return Read mode. Erase operation been interrupted, needs reinitiated after device resumes normal operation mode ensure data integrity. minimum period TRHR required after RST# goes high before valid read take place. reset signal must remain until stabilized. device will ready operation 20µs after completion reset reset driven high. Figures timing diagram. Software Data Protection (SDP) SST34HF162x/164x provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST34HF162x/ 164x shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15-DQ8 "Don't Care" during command sequence. Common Flash Memory Interface (CFI) SST34HF162x/164x also contain information describe characteristics device. order enter Query mode, system must write threebyte sequence, same Software Entry command with (CFI Query command) address 555H last byte sequence. Once device enters Query mode, system read data addresses given Tables through system must write Exit command return Read mode from Query mode.
2001 Silicon Storage Technology, Inc. S71172 523-2 1/01
Product Identification product identification mode identifies devices SST34HF162x/164x manufacturer SST. This mode accessed software operations only. hardware device Read operation, which typically used programmers cannot used this device because shared lines between flash SRAM multi-chip package. Therefore, application high voltage damage this device. Users software product identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Tables software operation, Figure software entry read timing diagram Figure entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION TABLE WORD Manufacturer's Device SST34HF1621 SST34HF1622 SST34HF1641 SST34HF1642 0000 0001 0001 0001 0001 DATA 00BF 2761 2762 2761 2762
T1.0
Product Identification Mode Exit/CFI Mode Exit order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/ Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications SRAM Operation With BES1# low, BES2 BEF# high, SST34HF162x operates 256K 128K CMOS SRAM, SST34HF164x operates 512K 256K CMOS SRAM, with fully static operation requiring external clocks timing strobes. CIOs configures SRAM SRAM operation modes. SST34HF162x SRAM mapped into first 256/128 KWord address space device, SST34HF164x SRAM mapped into first 512/ KWord address space. When BES1#, BEF# high BES2 low, memory banks deselected device enters standby. Read Write cycle times equal. control signals UBS# LBS# provide access upper data byte lower data byte. Table SRAM read write data byte control modes operation. SRAM Read SRAM Read operation SST34HF162x/164x controlled BES1#, both have with BES2 high system obtain data from outputs. BES1# BES2 used SRAM bank selection. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details. SRAM Write SRAM Write operation SST34HF162x/164x controlled BES1#, both have low, BES2 have high must high system write SRAM. During Word-Write operation, addresses data referenced rising edge either BES1#, BES2 WE#, whichever occurs first. write time measured from last falling edge first rising edge BES1#, BES2 WE#. Refer Write cycle timing diagram, Figures 5-6, further details.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers SuperFlash Memory (Bank RESET# BEF# LBS# UBS# BES1# BES2 CIOs RY/BY#
SuperFlash Memory (Bank Control Logic Buffers
DQ15
Address Buffers Most significant address
Mbit Mbit SRAM
B1.0
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
Bottom Sector Protection; KWord Blocks; KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH Block Block Block
Bank Bank
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
KWord Sector Protection (Four KWord Sectors)
001000H 000000H
Block
F02.0
FIGURE SST34HF1621 SST34HF1641, MEGABIT CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
Sector Protection; KWord Blocks; KWord Sectors
KWord Sector Protection (Four KWord Sectors)
FFFFFH FE000H F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 00FFFFH 000000H
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
Bank
F03.0
Bank
Block Block Block Block Block
FIGURE SST34HF1622 SST34HF1642, MEGABIT CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
VIEW (balls facing down)
DQ15 DQ14
DQ13 DQ12 VDDS CIOs VDDF DQ11
BES2 RST# RY/BY# LBS# UBS#
DQ10
BEF# BES1#
SST34HF162x/164x
F01.1
FIGURE ASSIGNMENTS 56-BALL LFBGA (8MM 10MM) TABLE DESCRIPTION Symbol Name Address Inputs DQ15-DQ0 Address Input (SRAM) Data Inputs/Outputs
BEF# BES1# BES2 UBS# LBS# CIOs RST# RY/BY# VDDF VDDS
Flash Memory Bank Enable SRAM Memory Bank Enable SRAM Memory Bank Enable Output Enable Write Enable Upper Byte Control (SRAM) Lower Byte Control (SRAM) Configuration (SRAM) Write Protect Reset Ready/Busy# Ground Power Supply (Flash) Power Supply (SRAM) Connection
Functions provide flash address, A19-A0. provide SRAM address, A16-A0 A17-A0 provide SRAM address input byte mode (x8) output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when BES# BEF# high. activate Flash memory bank when BEF# activate SRAM memory bank when BES1# activate SRAM memory bank when BES2 high gate data output buffers control Write operations enable DQ15-DQ8 enable DQ7-DQ0 CIOs Word mode (x16), CIOs Byte mode (x8) protect unprotect sectors from Erase Program operation Reset return device Read mode output status Program Erase operation 2.7-3.3V Power Supply Flash only 2.7-3.3V Power Supply SRAM only Unconnected pins
T2.0
Most Significant Address
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications TABLE OPERATIONAL MODES SELECTION Mode Full Standby Output Disable BEF# Flash Read Flash Write Flash Erase SRAM Read BES1# BES24 SRAM Write Product Identification2 DOUT HIGH-Z DOUT DOUT HIGH-Z DOUT DOUT HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DOUT CIOs1 LBS# UBS# HIGH-Z HIGH-Z HIGH-Z HIGH-Z DQ0-7 HIGH-Z DQ8-15 HIGH-Z
Manufacturer's Device
T2.0
Notes: SRAM configuration input CIOs; (word mode), (byte mode) Software mode only With Manufacturer's 00BFH, read with SST34HF1621/1622 Device 2761H, read with SST34HF1641/1642 Device 2762H, read with apply BEF# VIL, BES1# BES2 same time
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Write Cycle Write Cycle Addr1 Data1 Addr1 Data1 Write Cycle Write Cycle Addr1 Data1 Addr1 Data1 Write Cycle Write Cycle Addr1 Data1 Addr1 Data1 SAx2 BAx2 5555H
Word-Program 5555H 2AAAH 5555H Data Sector-Erase 5555H 2AAAH 5555H 5555H 2AAAH Block-Erase 5555H 2AAAH 5555H 5555H 2AAAH Chip-Erase 5555H 2AAAH 5555H 5555H 2AAAH Software 5555H 2AAAH 5555H Entry4, Query 5555H 2AAAH 5555H Entry5 Software Exit/ Exit Software Exit/ 5555H 2AAAH 5555H Exit Notes: Address format A14-A0 (Hex), Address A15-A19 "Don't Care" Command sequence. Data format DQ15-DQ8 "Don't Care" Command sequence. Sector-Erase; uses A19-A11 address lines Block-Erase; uses A19-A15 address lines Program word address Both Software Exit/CFI Exit operations equivalent DQ15 "Don't Care" Command sequence device does remain Software Product Identification Mode powered down.
T4.1
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications TABLE QUERY IDENTIFICATION STRING1 Address Data Data 0051H 0052H Query Unique ASCII string "QRY" 0059H 0001H Primary command 0007H 0000H Address Primary Extended Table 0000H 0000H Alternate command (00H none exists) 0000H 0000H Address Alternate extended Table (00H none exits) 0000H
Note: Refer publication more details.
T5.0
TABLE SYSTEM INTERFACE INFORMATION Address Data Data 0027H Min. (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts 0036H Max. (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts 0000H min. (00H pin) 0000H max. (00H pin) 0004H Typical time Word-Program 0000H Typical time min. size buffer program (00H supported) 0004H Typical time individual Sector/Block-Erase 0006H Typical time Chip-Erase 0001H Maximum time Word-Program times typical 0000H Maximum time buffer program times typical 0001H Maximum time individual Sector/Block-Erase times typical 0001H Maximum time Chip-Erase times typical
T6.0
TABLE DEVICE GEOMETRY INFORMATION Address Data Data 0015H Device size Byte (15H Bytes) 0001H Flash Device Interface description; 0001H x16-only asynchronous interface 0000H 0000H Maximum number byte multi-byte write (00H supported) 0000H 0002H Number Erase Sector/Block sizes supported device 00FFH Sector Information Number sectors; 256B sector size) 0003H 1023 1024 sectors (03FF 1023) 0008H 0000H Bytes KBytes/sector (0008H 001FH Block Information Number blocks; 256B block size) 0000H blocks (001F 0000H 0001H Bytes KBytes/block (0100H 256)
T7.0 2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V 0.5V Transient Voltage (<20 Ground Potential -1.0V 1.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current OPERATING RANGE Range Ambient Temp Commercial Extended CONDITIONS TEST 2.7-3.3V 2.7-3.3V Input Rise/Fall Time Output Load Figures
TABLE OPERATING CHARACTERISTICS (VDD VDDF VDDS 2.7-3.3V) Limits Symbol Parameter Units Test Conditions Power Supply Current Read Flash SRAM Concurrent Operation Write Flash SRAM Standby Current 3.0V 3.3V Auto Power Mode 3.0V 3.3V Reset Current Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) VDD-0.3 Output Voltage Output High Voltage VDD-0.2 Max, open, Address input VIL/VIH, f=1/TRC Min. VIL, BEF# VIL, BES# BEF# VIH, BES# BEF# VIH, BES# VIH, BEF# VIL, BES# BEF# VIH, BES# Max. BEF# BES# VIHC Max. BEF# VILC, VILC/VIHC Reset 0.3V =GND VDD, Max. VOUT =GND VDD, Max. Min. Max. Max. Max. Min. -100µA, Min.
T8.2
VILC VIHC
Note: VDDF VDDS
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ TPU-WRITE Power-up Read Operation Power-up Write Operation Minimum Units
T9.0
T10.0
TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition CI/O CIN1
Maximum
Capacitance Input Capacitance
VI/O
TABLE FLASH RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification NEND1 TDR1 VZAP_HBM1 VZAP_MM1 ILTH1 Endurance Flash Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch 10,000 2000
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T11.0
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications CHARACTERISTICS TABLE SRAM READ CYCLE TIMING PARAMETERS Symbol Parameter TRCS Read Cycle Time Address Access Time TAAS TBES Bank Enable Access Time TOES Output Enable Access Time TBYES UBS#, LBS# Access Time BES# Active Output TBLZS TOLZS1 Output Enable Active Output TBYLZS UBS#, LBS# Active Output TBHZS BES# High-Z Output TOHZS1 Output Disable High-Z Output TBYHZS UBS#, LBS# High-Z Output TOHS Output Hold from Address Change
Unit
T12.0
Note: This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM WRITE CYCLE TIMING PARAMETERS Symbol Parameter TWCS Write Cycle Time TBWS Bank Enable End-of-Write TAWS Address Valid End-of-Write TASTS Address Set-up Time TWPS Write Pulse Width TWRS Write Recovery Time TBYWS UBS#, LBS# End-of-Write TODWS Output Disable from TOEWS Output Enable from High TDSS Data Set-up Time TDHS Data Hold from Write Time
Unit
T13.0
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications CHARACTERISTICS TABLE FLASH READ CYCLE TIMING PARAMETERS 2.7-3.3V SST34HF162x/164x-70 Symbol Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time TCLZ BEF# Active Output Active Output TOLZ1 TCHZ BEF# High High-Z Output TOHZ1 High High-Z Output Output Hold from Address Change RST# Pulse Width TRHR1 RST# High Before Read RST# Read
SST34HF162x/164x-90
Units
T14.1
TABLE FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Word-Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time TOES High Setup Time TOEH High Hold Time BEF# Pulse Width Pulse Width TWPH Pulse Width High TCPH BEF# Pulse Width High Data Setup Time Data Hold Time TIDA Software Access Exit Time RY/BY# Delay Time RY/BY# Recovery Time Sector-Erase Block-Erase TSCE Chip-Erase
Units
T15.0
Note: This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase Program operations. This parameter does apply Chip-Erase. RY/BY# open drain output, 10KW 100KW pull-up resistor required allow RY/BY# transition high indicating device ready read.
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
TRCS ADDRESSES AMSS-0 TAAS BES1# TBES TOHS
BES2
TBES TBLZS TBHZS TOES TOLZS TOHZS TBYES TBYLZS TBYHZS DATA VALID
F15.0
UBS#, LBS#
DQ15-0
AMSS Most Significant SRAM Address
FIGURE SRAM READ CYCLE TIMING DIAGRAM
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
TWCS ADDRESSES AMSS-0 TASTS TWPS TWRS
TBWS
TAWS TBWS BES1#
BES2
TDSS TOEWS TDHS NOTE
TBYWS UBS#, LBS# TODWS DQ15-8, DQ7-0 NOTE
VALID DATA
F16.1 Notes: High during Write cycle, outputs will remain high impedance. BES# goes coincident with after goes Low, output will remain high impedance. BES# goes High coincident with before goes High, output will remain high impedance. Because signals output state this time, input signals reverse polarity must applied.
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
TWCS ADDRESSES AMSS-0 TWPS TWRS
TBWS BES1#
BES2
TBWS TAWS TASTS TBYWS
UBS#, LBS# TDSS DQ15-8, DQ7-0 NOTE TDHS NOTE
F18.0
VALID DATA
Notes: High during Write cycle, outputs will remain high impedance. Because signals output state this time, input signals reverse polarity must applied.
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
ADDRESS A19-0
BEF#
DATA VALID TCHZ HIGH-Z DATA VALID
F04.0
TOLZ
TOHZ
DQ15-0
HIGH-Z
TCLZ
FIGURE FLASH READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS A19-0 5555 BEF# RY/BY# TWPH 2AAA 5555 ADDR
DQ15-0
XXAA
XX55
XXA0
DATA WORD (ADDR/DATA)
F05.0
FIGURE FLASH CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS ADDRESS A19-0 5555 BEF# RY/BY# DQ15-0 TCPH 2AAA 5555 ADDR
XXAA
XX55
XXA0
DATA WORD (ADDR/DATA)
F06.0
FIGURE FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A19-0 BEF# TOEH RY/BY# TOES
DATA
DATA#
DATA#
DATA
F07.0
FIGURE FLASH DATA# POLLING TIMING DIAGRAM
2001 Silicon Storage Technology, Inc. S71172 523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
ADDRESS A19-0 BEF# TOEH TOES
READ CYCLES WITH SAME OUTPUTS F08.0
RY/BY#
FIGURE FLASH TOGGLE TIMING DIAGRAM
SIX-BYTE CODE CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
BEF#
RY/BY# DQ7-0
F09.1
Note: This device also supports BEF# controlled Chip-Erase operation. BEF# signals interchageable long minimum timings met. (See Table
FIGURE FLASH CONTROLLED CHIP-ERASE TIMING DIAGRAM
2001 Silicon Storage Technology, Inc. S71172 523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
SIX-BYTE CODE BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA
BEF#
RY/BY#
DQ7-0
F10.1
Note: This device also supports BEF# controlled Block-Erase operation. BEF# signals interchageable long minimum timings met. (See Table Block Address
FIGURE FLASH CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA
BEF#
RY/BY# DQ7-0
F11.1
Note: This device also supports BEF# controlled Sector-Erase operation. BEF# signals interchageable long minimum timings met. (See Table Sector Address
FIGURE FLASH CONTROLLED SECTOR-ERASE TIMING DIAGRAM
2001 Silicon Storage Technology, Inc. S71172 523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
TIDA
BEF#
TWPH DQ15-0 XXAA XX55 XX90
F12.1
00BF
Device
Device
2761H SST34HF1621 2762H SST34HF1622 2761H SST34HF1641 2762H SST34HF1642
FIGURE FLASH SOFTWARE ENTRY READ
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
BEF#
TWPH DQ15-0 XXAA XX55 XX98
F13.0
TIDA
FIGURE FLASH ENTRY READ
2001 Silicon Storage Technology, Inc. S71172 523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
TIDA
BEF#
F14.0
FIGURE FLASH SOFTWARE EXIT/CFI EXIT
RST#
OE#/CE# TRHR
F28.0
FIGURE 18A: SYSTEM POWER-UP TIMING DIAGRAM
BEF#/OE# TRHR RST# RY/BY#
F25.1
FIGURE 18B: RST# TIMING DIAGRAM
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F19.0
TESTER
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Inputs rise fall times (10% 90%)
Note: VOT-VOUTPUT Test VIT-VINPUT Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
F20.0
FIGURE TEST LOAD EXAMPLE
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
F21.2
FIGURE WORD-PROGRAM ALGORITHM
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match?
Program/Erase Completed
Program/Erase Completed
F22.0
FIGURE WAIT OPTIONS
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
Query Entry Command Sequence
Software Product Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXF0H Address:
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Wait TIDA
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
F23.1
FIGURE SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H Load data: XX30H Address: Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
F24.1
FIGURE ERASE COMMAND SEQUENCE
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST34HF16xx Package Modifier pins Package Type LFBGA (8mm 10mm) Temperature Range Commercial 70°C Extendedl -20° 85°C Minimum Endurance 10,000 cycles Read Access Speed Bank Split SRAM Density Mbit Mbit Flash Density Mbit Voltage 2.7-3.3V Device Family
SST34HF1621 Valid combinations SST34HF1621-70-4C-LFP SST34HF1621-90-4C-LFP SST34HF1621-70-4E-LFP SST34HF1621-90-4E-LFP SST34HF1622 Valid combinations SST34HF1622-70-4C-LFP SST34HF1622-90-4C-LFP SST34HF1622-70-4E-LFP SST34HF1622-90-4E-LFP SST34HF1641 Valid combinations SST34HF1641-70-4C-LFP SST34HF1641-90-4C-LFP SST34HF1641-70-4E-LFP SST34HF1641-90-4E-LFP SST34HF1642 Valid combinations SST34HF1642-70-4C-LFP SST34HF1642-90-4C-LFP SST34HF1642-70-4E-LFP SST34HF1642-90-4E-LFP
Example: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications PACKAGING DIAGRAMS
VIEW BOTTOM VIEW
10.00 0.20 5.60 0.80 0.05 (56x)
CORNER
8.00 0.20 5.60 0.80
CORNER
1.30 0.10
SIDE VIEW
SEATING PLANE 0.32 0.05
0.15
56ba LFBGA.LFP-8x10-ILL.5
Note:
Complies with general requirements JEDEC publication MO-210, although some dimensions more stringent. (This specific outline variant been registered) linear dimensions millimeters (min/max). Coplanarity: (±.05) actual shape corners different than portrayed drawing.
56-BALL PROFILE, FINE PITCH BALL GRID ARRAY (LFBGA) 10MM PACKAGE CODE:
POSSIBLE BALL POSTIONS)
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
Mbit Concurrent SuperFlash Mbit Mbit SRAM SST34HF162x SST34HF164x
Preliminary Specifications
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com
2001 Silicon Storage Technology, Inc.
S71172
523-2 1/01
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