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L64360 ATMizerArchitecture Technical Manual
This document preliminary. such, contains data derived from functional simulations performance estimates. Logic verified either functional descriptions, electrical mechanical specifications using production parts. Document MN71-000101-99 First Edition (February 1995) This document applies Revision L64360 ATMizerArchitecture subsequent versions unless otherwise indicated subsequent edition update this edition document. Publications stocked address given below. Requests should addressed Logic Corporation Literature Distribution, D-102 1551 McCarthy Boulevard Milpitas, 95035 Fax: 408.433.8989 Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. Copyright 1995 Logic Corporation. rights reserved. TRADEMARK ACKNOWLEDGMENT Logic logo design registered trademark ATMizer Self-Embedding trademarks Logic Corporation. other brand product names trademarks their respective companies.
Preface
This book primary reference technical manual L64360 chip ATMizer Architecture upon which based. contains complete functional description L64360 ATMizer Architecture includes complete physical electrical specifications L64360. Audience This book assumes that reader some familiarity with microprocessors related support devices. This book written for:
Engineers managers evaluating L64360 ATMizer
Architecture possible system
Engineers designing L64360 ATMizer Architecture into
system Organization This book following chapters appendices:
Chapter Introduction, provides overview ATMizer Architec-
ture, describes some ATMizer Architecture applications, lists ATMizer Architecture's features.
Chapter Functional Overview, provides functional overview
ATMizer Architecture L64360 implementation.
Chapter Signal Descriptions, describes signals that comprise bit-
level interface L64360.
Chapter ATMizer Processing Unit (APU) Prefetch Buffer,
describes function operation ATMizer Processing Unit Prefetch Buffer.
Chapter Instruction (IRAM) Serial Interface, describes
function operation Serial Interface load Instruction RAM.
Chapter Virtual Channel (VCR), describes function
operation Virtual Channel RAM.
Preface
Chapter Pacing Rate Unit (PRU), describes function operation
Pacing Rate Unit.
Chapter Controller (DMAC), describes function opera-
tion Controller, which contained within Host/DMA Port.
Chapter ACell Interface (ACI), describes function opera-
tion ACell Interface.
Chapter Secondary Port (SP), describes function operation
Secondary Port.
Chapter System Mapping, describes ATMizer Architecture system
hardware map.
Chapter Operation, describes ATMizer Architecture operation. Chapter Functional Waveforms, contains describes ATMizer
Architecture functional waveforms.
Chapter Registers, describes summarizes ATMizer Archi-
tecture registers.
Chapter Specifications, describes electrical mechanical charac-
teristics L64360.
Appendix Glossary Abbreviations, provides glossary abbrevia-
tions that used this manual.
Appendix Customer Feedback, provides form that
Logic your comments content quality this manual. Related Publications CW33300 Enhanced Self-EmbeddingProcessor Core User's Manual, Order C14014 LR33300 LR33310 Self-EmbeddingProcessors User's Manual, Order J14028 Conventions Used this Manual first time word phrase defined this manual, italicized. following signal naming conventions used throughout this manual:
level-significant signal that true valid when signal
always overbar
over name. over name.
edge-significant signal that initiates actions HIGH-to-LOW transi-
tion always overbar
word assert means drive signal true active. word deassert means drive signal false inactive.
Preface
Hexadecimal numbers indicated prefix "0x" before number-for example, 0x32CF. Binary numbers indicated subscripted following number-for example, 0011.0010.1100.11112.
Preface
Preface
Contents
Chapter
Introduction Overview Features General Features AAdaptation Layer Features ALayer Features ACell Interface (ACI) Features Diagnostic Support Features Applications Scatter-Gather Application Acceleration Cell Switching Congestion Control Realtime Data Streams Diagnostic Operation Functional Overview Overview Functional Blocks Buses Signal Descriptions L64360 Logic Symbol Host/DMA Port Transmitter Receiver Secondary Port Interrupt/Messaging Serial Interface Miscellaneous Operation
1-10 1-10 1-10
Chapter
Chapter
3-10 3-11 3-12
Contents
Chapter
ATMizer Processing Unit (APU) Prefetch Buffer Overview Header Trailer Generation Retrieval Pacing Rate Unit (PRU) Configuration Cell Queuing Cell Processing Memory Allocation ATMizer Architecture-to-Host Messaging Atomic Transactions Host/DMA Port Priority 4.10 Congestion Control 4.11 External Access 4.12 Prefetch Buffer Instruction (IRAM) Serial Interface Overview Serial Downloading Serial Interface Data Addressing Multiple Downloading ATMizer Booting Loading Code into IRAM Example Software Virtual Channel (VCR) Overview Storing Cells Incoming Cells Outgoing Cells Storing Channel Parameter Entries (CPEs) Channel Parameter Entries Channel Groups Cell Multiplexing Demultiplexing Partitioning Examples Pacing Rate Unit (PRU) Overview Peak Rate Pacing Counters (PRPCs) Channel Group Credit Register (CGCR)
Chapter
Chapter
Chapter
viii
Contents
Chapter
Count Initialization Register (CIR) Configuration Register (CR) Stall Register (SR) Cell Rate Pacing Peak Rate Pacing Burst Length Average Pacing Channel Priority
Controller (DMAC) Overview Registers DMAC Control Register's Effective Address DMAC Control Register CRC32 Register Programming DMAC Cell Switching, Segmentation, Reassembly Reassembly Cell Switching Segmentation Cell Switching CRC32 Generation Misaligned Operations Scatter Gather Operations Operation Completion Branch Coprocessor Condition True Interrupt ACell Interface (ACI) Overview ACell Size Frequency Decoupling Transmitter Transmitter Cell Sources Queuing Cell Transmission Cell Rate Decoupling Preparation Transmission Receiver Received Cell Handling Options Received Cell Indication Receiver Reset
8-10 8-11 8-14 8-14 8-15 8-15
Chapter
9-12
Contents
Traffic Shaping Generation Checking CRC10 Generation Error Checking Interfaces UTOPIA
9-12 9-14 9-14 9-16 9-16 9-18
Chapter
Secondary Port (SP) 10.1 Overview 10.2 Operation Instruction Fetch Single Load/Store Block Fetch Byte Device Access (Boot PROM) 10.3 Address Data (SP_AD[31:0]) 10.4 Hardware Design System Mapping 11.1 Memory Maps Internal Memory External Memory System Memory Summary 11.2 Interrupts 11.3 Coprocessor Condition (CpCond) Connections Operation 12.1 Programming ATMizer Architecture 12.2 Theory Operation Reassembly Segmentation 12.3 Initializing 12.4 ATMizer Architecture Operation Data Types Supported Cell Generation CS-PDU Reassembly Process 12.5 Congestion Notification Handling 12.6 Initializing Internal Registers
10-1 10-2 10-2 10-2 10-3 10-3 10-3 10-6
Chapter
11-1 11-1 11-5 11-7 11-8 11-8
Chapter
12-1 12-2 12-3 12-6 12-8 12-13 12-14 12-15 12-23 12-25 12-26
Contents
Chapter
Functional Waveforms 13.1 Secondary Port 13.2 Host/DMA Port 13.3 Serial Interface 13.4 Transmitter 13.5 Receiver Registers 14.1 System Control Register 14.2 Core Registers BIU/Cache Configuration Register Status Register Status Register Mode Bits Exception Processing Cause Register Address Register Target Address Register Exception Program Counter Register Processor Revision Identifier Register Debug Cache Invalidate Control Register Breakpoint Program Counter Register Breakpoint Program Counter Mask Register Breakpoint Data Address Register Breakpoint Data Address Mask Register 14.3 Other Registers Summary Host Interrupt Register Substitution Register Channel Group Credit Register 12-Bit Count Initialization Registers 24-Bit Count Initialization Registers Configuration Register Stall Register DMAC Control Register CRC32 Register Current Received Cell Address Register Received Cell Indicator Register Global Pacing Rate Register
13-1 13-5 13-12 13-15 13-17
Chapter
14-1 14-6 14-7 14-9 14-12 14-13 14-14 14-15 14-15 14-16 14-16 14-19 14-19 14-20 14-20 14-20 14-20 14-21 14-21 14-21 14-21 14-22 14-22 14-23 14-23 14-23 14-24 14-24
Contents
Chapter
Specifications 15.1 Timing 15.2 Electrical Requirements 15.3 Summary 15.4 Pinout, List, Package Information Glossary Abbreviations Customer Feedback
15-1 15-10 15-12 15-13
Appendix Appendix Figures
ATMizer Architecture Supported B-ISDN Layers ATMizer Architecture with Support Logic Network Interface Card with Local Memory ATMizer Architecture Functional Block Diagram L64360 Logic Symbol Substitution Register Host/DMA Port Address Byte Enables Formation Effective Address DMA/Host Port Access Cacheable Effective Address DMA/Host Port Access Non-cacheable Effective Address Secondary Port Access Cacheable Effective Address Secondary Port Access Non-cacheable Serial Downloading Example Software Structures Partitioning Partitioning Router Channel Group Credit Register 12-Bit Count Initialization Register 24-Bit Count Initialization Register Configuration Register Stall Register DMAC Control Register's Effective Address DMAC Control Register CRC32 Register CS-PDU Main Memory Cell Holder Addresses Transmitter Receiver Block Diagram Current Received Cell Address Register
9-10
Contents
10.1 10.2 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 13.14 13.15 13.16 13.17 13.18 13.19 14.1 14.2 14.3
Global Pacing Rate Register Maximum Line Utilization Rate (Count Assigned Cells) Maximum Line Utilization Rate (Count Assigned Cells) UTOPIA Connection ATMizer Architecture ATMizer Architecture-to- Device Connections SP_AD[31:0] Effective Address Idle Loop Reassembly Routine Segmentation Routine ATMizer Architecture Example Circuit Emulation Data Buffering CS-PDU Segmentation CS-PDU Segmentation Cell Generation Data Path Secondary Port One-Word Read Write Secondary Port Fastest Access Secondary Port Four-Word Read Secondary Port Four-Word Read with SP_ASEL Toggle Dynamic Sizing Secondary Port Direct Load/Store Word Through Port 16-Byte Transactions Non-Word-Aligned 16-Byte Transactions Block Fetch followed Single-Word Store 16-Byte Transaction with Steal Cycle Host/DMA Port Operation with HBS_AOE, HBS_DOE Toggle HBS_AS Save Cycle Serial Downloading Less Than Kwords Completion 4-Kword Serial Downloading Multiple Serial Downloading Transmitter Initialization Assigned Cell Transmission TX_FULL Assertion Receiver Initialization Receiver HEC_ERR RC_FULL Assertion System Control Register Status Register Exception Recognition Restoring from Exceptions
9-13 9-13 9-13 9-18 9-19 10-3 10-5 12-2 12-5 12-7 12-14 12-16 12-17 12-18 12-22 13-2 13-3 13-4 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-13 13-13 13-14 13-15 13-16 13-17 13-18 13-19 14-1 14-12 14-13
Contents
xiii
14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 14.12 14.13 14.14 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 Tables 11.1
Substitution Register Channel Group Credit Register 12-Bit Count Initialization Register 24-Bit Count Initialization Register Configuration Register Stall Register DMAC Control Register DMAC Control Register's Effective Address CRC32 Register Current Received Cell Address Register Global Pacing Rate Register Test Load Waveform Standard Outputs Test Load Waveform 3-State Outputs Secondary Port Timing Host/DMA Port Timing Host/DMA Port Timing Transmitting Cell Timing Transmitter TX_IDLE Timing Received Cell Timing Receiver RC_FULL Timing 208-Pin MQUAD Pinout Cavity Down 208-Pin MQUAD Mechanical Drawing Two-word Block Fetch Address Offset Four-word Block Fetch Address Offset Serial Interface Data Addressing through Secondary Port Serial Interface Data Addressing through Host/DMA Port CS-PDU Segmentation CS-PDU Reassembly Effective Address Bits [5:0] Selection PRPC Grouping Field Settings First Cell Field Settings First Five Bytes Second Cell Field Settings Remaining Bytes Second Cell Field Settings Final Cell Starting Address Offset Byte Count Internal Memory
14-21 14-21 14-21 14-22 14-22 14-22 14-23 14-23 14-23 14-24 14-24 15-2 15-2 15-6 15-7 15-8 15-9 15-9 15-10 15-10 15-14 15-16 4-10 4-10 8-11 8-12 8-12 8-12 8-13 11-2
Contents
11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8
PRPC Initialization Content Register Selection CRC10 Generation Control Error Control Control Register's Effective Address Fields Operation Direction (RD) Ghost Settings External Memory System Memory Summary Interrupts CpCond Definitions Timing Values 70-pF Loading Absolute Maximum Ratings Recommended Operating Conditions Worst Case Thermal Operating Conditions Capacitance Characteristics L64360 Description Summary L64360 List Abbreviation Glossary
11-3 11-3 11-3 11-4 11-5 11-6 11-7 11-8 11-9 15-3 15-11 15-11 15-11 15-11 15-11 15-12 15-15
Contents
Contents
Chapter Introduction
This chapter provides overview lists features ATMizer Architecture L64360 chip. This chapter three sections:
Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "Applications"
Overview
ATMizer Architecture from Logic provides powerful, flexible solution Asynchronous Transfer Mode (ATM) network control. ATMizer Architecture group carefully chosen hardware functional blocks that provide complete control over ASegmentation Reassembly (SAR) ALayer operations. architecture also includes AProcessing Unit (APU), 32-bit RISC (based Logic's MIPS R3000 architecture), which, through user firmware, controls functional blocks. This combination hardware function software control allows user dynamically solve ANetworking problem. ATMizer Architecture enables market leaders deploy unique Aproducts today, while working with standard evolves. on-chip processing power allows users simply download code accommodate changes Astandards congestion control algorithms. ATMizer Architecture either embedded Customer Specific Integrated Circuits (CSICs) Application Specific Standard Products (ASSPs), used stand-alone L64360 chip. ATMizer Architecture also perform management Convergence Sublayer-Protocol Data Unit (CS-PDU) link lists (lists CS-PDUs need segmentation), cell switching, scatter-gather DMA, memory buffers scatter-gather implementations), Aheader manipulation, traffic
shaping, congestion control, error monitoring, statistics gathering, host messaging, diagnostics, Virtual Channel Identifier (VCI) translation, Virtual Path Identifier (VPI) translation. also transmit receive various cell sizes, which enables users differentiate system cell structures. addition, perform Operation Management (OAM) functions supported layers firmware. ATMizer Architecture handles Broadband-Integrated Service Digital Network (B-ISDN) layers highlighted Figure 1.1.
Figure ATMizer Architecture Supported B-ISDN Layers
AAdaptation Layer (AAL) Convergence Sublayer CRC32 Generation Checking Segmentation Reassembly (SAR) Sublayer Type Constant Rate Type Variable Rate Type Variable Rate ALayer Cell Multiplexing Demultiplexing Generic Flow Control Cell Header Generation Extraction Cell Rate Pacing Cell Transmission Exceeding Pacing Rate Delay Priority Processing Cell Loss Priority Marking, Cell Loss Priority Reduction Explicit Forward Congestion Indication Higher Layers Cell Payload Type Marking, Differentiations Cell Relaying Cell VPI/VCI Translation Peak Rate Enforcement Physical Layer Transmission Convergence Sublayer Generation Cell Delineation Cell Rate Decoupling Transmission Frame Adaptation Transmission Frame Generation Recovery Physical Medium Sublayer Timing, Physical Medium Host
Operation Management (OAM) Functionality
ATMizer Architecture
Transmission Convergence Sublayer
supporting AALs 3/4, ATMizer process Virtual Channels (VCs) voice, data video simultaneously. This combination maximum support, programmability, simultaneous
Introduction
support data types provides unmatched flexibility emerging Astandard. Figure shows typical ATMizer Architecture with supporting logic.
Figure ATMizer Architecture with Support Logic
Optional Local Memory Host
Host
Secondary Port
Physical Layer Chip
ATMizer Cell Interface (ACI)
ATMizer Architecture
Host/ Port Shared Memory (Contains CS-PDUs)
Serial Interface
Serial PROM
embedded enables customers immediately realize Atermination single device, subsequently update signaling, congestion, traffic management algorithms firmware Astandard evolves. executing realtime instructions from internal instruction RAM, intelligent also enables Asystems respond immediately network congestion without Host intervention. ATMizer Architecture couples flexibility microprocessor with economies single-chip solution, enabling users differentiate their products both hardware software. ATMizer Architecture dramatically improves price/performance over alternative solutions incorporating wide range system-level capabilities single chip, including:
eight-byte buffer transmitter receiver eliminate need buffers when interfacing Physical Layer
Overview
4-Kbyte Virtual Channel provide additional cell buffering minimize external memory requirements powerful 32-bit scatter-gather engine that handles contiguous noncontiguous CS-PDU protocols better utilization system memory Secondary Port access external memory-mapped devices Channel Parameters when engine busy prefetch buffers
ATMizer Architecture also provides generic physical interface compatible with most physical interfaces, including proposed UTOPIA Interface through eight-bit parallel cell interface. Host/DMA Port provides 32-bit VLBus-like interface from on-chip linked-list Direct Memory Access Controller (DMAC). Features ATMizer Architecture features have been divided into five sections:
General Features AAdaptation Layer Features ALayer Features ACell Interface (ACI) Features Diagnostic Support Features
General Features
ATMizer Architecture general features are:
Supports Adata rates 155.52 Mbits/second Simultaneously supports AAdaptation Layers 3/4, Handles contiguous non-contiguous CS-PDUs 32-bit addressing capabilities 32-bit data interfacing capabilities Implements Peak Rate Pacing, Maximum Burst Length, Global Pacing aggregate traffic shaping Supports 65536 Supports simultaneous segmentation reassembly some while cell switching others
Introduction
Implements user-programmable 32-bit MIPS RISC (ATMizer Processing Unit) controls aspects Acell generation switching processes controls: Scatter-gather Algorithms SAR-PDU Header Trailer Generation AHeader Generation Manipulation Host Interrupt/Messaging Error Handling Congestion Control Statistics Gathering Diagnostic Operation User-defined Functions
Internal caching data structures, buffer link lists, messages 4-Kbyte Virtual Channel (VCR), coupled with received cell buffers, allows development memory-less network interface cards (all CS-PDUs undergoing segmentation reassembly reside system memory) General purpose 32-bit (address/data multiplexed) Secondary Port Interface with 4-Mbyte address space Four-word Prefetch Buffer Four-word Write Buffer Supports atomic (read-modify-write) transactions Host/DMA Port steal cycle Direct connection Universal Test Operations Cell-based Physical layer (PHY) Interface A(UTOPIA) Standard AInterface (SAI) Supports cell size transformation application that converts standard Acell into switch specific format
Features
AAdaptation Layer Features
AAdaptation Layer features are:
cell generation from realtime data-streams including Header generation Residual Time Stamp Insertion Supports simultaneous segmentation reassembly 3/4, CS-PDUs, cell generation from realtime datastreams Scatter-gather capabilities reassembly segmentation (implemented user firmware) CS-PDUs need contiguous system memory which allows efficient memory space, higher throughput moves necessary form contiguous CS-PDUs), latency attributable devices such routers
Higher-layer header extraction data alignment capabilities application acceleration CRC10 generation checking SAR-PDUs CRC32 generation checking CS-PDUs segmentation reassembly
ALayer Features
ALayer features are:
AHeader generation manipulation Support VCI/VPI translation cell switching Support user-defined cell size bytes allow prepending switch-specific header Peak Rate Pacing Counters Advanced congestion control capabilities User firmware specified congestion control algorithms provide immediate reaction congestion notification. Fast response (within cell time) results fewer cells sent into congested network, minimizing cell loss CS-PDU retransmissions resulting higher overall throughput. Congestion control routines part user firmware modified more learned about congestion actual Anetworks.
Cell Loss Priority marking manipulation (with HighMedium-Low Priority CS-PDU support)
Introduction
ACell Interface (ACI) Features
ACell Interface (ACI) features are:
Frequency decoupling logic Eight-bit parallel transmit-data output Eight-bit parallel receive-data input Eight-byte buffers transmitter receiver that allows direct connection data output input buses transceivers external buffering required) Global Pacing Rate Register that allows percentage Idle Cells sent over ACI, which enables aggregate traffic shaping quick reducing data speeds upon congestion notification. system gradually return full speed operation under control. buffering metastability issues dealt with inside ATMizer Architecture Automatic Cell Rate Decoupling through Idle Cell insertion Separate transmitter receiver data transfer acknowledgment input signals provide operation with free running transmitter receiver clocks (allows connection Transmission Convergence Sublayer framing logic that requires gaps assigned cell stream insertion/extraction framing overhead) Internal received cell buffers cells) second layer buffering between main memory This buffering allows ATMizer Architecture absorb periods high latency main memory long exception handling routines without losing received cells. This especially important memoryless network add-in cards Workstations where computer's main memory ATMizer Architecture's working memory space.
Conformance UTOPIA proposed standard (Version 1.22) Programmable Header Error Control (HEC) generation checking
Features
Diagnostic Support Features
diagnostic support features are:
User firmware controlled statistics gathering capabilities (keeps track statistics application network management architecture requires) CRC10 CRC32 error statistics gathering CRC32 errors forced diagnostic purposes Diagnostic firmware downloaded system level diagnostics when troubleshooting system line failures
Applications
Figure shows possible application L64360, network interface card with local memory. sections following figure discuss Anetwork issues:
Scatter-Gather Application Acceleration Cell Switching Congestion Control Realtime Data Streams Diagnostic Operation
Figure Network Interface Card with Local Memory
Optional Control Logic Transmission Lines Host/ L64360 Port Framing Logic Transceiver
Host
Connected
Introduction
Scatter-Gather
execute segmentation reassembly routines written system designer that perform scatter (segmentation) gather (reassembly) noncontiguous data structures (data structures that logically form single CS-PDU) done Scatter-Gather controller. user supply routines that handle AAdaptation Layer (AAL) Aheader generation extraction well link-list pointer management buffer allocation. Some applications accelerated header stripping data alignment. ATMizer Architecture network software stripping higher-layer headers from incoming CS-PDUs placing them specific memory locations. addition, ATMizer Architecture utilize powerful byte-alignment capabilities Controller ensure that user-data payload portion higher-layer written into memory word-aligned. This procedure releases application-layer software from responsibility ensuring proper data alignment. ATMizer Architecture allows terminate Virtual Channels (VCs) terminate some while switching others. per-VC basis make determination whether should reassemble Segmentation Reassembly (SAR) User-Payload into CS-PDU simply pass entire cell, headers trailers intact, some other memory-mapped Aport Aswitch interface. ATMizer Architecture even switch cells between receiver transmitter without touching system memory. This implementation structure ring, dual, triple-port switching fabrics, other topologies. make cell-switching decisions (whether translate VCI, VPI, both, neither, whether multicast expansion) realtime then perform operations. Furthermore, switching applications, ATMizer Architecture support user cell size bytes, which allows user include bytes switch-specific information each cell.
Application Acceleration
Cell Switching
Applications
Congestion Control
seen enough Anetworks operation gain real understanding Anetwork congestion. industry moves ahead with ATM, reassuring note that ATMizer Architecture, with user programmable positioned directly Aline interface, capable executing facilitating almost congestion control algorithm imaginable. because user firmware downloaded system reset, systems field updated with congestion control algorithms more learned about congestion real Anetworks. ATMizer Architecture also offers fast congestion response time. Cells arriving with notification network congestion affect transmission very next cell, either inhibiting altogether, slowing down rate transmission assigned cells, forcing Cell Loss Priority (CLP) reductions. user provides algorithm. ATMizer Architecture provides hardware pacing logic, aggregate traffic shaping capability, processor execute algorithm.
Realtime Data Streams
performs realtime data stream buffer (DS1, voice, video, etc.) transfers (limits Adata rates apply). Segmentation Reassembly (SAR) Header requires Residual Time Stamp (RTS). segmentation routine running access values from memory-mapped device location carefully interleave value into headers cell stream. When value needed, retrieves When sequence numbers sequence number protection called for, generates inserts appropriate information into Header. reassembly, will verify sequence number integrity sequentially pass value appropriate device. ATMizer Architecture actively participate diagnostic operations forcing CRC32 errors, gathering line statistics, user defined operations. under normal operating conditions, chartered with additional task statistics gathering network management process. these operations made possible inclusion user-programmable APU.
Diagnostic Operation
1-10
Introduction
Chapter Functional Overview
This chapter provides functional overview ATMizer Architecture L64360 chip. This chapter three sections:
Section 2.1, "Overview" Section 2.2, "Functional Blocks" Section 2.3, "Buses"
Overview
ATMizer Architecture provides Asystem designers with segmentation reassembly architecture that can, through user firmware control, implement Aend stations switching stations number different ways. ATMizer Architecture provides number critical hardware functions that controlled firmware that user downloads ATMizer Architecture system reset time. ATMizer Architecture contains following functional blocks:
Functional Blocks
ATMizer Processing Unit (APU) Prefetch Buffer Instruction (IRAM) Serial Interface Virtual Channel (VCR) Pacing Rate Unit (PRU) Controller (DMAC) ACell Interface (ACI) Secondary Port (SP)
Figure 2.1, ATMizer Architecture functional block diagram, shows relationship buses hardware functions that firmware controls
within ATMizer Architecture. Chapters through provide further description these functional blocks.
Figure ATMizer Architecture Functional Block Diagram
Address Byte Enables Data
Address/Data Secondary Port (SP)
External Access
Host/DMA Port with Controller (DMAC) CRC32 Generator Serial Interface
DMA-VCR
Transmit Cell Builders Receive Cell Holders
Virtual Channel (VCR)
Transmit Receive Virtual Channel Parameters
Prefetch Buffer Instruction Instruction (IRAM)
Pacing Rate Unit (PRU)
Data ATMizer Processing Unit (APU)
ACell Interface (ACI) (HEC CRC10)
Internal Access Data/Instruction Received Cell Indication
ATMizer Architecture
Buses
ATMizer Architecture contains following four buses that provide powerful solutions many Aapplications:
DMA-VCR
Functional Overview
DMA-VCR dedicated 32-bit data 12-bit address connection from Controller read/write ports VCR.
Internal Access Internal Access connects internal devices such registers, VCR, Prefetch Buffer APU. Internal Access shares second Port with ACI. Since Internal Access separate from DMA-VCR Bus, access internal registers while active.
External Access External Access enables perform direct load store operations from external devices. load store from Secondary Port done while active. example, program Controller during segmentation bring 48-byte SAR-PDU immediately after programming Register load store from Secondary Port.
Instruction Instruction enables perform instruction fetches from IRAM. also execute instructions from external devices firmware exceeds Kword.
Buses
Functional Overview
Chapter Signal Descriptions
This chapter describes signals that comprise bit-level interface L64360 chip. This chapter eight sections:
Section 3.1, "L64360 Logic Symbol" Section 3.2, "Host/DMA Port" Section 3.3, "ACI Transmitter" Section 3.4, "ACI Receiver" Section 3.5, "Secondary Port" Section 3.6, "Interrupt/Messaging" Section 3.7, "Serial Interface" Section 3.8, "Miscellaneous Operation"
L64360 Logic Symbol
Figure shows L64360 signals, their direction, their polarity.
Figure L64360 Logic Symbol
HBS_A[31:2] HBS_ACK HBS_AOE HBS_AS HBS_BE[3:0] HBS_BOOT HBS_D[31:0] HBS_DOE HBS_END HBS_GNT HBS_RQ HBS_S[2:0] HBS_WR SP_ACK SP_AD[31:0] SP_ASEL SP_BWIDE SP_GNT SP_RQ SP_WR GPINT_AUTO GPINT_TST HBS_INT
Transmitter Host/DMA Port
TX_ACK TX_BOC TX_CLK TX_D[7:0] TX_DRDY TX_FULL TX_IDLE TX_RST HEC_ERR RC_ACK RC_BOC RC_CLK RC_D[7:0] RC_FULL RC_RST
Receiver L64360
Secondary Port Miscellaneous Operation
PRU_CLK STALL TEST SRL_ACK SRL_BOOT SRL_CLK16 SRL_DIN
Interrupt/ Messaging
Serial Interface
Host/DMA Port
These signals interface L64360 Controller Host Bus. more information DMAC Chapter
HBS_A[31:2] Host/DMA Port Address Output During operations, Host /DMA Port drives this address provide L64360 addresses system components. Each time HBS_ACK asserted, word address HBS_A[23:2] incremented. HBS_A[31:24] never incremented, user firmware should never initiate burst operations that cross 16-Mbyte boundaries. After system reset, L64360 3-states HBS_A[31:2]. Host/DMA Port Data Acknowledgment Input Asserting HBS_ACK indicates that there valid data HBS_D[31:0]. During Host/DMA Port writes external device, device should assert HBS_ACK inform
HBS_ACK
Signal Descriptions
L64360 that going latch data current write operation next rising edge CLK. acknowledged transfer last transfer operation, L64360 deasserts HBS_RQ following rising edge CLK. HBS_AOE Host/DMA Port Address Output Enable Input Asserting HBS_AOE HIGH, enables Host/DMA Port Address (HBS_A[31:2]) control signals (HBS_AS, HBS_BE[3:0], HBS_END, HBS_WR, HBS_S[2:0]). Deasserting HBS_AOE LOW, 3-states address control signals. Host/DMA Port Address Strobe Output beginning each transaction, after L64360 granted (HBS_GNT asserted), L64360 asserts HBS_AS clock cycle indicate that HBS_A[31:2] HBS_BE[3:0] valid. After system reset, L64360 3-states HBS_AS. Host/DMA Port Byte Enables Output L64360 enables each four bytes HBS_D[31:0] asserting corresponding HBS_BE[3:0] LOW. When accessing single byte, only HBS_BE[3:0] signals asserted indicate valid data corresponding byte port. During 32-bit word access from external device, L64360 Host/DMA Port asserts HBS_BE[3:0] signals drives appropriate word address onto HBS_A[31:2]. table below maps HBS_BE[3:0] signals their corresponding bytes HBS_D[31:0].
HBS_BE[3:0] HBS_BE3 HBS_BE2 HBS_BE1 HBS_BE0 HBS_D[31:0] Byte HBS_D[31:24] HBS_D[23:16] HBS_D[15:8] HBS_D[7:0]
HBS_AS
HBS_BE[3:0]
After system reset, L64360 3-states HBS_BE[3:0]. HBS_BOOT Host/DMA Port Boot Select Input HBS_BOOT selects port used booting. Asserting HBS_BOOT HIGH selects Host/DMA Port. Deasserting HBS_BOOT selects Secondary Port.
Host/DMA Port
HBS_D[31:0]
Host/DMA Port Data Bidirectional During read operations, Host/DMA Port samples HBS_D[31:0] rising edge when HBS_ACK asserted. During write operations, Host/DMA Port sources data onto HBS_D[31:0]. Host/DMA Port responds HBS_ACK sourcing data next transfer onto HBS_D[31:0].
HBS_DOE
Host/DMA Port Data Output Enable Input Asserting HBS_DOE HIGH, enables output Host/DMA Port Data Bus, HBS_D[31:0]. Deasserting HBS_DOE 3-states data bus. Host/DMA Port Operation Ending Output During burst operation, Host/DMA Port asserts HBS_END LOW, when detects second-to-the-last HBS_ACK, warn memory controller that current transfer will next time HBS_ACK asserted LOW. HBS_END deasserted following rising clock edge during which L64360 samples final transfer acknowledgment (HBS_ACK asserted) given burst operation. HBS_END also asserted when suspended transaction. After system reset, L64360 3-states HBS_END. Host/DMA Port Grant Operation Input response HBS_RQ asserted, arbiter asserts HBS_GNT HIGH notify L64360 that been granted operation start. other Host requests bus, External Arbiter grant L64360 time, eliminating access cycle. Host/DMA Port Operation Request Output L64360 asserts HBS_RQ HIGH request access device attached Host/DMA Port. external arbiter should respond HBS_RQ asserting HBS_GNT, which allows L64360 proceed with transfer. queued back-to-back Operations have even entered write busy stall because attempted write initialization word busy DMAC), L64360 does deassert HBS_RQ response final Host/DMA Port Acknowledge next operation begins immediately. external device should check state HBS_END
HBS_END
HBS_GNT
HBS_RQ
Signal Descriptions
distinguish between operation boundaries. After system reset, L64360 drives HBS_RQ LOW. HBS_S[2:0] Host/DMA Port Transfer Size Output These three signals encoded value transfer size. They used when user attaches L64360 SBus. following table shows combinational values HBS_S[2:0].
Transfer Size (Bytes) Supported Supported Supported
HBS_S2
HBS_S1
HBS_S0
After system reset, L64360 3-states HBS_S[2:0]. HBS_WR Host/DMA Port Operation Type Output HBS_WR qualifies type operation requested L64360 asserting HBS_RQ. L64360 asserts HBS_WR HIGH when L64360 initiating write. L64360 deasserts HBS_WR when L64360 initiating read. After system reset, L64360 3-states HBS_WR.
Transmitter
These signals transmit Acell data control Acell data transmission. more information Chapter
TX_ACK Transmitter Data Acknowledgment Input Transmission Convergence Sublayer (TCS) framing logic (external L64360) asserts TX_ACK HIGH when sampled data value TX_D[7:0]. L64360 responds TX_ACK placing next byte onto TX_D[7:0]. next byte first byte cell, L64360 also asserts TX_BOC. L64360 Transmitter gapped deasserting TX_ACK when TX_CLK free-running, shutting TX_CLK while constantly asserting TX_ACK HIGH. external logic unable sample byte TX_D[7:0] given cycle, should deassert TX_ACK.
Transmitter
TX_BOC
Transmitter Beginning Cell Output L64360 Transmitter asserts TX_BOC HIGH while first byte cell sourced TX_D[7:0]. TX_BOC deasserted after first TX_ACK received. After system reset, L64360 drives TX_BOC LOW. Transmitter Clock Input transmission signals sourced sampled rising edge this clock. TX_CLK drives buffer inside Transmitter portion L64360 ACell Interface. data transfers from L64360 over TX_D[7:0] synchronized this clock, TX_DRDY, TX_BOC, TX_IDLE. Logic inside L64360 synchronizes L64360 System Clock Transmitter data buffer circuitry, which sequenced TX_CLK. system designer need worry about metastability transmitter output. TX_CLK byte clock external transmitter operated frequency less than equal half System Clock. Transmitter Data Output L64360 sources byte-aligned cell data onto TX_D[7:0]. first transmitted over serial line. After system reset, TX_D[7:0] undefined. Transmitter Data Ready Output L64360 asserts TX_DRDY three cycles after deasserts TX_RST HIGH. L64360 asserts TX_DRDY TX_BOC indicate that external logic sample TX_D[7:0] issue acknowledge (TX_ACK). Once asserted, TX_DRDY remains asserted until next system transmitter reset until TX_FULL asserted. After system reset, L64360 3-states TX_DRDY. Receive Buffer Full Input This signal provided UTOPIA Interface. When Receiver Buffer full, notifies asserting TX_FULL. responds deasserting TX_DRDY, which should connected directly Physical Layer enable signal. Transmitting Idle Cell Output L64360 Transmitter asserts TX_IDLE HIGH when next outgoing cell Idle Cell. Transmission convergence framing logic that does handle Idle Cells must still assert TX_ACK until entire Idle Cell passes. After system reset, L64360 3-states TX_IDLE.
TX_CLK
TX_D[7:0]
TX_DRDY
TX_FULL
TX_IDLE
Signal Descriptions
TX_RST
Transmitter Reset Output Asserting TX_RST resets Physical Layer. After L64360 powered L64360 asserts TX_RST within four cycles L64360 System Clock. TX_RST deasserted clock cycles after Transmit Initialize System Control Register one. After system reset, L64360 drives TX_RST LOW.
Receiver
These signals receive Acell data control Acell data reception. more information Chapter
HEC_ERR Error Output L64360 asserts HEC_ERR HIGH when Field that received (Byte cell) does equal Field that L64360 calculated from AHeader. HEC_ERR only active when receiver configured accept check byte. After system reset, L64360 drives HEC_ERR LOW. Receiver Data Acknowledgment Input Asserting RC_ACK HIGH indicates that valid data been placed RC_D[7:0]. Framing logic transmission convergence unit should assert RC_ACK HIGH when placed data RC_D[7:0]. L64360 responds RC_ACK sampling RC_D[7:0] rising edge RC_CLK. Receiver gapped deasserting RC_ACK external logic unable supply byte RC_D[7:0] given cycle. Receiver Beginning Cell Input Asserting RC_BOC HIGH signals beginning cell Receiver. When Physical Layer asserts RC_BOC, Receiver starts counter count number bytes incoming cell. Receiver Clock Input receive signals sourced sampled rising edge this clock. RC_CLK drives buffer inside ACell Interface Receiver. data transfers over RC_D[7:0] L64360, well assertion output signals, synchronized RC_CLK. Logic inside L64360 handles synchronization between L64360 System Clock Receive Data Buffer circuitry powered RC_CLK. system designer need worry about metastability Receiver input. RC_CLK likely clock derived from line data
RC_ACK
RC_BOC
RC_CLK
Receiver
operated frequency less than equal half System Clock. RC_D[7:0] Receiver Data Input L64360 receives byte aligned cell data RC_D[7:0]. Transmission Convergence Sublayer (TCS) framing logic uses RC_D[7:0] send byte aligned cell data L64360. first received over serial line. Receiver Cell Holder Buffer Full Output L64360 asserts RC_FULL HIGH when internal Received Cell Buffer (Holder) almost full (six bytes before full). When System Control Register zero (UTOPIA Mode), L64360 receives only more byte after asserting RC_FULL. When System Control Register (SAI mode), L64360 finishes receiving cell completely after asserting RC_FULL. After system reset, L64360 drives RC_FULL LOW. RC_RST Receiver Reset Output Because several parameters have configured before receive cell, firmware controls deassertion RC_RST. Setting System Control Register deasserts RC_RST. After system reset, L64360 drives RC_RST LOW.
RC_FULL
Secondary Port
These signals control Secondary Port, 32-bit, multiplexed address data port. more information Chapter
SP_ACK Secondary Port Data Acknowledgment Input Asserting SP_ACK indicates that valid data will read written SP_AD[31:0] next clock cycle. During Secondary Port read operation, external device should assert SP_ACK cycle before valid data available SP_AD[31:0]. During Secondary Port write operation, external device should also assert SP_ACK cycle before latches write data SP_AD[31:0]. Secondary Port Address/Data Bidirectional SP_AD[31:0] multiplexed address data Secondary Port. When SP_ASEL asserted HIGH, SP_AD[31:0]
SP_AD[31:0]
Signal Descriptions
contains information shown table below. When SP_ASEL deasserted LOW, SP_AD[31:0] contains data.
SP_AD Bits [31:28] [23:22] [21:0] Byte Enables Settings
Deasserted select Write, Asserted HIGH Read Used Deasserted Access Type Deasserted Data, Asserted HIGH Instruction Block Fetch Asserted HIGH Atomic Asserted HIGH Used Deasserted Address
Deasserting SP_GNT, 3-states SP_AD[31:0]. Byte Enables Secondary Port, SP_AD[31:28], only apply write transactions. During read transactions, SP_AD[31:28] must asserted HIGH. table below maps address phase SP_AD[31:28] signals their corresponding bytes data phase SP_AD[31:0].
SP_AD[31:28] (Address Phase) SP_AD31 SP_AD30 SP_AD29 SP_AD28 SP_D[31:0] Byte (Data Phase) SP_AD[31:24] SP_AD[23:16] SP_AD[15:8] SP_AD[7:0]
When Block Fetch set, external logic must respond with correct number acknowledge cycles. description Atomic Operation, refer Section 4.8, "Atomic Transactions." SP_ASEL Secondary Port Address/Data Select Input Asserting SP_ASEL HIGH causes L64360 drive address SP_AD[31:0]. During read operation, deasserting SP_ASEL causes L64360 3-state SP_AD[31:0] that external logic drive data onto SP_AD[31:0]. During write operation, deasserting SP_ASEL causes L64360 drive SP_AD[31:0] with data. Secondary Port Byte-wide Device Input Asserting SP_BWIDE LOW, during read operations, indicates that external device attached port eight bits wide.
SP_BWIDE
Secondary Port
With SP_BWIDE asserted, Secondary Port executes four cycles with sequential byte addresses beginning with effective address. external device assert SP_ACK along with SP_BWIDE four byte accesses guarantee L64360's proper operation. external device should provide data SP_AD[7:0] when asserts SP_BWIDE. SP_GNT Secondary Port Grant Input Asserting SP_GNT HIGH, causes L64360 drive address SP_AD[31:0]. transmission L64360 stops driving SP_AD regardless state SP_GNT. Deasserting SP_GNT LOW, 3-states SP_AD[31:0]. SP_GNT asserted continuously, external logic then sample correct address same cycle that SP_RQ asserted. Secondary Port Access Request Output When sourced valid address SP_AD[31:0], L64360 asserts SP_RQ HIGH initiate access Secondary Port. After system reset, SP_RQ undefined clock cycles, then L64360 drives SP_RQ LOW. Secondary Port Operation Type Output SP_WR valid only when SP_RQ asserted HIGH. L64360 asserts SP_WR HIGH indicate that requesting Secondary Port write operation. L64360 deasserts SP_WR indicate that requesting Secondary Port read operation. After system reset, L64360 drives SP_WR LOW.
SP_RQ
SP_WR
Interrupt/ Messaging
These signals control host messaging. based CW33300 described CW33300 Enhanced Self-Embedding Processor Core User's Manual.
GPINT_AUTO General Purpose Interrupt Input GPINT_AUTO connected Interrupt2. software disable enable interrupts necessary. GPINT_TST L64360 Interrupt Input GPINT_TST connected CpCond0 signal APU. External logic assert GPINT_TST alert APU. Asserting GPINT_TST HIGH sets Branch CpCond0 instruction TRUE.
3-10
Signal Descriptions
GPINT_TST used message passing. firmware samples this signal determine Host message APU. HBS_INT Host Interrupt Output L64360 asserts Host Interrupt when wishes interrupt Host. likely used part messaging system. interpretation this signal defined user firmware. L64360 assert HBS_INT HIGH indicate error conditions, congestion problems, CS-PDUs reassembled, other conditions. L64360 asserts HBS_INT performing store operation Host Interrupt Register (refer Section 4.7, "ATMizer Architecture-to-Host Messaging"). HBS_INT remains valid four clock cycles then deasserted. After system reset, L64360 drives HBS_INT LOW.
Serial Interface
Serial Interface signals control serial downloads. more information Chapter
SRL_ACK Serial Acknowledge Input SRL_ACK controls rate that applied L64360 during serial downloads. When downloading from serial PROM, asserting SRL_ACK HIGH causes L64360 latch SRL_DIN rising edge SRL_CLK16. Serial Boot Select Input Asserting SRL_BOOT enables Serial Interface. Deasserting SRL_BOOT HIGH disables Serial Interface. Serial Clock Output SRL_CLK16 clock rate serial download mode, System Clock rate divided This signal clocks bits from serial device used serial downloads L64360. When using serial PROM, SRL_ACK must asserted HIGH SRL_CLK16 should used clock bits into L64360. Serial Data Input Input SRL_DIN data input serial downloading mode. first Word followed Word
SRL_BOOT
SRL_CLK16
SRL_DIN
Serial Interface
3-11
Miscellaneous Operation
Miscellaneous Operation signals drive clocks system reset.
System Clock Input input runs APU, Host/DMA Port, Secondary Port, VCR, much logic ACI. does affect transfer byte data from L64360 over (ACI transactions controlled TX_CLK RC_CLK). Supported frequencies MHz. Pacing Rate Unit Clock Input clock connected PRU_CLK must half less System Clock Frequency (CLK). down counters associated with PRPCs count down every clock tick. Clock Select Configuration Register selects clock inputs PRPCs either PRU_CLK. most applications, PRPC clock should physical line frequency. this case either RC_CLK TX_CLK connected directly PRU_CLK. System Reset Input Asserting initiates master reset L64360. This signal also resets Transmitters Receivers. This signal asynchronous. Pipeline Stall Output L64360 asserts this signal when pipeline stalled. L64360 deasserts this signal HIGH when executing instructions. Test Mode Input Asserting this signal causes L64360 3-state output bidirectional pins. normal operation this signal should tied VDD.
PRU_CLK
STALL
TEST
3-12
Signal Descriptions
Chapter ATMizer Processing Unit (APU) Prefetch Buffer
This chapter describes function operation ATMizer Processing Unit Prefetch Buffer. This chapter twelve sections:
Section 4.1, "APU Overview" Section 4.2, "Header Trailer Generation Retrieval" Section 4.3, "DMA" Section 4.4, "Pacing Rate Unit (PRU) Configuration" Section 4.5, "ACI Cell Queuing Cell Processing" Section 4.6, "Memory Allocation" Section 4.7, "ATMizer Architecture-to-Host Messaging" Section 4.8, "Atomic Transactions" Section 4.9, "Host/DMA Port Priority" Section 4.10, "Congestion Control" Section 4.11, "APU External Access" Section 4.12, "Prefetch Buffer"
Overview
ATMizer Processing Unit (APU) 32-bit RISC core based MIPS R3000 architecture. includes CPU, four-word write buffer, cache controller. powerful, user-programmable gives ATMizer Architecture many unique capabilities. CW33300 Enhanced Self-Embedding Processor Core User's Manual describes core which basis APU. processes every incoming cell generates every outgoing cell. provides operational control necessary support functions
such cell switching multiple AAL-type cells, scatter-gather memory management operations, intelligent congestion control algorithms, traffic statistics gathering, robust ATMizer Architecture-toHost messaging. firmware builds cells, controls messages between ATMizer Architecture Host CPU, services channel sequencing. Cell building consists Header Trailer generation, AHeader retrieval from Channel Parameter Entry (CPE) Virtual Channel (VC), AHeader manipulation insertion, programming operation SAR-PDU retrieval. user-written firmware controls most ATMizer Architecture functions, including following:
Header Trailer Generation Retrieval Pacing Rate Unit (PRU) Configuration Cell Queuing Cell Processing Memory Allocation ATMizer Architecture-to-Host Messaging Atomic Transactions Host/DMA Port Priority Congestion Control External Access
Sections through 4.11 describe controls these functions. Note CpCond Interrupt signals internal APU. Refer CW33300 Enhanced Self-Embedding Processor Core User's Manual more information. firmware generates Headers (AAL 3/4) Trailers (AAL 3/4) during segmentation. Firmware program generate insert CRC10 Field. Header generation includes sequence number generation checking well message type insertion extraction (BOM, COM, EOM, SSM). also initiates appropriate operations retrieve SAR-Service Data Unit (SDU) from memory-based realtime data buffers (AAL CS-PDUs. also retrieves manipulates AHeaders, which includes modifying
Header Trailer Generation Retrieval
ATMizer Processing Unit (APU) Prefetch Buffer
fields. cells that switched, makes initial switching decision based information contained well VCI/VPI translation specified CPE. Controller (DMAC) within ATMizer Architecture handles memory transactions between Host memory. manages functions main local (VCR) memory address incrementing, byte count reduction, byte alignments. initiates operations
retrieve SAR-SDUs during segmentation restore SAR-SDUs their respective CS-PDUs during reassembly switch entire cells, headers trailers intact, other memorymapped Aports during switching operations transfer SAR-SDUs from realtime data stream buffers applications supporting circuit interfaces (such lines)
sets following parameters DMAC initiate operation:
Main Memory Starting Address Byte Offset Local Starting Address Local Byte Offset Number Bytes Transferred (less than equal Transfer Direction (Read Write) Ghost generate CRC32 non-contiguous PDUs
Writing DMAC causes DMAC initiate transfer. user firmware should check DMAC busy before issuing command ATMizer Architecture. busy, should wait. perform direct load/store operations from/to Host memory while DMAC busy (APU steal cycle). Pacing Rate Unit (PRU) Configuration writes Pacing Rate Unit implement Peak Rate Pacing Maximum Burst Length traffic shaping during segmentation process. consists Peak Rate Pacing Counters (PRPCs) Peak Rate Pacing Initialization Registers. sets initial count values Peak Rate Pacing Initialization Registers starts
count operation. When more counters time out, informs asserting Interrupt1 CpCond2. When Host CS-PDU ready segmentation, passes data structure, called Channel Parameter Entry (CPE), APU. describes segment CS-PDU kept either external memory. either case, pointer CPE, selects PRPCs, attaches pointer itself PRPC. When PRPC elapsed, more CS-PDUs ready segmentation. more counter expires same time, read Channel Group Credit Register (CGCR) determine which PRPCs have expired. Cell Queuing Cell Processing queues cells transmission writing Start Address cell into Transmit Cell Address FIFO Transmitter. cell address present FIFO when cell boundary reached, Transmitter automatically sends Idle Cell. received cells, decides between cell switching circuit termination each performs internal cell switching (cell switching between receiver transmitter) passing addresses received cell targeted internal switching Cell Address FIFO (ACell Interface) Transmitter. also sets Global Pacing Rate Register (GPRR) order shape assigned cell content outgoing cell stream. GPRR simple count-down counter. When reaches zero, Transmitter forces Idle Cell external framing logic. also program generate insert CRC10 Field Acells generates checks Field. Memory Allocation During reassembly process manages memory buffer. memory allocated incoming CS-PDUs fragments, APU:
tracks fragment boundaries issues additional fragments CS-PDUs needed generates link lists fragments allocated given CS-PDU
ATMizer Processing Unit (APU) Prefetch Buffer
sends messages from ATMizer Architecture Host inform Host CS-PDU completion, errors, congestion problems
CS-PDU contiguous transmit direction, firmware have recognize difference between end-of-fragment boundaries end-of-CS-PDU boundaries. ATMizer Architecture-toHost Messaging ATMizer Architecture does enforce particular messaging system between Host system. Using L64360, user implements messaging system polling L64360 Interrupt input signal, GPINT_TST (connected directly CpCond0 tested with Branch CpCond0 True instruction), indication that Host wishes pass messages L64360. read write from Host/DMA Port Secondary Port memory-mapped location part messaging mailbox system. Interrupt input signal, GPINT_AUTO, also used addition place GPINT_TST part messaging system. Please note that GPINT_AUTO true interrupt GPINT_TST polled condition input. L64360 asserts Host/DMA Port Interrupt output signal, HBS_INT, indicate Host that L64360 wishes already passed message Host system. L64360 asserts HBS_INT when performs store Host Interrupt Register. (The Host Interrupt Register really register. address decode circuit with Effective Address 0xFFF04B00.) Writing Host Interrupt Register causes L64360 assert HBS_INT four clock cycles then deasserts external system needs more than four cycles recognize interrupt, must latch HBS_INT then clear latch when finished. Atomic Transactions Secondary Port Host/DMA Port support atomic transactions (locked back-to-back read-modify-writes) hardware. perform atomic transactions, although MIPS architecture does have read-modify-write instruction. read-modify-write, Effective Address must one. Secondary Port, this reflected Physical Address during address cycle. set, responsibility external arbiter guarantee that given other master after current operation complete, because L64360 performs next operation locked
ATMizer Architecture-to-Host Messaging
back-to-back manner. Host/DMA Port, Effective Address set, L64360 asserts Host/DMA Port Operation Request output signal, HBS_RQ until both transactions have finished. When firmware initiating atomic transaction Host/ Port, does perform second transaction (write) after finishes first transaction (read), Host/DMA Port times-out cycles after acknowledge first transaction. then gives deasserting HBS_RQ, sets Timeout Error System Control Register, asserts internal Interrupt0 signal. Host/DMA Port Priority There only pair request grant signals Host/DMA Port. Since there three sources trying access Host/DMA Port, priority follows: Serial Request from Serial Interface Read Write Operations (Read Write) When attempts load, Host/DMA Port still busy with operation, load preempts operation (APU steal cycle). Host/DMA Port asserts Operation Ending signal, HBS_END, suspend while performing load. Host/ Port asserts Host/DMA Port Address Strobe, HBS_AS, following cycle, along with address load operation. When Host/DMA Port slave asserts Host/DMA Port Read/Write Acknowledgment, HBS_ACK, signal load transaction, operation resumes. preempt mechanism also applies stores. operations preempted more than once. However, when fast-page-mode DRAM used, preempt mechanism should avoided. Software avoid preempt mechanism performing transactions while still busy. 4.10 Congestion Control ATMizer Architecture capable executing facilitating almost congestion control algorithm. looks appropriate AHeader Fields each incoming cell notification congestion.
ATMizer Processing Unit (APU) Prefetch Buffer
congestion notification found, take immediate action. Such actions include more following: Notify Host that congestion been seen utilizing ATMizer Architecture-to-Host messaging scheme developed user Lower segmentation rate each Reduce overall assigned cell throughput rate setting lesser value Global Pacing Rate Register fields outgoing cells zero instead lowering overall information rate 4.11 External Access directly access external devices through either Host/ Port Secondary Port. direct access loads stores, address space both interfaces Mbytes. four-word write buffer which enhances throughput during back-to-back store transactions. also supports load scheduling, load operation does stall data required immediately. Effective Address Bits [23:22] define whether operation Host/ Port direct access Secondary Port direct access (see Figures through 4.6). This section explains direct access through Host/DMA Port. Direct access through Secondary Port explained Chapter Figure shows Host/DMA Port Substitution Register format.
Figure Substitution Register
Reserved1 Substitution Bits
reserved bits must
Substitution Register's Effective Address (the address used code) 0xFFF04D00. (Most Significant Bit) Substitution Register holds most significant bits address direct access through Host/ Port. These bits valid only during load store through Host/DMA Bus.
External Access
When accesses Host/DMA Port, uses lower bits Effective Address bits from Substitution Register form Host/DMA Port Address, HBS_A[31:2], Host/DMA Port Byte Enables, HBS_BE[3:0]. Figure shows Host/DMA Port Address Host/DMA Port Byte Enables formed from Effective Address Substitution Register.
Figure Host/DMA Port Address Byte Enables Formation
Substitution Register Effective Address HBS_BE[3:0] Encode
HBS_A[31:2]
Figures show format Effective Address direct access through Host/DMA Port.
Figure Effective Address DMA/Host Port Access Cacheable
4-Mbyte Address Space
atomic operation. single load/store.
Figure Effective Address DMA/Host Port Access Non-cacheable
4-Mbyte Address Space
atomic operation. single load/store.
Figures show format Effective Address direct access through Secondary Port. Only bits required access. Bits [21:0] Effective Address transferred directly SP_AD[21:0] during address phase.
ATMizer Processing Unit (APU) Prefetch Buffer
Figure Effective Address Secondary Port Access Cacheable
4-Mbyte Address Space
atomic operation. single load/store.
Figure Effective Address Secondary Port Access Non-cacheable
4-Mbyte Address Space
atomic operation. single load/store.
4.12 Prefetch Buffer
Prefetch Buffer four-word data cache that works just like normal write-through cache system. ATMizer Architecture uses Prefetch Buffer efficiently load CPEs, buffer lists, other data structures using burst block fetches. Whenever accesses external memory devices with cacheable addresses, either port (Host/DMA Port Secondary Port) perform block fetches, store data Prefetch Buffer, enhancing system performance. Block Fetch Size must either four both System Control Register BIU/Cache Configuration (BCC) Register (refer CW33300 Enhanced Self-Embedding Processor Core User's Manual). When executing block fetch from asserting SP_AD25 informs memory system that ATMizer Architecture requesting block Secondary Port. transfer through Host/DMA Port, Host/ Port protocol handles burst transaction automatically, which means that four-word block fetch functions same 16-byte wordaligned operation. block fetch address word aligned. address wraps around, based two-word four-word boundary, shown Tables 4.2.
Prefetch Buffer
Table Two-word Block Fetch Address Offset
Starting Address Offset
Subsequent Address Offset Subsequent Address Offset Subsequent Address Offset Subsequent Address Offset
Table Four-word Block Fetch Address Offset
Starting Address Offset
4-10
ATMizer Processing Unit (APU) Prefetch Buffer
Chapter Instruction (IRAM) Serial Interface
This chapter describes function operation Serial Interface load Instruction RAM. This chapter five sections:
Section 5.1, "Overview" Section 5.2, "Serial Downloading" Section 5.3, "Serial Interface Data Addressing" Section 5.4, "Multiple Downloading ATMizer Booting" Section 5.5, "Loading Code into IRAM Example Software"
Overview
Instruction (IRAM) 4-Kbyte single-cycle SRAM contained within ATMizer Architecture. IRAM holds 1024 instructions user-written firmware that power APU. During normal operation (when executing code) only read IRAM. write IRAM during diagnostic mode. load user firmware into IRAM, user disable cache mechanism explained Section 5.5, "Loading Code into IRAM Example Software." Disabling cache mechanism puts IRAM into diagnostic mode. When Serial Interface enabled, ATMizer Architecture stores bitstreams from Serial Interface external logic into Host/DMA Port Secondary Port memory. user must then copy user firmware into IRAM using Load IRAM Program Section 5.5, "Loading Code into IRAM Example Software."
Serial Downloading
Serial downloading process downloading code from serial device through Serial Interface either Secondary Port Host/ Port. RST, SRL_BOOT, HBS_BOOT, SRL_CLK16, SRL_ACK, SRL_DIN signals control serial downloading. enable serial downloading logic within ATMizer, external logic must first assert least four clock cycles. External logic must then deassert HIGH keep SRL_BOOT asserted throughout entire downloading process. When using serial PROM, should connected through inverter PROM Output Enable signal (OE) SRL_ACK should tied HIGH that when external logic deasserts RST, also enables Serial PROM. After external logic deasserts RST, ATMizer Architecture starts SRL_CLK16 (CLK divided 16). Since ATMizer Architecture Serial PROMs operate less than MHz, necessary divide clock SRL_CLK16 should connected Serial PROM clock input. Serial PROM presents data SRL_DIN signal, ATMizer Architecture latches this data rising edge SRL_CLK16. During serial download, ATMizer Architecture takes data from Serial Interface (SRL_DIN) time, packs data into 32-bit word stores data into either Host/DMA Port Secondary Port depending state HBS_BOOT signal. Asserting HBS_BOOT selects Host/DMA Port. Deasserting HBS_BOOT selects Secondary Port. external system control rate serial data transfer using SRL_ACK signal, since data SRL_DIN latched rising edge SRL_CLK16 only when SRL_ACK asserted. When external system ready present data SRL_DIN, stall ATMizer Architecture deasserting SRL_ACK LOW. Whenever external logic able provide data, assert SRL_ACK HIGH, which causes ATMizer Architecture receive more data. ATMizer Architecture expects serial bitstream start with Word continue Word where less than equal 4095. bitstream into ATMizer Architecture stored directly into IRAM. Instead bitstream passed from Serial Downloading Control Module either Secondary Port HBS_BOOT deasserted) Host/DMA
Instruction (IRAM) Serial Interface
Port HBS_BOOT asserted) 32-bit words. ATMizer Architecture stores these instructions temporarily into system memory. After entire code (less than equal Kbytes) been stored into system memory through ATMizer Architecture, external logic must deassert SRL_BOOT HIGH initiate boot. Since difficult design logic that deassert SRL_BOOT exactly cycle after last code been loaded, Logic recommends that system designer create Circuit deassert SRL_BOOT soon possible after entire code been loaded. This procedure cause some extra data loaded into Secondary Port Host/DMA Port, this should present problem long user program does access this extra data. Serial Interface Data Addressing ATMizer Architecture loads Kwords download cycle. provide flexibility serial downloading, portion first word that Serial Interface fetches (the Segment Address) used upper address serial downloading write operation. Host/DMA Port write operation, Segment Address Bits [31:14] passed Host/ Port HBS_A[31:14]. Secondary Port write, since there only bits address, Segment Address Bits [21:14] passed Secondary Port SP_AD[21:14]. Bits [31:23] [13:0] Segment Address ignored should cleared zeroes. This format allows system designer dump codes anywhere system memory 16-Kbyte boundary. each word arrives, ATMizer Architecture increments Host/DMA Secondary Port Address Bits [13:0] four. Tables show examples Segment Address used write address.
Serial Download Write Address (SP_AD[21:0]) Segment Address HBS_BOOT 0x00000000 0x00040000 0x003FC000 Word 0x000000 0x040000 0x3FC000 Word 0x000004 0x040004 0x3FC004
Table Serial Interface Data Addressing through Secondary Port
Word 4095 0x003FFC 0x043FFC 0x3FFFFC
Serial Interface Data Addressing
Table Serial Interface Data Addressing through Host/ Port
Serial Download Write Address (HBS_A[31:2] Bits [1:0] 002) Segment Address HBS_BOOT 0x00000000 0x01010000 0xFFFFC000 HIGH HIGH HIGH Word Word
Word 4095 0x00003FFC 0x01013FFC 0xFFFFFFFC
0x00000000 0x00000004 0x01010000 0x01010004 0xFFFFC000 0xFFFFC004
When code downloaded requires less than Kwords, external logic deassert SRL_BOOT HIGH when downloading finished. code downloaded requires more than Kwords, external logic must deassert SRL_BOOT 4-Kword boundary least system clock (CLK) ticks later, assert again (multiple downloading). first word second download decoded into another segment address same first download. Figure shows Serial Interface uses serial input address data store
Figure Serial Downloading
Host/DMA Port Memory Streams Word 0000 0000 0000 0000 10XX XXXX XXXX XXXX0 0000 0001 0010 0011 0100 0101 0110 0111 Word ATMizer Architecture Serial Interface
0x0000C000 0x00008000 0x00004000 0x00000000 0x89ABCDEF 0x01234567
Word 0000 0000 0000 0000 00XX XXXX XXXX XXXX0 Word 1000 1001 1010 1011 1100 1101 1110 1111
Multiple Downloading ATMizer Booting
ATMizer Architecture allows user have code larger than Kword. When code particular application exceeds Kword, non-timing critical routines kept external, non-cacheable memory. ATMizer Architecture then execute this code. perform second download, external logic must deassert SRL_BOOT after performing first download. This deassertion causes ATMizer Architecture fetch instructions from either Host/DMA Port
Instruction (IRAM) Serial Interface
HBS_BOOT asserted HIGH) Secondary Port HBS_BOOT deasserted LOW). After second downloading process starts, ATMizer Architecture arbitrates between serial request Instruction Fetch operation. serial request higher priority. while performing second serial downloading, Host/DMA Port instruction fetch, operation, serial request happen same time, serial request highest priority, second highest priority, Engine lowest priority. During system reset, hardware sets Reset Vector virtual address 0xBFC00000. ATMizer Architecture maps this virtual address physical address based state HBS_BOOT. Tying HBS_BOOT HIGH causes APU, upon reset, Reset Exception Vector virtual address physical address 0x00000000 Host/ Port. Tying HBS_BOOT causes APU, upon reset, Reset Exception Vector virtual address physical address 0x00000000 Secondary Port. code this boot starting address should have jump instruction which transfers program counter into appropriate virtual address space (0xA0800000 0xA08FFFFC Host/DMA Port, 0xA0C00000 0xA0CFFFFC Secondary Port). Using Secondary Port boot, example, following instructions should placed beginning memory location 0xA0C00000:
0xA0C00500
actual boot code starts address pointed (0x500 this case). jump ensures that program counter generates same effective address physical address. (Note that jump must absolute jump shown above.) From this point program counter 0xA0C00000 0xA0CFFFFC range. (Bit Status Register determines General Exception Vector Address. system reset sets one. Software clear Bit. Setting sets General Exception Vector Address non-cacheable virtual address 0xBFC00180. ATMizer Architecture maps this virtual address physical address
Multiple Downloading ATMizer Booting
based state HBS_BOOT. Tying HBS_BOOT HIGH causes APU, upon general exception, General Exception Vector virtual address physical address 0x00000180 Host/DMA Port. Tying HBS_BOOT causes APU, upon general exception, General Exception Vector virtual address physical address 0x00000180 Secondary Port. Logic recommends that first instruction exception handlers (located 0x00000180 either Host/DMA Port Secondary Port) redirect using jump instruction which transfers program counter into appropriate virtual address space (0xA0800000 0xA08FFFFC Host/DMA Port, 0xA0C00000 0xA0CFFFFC Secondary Port). Clearing zero sets General Exception Vector Address cacheable virtual address 0x80000080. ATMizer Architecture maps this address IRAM location 0x00000080 upon general exception jumps this location. After code loaded into IRAM through series load, invalidate, store, validate operations, should clear Validate IRAM then branch beginning executable code IRAM. This branch simple branch into cacheable space shown below (the beginning address IRAM, most likely Address 0x0000000).
0x00000000
Loading Code into IRAM Example Software
order load instruction code from Secondary Port Host/ Port into IRAM, must programmed invalidate IRAM setting (Bit Status Register. example code below, instructions loaded into IRAM reside Secondary Port (SP) beginning Address 0xA0C01000. There instructions loaded into IRAM space beginning Address 0x00000000. order transfer 1024 instructions, programmer must change contents from 1024. order load instructions from Host/ Port into IRAM, programmer must change Secondary Port Beginning Address into Host/DMA Port Beginning Address.
Instruction (IRAM) Serial Interface
more detail explanation Internal Registers please refer Chapter
Function: This program used load test program into IRAM from Secondary Port (SP). program loaded into IRAM loaded 0x1000 Secondary Port memory. #include "regdef.h" .text .set noreorder .set noat Value loaded into IBLKSZ INTP NOPAD BGNT LDSCH NOSTR (see Section 14.2, "APU Core Registers") r10, 0xfffe0130 BIU/Cache Config Address (r10) Write Config Program loop load test program from IRAM. contains number instructions transferred from IRAM. each pass loop, instruction word transferred from Register, from there IRAM. instr words fetch from 0x00010000 isolate cache r11, 0xa0c01000 address (physical address 0x1000) Where IRAM program transferred resides r12, first location IRAM loop: (r11) Fetch IRAM instr word from addi r11, Point next IRAM instr word 0x00034800
Loading Code into IRAM Example Software
mtc0 (r12) mtc0 loop addi r12,
Write Status Reg, enable Isolate cache Decrement counter store instr word from IRAM write Status Reg, disable isolate cache fetch next IRAM instruction word point next addr IRAM contains value which starting address IRAM
Instruction (IRAM) Serial Interface
Chapter Virtual Channel (VCR)
This chapter describes function operation Virtual Channel RAM. This chapter five sections:
Section 6.1, "Overview" Section 6.2, "Storing Cells" Section 6.3, "Storing Channel Parameter Entries (CPEs)" Section 6.4, "Cell Multiplexing Demultiplexing" Section 6.5, "VCR Partitioning Examples"
Overview
Virtual Channel (VCR) 1024 dual-ported Read/Write SRAM that provides ATMizer Architecture with many unique capabilities. Almost ATMizer Architecture operations involve transfer data from VCR. read written Controller, ACell Interface APU. incoming cells (cells arriving over Receiver) written into prior processing. decides whether terminate cell (reassemble into CS-PDU data buffer) switch cell (internally externally). outgoing cells either constructed (segmentation) transferred (external switching) prior transmission. addition, Channel Parameter Entries (CPEs), memory buffer lists, messages, other parameters stored within VCR. This ability store parameters inside ATMizer Architecture allows ATMizer Architecture used variety cost-sensitive applications such memory-less network interface cards that support limited number simultaneously active VCs. high-end applications, possible support unlimited number simultaneously active transmit receive channels storing CPEs
externally. This procedure puts certain demands speed local memory that force usage SRAM storage. most configurable aspect ATMizer Architecture. software partitioning vary dramatically between applications. configuration affects number channels supported size, structure, speed external memory system. cells received from ACell Interface written into await either reassembly switching operations initiated APU. 3/4, cells built combination operations operations before being passed Transmitter. also used store CPEs, available buffer lists, other data structures required system operation. Some applications store CPEs VCR, while other applications store CPEs main memory. Some applications store CPEs both places. used following functions:
Storing Cells Storing Channel Parameter Entries (CPEs) Cell Multiplexing Demultiplexing
following three sections describe these functions more detail. Storing Cells Incoming Cells used store incoming outgoing cells.
Receiver ATMizer Architecture ACell Interface reconstructs cells received from external transmission convergence framing logic VCR. allocates bytes memory each incoming cell, although actual cell size user selectable bytes). cell size must programmed into System Control Register part APU's system initialization routine. first bytes cells), bytes cells), 1024 bytes cells) 2048 bytes cells) aside Received Cell Holders (selected BUFSIZ Field System Control Register). Cells written into modulo Cells must processed before they overwritten. Cell buffering helps decouple incoming cell stream from memory interface latency especially helpful situations where
Virtual Channel (VCR)
temporarily unable process incoming cells execution extended routine. Cells written into processed order their arrival either switched over internal Transmitter, switched over main memory interface, reassembled into memory-based realtime data stream buffers CS-PDUs. decision switch terminate cell made after examining information stored over which cell arrived. Outgoing Cells cells must either moved (external switching) constructed (segmentation) prior transmission. Firmware aside area staging area cell switching generation. Outgoing cells transferred from external transmission convergence framing logic Transmitter. Transmitter uses memory pointers. Whenever wishes have resident cell transferred Transmission Convergence Framing Logic, simply writes pointer cell into Transmitter Cell Address FIFO. Transmitter then performs transfer. This pointer method puts restrictions internal location cells slated transmission except that they VCR. ATMizer Architecture switch Received Cell Holder resident cells over Transmitter simply passing pointer cell) Cell Address FIFO (internal switching). switch cell from external device source pre-existing memory based cell over ATMizer Architecture Transmitter), must first initiate operation bring cell into from some temporary memory buffer. Once cell VCR, passes pointer cell Cell Address FIFO same does internal switching. Segmentation requires Aand (AAL 3/4) Headers Trailers (AAL 3/4) appended SDUs APU. Once cell constructed VCR, again passes cell pointer Cell Address FIFO. Transmitter sends cell transmission convergence framing logic, byte time. Storing Channel Parameter Entries (CPEs) used storing Channel Parameter Entries.
Storing Channel Parameter Entries (CPEs)
Channel Parameter Entries
Channel Parameter Entry contains pertinent information about single system that supports CS-PDU segmentation reassembly requires less information than system that supports CS-PDU segmentation reassembly cell switching. system that supports simultaneous segmentation reassembly 3/4, CS-PDUs requires even more robust each ATMizer Architecture does enforce specific format. structure location CPEs defined user. User firmware dictates format, grouped together, segmentation process performed grouping. system designer creates format system then writes firmware work within this environment. generate cell, must know certain information about Virtual Circuit (VC) over which cell will pass information about CS-PDU from which cell generated. This information includes: main memory address CS-PDU realtime data buffer from which SAR-SDU retrieved number bytes remaining CS-PDU CS-PDU fragment scatter-gather applications) scatter-gather applications, whether current CS-PDU fragment last fragment multi-fragment CS-PDU AHeader that appended each cell AAdaptation Layer type (number) that used activate appropriate circuitry segment reassemble cells originating terminating given previous Header/Sequence Number CRC32 Partial Result CS-PDU Collectively, these parameters provide with information that needed process incoming cell segment CS-PDU into stream cells. Tables show CPEs implemented Logic ATMizer System Development Platform Demo supporting CS-PDU segmentation reassembly only.
Virtual Channel (VCR)
Table CS-PDU Segmentation
Entry Link List Pointer Next Link List Pointer Previous CS-PDU Memory Starting Address Base AHeader appended each cell) CRC32 Partial Result Next Address Channel Group Number Number Bytes Left Total Byte Count
Size Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes
handles manipulation. bytes number bytes left bytes total byte count.
Table CS-PDU Reassembly
Entry CS-PDU Memory Starting Address CRC32 Partial Result CRC32 Final Result Next Address
Size Bytes Bytes Bytes Bytes
Channel Groups
Channel Group group whose CPEs form contiguous list, either main memory. Channel Groups defined user. that form Channel Group reach their segmentation service intervals simultaneously (they driven common PRPC). Once PRPC times out, firmware running sequences through list VCs/CS-PDUs (the Channel Group), generating specified number cells from each CS-PDU before proceeding next entry Channel Group (see Figure 6.1). number cells generated from each CS-PDU before proceeding next Channel Group entry (and therefore, next CS-PDU) controlled user firmware. Figure shows some examples software structures that stored VCR. example shown Figure 6.1, over which segmenting transmitting CS-PDU, requires bytes information. These bytes include:
Four bytes link list pointer, which points next Four bytes link list pointer, which points previous
Storing Channel Parameter Entries (CPEs)
Four bytes starting address CS-PDU memory Four bytes storing AHeader appended each SAR-PDU Four bytes CRC32 partial storage (AAL5) next starting address Channel group number used bytes number bytes left, bytes total byte count CS-PDU
Note that Channel Group user defined data-structure structure enforced ATMizer Architecture. Host System manages CS-PDU sequencing over single through either linked-list mechanism (parsing driven ATMizer Architecture) through explicit messaging mechanism (the Host waits message from ATMizer Architecture that indicates that CS-PDU Segmentation complete, then passes CS-PDU ATMizer Architecture segmented transmitted over VC). Passing CS-PDU ATMizer Architecture means passing ATMizer Architecture along with indication which Channel Group/PRPC append CPE. ATMizer Architecture appends this entry specified Channel Group. Host uses memory mailboxes Host-to-ATMizer messaging pass ATMizer Architecture. CPEs channels carrying CS-PDUs undergoing reassembly built more compactly than CPEs channels carrying CS-PDUs undergoing segmentation. Figure shows possible construction system supporting only active both transmit receive directions. this example, uses contained AHeader incoming cell index into look-up table retrieve CPEs receiver-oriented channels listed order their VCIs. This restriction does apply transmit direction where grouping parsing mechanism employed.
Virtual Channel (VCR)
Figure Example Software Structures
Bits 0x0000 0x003C 0x0040 0x007C 0x0003 Transmit Cell Builder 0x0000 0x0004 0x0008 0x000C 0x0034 0x0038 0x003C Bits AAL5 Receive Cell Holder Transmit Cell Builder Used AHeader
Received Cell Holder 0x003F 0x0043 Received Cell Holder 0x007F
Transmit Cell Builder
Payload
Received Cell Holder
Transmit Cell Builder
Transmit Channel Parameter Entry Received Cell Holder Transmit Cell Builder Next CRC32 Partial Result Next Address Bytes Left Total Bytes AHeader CS-PDU Starting Address Previous Group Number Receive Channel Parameter Entry CS-PDU Starting Address CRC32 Partial Result Next Address CRC32 Final Result
Transmit VC/CS-PDU Received Cell Holder Transmit VC/CS-PDU Transmit VC/CS-PDU Transmit VC/CS-PDU Receive VC/CS-PDU Receive VC/CS-PDU Receive VC/CS-PDU Receive VC/CS-PDU Free Space Group Table
Received Cell Holder 0x07C0 0x07FC 0x07C3
Received Cell Holder 0x07FF
Idle Cell Holder
Storing Channel Parameter Entries (CPEs)
Cell Multiplexing Demultiplexing
ATMizer Architecture simultaneously handle 65536 VCs, performing cell multiplexing pacing active channels. However, there trade-offs made between number channels supported, data rate APort, cost structure memory. example, network interface card operating desktop speeds less than equal Mbits/s, possible limit number supported Transmission Receive). this case:
used cache relative parameters each these channels ATMizer Architecture need only access main memory retrieve retire SAR-SDUs Host Memory used CS-PDU storage itself need contain memory
applications requiring support very large number channels, hold needed channel information. necessary provide high-speed SRAM, that accessed ATMizer Architecture Secondary Port, Channel Parameter Entry storage. SRAM gives ATMizer Architecture fast access information needed segmenting reassembling CS-PDUs switching cells. CS-PDU storage could handled local DRAM SRAMbased memory system that accessible ATMizer Architecture Controller. Systems cross between examples above. some systems, possible limit number simultaneously active transmission channels. There limit number transmission VCIs supported, only number that have CS-PDUs under segmentation time. number limited then Transmission Channel Parameters cached internally. time saved caching Transmission Parameters used retrieve parameters needed reassembly. This time usage allow single interleaved DRAM system both CS-PDU Channel Parameter storage. unlimited number transmission VCIs supported swapping CPE/VC/CS-PDU CPE/VC/CS-PDU once CS-PDU CSPDU fragment) been segmented.
Virtual Channel (VCR)
Partitioning Examples
Figures show examples constructions. Figure shows partitioning Network Interface Card (for Workstation) that supports limited number open channels. this example, Channel Parameter Entries (CPEs) both transmit receive channels stored VCR, eliminating need local memory Secondary Port. Figure shows partitioning router that supports unlimited number open channels places restriction number that have CS-PDUs under active segmentation time. This example system limits number transmission channels that active simultaneously caches CPEs active channels VCR. This example does limit number open transmission channels, only number channels that have CS-PDUs undergoing segmentation simultaneously.
Figure Partitioning
Transmit Receive Cell Holders Active Transmission Channels Bytes Memory Fragment Cache Receive Channels Bytes
Figure Partitioning Router
Transmit Receive Cell Holders Memory Fragment Cache Active Transmission Channels Bytes
Once CS-PDU been completely segmented, swap next line. CPEs channels that active receive direction stored external local memory, which allows router support unlimited number simultaneously active receive channels. Without intelligent memory fragment allocation plan, support large number would overload most memory systems. Fortunately ATMizer Architecture combines support external CPEs with capability link list-based CS-PDU scattering during reassembly allo-
Partitioning Examples
cating memory fragments small necessary. result that example router able support unlimited number open transmit receive channels from single unified DRAM-based memory system with single restriction number transmission channels that actively undergoing segmentation time.
6-10
Virtual Channel (VCR)
Chapter Pacing Rate Unit (PRU)
This chapter describes function operation Pacing Rate Unit. This chapter eight sections:
Section 7.1, "Overview" Section 7.2, "Peak Rate Pacing Counters (PRPCs)" Section 7.3, "Channel Group Credit Register (CGCR)" Section 7.4, "Count Initialization Register (CIR)" Section 7.5, "Configuration Register (CR)" Section 7.6, "Stall Register (SR)" Section 7.7, "Cell Rate Pacing" Section 7.8, "Channel Priority"
Overview
Pacing Rate Unit (PRU) implements Peak Rate Pacing Maximum Burst Length control functions. When Peak Rate Pacing Counters (PRPCs) reaches zero, firmware starts segment cell(s) from CS-PDUs associated with that PRPC. Anytime more PRPCs timed-out been serviced, internal hardware asserts input CpCond2 Interrupt1 signal depending timeout mode selected Configuration Register. Firmware running periodically checks state CpCond2 executing Branch Coprocessor Condition True Instruction. CpCond2 true, least PRPC timed-out must segment CS-PDUs attached PRPCs that have reached their service intervals. determines which PRPCs have timed-out reading 10-bit Channel Group Credit Register (CGCR). Each CGCR indicates that corresponding PRPC timed-out. PRPC clocked System Clock (CLK) transmission line clock connected PRU_CLK pin. Note that maximum frequency
PRU_CLK cannot exceed half System Clock frequency. some applications, PRPC counters must count with transmission line clock, Transmission Clock, TX_CLK, connected PRU_CLK. Pacing Rate Unit consists
Peak Rate Pacing Counters (PRPCs) Channel Group Credit Register (CGCR) Count Initialization Register (CIR) Configuration Register (CR) Stall Register (SR)
following five sections describe these components. Note CpCond Interrupt signals internal core which part ATMizer Architecture. Refer CW33300 Enhanced SelfEmbedding Processor Core User's Manual more information.
Peak Rate Pacing Counters (PRPCs)
Peak Rate Pacing Counters pacing rate CSPDU segmentation, implementing leaky bucket algorithm, controlling usage parameters, general purpose counters. Each counter associated Count Initialization Register (CIR). Eight PRPCs their associated CIRs bits wide. PRPCs their associated CIRs bits wide. Peak Rate Pacing Counters used control rate CSPDU segmentation. Whenever more PRPCs times out, asserts CpCond2 Interrupt1 input inform firmware, which will then branch Segmentation routine. 24-bit PRPCs used implement leaky bucket algorithm. counter tracks rate fill bucket, second counter tracks number tokens bucket.
Channel Group Credit Register (CGCR)
Channel Group Credit Register 16-bit read/write register containing each PRPC (PRPCs through directly correspond Credit Bits [9:0]). When PRPC counts down zero, sets corresponding PRPC Credit CGCR. Software read contents CGCR time which PRPCs timed-out.
Pacing Rate Unit (PRU)
should either Load Halfword Load Word instruction read CGCR. Reading CGCR clears CGCR. Figure shows Channel Group Credit Register format.
Figure Channel Group Credit Register
Reserved1 Credit Bits (PRPCs
reserved bits must
CGCR's Effective Address (the address that used code) 0xFFF040X0. Since some PRPCs associated with CpCond2 other PRPCs associated with interrupts, allows indicate which bits CGCR should cleared when reading register. Clearing CGCR Effective Address zero causes clear only those bits configured CpCond2 method. Setting Effective Address causes clear only those bits configured Interrupt Method. should clear Effective Address Bits [6:4] zero. Firmware running implement channel priority selectively servicing Channel Groups that have timed-out. Count Initialization Register (CIR) initializes PRPC counter value writing corresponding Count Initialization Register. PRPCs through initial value placed Bits [11:0] PRPCs initial value placed Bits [23:0]. also read PRPCs same addresses (the addresses read/write). Store Halfword instructions should used write PRPCs through Store Word instructions should used write PRPC Load Halfword instructions should used read PRPC through Load Word instructions should used read PRPC Figure shows 12-bit Count Initialization Register format used PRPCs
Figure 12-Bit Count Initialization Register
Reserved
Initialization Value
reserved bits must zero.
Count Initialization Register (CIR)
Figure shows 24-bit Count Initialization Register format used PRPCs
Figure 24-Bit Count Initialization Register
Reserved1 Initialization Value
reserved bits must
Count Initialization Register's Effective Addresses 0xFFF043XX (see Table 11.8). Setting Effective Address causes write initialization value into PRPC immediately. Clearing Effective Address zero causes write initialization value into immediately, update PRPC after reaches zero. Effective Address should cleared zero. Table shows Effective Address Bits [5:0] select size CIR.
Table Effective Address Bits [5:0] Selection
Bits [5:0] 0000002 0000102 0001002 0001102 0010002 0010102 0011002 0011102 1000002 1001002 Size (Bits)
Configuration Register (CR)
Configuration Register Timeout Clock Select fields each corresponding PRPC. Timeout Field used notify when PRPC counted down zero. There methods indicating timeout APU. first method, check PRPC timed-out executing Branch Coprocessor Condition Instruction. asserts CpCond2 long least PRPC associated with CpCond2 timeout indication method CGCR. second method,
Pacing Rate Unit (PRU)
asserts timeout interrupt. asserts Interrupt1 long least PRPC associated with interrupt timeout indication method CGCR. PRPC configured either timeout indication method, both. PRPCs grouped, PRPCs grouped, PRPCs grouped. Software must determine which method each group timers will timeout indication. Table shows Timeout Field used this purpose. Software change timeout mechanism dynamically. When counters group times-out, software must read CGCR find which PRPC caused CpCond2 interrupt. Each PRPC driven either System Clock (CLK) Pacing Rate Unit Clock (PRU_CLK). uses Clock Select Field select between these clocks. Bits [9:0] select clock PRPCs through Clearing PRPC's corresponding zero causes PRPC clocked using CLK. Setting PRPC's corresponding causes PRPC clocked using PRU_CLK. Figure shows Configuration Register format.
Figure Configuration Register
Clock Select (PRPCs
Reserved1
Timeout
reserved bits must CLK, cleared zero. PRU_CLK, one.
Configuration Register's Effective Address 0xFFF04100. Note Firmware must write Configuration Register using Store Halfword instruction.
Timeout Method1 PRPCs
Table PRPC Grouping
CpCond Method, cleared zero. Interrupt Method, one.
Configuration Register (CR)
Stall Register (SR)
contains Stall Register used suspend more PRPCs. Setting Stall Mask Stall Register causes corresponding PRPC stop counting. Stall Mask Bits [9:0] correspond PRPCs through Credit does accumulate PRPC with Stall Mask when PRPC stalled zero. PRPC stalled zero, sets Credit soon Stall cleared. Once Stall Mask cleared zero, corresponding PRPC begins counting again from where left off. should either Store Halfword Store Word instruction write this register. Figure shows Stall Register format.
Figure Stall Register
Reserved1
Stall Mask (PRPCs
reserved bits must
Stall Register's Effective Address 0xFFF04200. Cell Rate Pacing Peak Rate Pacing Burst Length ATMizer Architecture implement Cell Rate Pacing controlling CS-PDU Segmentation Rates. ATMizer Architecture implement ALayer Peak Rate Pacing Maximum Burst Length control functions. Once CS-PDU CS-PDU fragment been passed ATMizer Architecture segmentation, ATMizer Architecture controls rate cell generation from CS-PDU number back-to-back cells generated from each CS-PDU. CS-PDU attached user-programmable Peak Rate Pacing Counters ATMizer Architecture. Each PRPC counts down each clock tick. Since each CSPDU attached given PRPC have Burst Length value, count Peak Rate Pacing Register actually determines Service Interval Channel Group, necessarily peak rate cell generation CS-PDUs attached that PRPC. CS-PDUs attached particular PRPC with similar characteristics, such channel priority, collectively referred Channel Group. More than Channel Group attached single PRPC. Burst Lengths each CS-PDU attached PRPC identical, PRPC count determines actual peak rate segmentation CS-PDUs belonging that Channel Group.
Pacing Rate Unit (PRU)
CS-PDUs attached PRPC Host Processor. When Host passes Segment CS-PDU information packet ATMizer Architecture, includes information packet indication which PRPC should used define Service Interval segmenting CS-PDU. also includes Burst Length value CS-PDU (how many cells should generated sent, back-to-back, CS-PDU each service interval). ATMizer Architecture, upon receiving this Segment CS-PDU information packet (through Host-ATMizer Messaging) appends Channel Parameters CS-PDU specified Channel Group begins segmentation process CS-PDU next time associated PRPC times-out. When servicing Channel Group, firmware generate send more cells before servicing next Channel Group. number cells sent before proceeding next Channel Group entry defined either construction (this value same each member Channel Group embedded into firmware directly) field inside Channel Parameter Entry Firmware running ATMizer Architecture segments number cells specified this Burst Length value before proceeding next Channel Group entry. side effect this process that amount time required access restore Channel Parameter Entry amortized over several cells, effectively reducing number instructions amount time required generate cell. This time savings importance high-speed applications (155 Mbits/s) supporting large number (more than 512). Average Pacing Average Pacing implemented ATMizer Architecture. will probably implemented Host Processor, which access realtime clock. maintain Average Pacing Rate agreed connection establishment, Host Processor keeps running total number bytes sent over each established Prior queuing CS-PDU segmentation over given Host Processor must first determine queuing CS-PDU would violate Average Rate this processor calculates amount time that passed since last checkpoint. then divides total number bytes sent over since last checkpoint elapsed time. result actual Average Pacing Rate bytes second. queuing next CS-PDU would result
Cell Rate Pacing
violation agreed Average Pacing Rate Virtual Circuit, then Host Processor waits period time before passing CS-PDU ATMizer Architecture segmentation. queuing CS-PDU would violate Average Pacing Rate parameter, CS-PDU passed ATMizer Architecture segmentation. statistical multiplexing issues become better understood, software modified implement Average Rate Pacing best way. Channel Priority
Firmware CGCR implement virtually Channel Priority algorithm. There priority mechanisms enforced hardware. checking CGCR Bits particular order, implement high-priority low-priority Channel Groups. give higher priority CS-PDUs/VCs belonging high-priority Channel Groups, read CGCR during servicing lower-priority Channel Group higher-priority Channel Group timed-out. has, suspend servicing lower-priority Channel Group service higher-priority Channel Group. After servicing higher-priority channels, resume servicing lower-priority channel where left off. user attach both high-priority low-priority CS-PDUs single PRPC order pace high-priority low-priority CS-PDUs/VCs same Service Interval Rate. Each PRPC have more) Channel Groups associated with PRPC have high-priority Channel Group low-priority Channel Group attached service channels belonging high-priority Channel Group then check pending high-priority requests reading CGCR before servicing low-priority Channel Group attached that particular PRPC. PRPCs their associated Channel Group Channel Groups given different priorities. more than Channel Group reached service interval awaiting servicing following servicing protocol implemented:
High-priority requests serviced before low-priority requests Existing high-priority requests serviced before high-priority requests high-priority requests serviced before existing low-priority requests
Pacing Rate Unit (PRU)
This implementation channel priority different from highmedium-low CS-PDU Priority assignment, both these priority constructions influence cell generation process. Channel priority affects Channel Group/CS-PDU servicing sequence. AAAL CSPDU priority reflected fields AHeader. Both functions controlled ATMizer Architecture. traffic, Host must include CS-PDU priority Segment CSPDU message packet sent ATMizer Architecture.
Channel Priority
7-10
Pacing Rate Unit (PRU)
Chapter Controller (DMAC)
This chapter describes function operation Controller, which contained within Host/DMA Port. This chapter eight sections:
Section 8.1, "Overview" Section 8.2, "Registers" Section 8.3, "Programming DMAC" Section 8.4, "Cell Switching, Segmentation, Reassembly" Section 8.5, "CRC32 Generation" Section 8.6, "Misaligned Operations" Section 8.7, "Scatter Gather Operations" Section 8.8, "DMA Operation Completion"
Overview
uses Controller (DMAC) perform data transfers between Host/DMA Port external memory. DMAC, which perform block transfers bytes, supports every combination local main memory byte alignment transfers. This support misaligned operations gives ATMizer Architecture ability participate robust Scatter-Gather operations. Controller includes registers, counters, data path that collectively control data transfer operations between Host/DMA Port external memory. DMAC also generates CRC32 CS-PDUs used retrieve restore memory-based channel parameters. main Controller functions include following:
Retrieve user payloads from memory-based CS-PDUs during segmentation operations
Write user payloads back into memory-based CS-PDUs during reassembly operations Retrieve restore application-specific data structures
Controller also contains CRC32-generation circuitry that generates CRC32 values required CS-PDU. CRC32 calculated individually each CS-PDU actively undergoing either segmentation reassembly. CS-PDUs undergoing segmentation, final CRC32 result appended, under control, Bytes [48:44] SAR-SDU last cell generated from CS-PDU. CS-PDUs undergoing reassembly, CRC32 result compared with CRC32 received last cell CS-PDU checking mechanism. Because ATMizer Architecture supports cell multiplexing demultiplexing from VCs, must provide CRC32 partial result storage into CPEs retrieval services allow multiple concurrently active CRC32 calculations performed single CRC32 generator. Registers This section defines registers used DMAC. Please note that some fields DMAC Control Register's Effective Address contain control data. Both DMAC Control Register some fields from DMAC Control Register's Effective Address used configure DMAC Registers Counters. Using this method user program with store instruction. Figure shows format Effective Address DMAC Control Register. more information Section 11.1, "Memory Maps."
DMAC Control Register's Effective Address
Figure DMAC Control Register's Effective Address
Local Address Byte Offset [31:30] firmware uses inform Controller offset bytes) first byte valid data VCR.
Controller (DMAC)
Byte Count [29:24] firmware uses size bytes) transfer. Since only hold six-bit value (from 63), 0000002 sets size bytes. Read/Write (Operation Direction) This controls direction operation. firmware sets this indicate that wishes perform read from main memory. clears this zero indicate that wishes perform write main memory. Ghost This used inform DMAC that operation being programmed being done solely purpose creating CRC32 Partial Result intermediate calculation) SAR-SDU that been constructed from more CS-PDU data block fragments. SAR-SDU built from more than data block, data blocks word aligned size evenly divisible four, CRC32 Partial Generator DMAC able calculate correct CRC32 Partial Result SAR-SDU over numerous operations. Therefore, once entire SAR-SDU been built VCR, force CRC32 partial generation initiating Ghost Write operation. When Ghost write operation, write transaction does bus. DMAC, however, performs Ghost Write operation, which calculates Partial Result places CRC32 Register. Once operation complete, read Partial Result. Ghost Write operation initiated setting zero Effective Address.
Local Address Counter [11:2] Local Address Counter holds read write word address (the local address). initializes with Local Starting Address beginning operation. DMAC increments operation proceeds.
Registers
DMAC Control Register
Figure shows format DMAC Control Register.
Figure DMAC Control Register
Memory Address Register [31:22] Memory Address Register holds most significant bits main memory address during operations. While DMAC does increment main memory address consecutive transfers multiple word operation, does increment value MAR. Therefore, external logic relies sequential incrementing Host/DMA Port Address during multiple word operations, should initiate operation that crosses 16-megabyte boundary. contents reflected output pins HBS_A[31:24] when HBS_GNT signal asserted. Memory Address Counter [21:2] Memory Address Counter holds starting word address operation. During operation, Memory Address Counter incremented when HBS_ACK asserted external logic. contents reflected HBS_A[23:2] when HBS_GNT asserted. Memory (Byte) Offset Register [1:0] Memory Offset Register holds least significant bits main memory starting address operation. DMAC starts memory access beginning byte pointed MOR. HBS_BE[3:0] outputs indicate which bytes should stored memory during transfers.
Controller (DMAC)
CRC32 Register
Figure CRC32 Register
Figure shows format CRC32 Register.
CRC32 Partial Result
CRC32 Register should initialized ones prior beginning first User Payload retrieval CS-PDU. CRC32 Partial Result intermediate CRC32 calculation. CRC32 Partial Result, generated during operation, read from CRC32 Register operation. saved then restored prior next segmentation operation. register also used this CRC32 generation during reassembly. CRC32 Register's Effective Address (EA[31:0]) 0xFFF04CX0. Clearing zero causes DMAC return CRC32 Partial Result. Setting causes DMAC return CRC32 Final Results. EA[6:4] must always cleared zeroes. Programming DMAC order initiate operation between main memory VCR, programs DMAC with starting main memory address (byte address), local/VCR starting address (word aligned address written into Effective Address starting byte offset within targeted word written into Effective Address LO), number bytes transferred, direction transfer. addition, need preset CRC32 Generator CS-PDU CRC32 support Ghost Bit. Both DMAC Control Register some fields from DMAC Control Register's Effective Address used configure DMAC Registers Counters. configure DMAC Control Registers Counters, initiate operation executing single Store Word instruction. CS-PDU Segmentation Reassembly, ATMizer Architecture used CRC32 generation checking, second Store Word instruction needed initialize CRC32 Generator with correct CRC32 Partial Result value. This second instruction should executed immediately before Store Word
Programming DMAC
instruction that used initialize DMAC Registers initiate operation. CRC32 Register read operation using Load Word instruction. Cell Switching, Segmentation, Reassembly ATMizer Architecture, under user firmware control, used implement CS-PDU segmentation, CS-PDU reassembly, Acell switching. each decide whether switch terminate incoming cell. decision based static principles (certain numbers dedicated switched while other numbers dedicated terminating VCs) dynamic principles (the given have flag that indicates whether cells should switched terminated). incoming cell switched, passed, headers trailers intact, memory-mapped device using ATMizer Architecture Controller. networks implementing ringlike structure simple two-way switching matrix, incoming cells switched directly between Receiver Transmitter simply passing pointer cell cell's starting address) Transmitter (the same procedure that used queuing cell transmission). Using this method, cells switched within ATMizer Architecture, without using system memory. perform operations, such Virtual Path Indicator (VPI)/ Virtual Channel Indicator (VCI) Translation, Congestion Notification Insertion, cell before switching performs these operations overwriting values into specific fields cell. example, translation required, firmware sets flag CPE, that received cell, that indicates that cell switched with Translation. included well. reads from writes into Field cell held (the holds either 64-byte cells Receiver writes cells into using modulo 32). firmware decides whether switch cell over backplane using Controller pass pointer cell Transmitter. specific procedures implementing cell switching always defined user firmware. From perspective Controller ACell Interface, there distinction between cell switching circuit termination. Cells
Reassembly Cell Switching
Controller (DMAC)
arriving over Receiver written into VCR. case circuit termination, initiates operation transfer User Payload portion cell corresponding memory-based CS-PDU sets LAC, values DMAC accordingly. cell switching applications where cell transferred memory-mapped device, entire cell (headers trailers included) must transferred. pointer written into should point beginning cell instead beginning User Payload Field. Local Offset most likely zero, value should large enough include switching information, ATM, headers trailers. diagrams Figure page 8-9) show local address pointers (labeled that would written into DMAC Local Address Counter, Local Offset Register, Transfer Length Counter perform Reassembly 60-byte cells well pointers (labeled that would written into these same registers perform Switching operations 52and 60-byte cells. diagrams also point that case cells, User Payload word aligned VCR. Therefore, must Local Offset Field when initiating transfer inform Controller alignment condition. Controller merges bytes from words into single word written word aligned data structure main memory. indicates that targeted memory address word aligned, Controller also adjusts targeted local data proper memory alignment. DMAC capability transfer from local offset memory offset vice versa. This capability especially important Segmentation Reassembly operations, Gather operations, Scatter operations where system designer wishes rely ATMizer Architecture higher layer (TCP/IP) header stripping packet alignment accelerate Application Layer routines. Note When switching Cells, Local Offset should because even though User Payload Field misaligned, cell itself not.
Cell Switching, Segmentation, Reassembly
Segmentation Cell Switching
Fetching cell from memory differs from fetching User Payload from memory both size transfer cell larger than SARSDU) initialization values. Segmentation usually triggered event such Peak Rate Pacing Counter timing-out. switching cell from external memory-mapped device must triggered external event. Figure shows relationship between CS-PDU main-memory addresses Cell Holder (Addresses standard 52-byte cell user specific 60-byte cell).
Controller (DMAC)
Starting Mar-Mac Pointer Cell
AHeader Header
User Header User Header AHeader
Header
Starting Mar-Mac Pointer Cell
Byte Trailer Byte
Trailer
SAR-SDUs always word aligned main memory. SAR-SDUs half-word aligned Cell Builder.
DMAC LO=10 DMAC LO=00 Switching DMAC TLC=44 Bytes DMAC TLC=52 Bytes
DMAC LO=10 DMAC LO=00 Switching DMAC TLC=44 Bytes DMAC TLC=60 Bytes
CS-PDU Main Memory Starting Mar-Mac Pointer Cell
Cell Bytes) (Cell Builder Area)
Cell Bytes) (Cell Builder Area) Words Cell Holder Area
User Header User Header
AHeader
AHeader
Starting Mar-Mac Pointer Cell
CRC32
Byte Byte
SAR-SDUs always word aligned both main memory Cell Builder.
DMAC LO=10 DMAC LO=00 Switching DMAC TLC=48 Bytes DMAC TLC=52 Bytes
DMAC LO=10 DMAC LO=00 Switching DMAC TLC=48 Bytes DMAC TLC=60 Bytes
SAR-SDU Unused P
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