Bidirectional Programmable Interrupt Structure Three Serial Memory Por
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Single-Chip Fax/Data/Voice Modem AD1801
Bidirectional Programmable Interrupt Structure Three Serial Memory Port Interface/ICE-PortEmulator Interface/JTAG Boundary Scan Test Interface Programmable Gain, Attenuation Mute On-Chip Signal Filters Digital Interpolation Decimation Analog Output Pass Resolution Programmable Audio (Handset) Sample Rates from kHz, Modem Sample Rates from kHz, with 10/7 Resolution 128-Lead PQFP 128-Lead TQFP Packages Operation from Single Supply Advanced Power Management
FEATURES Single-Chip Integrated Fax/Data/Voice Modem Channel Three Channel Supports V.34+, V.17 Fallback Modem/Fax Standards V.70 DSVD ADSP-21xx MIPS Core with SPORTs IDMA Controller Words Data Memory (RAM), Words Program Memory (RAM ROM), Byte PC`97-Compliant Single Function Plug Play ISA/Multifunction PCMCIA Parallel Interfaces Single 16.9344 Clock Input Analog Inputs Three Analog Outputs Eight Programmable Pins
FUNCTIONAL BLOCK DIAGRAM
SERIAL PORT/EXTERNAL FUNCTION PORT +12dB RCVP RCVN XMITP XMITN PWDACK 16.9344 XTALI XTALO RING
48kHz 16-BIT 16-BIT CODEC ENGINE
CONTROL STATUS REGISTERS
CLOCK GENERATION
PCM_ISA PNP_STD EMULATOR IRQx/PCMCIA EXT. PORT (15:0) (15:0)/PCMCIA EXT. PORT AEN/REG IOCHRDY/WAIT SBHE/CE2 IOCS16/IOIS16 RESET
ATTEN -31dB 20dB
SPORT0 SELECTOR DATA SRAM ADSP-21xx CORE MIPS PROGRAM SRAM SPORT1 IDMA PROGRAM CONTROLLER BOOT SINGLE FUNCTION PLUG PLAY ISA/ MULTIFUNCTION PCMCIA INTERFACE
48kHz 16-BIT
HANDSET LINE LINE GAIN
+22.5dB
48kHz HANDSET CODEC ENGINE
-34.5dB HANDSET SPKRP HANDSET SPKRN MUTE/ ANALOG SWITCH GN/AT
48kHz 16-BIT
GN/AT GAIN/ATTENUATION
AD1801
-12dB MONITOR SPKR MUTE/ ATTEN/ DRIVER 48kHz 16-BIT MONITOR SPEAKER ENGINE
MAPPED WORD FIFO
DUAL PORT
RESET EEPROM PORT JTAG INTERFACE
VOLTAGE REFERENCE
VREF
FILT CMOUT
AGND
AVDD
DGND
DVDD
ICE-Port trademark Analog Devices, Inc. other trademarks property their respective holders.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1998
AD1801-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Input Signal Analog Output Passband Size Size
RECEIVE PATH
25°C 1008 2048 8192
Output Conditions Autocalibrated Attenuation Output Relative Full Scale 16-Bit Linear Mode Load Handset Load Line Load Mute Transmit Handset Speaker Specifications Measured Differentially Input Conditions Gain Disabled Autocalibrated -1.0 Input Relative Full Scale 16-Bit Linear Mode
Full-Scale Input Voltage (RMS Values Assume Sine Wave Input, Gain Offset Error Receive Differential Input Resistance-DAA Input Capacitance-DAA Input Programmable Gain Amplifier (Relative Full-Scale Input Voltage) Gain Gain Analog-to-Digital Converter Differential Dynamic Range (-60 Input, THD+N Referenced Full Scale, Analog Output Passband, 12.0 kHz, Gain Differential Dynamic Range (-60 Input, THD+N Referenced Full Scale, Analog Output Passband, 12.0 kHz, Gain Differential Dynamic Range (-60 Input, THD+N Referenced Full Scale, Analog Output Passband, 12.0 kHz, Gain Differential THD+N (-1.0 Referenced Full Scale, Analog Output Passband, 12.0 kHz) Differential Signal-to-Intermodulation Distortion [CCIF Method] Single-Ended Dynamic Range (-60 Input, THD+N Referenced Full Scale, Analog Output Passband, 12.0 kHz, Gain [Effectively Gain; Below*]) Single-Ended Dynamic Range (-60 Input, THD+N Referenced Full Scale, Analog Output Passband, 12.0 kHz, Gain [Effectively Gain; Below*]) Single-Ended Dynamic Range (-60 Input, THD+N Referenced Full Scale, Analog Output Passband, 12.0 kHz, Gain [Effectively Gain; Below*]) Single-Ended THD+N (-1.0 Referenced Full Scale, Analog Output Passband, 12.0 kHz) Single-Ended Signal-to-Intermodulation Distortion [CCIF Method] Crosstalk* (DAA Input Handset MIC/Line Input) Offset Error Differential Analog Input) Gain Gain Gain 4.523
Units
5.656
6.787
0.02
0.02
LSBs LSBs LSBs
*When Receive used single-ended input circuit configuration, user would apply full-scale input RCVP connect RCVN capacitor ground. However, this will result output word that down from full scale when because input sees half signal swing compared when driven differentially. Therefore, effective gain ADC, when used single-ended, less than when used differentially. full-scale output with input, should programmed gain, which effective single-ended gain
REV.
AD1801
HANDSET MIC/LINE INPUT PATH
Full-Scale Input Voltage (RMS Values Assume Sine Wave Input) Handset Single-Ended Input with Gain 0.226 Handset Single-Ended Input with Gain 2.26 Line Single-Ended Input Resistance-Handset Input Resistance-Line Input Capacitance-Handset MIC, LINE Input Programmable Gain Amplifier Step Size 22.5 (All Steps Tested) Gain Range Span Analog-to-Digital Converter Dynamic Range (-60 Input, THD+N Referenced Full Scale, A-Weighted) THD+N (-1.0 Referenced Full Scale) Signal-to-Intermodulation Distortion [CCIF Method] Crosstalk (Handset MIC/Line Input Input) Offset Error (Relative Full-Scale Analog Input, Gain
TRANSMIT PATH
0.2828 2.828 2.828
Units LSBs
0.339 3.39 3.39
2.26
21.5
22.5 -100
23.5
0.03 2048
Digital-to-Analog Converter Dynamic Range (-60 Input, THD+N Referenced Full Scale, Analog Output Passband, Output Gain 12.0 kHz) THD+N (-1.0 Referenced Full Scale, Analog Output Passband, Output Gain 12.0 kHz) Signal-to-Intermodulation Distortion [CCIF Method] Crosstalk (DAA XMIT Output Handset Speaker/Line Output) Total Out-of-Band Energy (Measured from 0.555 kHz) Audible Out-of-Band Energy (Measured from 0.555 kHz, Tested kHz) Common-Mode Offset (Referenced Voltage Reference [CMOUT] Output) Differential Offset Programmable Attenuator Step Size -31.0 (All Steps Tested) Output Attenuation Span Full-Scale Output Voltage (RMS Values Assume Sine Wave Output) XMIT Differential Output Output Source Impedance-DAA XMIT External Load Impedance-DAA XMIT Capacitance-DAA XMIT Load Capacitance-DAA XMIT
Units
-78.5 -100 0.016 1.513 31.513
0.487 30.487
31.0 2.121
REV.
AD1801
HANDSET SPEAKER/LINE OUTPUT PATH
Digital-to-Analog Converter Dynamic Range (-60 Input, THD+N Referenced Full Scale, A-Weighted) THD+N (-1.0 Referenced Full Scale) Signal-to-Intermodulation Distortion [CCIF Method] Crosstalk (Handset Speaker/Line Output XMIT Output) Total Out-of-Band Energy (Measured from kHz) Audible Out-of-Band Energy (Measured from kHz, Tested kHz) Handset Speaker Common-Mode Offset (Relative Voltage Reference [CMOUT] Output) Line Output Common-Mode Offset (Relative Voltage Reference [CMOUT] Output) Differential Offset Programmable Amplifier/Attenuator Step Size (+12.0 -34.5 (All Steps Tested) Output Attenuation Span Mute Attenuation Full-Scale Output Voltage (RMS Values Assume Sine Wave Output) Handset Speaker Differential Output Line Single-Ended Output Load) 1.56 Output Source Impedance-Handset Speaker Output Source Impedance-Line External Load Impedance-Handset Speaker External Load Impedance-Line Capacitance-Handset Speaker Capacitance-Line Load Capacitance-Handset Speaker Load Capacitance-Line
MONITOR SPEAKER PATH
-100
Units
0.03
43.5 46.5 -100
49.5
1.414 0.707
2.44
Digital-to-Analog Converter THD+N (Referenced Full Scale) Dynamic Range (-60 Input, THD+N Referenced Full Scale, A-Weighted) Programmable Attenuator Step Size (All Steps Tested) Output Attenuation Span Mute Attenuation Full-Scale Output Voltage (RMS Values Assume Sine Wave Output) Monitor Speaker Output Output Source Impedance-Monitor Speaker External Load Impedance-Monitor Speaker Capacitance-Monitor Speaker Load Capacitance-Monitor Speaker
0.316
Units
-6.513 -12.513
0.707
-5.487 -11.487
REV.
AD1801
DIGITAL DECIMATION INTERPOLATION FILTERS-MODEM MODE
Passband Edge (-0.220 Point) Passband (-3.0 Point) Passband Ripple Transition Band Stopband Edge1 Stopband Rejection (Plus Rolloff) Group Delay Group Delay Variation Over Passband Sample Rate 0.445 0.555 78.0
0.445 0.490 -0.17 0.555 19/FS
Units
DIGITAL DECIMATION INTERPOLATION FILTERS-MODEM MODE
Passband Edge (-0.24 Point) Passband (-3.0 Point) Passband Ripple Transition Band Stopband Edge2 Stopband Rejection (Plus Rolloff) Group Delay Group Delay Variation Over Passband Sample Rate
DIGITAL DECIMATION INTERPOLATION FILTERS-AUDIO MODE
0.400 0.453 -0.24 0.555 10/FS
Units
0.400 0.555 52.8
Passband Edge (-0.18 Point) Passband (-3.0 Point) Passband Ripple Transition Band Stopband Edge3 Stopband Rejection (Plus Rolloff) Group Delay Group Delay Variation Over Passband Sample Rate
DIGITAL INTERPOLATION FILTERS-MONITOR SPEAKER
0.400 0.462 -0.18 0.600 11/FS
Units
0.400 0.600 78.0
Passband Edge (-0.74 Point) Passband (-3.0 Point) Passband Ripple Transition Band Stopband Edge4 Stopband Rejection (Plus Rolloff) Group Delay Group Delay Variation Over Passband Sample Rate 0.350 0.650 55.5
0.350 0.412 -0.74 0.650 10/FS
Units
NOTES stopband repeats itself multiples where sampling frequency. Thus modem mode digital filter will attenuate -78.0 better across frequency spectrum, except range 0.555 wide multiples stopband repeats itself multiples where sampling frequency. Thus modem mode digital filter will attenuate -52.8 better across frequency spectrum, except range 0.555 wide multiples stopband repeats itself multiples where sampling frequency. Thus audio mode digital filter will attenuate -78.0 better across frequency spectrum, except range 0.600 wide multiples stopband repeats itself multiples where sampling frequency. Thus audio mode digital filter will attenuate -55.5 better across frequency spectrum, except range 0.650 wide multiples Specifications subject change without notice.
REV.
AD1801
VOLTAGE REFERENCE
CMOUT External CMOUT Load Current CMOUT Output Impedance
SYSTEM SPECIFICATIONS
2.45
Units
System Frequency Response Ripple (Line Line Out) Differential Nonlinearity Phase Linearity Deviation
STATIC DIGITAL SPECIFICATIONS
Units Degrees
High-Level Input Voltage (VIH) Digital Inputs, Except XTALI XTALI Low-Level Input Voltage (VIL) Digital Inputs, Except XTALI XTALI High-Level Output Voltage (VOH) Low-Level Output Voltage (VOL) Input Leakage Current (GO/NOGO Tested) Output Leakage Current (GO/NOGO Tested) -0.3 -0.3
DVDD DVDD
Units
TIMING PARAMETERS (Guaranteed Over Operating Temperature Digital Supply Range)
RESET Pulse Width (tRPWL) IOR/IOW Strobe Width (tSTW) Setup IOR/IOW Falling (tAESU) Hold from IOR/IOW Rising (tAEHD) Address Setup IOR/IOW Falling (tADSU) Address Hold from IOR/IOW Rising (tADHD) Data Hold from Rising (tDHD1) Data Hold from Rising (tDHD2) Falling Valid Read Data (tRDDV) Write Data Setup Rising (tWDSU)
Units
CLKOUT
SCLK TFSIN RFSIN RFSOUT TFSOUT
tSCH
tSCK
tAESU
tSCH tSCP tSCP
tAEHD
tSCDD tSCDH
IOCS16
ALTERNATE FRAME MODE MULTICHANNEL MODE, FRAME DELAY (MFD
SBHE
tSTW
tRDDV
SD[0:15]
tDHD1 tADHD
tADSU
SA[0:15]
Figure Serial Port Timing
Figure Read Cycle
REV.
AD1801
tAESU
tAEHD
IOCS16
SBHE
tSTW
tWDSU tDHD2
SD[0:15]
tADSU
SA[0:15]
tADHD
Figure Write Cycle
POWER SUPPLY
Power Supply Range-AVDD DVDD Power Supply Current-5.0 AVDD DVDD Operating Power Supply Current-5.0 AVDD DVDD Power-Down Power Dissipation-5.0 AVDD DVDD Operating (Current Nominal Supply) Power Dissipation-5.0 AVDD DVDD Power-Down (Current Nominal Supply) Power Supply Rejection (100 Signal kHz) Both Analog Digital Supply Pins, DAC)
CLOCK SPECIFICATIONS
5.25 1000
Units
4.75
Input Crystal/Clock Frequency Input Clock Duty Cycle (When External Clock Used Instead Crystal) Initialization Sample Rate Change Time (Neglecting Pipeline Delay Sample Period)
Guaranteed, tested. Specifications subject change without notice.
16.9344
75/25
Units
25/75
REV.
AD1801
PACKAGE CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS*
PQFP (Thermal Resistance [Junction-to-Ambient]) PQFP (Thermal Resistance [Junction-to-Case]) TQFP (Thermal Resistance [Junction-to-Ambient]) TQFP (Thermal Resistance [Junction-to-Case]) 35.9 8.38 36.1 3.81
Units °C/W °C/W °C/W °C/W
AD1801 analog digital power pins (AVDD DVDD) must powered same supply. analog digital power pins must always same potential, AD1801 could permanently damaged. Power Supply Digital (VDD) Analog (VCC) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature -0.3 -0.3 10.0 AVDD DVDD +150 Units
-0.3 -0.3
*Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model AD1801JS AD1801JST AD1801JST-REEL
Temperature Range +85°C +85°C +85°C
Package Description 128-Lead PQFP 128-Lead TQFP 128-Lead TQFP
Package Options* S-128A ST-128 ST-128 Tape Reel
Plastic Quad Flatpack; Thin Quad Flatpack.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD1801 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD1801
CONFIGURATION S-128A 128-Lead PQFP
SA12/OE
CMOUT
AGND
AVDD
DVDD
DGND
VREF
SA11
SA10
FILT
IDENTIFIER
SA13/WE SA14/INT1 SA15/CE1 SBHE/CE2 AEN/REG IOCHRDY/WAIT IRQ3/VCTL1/EXTRD IRQ4/INPK IRQ5/CHG IRQ7/SPKR DVDD DGND IRQ9/IREQ IRQ10/CS1 DVDD
LOUT RCVP RCVN XMITP XMITN AGND HSPKRP HSPKRN AVDD MSPKR AGND AGND AVDD AVDD AGND PCM_ISA PNP_STD RESET RESET ERESET DVDD DVDD ELIN EINT ECLK ELOUT
AD1801JS
VIEW (Not Scale) (PINS DOWN)
DGND IRQ11/RS1 IRQ12/PD1 IRQ15/VCTL2/EXTWR IOCS16/IOIS16 DVDD DGND DVDD DGND DGND SD10
DGND SCLK SD12
DGND XTALO
PWDACK
RFS/CS2
DGND DVDD
DR/INT2
TFS/RS2
DT/PD2
DVDD
DVDD
SD14
RING
SD15
SDATA
REV.
XTALI
SD13
SD11
AD1801
CONFIGURATION ST-128 128-Lead TQFP
SA12/OE SA13/WE
IDENTIFIER
AGND
CMOUT
AVDD
DVDD
DGND
VREF
FILT LOUT RCVP RCVN XMITP XMITN AGND HSPKRP
SA11
SA10
SA14/INT1 SA15/CE1 SBHE/CE2 AEN/REG IOCHRDY/WAIT IRQ3/VCTL1/EXTRD IRQ4/INPK IRQ5/CHG IRQ7/SPKR DVDD DGND IRQ9/IREQ IRQ10/CS1 DVDD DGND IRQ11/RS1 IRQ12/PD1 IRQ15/VCTL2/EXTWR IOCS16/IOIS16 DVDD DGND DVDD DGND DGND SD10 PWDACK DGND DVDD TFS/RS2 SCLK DR/INT2 SD12 DGND RFS/CS2 DT/PD2 DVDD SD14
HSPKRN AVDD MSPKR AGND AGND AVDD AVDD AGND PCM_ISA PNP_STD RESET RESET ERESET DVDD DVDD ELIN EINT ECLK ELOUT SDATA XTALO XTALI DGND DVDD RING SD15 SD13 SD11
AD1801JST
VIEW (Not Scale) (PINS DOWN)
-10-
REV.
AD1801
FUNCTION DESCRIPTIONS Device Configuration Signals
Name PCM_ISA PNP_STD
PQFP
TQFP
Description PCMCIA Host Select Control. This weak internal pull-up device. below more information. Standard Mode Select Control. When AD1801 configured PCMCIA mode (i.e., when PCM_ISA HI), then PNP_STD used general purpose input. PNP_STDZ register used monitor state this general purpose input under those conditions. This weak internal pull-up device. below more information.
Core ICE-Port Emulator Interface
Name ERESET EINT ECLK ELIN ELOUT
Ring Indicator
PQFP
TQFP
Description Emulator Enable. Emulator Request. Emulator Grant. Emulator Reset. Emulator Memory Select. Emulator Interrupt. Emulator Clock. Emulator Input. Emulator Output.
Name RING
Port
PQFP
TQFP
Description Phone Ring Indicator.
Name
PQFP
TQFP
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
Description Controlled Programmable This weak internal pull-up device. below more information. Controlled Programmable This weak internal pull-up device. below more information. Controlled Programmable This weak internal pull-up device. below more information. Controlled Programmable This weak internal pull-up device. below more information. Controlled Programmable This weak internal pull-up device. below more information. Controlled Programmable This weak internal pull-up device. below more information. Controlled Programmable This weak internal pull-up device. below more information. Controlled Programmable This weak internal pull-up device. below more information.
Serial Memory (EEPROM) Port
Name SDATA
PQFP
TQFP
I/O/Z I/O/Z I/O/Z
Description Serial Data Clock. This weak internal pull-up device. below more information. Serial Data Enable Control. This weak internal pull-up device. below more information. Bidirectional Serial Data. This weak internal pull-up device. below more information.
REV.
-11-
AD1801
Interface/PCMCIA Interface
Name SD15 SD14 SD13 SD12 SD11 SD10 SA11 SA10 Name IOCS16/IOIS16 SA12/OE SA13/WE SA14/INT1 SA15/CE1 SBHE/CE2 AEN/REG IRQ9/IREQ IOCHRDY/WAIT IRQ3/VCTL1/ EXTRD
PQFP PQFP
TQFP TQFP
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
Description System Data System Data System Data System Data System Data System Data System Data System Data System Data System Data System Data System Data System Data System Data System Data System Data System Address System Address System Address System Address System Address System Address System Address System Address System Address System Address System Address System Address System Read Strobe. System Write Strobe. Description System 16-Bit Card Indicator. System Address System Address System Address System Address System Byte High Enable. System Address Valid Indicator. System Interrupt Request Mapped IRQ9. System Cycle Extension Control. System Interrupt Request Mapped IRQ3. PCMCIA Description System 16-Bit Card Indicator. System Attribute Space Read Control. System Memory Space Write Control. Function Interrupt Request. System Card Enable System Card Enable System Attribute Space Select. System Interrupt Request/Ready Indicator. System Cycle Extension Control. Reflects opposite state PCMCIA COR1 Register COR1 defaults "0," this defaults Read Strobe interfacing External Functions, such SMC91C94. below more information. System Read Cycle Acknowledgment. System Status Bit. Digital Audio Binary Waveform Driving Host's Loudspeaker.
IRQ4/INPK IRQ5/CHG IRQ7/SPKR
System Interrupt Request Mapped IRQ4. System Interrupt Request Mapped IRQ5. System Interrupt Request Mapped IRQ7.
-12-
REV.
AD1801
Interface/PCMCIA Interface (Continues)
Name IRQ10/CS1 IRQ11/RS1 IRQ12/PD1 IRQ15/VCTL2/ EXTWR
PQFP
TQFP
Description System Interrupt Request Mapped IRQ10. System Interrupt Request Mapped IRQ11. System Interrupt Request Mapped IRQ12. System Interrupt Request Mapped IRQ15.
PCMCIA Description Function Chip Select. Function Reset. Function Power-Down Control. Reflects opposite state PCMCIA COR2 Register COR2 defaults "0," this defaults Write Strobe interfacing External Functions, such SMC91C94. below more information.
Reset Signals
Name RESET RESET
PQFP
TQFP
Description Reset. RESET active assertion this signal will initialize on-chip registers their default values. Power-Up Reset. RESET active assertion this signal will initialize on-chip registers their default values.
Serial Port (SPORT)/External Function Port
Name SCLK RFS/CS2 TFS/RS2 DR/INT2 DT/PD2
PQFP
TQFP
SPORT Interface Serial Clock. Receive Frame Sync. Transmit Frame Sync. Serial Data Receive. Serial Data Transmit.
External Function Port Function Chip Select. Function Reset. Function Interrupt Request. Function Power-Down Control.
Boundary Scan JTAG Interface
Name
PQFP
TQFP
Description Boundary Scan Function Mode Select. This weak internal pullup device. below more information. Boundary Scan Function Clock. This weak internal pullup device. below more information. Boundary Scan Function Data Input. This weak internal pullup device. below more information. Boundary Scan Function Data Output. Boundary Scan Function Reset. This weak internal pull-up device. below more information. must connected digital ground (dissipates small amount power) RESET (recommended) ensure reliable operation.
Analog Signals
Name RCVP RCVN HSPKRP HSPKRN LOUT XMITP XMITN MSPKR
PQFP
TQFP
Description Receive Line Input Positive Differential Signal. Receive Line Input Negative Differential Signal. Handset Microphone Mono Input. This signal either line level from line level. Line Level Single-Ended Input. Handset Speaker Output Positive Differential Signal. Handset Speaker Output Negative Differential Signal. Line Level Single-Ended Output. Transmit Output Positive Differential Signal. Transmit Output Negative Differential Signal. Monitor Speaker Single-Ended Output.
REV.
-13-
AD1801
Crystal Power-Down Signals
Name XTALI
PQFP
TQFP
Description 16.9344 Crystal Input. When using crystal clock source, crystal should connected between XTALI XTALO pins. This crystal should 16.9344 normal sampling rate range, i.e., 44.1 kHz. clock input driven into XTALI place crystal. 16.9344 Crystal Output. When using crystal clock source, crystal should connected between XTALI XTALO pins. clock driven directly into XTALI, then XTALO should left unconnected. Power-Down Control. active Power-Down Acknowledge.
XTALO PWDACK
Voltage Reference
Name CMOUT
PQFP
TQFP
Description Common-Mode Voltage Output. Nominal 2.25 volt reference available externally coupling level-shifting. CMOUT should used where will sink source current. tantalum capacitor parallel with ceramic capacitor required. Voltage Reference Filter. Voltage reference filter point external bypassing only. tantalum capacitor parallel with ceramic capacitor required.
VREF
Filter Connections
Name FILT
PQFP
TQFP
Description Filter. This requires capacitor analog ground proper operation. Monitor Speaker Filter. This requires capacitor analog ground proper operation.
Power Supplies Connects
Name AVDD AGND
PQFP
TQFP
Description Analog Supply Voltage 5%). Analog Ground. Digital Supply Voltage 5%).
DVDD
DGND
Digital Ground.
Pull-Up Resistors: Pins PCM-ISA, PNP_STD, IO[7:0], SEN, SDATA, SCK, TCK, TDI, have internal pull-up devices. pull-up device consists weak PMOS transistor that will source anywhere from current when held volts, depending operating temperature voltage.
-14-
REV.
AD1801
MIXED SIGNAL FUNCTIONAL DESCRIPTION
FEATURES Modem V.34/V.34bis modem codec (Analog Front-End [AFE]) with 10/7 programmable sample rates from kHz, using times oversampled, singlebit sigma-delta data conversion. Support V.34 symbol sample rates, including 10/7 symbol rates from single external 16.9344 crystal clock. Differential analog to/from modem highest signal quality. Programmable gain amplifier modem receive input with gain. Programmable attenuator modem transmit output, with typical step size.
DIGITAL FUNCTIONAL DESCRIPTION
FEATURES ADSP-2181 microcomputer core: 16.9344 crystal, 33.8688 MIPS sustained performance. Internal memory: bits boot/program ROM, bits program RAM, bits data RAM, bits dual port PCMCIA card configuration (Card Information Structure [CIS]) data tables Plug Play (PnP) resource data. Host interface option: 16-bit 16-bit PCMCIA Card bus. compliant single function Plug Play (PnP) option. PCMCIA Card interface multifunction card configuration controller Card multifunction compliant). PCMCIA interface supports external card function ports interfacing communications ICs, e.g., ethernet controllers ISDN devices. Five synchronous serial port (SPORT) option over second external function port external serial communications with (communication modem handset lost). Internal controller handling host program code download data download/upload operations into internal memory. Eight programmable lines under control. Power management: hardware software controlled power-down modes with ring awakening option. Programmable interrupt requests.
Handset Full featured audio/handset codec (AFE) with programmable sample rates from kHz, using times oversampled, single-bit sigma-delta data conversion.
Selectable gain block condenser microphones selectable line input. Selectable line output differential analog output handset speaker. Programmable gain amplifier input, +22.5 with typical step size. Programmable gain amplifier/attenuator output -34.5 with typical step size full analog mute.
Monitor Speaker Sixteen word output FIFO minimize overhead.
Sigma-delta with sample rates tied either modem codec handset codec. Programmable attenuator output with attenuation, full analog mute. Output buffer drive external monitor speaker.
REV.
-15-
AD1801
AD1801 comprises 21xx family core, data memory, program memory, bytes words boot/program ROM. Please refer ADSP-2181 Microcomputer data sheet (Analog Devices publication C2041a-4-12/95) additional information ADSP-2181 core, memory peripheral features, functions. This data sheet makes attempt document
DIGITAL ARCHITECTURAL OVERVIEW
ADSP-2181 core AD1801. Figure illustrates ADSP-2181 functional block diagram. Figure functional block diagram unique Windows® modem function AD1801. controller interfaces directly ADSP-2181's Internal (IDMA) port.
ADSP-2181
INSTRUCTION REGISTER PROGRAM SRAM DATA SRAM BYTE CONTROLLER
POWER-DOWN CONTROL LOGIC PROGRAMMABLE
DATA ADDRESS GENERATOR
DATA ADDRESS GENERATOR
PROGRAM SEQUENCER
FLAGS EXTERNAL ADDRESS
EXTERNAL DATA
EXCHANGE
INPUT REGS INPUT REGS
INPUT REGS INPUT REGS
INPUT REGS SHIFTER
COMPANDING CIRCUITRY TIMER FIFO FIFO FIFO FIFO
OUTPUT REGS OUTPUT REGS
INTERNAL PORT
OUTPUT REGS OUTPUT REGS
OUTPUT REGS
SERIAL PORT
SERIAL PORT
INTERRUPTS
Figure ADSP-2181 Block Diagram
SCLK SDATA
SERIAL MEMORY EEPROM PORT
TIMING CONTROL
PROGRAMMABLE
(7:0)
SYSTEM ADDRESS ADDRESS SYSTEM DATA DATA
(15:0)
(10:0)
(15:0)
(15:0)
SYNCHRONOUS SERIAL PORT EXTERNAL FUNCTION PORT EXTERNAL FUNCTION PORT RING PCMCIA CARD CONFIGURATION INTERFACE CONTROLLER
PLUG PLAY CARD CONFIGURATION INTERFACE CONTROLLER
CONTROLLER
IDMA
Figure AD1801 Windows Modem Functional Block Diagram
Windows registered trademark Microsoft Corporation.
-16-
REV.
AD1801
ADSP-2181 (DSP) INTERFACE External Plug Play Card Configuration Controller
Windows modem function block interfaces ADSP2181's external peripheral give access control registers, status bits ports. Note that physical connections this interface made completely inside AD1801. 7-bit base address A[10:4], starting address 0x000 (see Table VII), plus 4-bit destination address, A[3:0], decoded inside Windows modem function. operation qualified active IOMS signal initiated DSP. bits external data bus, D[15:0], used passing data into Windows modem block; direction determined memory enables controls wait states required internal operations.
Internal Port
AD1801 Plug Play (PnP) module provides nine output enables interrupt request pins, only which active after configuration session. module also determines card's 7-bit memory base address provides internal "card select" signal whenever host accesses AD1801 programmable register general purpose port. PNP_STD control input left unconnected tied enable this function. single function module AD1801 meets Microsoft's requirements. This means that provides minimum seven base locations interrupts well performing full 16-bit address decode. Since PCMCIA mode only single interrupt request required, interrupt request pins redefined when AD1801 configured PCMCIA mode. These dual function pins listed Table below. Since PCMCIA requirements exceed minimum requirements, additional interrupt requests readily accommodated reflected table. addition, AD1801 provides core with means take function "off line" permit access internal registers. This allows option configuring card power-up, effectively bypassing card configuration sequence.
Table PCMCIA Signal Mapping
Windows modem function block interfaces ADSP2181's internal port provide host with means access on-chip program data memory. This communications path crucial operation AD1801; handles back-to-back host read write operations active interface, i.e., sustains data transfers 4.17 Mbytes/s over 16-bit data Mbytes/s over Card 16-bit data bus. This interface consists 16-bit multiplexed address/data (IAD[15:0]), port read (IRD), write (IWR), address latch (IAL) start (IS) control pins plus acknowledge (IACK) output.
Timing Control
Windows modem block AD1801 uses maximum 33.8688 clock output generated core from external 16.9344 source. external power-on reset circuit host reset provides reset both core Windows modem blocks; this forces reboot from internal ROM, rebuild table small internal RAM, initialize various Windows modem programmable registers. RING input used interrupt DSP; second interrupt generated Windows modem Timing Control block under host program control. selectively enable/disable ring detection interrupt Control Register.
Platform Compatible Host
AD1801 Name IRQ9/IREQ IRQ3 IRQ4/INPK IRQ5/CHG IRQ7/SPKR IRQ10/CS1 IRQ11/RS1 IRQ12/PD1 IRQ15
Signal IRQ9 IRQ3 IRQ4 IRQ5 IRQ7 IRQ10 IRQ11 IRQ12 IRQ15
PCMCIA External Function Signal Port-1 Signal IREQ INPACK STSCHG SPKR
AD1801 targeted add-on slave card designs. provides glueless interface whenever PCM_ISA control input tied drivers compliant with interface, electrical switching drive capability specifications. particular, "fast" outputs used collectively they induce glitches onto other controls when they simultaneously switched.
16-Bit Data Interface
AD1801's data address maintained Timing Control block, Controller used access data from DSP's data memory without interrupting DSP, thus stealing more than single cycle transfer. This desirable since data request occur time during normal operations.
Standard Mode Compatibility
AD1801's interface meets timing specifications defined 16-bit data standard access cycles. This interface consists 16-bit address (SA[15:0]), 16-bit data (SD[15:0]), read write strobes (IOR IOW), hardware reset RESET, IOCHRDY/WAIT, IOCS16/IOIS16, nine interrupt requests. interrupts selected card when configured; others remain high impedance state allow other cards their use. AD1801's Control register serves interrupt request logic state totally under program control. Control register allows host disable interrupt requests. REV.
Standard mode select input, PNP_STD, used enable/disable logic module. tied DVDD left unconnected enable logic tied DGND supported. internal pull-up ensures that state seen when left unconnected. This input available read. This allows implementation schemes that require determine suitable space base address interrupt slave card when standard mode active. must program 13-bit Default Base Address register with 13-bit Memory Base address 4-bit Default Interrupt Select register selecting active output. These registers located AD1801's Timing Control block active whenever inputs PNP_STD PCM_ISA tied DGND. -17-
AD1801
PCMCIA Platform Compatible Host
AD1801 also targeted PCMCIA's Card Standard slave card designs. provides glueless interface Card whenever PCM_ISA control input unconnected tied DVDD. internal pull-up allows this left unconnected this mode.
PCMCIA 16-Bit Card Interface
AD1801's Card interface meets timing specifications defined PCMCIA's Card Standard both memory access cycles. This interface consists 12-bit address (SA[11:0]), 16-bit data (SD[15:0]), read write strobes (IOR IOW), card enables (CE1 CE2), hardware reset (RESET), memory read write strobes WE), attribute memory select (REG), interrupt/ready control (IOIS16) read cycle acknowledge control (INPK).
PCMCIA Card Configuration Controller
card's modem function implemented primarily within AD1801. RING input used activate PCMCIA's STSCHG status line notify host ringing phone line. host must Req_AttnEnab SigChg bits AD1801's Extended Status register Card Configuration Status register, respectively, activate this feature. binary audio waveform, SPKR, available lieu output. This signal intended drive host's loudspeaker. Mb/sec bitstream from monitor speaker sigma delta engine provides binary audio data stream this pin. host must Audio Card Configuration Status register enable this output. AD1801 provides external function ports supporting limited control communications ICs, such ethernet controller ISDN devices, example. Each external function port will consist function reset, chip select, address latch control, power-down control, function interrupt input. This interrupt will passed host particular function enable interrupt enable controls activated. AD1801 also generates read write strobes facilitate data transfers between host communication Strobe timing designed meet timing requirements Standard Microsystems Corporation's SMC91C94 Ethernet Controller whenever External Function accessed host host PC's read write strobes will passed through AD1801 whenever External Function accessed host Table identifies PCMCIA Function Configuration registers needed support each card function.
This module supports three card functions. Multiple function Cards require separate Configuration registers function. Primary common functions plus separate Secondary CIS's, function, also required. Data Card Information Structures (CISs) loaded into internal 512-byte during bootstrap loading. obtain data needs from both internal and, card-specific data, from external serial EEPROM. sets control AD1801 indicate that initialization completed. does have read access memory. host read memory time. needed, WAIT control activated extend read operation meet cycle timing specifications. host does have write access memory.
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REV.
AD1801
Table PCMCIA Function Configuration Registers
Function Configuration Registers Number Card Configuration Status Register Replacement Register Socket Copy Register reserved Extended Status Register Base Address Registers (7:0) (15:8) (23:16) (31:24) Size Register (7:0) 3-BIT COPY NUMBER 3-BIT SOCKET NUMBER RsvdEvt3 RsvdEvt2 RsvdEvt1 ReqAttnEvt RsvdEnab3 RsvdEnab2 RsvdEnab1 ReqAttnEnab BASE BASE BASE BASE SIZE Name SRESET LevlREQ vendor option vendor option vendor option IREQ BASE FUNC. Chng SigChg IOis8 defined Audio PwrDn Intr IntrAck CBVD1 CBVD2 CRdy CWProt RBVD1 RBVD2 RREADY RWProt Required Registers Bits Internal Modem External Function External Function Function Port-1 Port-2
Name
Configuration Option Register
*Not Implemented, Reads Writes Ignored.
REV.
-19-
AD1801
registers PCMCIA Attribute Memory Space (0x200 0x27F) will read ignore writes unless specifically documented sections below.
Table III. PCMCIA Transaction
Transaction Type Read Write Attribute Memory Read Attribute Memory Write
IORD
IOWR
CYCLE TIME
CYCLE TIME
ADDR SA[15:0]
ADDR SA[15:0]
DATA SD[15:0]
D7:D0 (EVEN BYTE)
DATA SD[15:0]
D7:D0 (EVEN BYTE)
SETUP
COMMAND
HOLD
SETUP
COMMAND
HOLD
Figure PCMCIA Attribute Memory Read Transfer
Figure PCMCIA Attribute Memory Write Transfer
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REV.
AD1801
CYCLE TIME (255
CYCLE TIME (255
ADDR SA[15:1]
ADDR SA[15:1]
IORD
IORD
IOWR
IOWR
IOIS16
IOIS16
WAIT
WAIT
DATA SD[15:0]
D7:D0 (EVEN BYTE)
DATA SD[15:0]
D7:D0 (EVEN BYTE)
SETUP
COMMAND
RECOVERY
SETUP
COMMAND
RECOVERY
Figure PCMCIA Default Read Cycle
Figure PCMCIA Default Write Cycle
REV.
-21-
AD1801
CYCLE TIME (255
CYCLE TIME (255
ADDR SA[15:1]
ADDR SA[15:1]
IORD
IORD
IOWR
IOWR
IOIS16
IOIS16
WAIT
WAIT
DATA SD[15:0]
D15:D0 (WORD)
DATA SD[15:0]
D15:D0 (WORD)
SETUP
COMMAND
RECOVERY
SETUP
COMMAND
RECOVERY
Figure PCMCIA 16-Bit Word Read Cycle
Figure PCMCIA 16-Bit Word Write Cycle
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REV.
AD1801
Interrupt Architecture
signals used generating interrupts shown Table
Table Interrupt Architecture
Pins PCM_ISA RING INT1 INT2 PCMCIA/ Signals Func0En Func1En Func2En IntrACKx
Description Indicates that AD1801 PCMCIA mode mode. Falling edge signal indicates ring interrupt. External Function interrupt request pin. Assumed level signal IntrACK1 edge IntrACK1 External Function interrupt request pin. Assumed level signal IntrACK2 edge IntrACK2 Description PCMCIA mode, Func0En "Enable Function" Configuration Option Register, COR0[0]. mode, Func0En "active" logical device zero. PCMCIA mode, Func1En "Enable Function" Configuration Option Register, COR1[0]. mode, Func1En deasserted. PCMCIA mode, Func2En "Enable Function" Configuration Option Register, COR2[0]. mode, Func2En deasserted. PCMCIA defined that determines mode clearing interrupts. When IntrACKx interrupts cleared function (i.e., Host writing bits). When IntrACKx interrupts cleared Intr (CSRx[1]). IntrACKx CSRx[0]. assertion three IntrACKs (from three registers) will cause entire part behave three IntrACKs were asserted. Reads IntrACK bits will always return what written. CSR0[1]. Reads Intr0 indicate DSP/RING interrupt asserted even interrupt enable (IREQ0En) deasserted. CSR1[1]. Reads Intr1 indicate external Function interrupt asserted even interrupt enable (IREQ1En) deasserted. CSR2[1]. Reads Intr2 indicate external Function interrupt asserted even interrupt enable (IREQ2En) deasserted. write Intr0 bit, CSR0[1]. When IntrACK0 this causes both RING interrupts clear. When IntrACKx write effect. write Intr1 bit, CSR1[1]. When IntrACK1 this causes External Function (INT1) interrupt clear. When IntrACK1 write effect. write Intr2 bit, CSR2[1]. When IntrACK2 this causes External Function (INT2) interrupt clear. When IntrACK2 write effect. Host writable PCMCIA control registers) that enables DSP/RING interrupts IREQ# pin. PCMCIA mode only. (Created from COR0[2].) Host writable PCMCIA control registers) that enables External Function interrupts IREQ# pin. PCMCIA mode only. (Created from COR1[2].) Host writable PCMCIA control registers) that enables External Function interrupts IREQ# pin. PCMCIA mode only. (Created from COR2[2].) Nine versions this signal exists each nine interrupt levels possible; assertion mutually exclusive. IRQSELn signals created from level register.
Intr0 Intr1 Intr2 Intr0 Intr1 Intr2 IREQ0En IREQ1En IREQ2En IRQSELn
REV.
-23-
AD1801
Table Interrupt Architecture (Continued)
Accessible Signals PCIRQ DSPIX RNGIX
Description writable request interrupt system bus. writable acknowledge/clear interrupt. Interrupt acknowledged/cleared when DSPIX "1." Writing this effect when PCMCIA mode with IntrACK0 writable acknowledge/clear RING interrupt. Writing this effect when PCMCIA mode with IntrACK0
Host Accessible Signal (Not Including Those PCMCIA/PnP Registers) DSPIE RNGIE DSPI RNGI DSPIA RNGIA
Description Host writable which enables interrupts. Host writable which enables RING interrupts. Host readable which indicates whether interrupt pending from DSP. Host readable which indicates whether interrupt pending from RING pin. Host writable acknowledge/clear interrupt. Writing this effect when PCMCIA mode with IntrACK0 Host writable acknowledge/clear RING interrupt. Writing this effect when PCMCIA mode with IntrACK0
Table Interrupt Mapping
Interrupt Source
Interrupt Vector Address 0x2000 (ROM) 0x002C (RAM) 0x0004 (RAM) 0x0008 (RAM) 0x000C (RAM) 0x0010 (RAM) 0x0014 (RAM) 0x0018 (RAM) 0x0020 (RAM) 0x0024 (RAM) 0x0028 (RAM)
Comment Highest Priority Triggered Writing Register Triggered Rising Falling Edge Triggered While PWRDN CSR0
RESET Power Down Host (IRQ2) (IRQL1) PCMCIA Power-Down (IRQL0) SPORT Transmit SPORT Receive RING (IRQE) SPORT Transmit SPORT Receive Timer
Triggered Falling Edge RING
Lowest Priority
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REV.
AD1801
!FUNC0EN DSPIE PCIRQ DSPIX DSPIA INTR0 (WR=0) (PCMCIA INTRACK0) !FUNC0EN RNGIE RING RNGIX RNGIA INTR0 (WR=0) (PCMCIA INTRACK0) IRQSEL4 !FUNC1EN !PCMCIA+!INTRACK1 INT1 IRQSEL7 (PCMCIA INTRACK1) !FUNC2EN !PCMCIA+!INTRACK2 INT2 IRQSEL12
DSPI
500ns DELAY ARBITER
STICKY LATCH
INTR0
IREQ0EN RNGI PNPIRQnEN PCMCIA IRQSEL3
IREQ (PCMCIA)
STICKY LATCH
IRQ3 (ISA) IRQ4 (ISA)
IRQSEL5 STICKY LATCH
IRQ5 (ISA) IRQ7(ISA) IRQ9 (ISA)
INTR1 (WR=0)
INTR1 IRQSEL9 IREQ1EN IRQSEL10 IRQ10 (ISA) IRQ11(ISA) IRQ12 (ISA) IRQ15 (ISA)
IRQSEL11
STICKY LATCH INTR2 (WR=0) INTR2
IRQSEL15 IREQ2EN
(PCMCIA INTRACK2)
Figure Interrupt Structure
Controller
AD1801's Controller block ensures that both program code data supplied host loaded into onchip memory efficient manner. address counter IDMA Port facilitate block transfers using auto incrementing mechanism. host uses locations memory transferring data from on-chip program/data memory. location allows host effective access IDMA Control (IDMAC) register. This register used host program 14-bit memory address counter (register bits 13:0) 1-bit destination indicator (Register 14). This register needs only programmed once block transfers to/from same type memory, since address counter automatically incremented each IDMA read/write operation. destination indicator programmed whenever host wishes access data memory, otherwise program memory will accessed. second location reserved 16-bit data word provided supplied host This location mapped read-only Memory Data Input (MDI) register write-only Memory Data Output (MDO) register. When accessing 24-bit program memory, host read write cycles from MDO, respectively, required. first program memory access, numbered access following IDMAC register update applies Most Significant (MS) bits 24-bit program data word
(Bits 23:8). second access, even numbered access following IDMAC register update applies Least Significant (LS) eight bits 24-bit program word (Bits 7:0). Bits MDO(15:8) ignored AD1801 this case write operations; host will receive valid data MDI(7:0) read operations. IDMA address counter incremented until after byte portion 24-bit program data word been addressed. IDMAC register updated before second half program data read/write operation executed, capability access byte previous address value will lost; controller will access bits data address during following program memory read/write operations. When accessing data memory, only single read write cycle required since 16-bit memory words accommodated bus, IAD(15:0), host data bus, SD(15:0); however, IDMAC register must programmed first controller know that next host initiated memory access cycles targeted data memory define starting address. IDMAC register incremented upon completion each successive write/read operation to/from memory data registers, MDI. Controller able provide host with data without wait states back-to-back read write operations. continues full speed while synchronization achieved over cycle request; only then single cycle stolen from DSP. entire
REV.
-25-
AD1801
cycle take from maximum cycles complete. cycles required synchronization, then there half cycle setup time IACK control, followed single data transfer cycle. data cannot presented onto Card within from falling edge read strobe using either long short IDMA Read Cycle timing, data prefetch mechanism every address counter update will required. Internal holding registers used, essentially, create 1-word deep FIFO create word register pair employing ping-pong access arrangement, order meet Card timing requirements.
Synchronous Serial Port JTAG Scanning Logic
JTAG boundary scan logic included AD1801. AD1801 compliant with IEEE std. 1149.1a-1993. Only mandatory instructions supported. These are: BYPASS, SAMPLE/PRELOAD, EXTEST. Scan order, from first last follows.
Table JTAG Scan Order
PCM_ISA PNP_STD RESET RESET ERESET TESTB (DVDD) ELIN EINT ECLK OutEn ELOUT OutEn OutEn OutEn OutEn OutEn OutEn OutEn OutEn OutEn SDATA OutEn SDATA OutEn RING XTALI XTALO PWDACK DR/INT2 RFS/CS2 OutEn RFS/CS2 DT/PD2 OutEn DR/PD2 TFS/RS2 OutEn TFS/RS2 SCLK OutEn SCLK SD15 OutEn SD15 SD14 OutEn SD14 SD13 OutEn SD13 SD12 OutEn SD12 SD11 OutEn SD11 SD10 OutEn SD10 OutEn OutEn OutEn OutEn OutEn OutEn OutEn OutEn OutEn OutEn IOCS16/IOIS16 OutEn IOCS16/IOIS16 IRQ15/VCTL2 OutEn IRQ15/VCTL2 IRQ12/PD1 OutEn IRQ12/PD1 IRQ11/RS1 OutEn IRQ11/RS1 IRQ10/CS1 OutEn IRQ10/CS1 IRQ9/IREQ OutEn IRQ9/IREQ IRQ7/SPKR OutEn IRQ7/SPKR IRQ5/CHG OutEn IRQ5/CHG IRQ4/INPK OutEn IRQ4/INPK IRQ3/VCTL1 OutEn IRQ3/VCTL IOCHRDY/WAIT OutEn IOCHRDY/WAIT AEN/REG SBHE/CE2 SA15/CE1 SA14/INT1 SA13/WE SA12/OE SA11 SA10
AD1801 provides external synchronous serial port (identical SPORT module ADSP-2181) that optionally selected place second external function under PCMCIA module's control. Port Mode (PM) Control register used select enable option.
Power-Down Modes
power-down control pins, PWDACK, available ADSP-2181, brought AD1801 provide hardware option putting core power state. active PWDACK control indicates when processor powered down; deactivated when processor completed power-up sequence. logic this also indicates that processor's CLKOUT signal valid that program execution begun.
General Purpose Port
AD1801 provides eight bits general I/O, IO(7:0), that programmed DSP. Port Control (IPC) register determines port direction; logic sets port output while logic sets port input. Each port tied internal weak pull-up resistor. AD1801 provides single 8-bit output port register that programmed DSP. Input port bits registered; they simply passed onto data (D[15:0]) during active read operations accessing Input Port. Note that will read internally generated output port bits that active along with active externally supplied input port bits. eight programmable pins AD1801 (Pins through will source between when they three-stated. This feature provides weak pull-up capability from power-on. This current sourcing capacity should only used determine fast AD1801 will pull much current devices driving AD1801's pins need sink drive logic When configured outputs, pins will source level output voltage) will sink level output voltage). They conservative ratings edge transitions with load.
NOTE JTAG input (Pin 122) must connected digital ground (which dissipates small amount power on-chip weak pull-up device) RESET (recommended) ensure reliable AD1801 operation.
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REV.
AD1801
Emulation Mode (EZ-ICE Port)
Unlike ADSP-2181, which ignores normal (non-emulator) reset when emulator mode, AD1801 reset sources still functional when emulator mode. This includes RESET (ISA reset), RESET (power-up reset), (Host reset) mapped register PCC, reset, PCMCIA reset. result, order avoid erroneous emulator results, care must taken prevent assertion these resets during periods time when emulator actually takes control core. 14-pin EZ-ICE port interface should connected AD1801 indicated below.
Table VII. Emulator Connections
MAPPED REGISTER DESCRIPTIONS Memory
AD1801 interface uses base address determined during initialization period allow host access internal registers ports according table below. base address will correspond system address bits (15:3) when AD1801 "ISA" mode bits (11:3) when AD1801 "PCMCIA" mode.
Table VIII. Memory
System Address Bits [11:3] Base Addr Base Addr Base Addr Base Addr Resource Accessed Reads Writes Reserved IDMAC Function Host Status Control Internal Address Memory Data Test Mode
EZ-ICE Connector EINT "key" ELIN ELOUT ECLK RESET ERESET
AD1801 Connection Digital (Not Analog Supply) Connect (Pin Digital (Not Analog Supply) (Pin EINT (Pin Connect ELIN (Pin ELOUT (Pin ECLK (Pin (Pin (Pin Digital (Not Analog Supply) ERESET (Pin
Attribute Memory
Attribute memory space defined PCMCIA AD1801 configurations only. registers PCMCIA Attribute Memory Space (0x200 0x27F) will read ignore writes unless specifically documented. AD1801 provides three PCMCIA Functions. Function completely contained AD1801 chip (i.e., fax/data/ voice modem), while Functions implemented externally AD1801 supported with pins.
Table Attribute Memory
with ADSP-2181, AD1801 emulation pins (Pins 25-32) should floated when connected EZ-ICE port. Within AD1801 there pull-down resistor (emulation enable) which disables emulation mode when floated. Note that ADSP-2181 chip includes emulator signals found (and required) AD1801 (Bus Grant) (Bus Request). Under normal ADSP-2181 operation, external device interrupt bus. This done with pins; external device asserts ADSP-2181 asserts when available. same scenario with EZ-ICE system, EZ-ICE takes signal, request, generates ADSP-2181. ADSP-2181 then asserts EBG, which emulator pass external device During emulator mode, ADSP-2181 ignores three-states that emulator drive instead). Since AD1801 does allow external devices connected core, there need signals. When using emulator, should wired deasserted (HI) emulator connector.
System Address 0x000-0x3FF 0x400 0x402 0x406 0x408 0x40A 0x40C 0x412 0x440 0x442 0x446 0x44A 0x44C 0x452 0x480 0x482 0x48A 0x48C 0x492
Register/RAM Accessed Name Valid Operation COR0 CSR0 SCR0 ESR0 IOBL0 IOBH0 IOS0 COR1 CSR1 SCR1 IOBL1 IOBH1 IOS1 COR2 CSR2 IOBL2 IOBH2 IOS2 Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
EZ-ICE registered trademark Analog Devices, Inc.
REV.
-27-
AD1801
PCMCIA Configuration Option Registers COR0: PCMCIA Function Configuration Register
Data SRESET Data LevlReq Data ConfIndex[5] Data ConfIndex[4]
Access: Read/Write
Data ConfIndex[3] Data ConfIndex[2] Data ConfIndex[1]
Address: 0x400
Data ConfIndex[0]
SRESET
Function Software Reset. Setting this places AD1801 reset state. This equivalent assertion hardware RESET signal except that this cleared. Resetting this leaves AD1801 same state that follows hardware reset. This reset power-up hardware reset. This sticky. Function Level Mode IREQ. Level mode interrupts defined when this "1." Pulse mode (edge triggered) interrupts defined when this "0." This hardcoded (level mode interrupts). Configuration Index Bits through defined "vendor specific" used control anything AD1801. These bits written read general scratchpad purposes. Configuration Index enables IREQ routing. When "1," IREQ interrupts enabled Function When reset "0," IREQ interrupts disabled Function This valid only when ConfIndex[0] (Function Enable) (enabled). Configuration Index specifies addressing used. When "1," addresses specified base limit registers passed Function When reset "0," host addresses passed Function This valid only when ConfIndex[0] (Function Enable) (enabled). Configuration Index enables disables Function When "1," Function enabled. When reset "0," Function disabled does decode addresses generate IREQ.
Access: Read/Write
Data ConfIndex[4] Data ConfIndex[3] Data ConfIndex[2] Data ConfIndex[1]
LevlReq ConfIndex[5:3] ConfIndex[2]
ConfIndex[1]
ConfIndex[0]
COR1: PCMCIA Function Configuration Register
Data SRESET Data LevlReq Data ConfIndex[5]
Address: 0x420
Data ConfIndex[0]
SRESET LevlReq ConfIndex[5:3] ConfIndex[2]
Function Software Reset. Setting this drives IRQ11/RS1 output signal from AD1801 IRQ11/RS1 Function reset signal when AD1801 configured PCMCIA mode. Function Level Mode IREQ. Level mode interrupts defined when this "1." Pulse mode (edge triggered) interrupts defined when this "0." This hardcoded (level mode interrupts). Configuration Index Bits through defined "vendor specific" used control anything AD1801. These bits written read general scratchpad purposes. Configuration Index enables IREQ routing. When "1," IREQ interrupts enabled Function When reset "0," IREQ interrupts disabled Function This valid only when ConfIndex[0] (Function Enable) (enabled). Configuration Index specifies addressing used. When "1," addresses specified base limit registers passed Function When reset "0," host addresses passed Function This valid only when ConfIndex[0] (Function Enable) (enabled). Configuration Index enables disables Function When "1," Function enabled. When reset "0," Function disabled does decode addresses generate IREQ.
Access: Read/Write
Data ConfIndex[4] Data ConfIndex[3] Data ConfIndex[2] Data ConfIndex[1]
ConfIndex[1]
ConfIndex[0]
COR2: PCMCIA Function Configuration Register
Data SRESET Data LevlReq Data ConfIndex[5]
Address: 0x440
Data ConfIndex[0]
SRESET LevlReq ConfIndex[5:3] ConfIndex[2]
Function Software Reset. Setting this drives TFS/RS2 output signal from AD1801 SCLK/ Function reset signal when AD1801 configured PCMCIA mode. Function Level Mode IREQ. Level mode interrupts defined when this "1." Pulse mode (edge triggered) interrupts defined when this "0." This hardcoded (level mode interrupts). Configuration Index Bits through defined "vendor specific" used control anything AD1801. These bits written read general scratchpad purposes. Configuration Index enables IREQ routing. When "1," IREQ interrupts enabled Function When reset "0," IREQ interrupts disabled Function This valid only when ConfIndex[0] (Function Enable) (enabled).
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REV.
AD1801
ConfIndex[1] Configuration Index specifies addressing used. When "1," addresses specified base limit registers passed Function When reset "0," host addresses passed Function This valid only when ConfIndex[0] (Function Enable) (enabled). Configuration Index enables disables Function When "1," Function enabled. When reset "0," Function disabled does decode addresses generate IREQ.
Access: Read/Write
Data Audio Data PwrDn Data Intr
ConfIndex[0]
PCMCIA Card Configuration Status Registers CSR0: PCMCIA Function Configuration Status Register
Data Chng Data SigChg Data IOis8 Data Res(0)
Address: 0x402
Data IntrAck
Chng
Status Change Detected. This indicates that more Replacement register bits (CBVD1, CBVD2, CRDY CWProt) one, normally causing signal (Pin asserted; however, SigChg (see below) "1," card configured interface, asserted when this set. Signal Change Enable/Disable. This reset host enable disable status change signal from status register. When this card configured interface, Chng controls (CHG). status change signal desired, should zero signal will held deasserted when card configured I/O. Cycles Occur Only 8-Bit Transfers. When host provide cycles only using SD7:SD0 data path, PCMCIA software will this card guaranteed that accesses 16-bit registers will occur byte accesses rather than single 16-bit access. This information useful when 16-bit 8-bit registers overlap. AD1801, this hardcoded (16-bit transfers allowed). Reserved bits must Audio Enable. This enables audio information sent Host Adapter speaker SPKR (Pin when configured interface. Power-Down. This request that Function enter power-down state. PCMCIA software must place Function into power-down state while Function's READY (busy) state. Interrupt Request Pending. This represents internal state interrupt request. This value available whether interrupts have been configured. Intr cleared dependent IntrAck configured. IntrAck 0-Intr reflects function's interrupt request status. interrupt cleared within function, Intr reset function. IntrAck 1-Intr remains even though interrupt condition been cleared (i.e., sticky). reset system software indicate ready receive another interrupt (implemented support interrupt sharing).
SigChg
IOis8
Audio PwrDn Intr
IntrAck
Interrupt Acknowledge. This determines response Intr bit. functionality associated with IntrAck permits more functions share Card's IREQ pin. IntrAck 0-When IntrAck reset, Intr functions described above support single interrupt implementation. IntrAck 1-This causes Intr remain even though interrupt service routine already serviced interrupt. Normally, interrupt service routine clears interrupt pending function specific register, causing Intr also cleared; however, support interrupt sharing, Intr cleared until PCMCIA specific software ready handle next interrupt request. When cleared PCMCIA software, other interrupt requests that pending asserted over Card's IREQ pin.
CSR1: PCMCIA Function Configuration Status Register
Data Chng Data SigChg Data IOis8 Data Res(0)
Access: Read/Write
Data Audio Data PwrDn Data Intr
Address: 0x422
Data IntrAck
Chng
Status Change Detected. This indicates that more Replacement register bits (CBVD1, CBVD2, CRDY CWProt) one, normally causing signal (Pin asserted. However, SigChg (see below) "1," card configured interface, asserted when this set. AD1801, Chng Function
REV.
-29-
AD1801
SigChg Signal Change Enable/Disable. This reset host enable disable status change signal from status register. When this set, card configured interface, Chng controls (CHG). status change signal desired, should zero signal will held deasserted when card configured I/O. AD1801, SigChg Function IOis8 cycles occur only 8-bit transfers. When host provide cycles only using SD7:SD0 data path, PCMCIA software will this card guaranteed that accesses 16-bit registers will occur byte accesses rather than single 16-bit access. This information useful when 16-bit 8-bit registers overlap. AD1801, this hardcoded (16-bit transfers allowed). Audio Reserved bits must Audio Enable. This enables audio information sent Host Adapter speaker SPKR (Pin when configured interface. AD1801, Audio Function PwrDn Intr Power-Down. This request that Function enter power-down state. PCMCIA software must place Function into power-down state while Function's READY (busy) state. Interrupt Request Pending. This represents internal state interrupt request. This value available whether interrupts have been configured. Intr cleared dependent IntrAck configured. IntrAck 0-Intr reflects function's interrupt request status. interrupt cleared within function, then Intr reset function. IntrAck 1-Intr remains even though interrupt condition been cleared (i.e., sticky). reset system software indicate ready receive another interrupt (implemented support interrupt sharing). IntrAck Interrupt Acknowledge. This determines response Intr bit. functionality associated with IntrAck permits more functions share Card's IREQ pin. IntrAck 0-When IntrAck reset, Intr functions described above support single interrupt implementation. IntrAck 1-This causes Intr remain even though interrupt service routine already serviced interrupt. Normally, interrupt service routine clears interrupt pending function specific register, causing Intr also cleared; however, support interrupt sharing, Intr cleared until PCMCIA specific software ready handle next interrupt request. When cleared PCMCIA software, other interrupt requests that pending asserted over Card's IREQ pin.
CSR2: PCMCIA Function Configuration Status Register
Data Chng Data SigChg Data IOis8 Data Res(0) Data Audio
Access: Read/Write
Data PwrDn Data Intr
Address: 0x442
Data IntrAck
Chng
Status Change Detected. This indicates that more Replacement register bits (CBVD1, CBVD2, CRDY CWProt) one, normally causing signal (Pin asserted. However, SigChg (see below) card configured interface, asserted when this set. AD1801, Chng Function Signal Change Enable/Disable. This reset host enable disable status change signal from status register. When this card configured interface, Chng controls (CHG). status change signal desired, should zero signal will held deasserted when card configured I/O. AD1801, SigChg Function Cycles Occur Only 8-Bit Transfers. When host provide cycles using only SD7:SD0 data path, PCMCIA software will this card guaranteed that accesses 16-bit registers will occur byte accesses rather than single 16-bit access. This information useful when 16-bit 8-bit registers overlap. AD1801, this hardcoded (16-bit transfers allowed). Reserved bits must Audio Enable. This enables audio information sent Host Adapter speaker SPKR (Pin when configured interface. AD1801, Audio Function -30- REV.
SigChg
IOis8
Audio
AD1801
PwrDn Intr Power-Down. This request that Function enter power-down state. PCMCIA software must place Function into power-down state while Function's READY (busy) state. Interrupt Request Pending. This represents internal state interrupt request. This value available whether interrupts have been configured. Intr cleared dependent upon IntrAck configured. IntrAck 0-Intr reflects function's interrupt request status. interrupt cleared within function, Intr reset function. IntrAck 1-Intr remains even though interrupt condition been cleared (i.e., sticky). reset system software indicate ready receive another interrupt (implemented support interrupt sharing). AD1801, Intr Function IntrAck Interrupt Acknowledge. This determines response Intr bit. functionality associated with IntrAck permits more functions share Card's IREQ pin. IntrAck 0-When IntrAck reset, Intr functions described above support single interrupt implementation. IntrAck 1-This causes Intr remain even though interrupt service routine already serviced interrupt. Normally interrupt service routine clears interrupt pending function specific register, causing Intr also cleared; however, support interrupt sharing, Intr cleared until PCMCIA specific software ready handle next interrupt request. When cleared PCMCIA software, other interrupt requests that pending asserted over Card's IREQ pin. AD1801, IntrAck ignored Function
PCMCIA Extended Status Register ESR0: PCMCIA Function Extended Status Register
Data Event3 Data Event2 Data Event1 Data Attn
Access: Read/Write
Data Enable3 Data Enable Data Enable1
Address: 0x408
Data Attn Enable
Event3 Event2 Event1 Attn
Reserved future expansion/definition-must reset (0). Reserved future expansion/definition-must reset (0). Reserved future expansion/definition-must reset (0). This latched within event occurring Card, such start each cycle ring frequency indicate presence ringing phone line case modem card. When this (1), Attn Enable (1), Changed Configuration Status register will also (1), SigChg Configuration Status register also been host, (Pin will asserted. host writing this will reset zero (0). Writing zero this will have effect. Reserved future expansion/definition-must reset (0). Reserved future expansion/definition-must reset (0). Reserved future expansion/definition-must reset (0).
Enable3 Enable2 Enable1
Attn Enable Setting this enables setting Changed Configuration Status register when Attn set. When this reset zero (0), this feature disabled. state Attn affected Attn Enable bit.
PCMCIA Base Registers IOBL0: PCMCIA Function Base Register
Data IOBL0[7] Data IOBL0[6] Data IOBL0[5] Data IOBL0[4] Data IOBL0[3] Data IOBL0[2] Data IOBL0[1]
Address: 0x40A
Data IOBL0[0]
IOBL0[7:0]
order byte base Function Address: 0x42A
Data IOBL1[4] Data IOBL1[3] Data IOBL1[2] Data IOBL1[1] Data IOBL1[0]
IOBL1: PCMCIA Function Base Register
Data IOBL1[7] Data IOBL1[6] Data IOBL1[5]
IOBL1[7:0]
order byte base Function
REV.
-31-
AD1801
PwrDn Intr Power-Down. This request that Function enter power-down state. PCMCIA software must place Function into power-down state while Function's READY (busy) state. Interrupt Request Pending. This represents internal state interrupt request. This value available whether interrupts have been configured. Intr cleared dependent upon IntrAck configured. IntrAck 0-Intr reflects function's interrupt request status. interrupt cleared within function, Intr reset function. IntrAck 1-Intr remains even though interrupt condition been cleared (i.e., sticky). reset system software indicate ready receive another interrupt (implemented support interrupt sharing). AD1801, Intr Function IntrAck Interrupt Acknowledge. This determines response Intr bit. functionality associated with IntrAck permits more functions share Card's IREQ pin. IntrAck 0-When IntrAck reset, Intr functions described above support single interrupt implementation. IntrAck 1-This causes Intr remain even though interrupt service routine already serviced interrupt. Normally interrupt service routine clears interrupt pending function specific register, causing Intr also cleared; however, support interrupt sharing, Intr cleared until PCMCIA specific software ready handle next interrupt request. When cleared PCMCIA software, other interrupt requests that pending asserted over Card's IREQ pin. AD1801, IntrAck ignored Function
PCMCIA Extended Status Register ESR0: PCMCIA Function Extended Status Register
Data Event3 Data Event2 Data Event1 Data Attn
Access: Read/Write
Data Enable3 Data Enable2 Data Enable1
Address: 0x408
Data Attn Enable
Event3 Event2 Event1 Attn
Reserved future expansion/definition-must reset (0). Reserved future expansion/definition-must reset (0). Reserved future expansion/definition-must reset (0). This latched within event occurring Card, such start each cycle ring frequency indicate presence ringing phone line case modem card. When this (1), Attn Enable (1), Changed Configuration Status register will also (1), SigChg Configuration Status register also been host, (Pin will asserted. host writing this will reset zero (0). Writing zero this will have effect. Reserved future expansion/definition-must reset (0). Reserved future expansion/definition-must reset (0). Reserved future expansion/definition-must reset (0).
Enable3 Enable2 Enable1
Attn Enable Setting this enables setting Changed Configuration Status register when Attn set. When this reset zero (0), this feature disabled. state Attn affected Attn Enable bit.
PCMCIA Base Registers IOBL0: PCMCIA Function Base Register
Data IOBL0[7] Data IOBL0[6] Data IOBL0[5] Data IOBL0[4] Data IOBL0[3] Data IOBL0[2] Data IOBL0[1]
Address: 0x40A
Data IOBL0[0]
IOBL0[7:0]
order byte base Function Address: 0x42A
Data IOBL1[4] Data IOBL1[3] Data IOBL1[2] Data IOBL1[1] Data IOBL1[0]
IOBL1: PCMCIA Function Base Register
Data IOBL1[7] Data IOBL1[6] Data IOBL1[5]
IOBL1[7:0]
order byte base Function
-32-
REV.
AD1801
RNGIA Host Interrupt from RING Acknowledge. mode, RING initiated interrupts host cleared writes this bit. Each time written this bit, RNGI (Host interrupt request from RING Pin) mapped register cleared "0." Writing this effect RNGI. Host Interrupt from Enable. Used only mode. This determines pending host interrupt request from DSP, indicated DSPI register being "1," cause host interrupt. state this does however effect ability clear DSPI itself. Host when DSPI Equals Disabled (default) Host when DSPI Equals Enabled Host Interrupt from RING Enable. Used only mode. This determines pending host interrupt from RING Pin, indicated RNGI register being "1," cause host interrupt. state this does not, however, effect ability clear RNGI itself. Host when RNGI Equals Disabled (default) Host when RNGI Equals Enabled Interrupt. sent interrupt pulse IRQ2 each time written this bit. Note: IRQ2 must configured edge-sensitive. Reset. Each time this "1," sent reset pulse. Setting this also causes: Reset source indicator bits (see DRST[1:0] mapped register "11"; codec channel enable bits (see MEN, MSEN mapped register reset "0." AD1801 Power-Down. Writing this initiates process powering down AD1801. Writing this effect. read this will always return "0." Power Consumption section this document important additional details.
Mnemonic:
Data RNGI Data Data Data Data Data
DSPIE
RNGIE
Default state after reset: 0000 0000 0000 0000 (0x0000).
Status
Data DSPI Data
Access: Read Only
Data Data Data Data Data Data
Address Offset:
Data Data
DSPI2
Host Interrupt Request from DSP. This whenever writes PCIRQ (Host interrupt request) (DSP Control) register. This cleared each time host writes DSPIA (Host interrupt from acknowledge) Control) register. When "1," host interrupt will generated driving selected provided: AD1801 mode; host interrupts from enabled (see DSPIE register); interrupt from RING already active, i.e., already driven RING interrupt already active, interrupt will postponed until after RING interrupt cleared, provided conditions necessary generate interrupt still active. Although this used PCMCIA mode generate host interrupts, still monitored distinguishing between RING interrupts provided cleared appropriate times. Host Interrupt Request from RING Pin. This whenever RING driven from This cleared each time host writes RNGIA (Host interrupt from RING acknowledge) Control) register. When "1," host interrupt will generated driving selected provided: AD1801 mode; host interrupts from RING enabled (see RNGIE register); interrupt from already active, i.e., already being driven interrupt already active, RING interrupt will postponed until after interrupt cleared, providing conditions necessary generate RING interrupt still active. Although this used PCMCIA mode generate host interrupts, still monitored distinguishing between RING interrupts, provided cleared appropriate times.
RNGI
Default state after reset: 0000 0000 0000 0000 (0x0000).
REV.
-33-
AD1801
Internal Control
Data Data Data TYPE Data
Mnemonic: IDMAC
Data MA13 Data Data MA12 Data
Access: Write Only
Data MA11 Data Data MA10 Data Data Data
Address Offset:
Data Data
Note: After writing this register, register must read least (assuming 16.9344 clock input XTALI pin). Performing dummy read register immediately after writing this register would satisfying this required delay. Read Write Select. Specifies which access enabled. Read Access Register Enabled (Write Access Register Ignored) Write Access Register Enabled (Read Access Yield Data) Memory Type Select. Specifies memory type accessed reads register writes register. Program Memory Accessed Data Memory Accessed Memory Address. Specifies initial memory address read reads register, written writes register. After either read write, this address auto-incremented.
Mnemonic:
Data MDI14 Data MDI6 Data MDI13 Data MDI5 Data MDI12 Data MDI4
TYPE
MA[13:0]
Default state after system reset: 0000 0000 0000 0000 (0x0000).
Memory Data Inputs
Data MDI15 Data MDI7
Access: Read Only
Data MDI11 Data MDI3 Data MDI10 Data MDI2 Data MDI9 Data MDI1
Address Offset:
Data MDI8 Data MDI0
MDI[15:0]
Memory Data Input. Reading this register returns stale data IDMA read access enabled. register IDMAC.
When reading program memory: upper bits 24-bit program memory word read first read this register. lowest eight bits program memory word read bits this register next read this register. During second read, bits 15:8 always read zeros.
Memory Data Output
Data MDO15 Data MDO7 Data MDO14 Data MDO6
Mnemonic:
Data MDO13 Data MDO5 Data MDO12 Data MDO4
Access: Write Only
Data MDO11 Data MDO3 Data MDO10 Data MDO2 Data MDO9 Data MDO1
Address Offset:
Data MDO8 Data MDO0
MDO[15:0]
Memory Data Output. Writes this register ignored IDMA write access enabled. register IDMAC.
When writing program memory: upper bits 24-bit program memory word written first write this register. lowest eight bits program memory word written bits this register next write this register. During second write, bits 15:8 ignored.
Test Modes
Data TM15 Data Data TM14 Data
Mnemonic:
Data TM13 Data Data TM12 Data
Access: Write Only
Data TM11 Data Data TM10 Data Data Data
Address Offset:
Data Data
TM[15:0]
Test Mode Control Bits.
Default state after system reset: 0000 0000 0000 0000 (0x0000). -34- REV.
AD1801
Memory
AD1801 uses DSP's IOMS control 10-bit address A(9:0) qualify accesses internal RAM, registers port pins addressed according table below. host will access until detects deactivation IREQ signal after system reset. control over deactivation this after reset occurred Control register. Under normal operations, will initialize RAM, then bit; will access memory again until after next reset. additional qualifying control, register OVRIDE bit, used determine whether access function registers listed table not. (The must this logical temporarily take function "off-line" from host order initialize configure function itself. clears this return function back "on-line" host use.) Note: memory space must least wait state proper AD1801 functionality.
Table Memory
Address Bits A[13:0] 0x000-0x1FF 0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20A
Reads reserved reserved reserved reserved reserved
Resource Accessed Writes
Function PCMCIA Attribute Configuration Control Port Control Port Data Base Address Interrupt Select Codec Configuration Modem Sample Rate Handset Sample Rate Modem Levels Handset Levels Monitor Speaker
Program Memory Organization
Program Memory Organization controlled value PMOVLAY register. AD1801, valid settings this register When internal program memory addressed. When upper swapped replaced with 4080 word ROM. After reset, PMOVLAY defaults code execution commences first address, which 0x2000.
Table Program Memory Organization
Address
PMOVLAY (Default after Reset) Program Memory Lower Internal 4080 Words Internal Words Reserved Analog Devices Reserved (Invalid Addresses) PMOVLAY Program Memory Lower Internal Upper Internal
Address 0x000 0x1FF
Data DATA3 Data ignored Data DATA2 Data ignored Data DATA1 Data ignored Data DATA0 Data ignored
0x0000-0x1FFF 0x2000-0x2FEF 0x2FF0-0x2FFF 0x3000-0x3FFF Address 0x0000-0x1FFF 0x2000-0x3FFF
Data DATA7 Data ignored Data DATA6 Data ignored Data DATA5 Data ignored
Access: Write Only
Data DATA4 Data ignored
REV.
-35-
AD1801
DATA[7:0] Only byte data written cycle, must justified 16-bit data bus. Each address points single byte. Mode: Identifier must written into first nine bytes RAM, i.e., addresses 0x000 0x008. Immediately after Identifier, Resource Data must loaded. Resource Data number remaining bytes. first Identifier byte must written into within after system reset (RESET pin) deasserted. remaining eight Identifier bytes must loaded rate every faster. Resource Data written into rate. bytes, whether Identifier Resource Data, must written into consecutively, single pass. PCMCIA Mode: Writes tuples rate order. Once configured, register must indicate load completion. After setting "1," further writes must occur.
Control
Data DSPIX Data PMODE Data RNGIX Data PSPORT
Mnemonic:
Data PCIRQ Data SPCHAN Data Data IO01A
Access: Read/Write
Data BYPAS Data SBWAIT Data Data PDRM Data FP1DBW Data PDRN
Address: 0x200
Data FP2DBW Data
DSPIX
Alternate access mapped register bits. Reading this returns state DSPI memory mapped register PCS. Writing this identical writing DSPIA memory mapped register PCC. Alternate access mapped register bits. Reading this returns state RNGI memory mapped register PCS. Writing this identical writing RNGIA memory mapped register PCC. Interrupt Request. PCMCIA mode, writing this sets DSPI (host interrupt request from DSP) mapped register PCS. mode, interrupt host asserted DSPI "1," provided interrupts host enabled (see DSPIE mapped register PCC). PCMCIA mode, DSPI itself does cause host interrupt, monitored distinguish between RING interrupts host When PCMCIA mode, writing PCIRQ sets CSR0 "1," addition setting DSPI. CSR0 "1," interrupt host asserted, provided interrupts host enabled (see COR0 function enabled (see COR0). Bypass. Used mode only ignored PCMCIA mode. When this "0," PNP_STD determines whether AD1801 non-PnP mode. When "1," PNP_STD ignored, AD1801 always non-PnP mode. When non-PnP mode, registers must written select base address IRQ. PNP_STD Selects Mode PNP_STD Ignored, Non-PnP Mode Forced Memory Initialized Indicator. Used PCMCIA mode only ignored mode. This should changed from reset default once completely initialized RAM. When "1," IREQ pin, which serves PCMCIA READY startup, released from reset default driven This indicates PCMCIA host adapter that AD1801 completed self-initialization ready accessed. PCMCIA Function Port Data Width Identifier. Used PCMCIA mode only ignored mode. This must written before AD1801 indicates ready proceed with configuration startup, i.e., before coincident with this register being written "1." used define behavior IOCS16 when function port read. PCMCIA Function Port bits PCMCIA Function Port bits PCMCIA Function Port Data Width Identifier. Used PCMCIA mode only ignored mode. This must written before AD1801 indicates ready proceed with configuration startup, i.e., before coincident with this register being written "1." used define behavior IOCS16 when function port read. PCMCIA Function Port bits PCMCIA Function Port bits
RNGIX
PCIRQ
BYPAS
FP1DBW
FP2DBW
-36-
REV.
AD1801
PMODE Port Mode Select. Selects which feature supported Pins either secondary PCMCIA function port serial port. When serial port selected, data either modem handset codec channels sacrificed since both serial ports nominally used within AD1801 codec communication. PSPORT SPCHAN bits further details which codec channels lost. PCMCIA Function Port Activated (default) Serial Port Activated (Modem Handset Data Sacrificed) Port Serial Port Select. When PMODE reset "0," this ignored. When PMODE "1," this selects which serial ports connected Pins Note that this bit, together with SPCHAN bit, determine whether modem handset codec channels sacrificed when serial port assigned Pins Port Assigned Pins when PMODE (default) Port Assigned Pins when PMODE Serial Port Channel Assignment. This selects which codec channel uses which serial port data communication. Modem Data Sent SPORT Handset Data Sent SPORT (default) Modem Data Sent SPORT Handset Data Sent SPORT Interrupt Acknowledge. Writing this acknowledges deasserts DSP's IRQL1 level interrupt. This interrupt asserted time logical input level changes state, either from System Wait. This used when servicing power-down interrupt support entering exiting AD1801 power-down mode. Once this "1," future read/write cycles AD1801 will extended through assertion IOCHRDY/WAIT pin. When reset "0," IOCHRDY/WAIT will deasserted asserted) allow completion extended cycle. Resetting this also mechanism clearing power-down interrupt initiated (see mapped register PCC), this should reset before exiting power-down interrupt service routine, even "1." Power-Down section this document important additional details. Power-Down Request from PCMCIA. This reflects state PWRDN PCMCIA register CSR0. While "1," level interrupt IRQL0 asserted DSP. This used determine source IRQL0 interrupt, PDRN below also asserts IRQL0. Writing this effect. Power-Down section this document important additional details. Power-Down Request from pin. This reflects state pin. While held level interrupt IRQL0 asserted DSP. This used determine source IRQL0 interrupt, PDRM above also asserts IRQL0. Writing this effect. Power-Down section this document important additional details. AD1801 Power-Down. Writing this initiates process powering down AD1801. Writing this effect. When read "1," this indicates that there active nonextended system access AD1801. Power-Down section this document further clarification important additional details.
Mnemonic:
Data Data IPC6 Data Data IPC5 Data Data IPC4
PSPORT
SPCHAN
IO0IA SBWAIT
PDRM
PDRN
Default state after reset: 0000 0000 0000 0000 (0x0000).
Port Control
Data Data IPC7
Access: Read/Write
Data Data IPC3 Data SCKIE Data IPC2 Data SENIE Data IPC1
Address 0x201
Data SDIE Data IPC0
Serial Memory Port Data Direction. Determines directionality SDATA pin. SDATA Output with Logic Level (see register). SDATA Input (default). SENIE Serial Data Enable Control Direction. Determines directionality pin. Output with Logic Level (see register) (default). Input Pin. SCKIE Serial Data Clock Direction. Determines directionality pin. Output with Logic Level (see register) (default). Input Pin. IPC[7:0] Port Control. Defines directionality associated port Pins through IO0. Output Input (default) Default state after system reset: 0000 0001 1111 1111 (0x01FF). REV. -37-
SDIE
AD1801
Input Port/Status
Data DRST1 Data Data DRST0 Data
Mnemonic:
Data RING Data Data PNP_STDZ Data
Access: Read Only
Data PCM_ISAZ Data Data Data Data Data
Address 0x202
Data Data
DRST[1:0]
RING PNP_STDZ
Reset Indicator. These bits identify source most recent reset. Last Reset Hard from RESET (Power-Up Reset) Last Reset Hard from RESET (ISA Reset) Last Reset Soft from PCMCIA Last Reset Soft from Memory Mapped Register RING Status. Reflects logic level RING pin. Mode Configuration Status. Reflects logic level PNP_STD pin. Standard Mode (PnP Disabled: Base Address Register, Register) Mode When AD1801 configured PCMCIA mode (i.e., when PCM_ISA HI), then PNP_STD used general purpose input. PNP_STDZ register used monitor state this general purpose input under those conditions. AD1801 Operating Mode Status. Reflects logic level PCM_ISA pin. Mode PCMCIA Mode Serial Data Clock Status. Reflects logic level pin. Serial Data Enable Control Status. Reflects logic level pin. Serial Data Status. Reflects logic level SDATA pin. Port Input State. Reflects logic levels associated port pins through IO0. port pins connected externally evaluated logic internal pull-up resistors. Will drive weak level externally.
Mnemonic:
Data Data Data Data Data Data
PCM_ISAZ
IP[7:0]
Default state after system reset: 0000 X0XX XXXX XXXX (0x0XXX).
Output Port
Data Data
Access: Write Only
Data Data Data Data Data Data
Address 0x202
Data Data
OP[7:0]
Serial Memory Port Clock Output. state this reflected pin. Serial Memory Port Chip Enable Output. state this reflected pin. Serial Memory Port Data Output. state this reflected SDATA provided SDIE (register IPC) reset "0." Port Output State. Defines logic levels driven port pins through provided associated port control register reset "0."
Mnemonic:
Data BA10 Data Data Data
Default state after system reset: 0000 0000 1111 1111 (0x00FF).
Default Base Address
Data BA12 Data Data BA11 Data
Access: Write Only
Data Data Data Data Data Data
Address 0x203
Data Data
-38-
REV.
AD1801
BA[12:0] Default Base Address. These bits used qualify host access AD1801 either non-PnP mode (PCM_ISA tied PNP_STD tied LO), BYPAS Control (DC) register "1." NOTE: This register always qualifies host access, must initialize when AD1801 configured non-PnP mode, since PnP/PCMCIA hardware/software does not. Note that independent mode, always write Base Address register, under obvious risk interfering with PCMCIA transactions. Default state after system reset: 0000 0000 0000 0000 (0x0000).
Default Interrupt Select
Data INTP2 Data Data INTP1 Data
Mnemonic:
Data SMODE Data Data Data
Access: Write Only
Data Data Data Data Data Data
Address 0x204
Data Data
INTP2
Interrupt Edge Polarity PCMCIA Function This ignored unless PCMCIA mode. defines edge necessary INT2 cause Function interrupt. Falling Edge Interrupt (default). Rising Edge Interrupt. Interrupt Edge Polarity PCMCIA Function This ignored unless PCMCIA mode. defines edge necessary INT1 cause Function interrupt. Falling Edge Interrupt (default). Rising Edge Interrupt. Strobe Mode. This selects functionality Pins when AD1801 PCMCIA mode. Pins function VCTL2 VCTL1, respectively (default) Pins function EXTWR EXTRD, respectively. Default Interrupt Request. These bits ignored unless mode (PCM_ISA tied LO). When mode, these bits select AD1801 either non-PnP mode (PNP_STD tied LO), register BYPAS "1." Valid settings IS[3:0] are: Other settings ignored result selection. NOTE: This register always selects AD1801 when mode, must initialize when AD1801 configured non-PnP mode, since PnP/PCMCIA hardware/software does not. Note that independent mode, always write Interrupt Select register, under obvious risk interfering with transactions.
INTP1
SMODE
IS[3:0]
Default state after system reset: 0000 0000 0000 0000 (0x0000).
Codec Configuration
Data Data MSSDR1 Data MDFS Data MSSDR0
Mnemonic:
Data MLCT Data MSAEN Data MSM1 Data
Access: Read/Write
Data MSM0 Data Data MSSR Data MSEN Data MSSD0 Data SBEN
Address 0x205
Data MSSDR2 Data
MDFS
Modem Digital Filter Select. This used select which digital filters applied modem channels. first choice been optimized filter performance, while second choice been optimized reduced linear group delay. Ripple1 -017 -0.24 Passband Edge 0.445 0.400 Stopband Point 0.490 0.453 Ripple2 <-78.0 <-52.8 Edge 0.555 0.555 Linear Group Delay <19/MSR <10/MSR
MDFS
modem sample rate MSR[15:0] register.
NOTES Passband ripple listed above does include following fixed (sample rate independent) roll-off which appears channels. channels have this roll-off. Consult filter plots this document further details. Stopband ripple listed does include filter peaks near MSR. When using modem filter (MDFS tallest these peaks -55.2 When using modem filter (MDFS tallest these peaks -58.6 While these peaks will further attenuated analog continuoustime filters within AD1801, corner frequency this analog filter high have substantial effect when sample rates used. Consult filter plots this document further details.
REV.
-39-
AD1801
Frequency Range MLCT Roll-Off <0.0016 <0.01 <0.05 <0.10
MSM[1:0]
MSSR
MSSDO
MSSDR[2:0]
MSAEN
MSEN
Modem Level Change Timing. This controls when changes modem level (see MDAM MDAL[4:0] bits register) take effect. When reset "0," changes take effect immediately. When "1," changes delayed until either output level crosses zero (midscale), until timeout period reached. Delaying level changes until zero crossings reduces instantaneous output voltage changes, that reduces audible "clicks." Level Changes Applied Immediately (default) Level Changes Applied Signal Zero (Midscale) Crossing After ms-12 Timeout Modem Sample Rate Modifier. These bits used select weighting MSR[15:0] (Modem Sample Rate) bits register. MSR[15:0] Weight Hertz (default) MSR[15:0] Weight Hertz MSR[15:0] Weight 10/7 Hertz Reserved Monitor Speaker Sample Rate Select. Monitor Speaker Sample Rate Locked Modem Sample Rate (See Register) Monitor Speaker Sample Rate Locked Handset Sample Rate (See Register) Monitor Speaker Sigma-Delta Order Bitstream Density Select. Available PCMCIA mode mode. Setting this will double nominal output volume from speaker connected SPKR MSPKR pin, will also significantly increase output noise. state MSSDO should only changed when monitor speaker powered down (i.e., MSEN Third Order Modulator with 75%/25% Bitstream Positive/Negative Full-Scale Mapping First Order Modulator with 100%/0% Bitstream Positive/Negative Full-Scale Mapping Monitor Speaker Sigma-Delta Bitstream Rate Select. Used PCMCIA mode only ignored mode. These bits used decrease nominal output bitstream rate sent SPKR pin. decreased bitstream rate will allow more time piezoelectric speaker properly discharge before being redriven, will also decrease oversampling rate, resulting more output noise. state MSSDR[2:0] bits should only changed when monitor speaker powered down (i.e., MSEN 1411.2 Bitstream Rate (default) 705.6 Bitstream Rate 352.8 Bitstream Rate 176.4 Bitstream Rate 88.2 Bitstream Rate Monitor Speaker Analog Output Enable. Used PCMCIA mode only ignored mode. Analog Monitor Speaker Output (pin MSPKR) Always Powered Down Analog Monitor Speaker Output (pin MSPKR) Powered when MSEN Modem Enable. required enable (power-up) modem codec channels once codec enabled (see CEN). Approximately required power down these channels MLCT (Modem Level Change Timing) reset "0." Both power-up power-down internally sequenced minimize instantaneous output voltage changes; however, power-down sequence this channel quieter MLCT "1." Modem Power-Down (default) Modem Enabled Provided (Codec Enable Bit) Handset Enable. required enable (power-up) handset codec channels once codec enabled (see CEN). Approximately required power down these channels. Both power-up powerdown internally sequenced minimize instantaneous output voltage changes (i.e., pops clicks). Handset Powered-Down (default) Handset Enabled Provided (Codec Enable Bit) Monitor Speaker Enable. required enable (power monitor speaker channel once enabled (see CEN). Approximately required power down this channel. Both power-up power-down internally sequenced minimize instantaneous output voltage changes (i.e., pops clicks). Monitor Speaker Powered Down (default) Monitor Speaker Enabled Provided (Codec Enable Bit) -40- REV.
AD1801
SBEN Codec Standby Enable. either this (Codec Enable) "1,'' process powering AD1801's codec voltage reference initiated. both this reset "0," process powering down AD1801's codec voltage reference initiated. Approximately required power codec voltage reference while only required power down. This used keep codec voltage reference powered when rest codec powered down, which results much quicker power-up sequence. further details. Codec Powered Down (Provided (default) Codec Standby (Provided Codec Enable. When written this bit, process powering AD1801 codecs initiated. When written this bit, process powering down AD1801 codecs initiated. When read "0," codecs either powered down process powering When read "1," codecs either powered process powering down. Therefore, completion process powering down detected writing appropriate value this reading this until written value echoed. Power-up normally requires more than will required first time codecs powered after AD1801 reset, since this when codecs perform autocalibration. Note that codecs first standby using SBEN (and given time complete transition into standby), only will required after setting complete power-up process. Powering down codecs never requires more than Table complete summary.
Mnemonic: Access: Read/Write Address: 0x206
Default state after system reset: 0000 0000 0000 0000 (0x0000).
Modem Sample Rate
Data MSR15 Data MSR7
Data MSR14 Data MSR6
Data MSR13 Data MSR5
Data MSR12 Data MSR4
Data MSR11 Data MSR3
Data MSR10 Data MSR2
Data MSR9 Data MSR1
Data MSR8 Data MSR0
MSR[15:0]
Modem Sample Rate. Together with MSM[15:0] (Modem Sample Rate Modifier) register, these bits define conversion rate modem channels. MSSR (Monitor Speaker Sample Rate Select) register reset (default), these bits also define conversion rate monitor speaker DAC. With 16.9344 clock input XTALI pin, represents: exactly Hertz when MSM[1:0] exactly Hertz when MSM[1:0] exactly 10/7 Hertz when MSM[1:0] Permitted settings MSR[15:0] range from: 5400 48000 when MSM[1:0] 4725 42000 when MSM[1:0] 3780 33600 when MSM[1:0] Resultant sample rate, regardless MSM[1:0] setting, always ranges from 5400 48000
Mnemonic:
Data HSR13 Data HSR5 Data HSR12 Data HSR4
Default state after system reset: 0001 1100 0010 0000 (0x1C20) which 7200 with MSM[1:0]
Handset Sample Rate
Data HSR15 Data HSR7 Data HSR14 Data HSR6
Access: Read/Write
Data HSR11 Data HSR3 Data HSR10 Data HSR2 Data HSR9 Data HSR1
Address: 0x207
Data HSR8 Data HSR0
HSR[15:0]
Handset Sample Rate. Defines conversion rate Handset channels. MSSR (Monitor Speaker Sample Rate select) register "1," these bits also define conversion rate monitor speaker DAC. represents exactly Hertz, assuming 16.9344 clock input XTALI pin. Usable range 5400 (0x1518) 48000 (0xBB80).
Mnemonic:
Data Data MDAL4 Data Data MDAL3 Data Data MDAL2
Default state after system reset: 0001 1111 0100 0000 (0x1F40) which kHz.
Modem Levels
Data Data MDAM
Access: Read/Write
Data Data MDAL1 Data Data MDAL0 Data MADL1 Data SDAL1
Address: 0x208
Data MADL0 Data SDAL0
REV.
-41-
AD1801
MADL[1:0] Modem Gain Level Select. Least significant represents +6.0 Gain (default) +6.0 Gain +12.0 Gain Reserved MDAM Modem Mute. Enabled Muted (default) MDAL[4:0] Modem Attenuation Level Select. Least significant represents -1.0 00000 Attenuation (default) 11111 Attenuation SDAL[1:0] Monitor Speaker Attenuation Level. Attenuation -6.0 Attenuation -12.0 Attenuation Muted (default) Default state after system reset: 0000 0000 1000 0011 (0x0083).
Handset Levels
Data HADS Data HDASM Data HMGE Data HDALM
Mnemonic:
Data Data Data Data HDAL4
Access: Read/Write
Data HADL3 Data HDAL3 Data HADL2 Data HDAL2 Data HADL1 Data HDAL1
Address: 0x209
Data HADL0 Data HDAL0
HADS
HMGE
HADL[3:0]
HDASM
Handset Input Select. (default) Line Handset Gain Enable. Gain (default) Gain Handset Gain Level Select. Least significant represents +1.5 0000 Gain (default) 1111 +22.5 Gain Handset Speaker Mute. Enabled Muted (default)
HDALM
Handset Line Mute. Enabled Muted (default). Midscale voltage output HSPKRP HSPKRN HDAL[4:0] Handset Attenuation Level Select. Least significant represents -1.5 00000 +12.0 Gain 01000 Attenuation (default) 11111 -34.5 Attenuation Default state after system reset: 0000 0000 1100 1000 (0x00C8).
Modem Speaker DatData MSD15 Data MSD7 Data MSD14 Data MSD6
Mnemonic:
Data MSD13 Data MSD5 Data MSD12 Data MSD4
Access: Write
Data MSD11 Data MSD3 Data MSD10 Data MSD2 Data MSD9 Data MSD1
Address: 0x20A
Data MSD8 Data MSD0
MSD[15:0]
Monitor Speaker Data. Writes this register fill deep FIFO. this FIFO underruns, last sample will repeated monitor speaker consecutive underruns; thereafter, midscale sample data used additional underruns. This avoids clicks momentary FIFO underruns (easing playback startup) avoids sustained output levels. Data written this FIFO that would cause FIFO overrun ignored. status bits needed this FIFO since locked either modem handset sample rate (see MSSR register CC). -42- REV.
AD1801
POWER CONSUMPTION
AD1801 power consumption dependent many factors, including codec resources used, ADSP-2181 core resources used instruction mix. Table provides some estimates maximum current consumption AD1801 function device resources used.
Table XII. AD1801 Current Consumption Estimates
Power States 1MHS* Active 1MH* Codec System Interface Responsive Responsive Responsive Responsive Responsive Responsive Responsive Responsive Nonresponsive Responsive Responsive Slow Responsive Slow Responsive Nonresponsive Nonresponsive Estimated Current
reset pins) until clock input XTALI stabilizes, plus another 1000 XTALI cycles allow AD1801's phase locked loop lock. With crystal connected between XTALI XTALO pins, time required clock input stabilize dependent upon type crystal used capacitance external crystal circuit; typically 2000 XTALI cycles adequate. AD1801 Power State prior assertion reset, procedure listed above initial power-up must followed since clocks were stopped while Power State AD1801 Power State prior assertion reset pin, AD1801 must kept this Power State continuous assertion least reset pins) least five XTALI cycles. Note that asserting reset while Power State recommended "noisy" abrupt shutdown codec. Power State DSP: Codec: Interface: Crystal: Active Powered Down Standby Responsive Enabled
Enabled Active Enabled Active Enabled Active Enabled Active Enabled Active Channels Disabled Active Standby Active Down Down Idle Standby Idle Down Standby Standby Standby Down Down Down Standby Down
codec standby (see SBEN mapped register CC), voltage reference circuitry powered down which results greater power consumption; however, time required transition from Power State Power State decreased from approximately approximately (Codec Enable) (see mapped register CC), process entering Power State will initiated. poll codec reading waiting echo "1") determine when Power State actually entered. Power State will entered IDLE instruction executed DSP, provided currently servicing power-down interrupt. Note that IDLE(n) instruction must used since internal clock slow down caused this instruction will interfere with AD1801 interface logic. Power State (Any Form) DSP: Active Codec: Powered combination Modem, Handset Speaker Codec Channels Enabled. Interface: Responsive Crystal: Enabled Although codec powered this Power State, amount power actually consumed still dependent number codec channels actually enabled. modem (ADC DAC), handset (ADC DAC) speaker (DAC) channels independently enabled disabled using MEN, MSEN bits mapped register Before enabling either modem handset codec channels, serial port used communicate with codec channels must first properly configured DSP. serial port used, "SPORT Control" register 0x3FF6 must 0x3C0F. serial port used, "SPORT Control" register 0x3FF2 must 0x3C0F. Also, used serial ports must enabled setting appropriate bits
*When Power State combination Modem (Mod), Handset (Hnd), Speaker (Spk) channels enabled through independent channel enable bits (see mapped register). Only combinations thought most likely used have been listed. *Current numbers assume: instructions multifunction (Types 14), Type Type idle. Device operating with ISA/PCMCIA loads.
WARNING: proper operation AD1801, code must never: IDLE(n) instruction (critical internal clocks will slowed). Write PDFORCE (power-down interrupt force) SPORT1 Autobuffer Control Register (this would power down AD1801 with means powering back other than reset).
Power-Down States
Power State DSP: Codec: Interface: Crystal:
Running Powered Down Nonresponsive Enabled
AD1801 forced into this Power State time both reset pins (RESET RESET) asserted. AD1801 will remain this Power State until both reset pins deasserted. Immediately after both reset pins deasserted, AD1801 will enter Power State commence instruction execution location 0x2000 ROM. When power first applied, AD1801 must kept this Power State continuous assertion least REV.
-43-
AD1801
"System Control" register 0x3FFF. Finally, note that PMODE, PSPORT SPCHAN bits mapped register which specify serial port usage, must also defined before enabling related codec channels. (Codec Enable) reset (see mapped register CC), process entering Power State will initiated. poll codec reading waiting echo "0") determine when Power State actually entered. Power State DSP: Codec: Interface: Crystal: Idle Powered Down Standby Responsive Enabled Beginning 0x002C, number housekeeping instructions executed prior entering actual powerdown. These instructions must ensure that codec powered down before continuing with this procedure. (Codec Enable) located mapped register (Codec Configuration) detailed information power-down codec check power-up/ -down status. These instructions must also program "SPORT1 Autobuffer/Power-Down Control Register" memory mapped location 0x3FEF 0x0XXX unless these settings made advance. This sets: XTALDIS which causes crystal oscillator stay enabled during powerdown.
Power State will entered IDLE instruction executed DSP, provided currently servicing power-down interrupt. Note that IDLE(n) instruction must used since internal clock slow down caused this instruction will interfere with AD1801 interface logic. this Power State, idle codec powered down. When unmasked interrupt occurs, AD1801 will return Power State immediately service interrupt. Power State DSP: Codec: Interface: Crystal: Powered Down Powered Down Standby Slow responsive Enabled
XTALDELAY which causes startup delay less than cycles. PDFORCE PUCR which should never AD1801. which avoids power-up reset instruction execution continues power-down handler after power-up.
Entering exiting this Power State requires code support. This code outlined below. While this Power State, AD1801 will immediately responsive system accesses, will extend cycles through assertion IOCHRDY/WAIT until able respond. system access AD1801, read write, will wake AD1801 from this Power State return Power State where AD1801 respond cycles. system will stalled more than which acceptable both PCMCIA buses. specifies maximum stall 15.6 PCMCIA specifies maximum stall
Entering Power State
must write SBWAIT (System Wait) mapped register transactions AD1801 started AFTER this point will extended (through assertion IOCHRDY/WAIT pin) until wakes again after being powered down steps below. currently active access AD1801 will completed without cycle extension insure that AD1801 doesn't assert IOCHRDY/WAIT close access. must poll mapped register until read "1." most systems, this will require more than When read "1," this indicates that there either active system access AD1801, that access AD1801 been stalled through assertion IOCHRDY/WAIT pin. Once read "1," safe power down stop AD1801 internal clocks. powers itself down with execution IDLE instruction. This completes transition into Power State While AD1801 mostly powered down, continues decoding traffic waiting AD1801 access, read write, which will initiate AD1801 wakeup. Note that accesses PCMCIA external devices will occur without waking AD1801. process entering Power State aborted until step where SBWAIT "1." Once "1," Steps must also executed proper future AD1801 operation. SBWAIT "1," Power State aborted first resetting SBWAIT "0," that signals early exit AD1801, then executing instruction which will exit power-down handler.
transition Power State initiated assertion nonmaskable power-down interrupt. source this power-down interrupt writing memory mapped register PCC; writing memory mapped register This interrupt will cause vector address 0x002C. transition this Power State indirectly initiated asserting (power-down pin) PCMCIA power-down (bit PWRDN register CSR0). Either these actions will cause IRQL0 interrupt DSP, causing vector address 0x000C. this interrupt handler, turn write bit. Note that access flag bits (PDRN PDRM mapped register that indicate source IRQL0 interrupt.
-44-
REV.
AD1801
Exiting Power State
There conditions under which will powered Power State exited. first host initiating read write access AD1801. second logic transition (either following input signals: RING, INT1, INT2. When host initiates read write access, AD1801 asserts IOCHRDY/WAIT extend cycle until respond, begins process powering DSP. When wake caused transition RING, INT1, INT2, IOCHRDY/WAIT signal asserted. Powering requires about When wakes continues executing code where left power-down handler. first instruction should reset SBWAIT allow completion extended cycle. number housekeeping instructions executed before power-down interrupt handler exited instruction. Power State also exited with assertion reset, RESET RESET. Power State DSP: Codec: Interface: Crystal: Powered Down Powered Down Standby Nonresponsive Disabled
Beginning 0x002C, number housekeeping instructions executed prior entering actual powerdown. These instructions must insure that codec powered down before continuing with this procedure. (Codec Enable) located mapped register (Codec Configuration) detailed information power down codec check power down status. These instructions must also program "SPORT1 Autobuffer/Power-Down Control Register" memory mapped location 0x3FEF 0x0XXX unless these settings made advance. This sets: XTALDIS XTALDELAY PDFORCE PUCR which causes crystal oscillator power down during power-down. which causes startup delay 4096 clock cycles. which should never AD1801. which avoids power reset instruction execution continues power-down handler after power-up.
WARNING: When this Power State, accesses AD1801 possible. This Power State must used PCMCIA configuration register access must maintained. Entering exiting this Power State requires code support. This code outlined below. While this Power State, AD1801 will responsive system accesses. system access AD1801, read write, will, however, wake AD1801 from this Power State into Power State order plus crystal settle time will necessary wake AD1801. Unlike waking from Power State cycles will extended when waking from this Power State.
Entering Power State
powers itself down with execution IDLE instruction. This completes transition into Power State While AD1801 mostly powered down, continues decoding traffic waiting AD1801 access, read write, that will initiate AD1801 wakeup. Note that accesses PCMCIA external devices will occur without waking AD1801. process entering Power State aborted until Step where IDLE instruction executed. Power State aborted first resetting SBWAIT "0," which signals early exit AD1801, then executing instruction which will exit power-down handler.
Exiting Power State
transition Power State initiated assertion nonmaskable power-down interrupt. source this power-down interrupt writing memory mapped register PCC; writing memory mapped register This interrupt will cause vector address 0x002C. transition this Power State indirectly initiated asserting (power-down pin) PCMCIA power-down (bit PWRDN register CSR0). Either these actions will cause IRQL0 interrupt DSP, causing vector address 0x000C. this interrupt handler, turn write bit. Note that access flag bits (PDRN PDRM mapped register DC), which indicate source IRQL0 interrupt.
There conditions under which will powered Power State exited. first host initiating dummy read access AD1801. This access AD1801, others until AD1801 awake, lost. second logic state transition (either following input signals: RING, INT1, INT2. When wakes continues executing code where left power-down handler. first instruction should reset SBWAIT clear power-down logic. number housekeeping instructions executed before power-down interrupt handler exited instruction. desirable send interrupt host signal AD1801 wakeup. Power State also exited with assertion reset, RESET RESET.
REV.
-45-
AD1801
Table XIII. Power State Transitions
Initial State 1[M, 1[M, 2[C]** 3[C]** 2[C]** 4[C]** 2[C]** 5[C]**
Final State 1[M, 1[M, 3[C]** 2[C]** 4[C]** 2[C]** 5[C]** 2[C]**
Transition Trigger (Bits Register) [MEN, HEN, MSEN] Reset SBEN [MEN, HEN, MSEN] Reset SBEN Reset MSEN MSEN Reset Reset Reset SBEN Don't Care Reset SBEN Reset SBEN Don't Care Reset SBEN Reset SBEN Reset Reset SBEN Executes IDLE Instruction Stops Executing IDLE Power State Paragraph Power State Paragraph Power State Paragraph Power State Paragraph
Time Required Transition None None Par. Par.
Indicator Transition Completion Read Back Read Back Read Back Read Back None None SPORT Activity SPORT Activity Stops SPORT Activity SPORT Activity Stops Read Back Read Back Read Back Read Back None None None None PWDACK PWDACK PWDACK PWDACK
**Delay will increased AD1801 autocalibrated itself. Autocalibration executed first time AD1801 transitions Power State after hard reset, i.e., reset initiated either RESET RESET pin. transition Power State aborted before completed resetting autocalibration postponed until next transition Power State However, once autocalibration actually begun, wh
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