ThirdGeneration 32-bit Microprocessor TS68040 Description TS

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ThirdGeneration 32-bit Microprocessor TS68040 Description TS

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26-42 MIPS Integer Performance 3.5-5.6 MFLOPS Floating-Point-Performance IEEE 754-Compatible Independent Instruction Data MMUs bytes Physical Instruction Cache bytes Physical Data Cache Accessed Simultaneously 32-bit, Nonmultiplexed External Address Data Buses with Synchronous Interface User-Object-Code Compatibility with Earlier TS68000 Microprocessors Multimaster/Multiprocessor Support Snooping Concurrent Integer Unit, FPU, MMU, Controller, Snooper Maximize Throughput bytes Direct Addressing Range Software Support Including Optimizing Compiler UNIX® System Port IEEE 1149-1 Test Mode (JTAG) MHz, MHz; TS88915T Clock Driver Suggested
ThirdGeneration 32-bit Microprocessor TS68040
Description
TS68040 Atmel's third generation 68000-compatible, high-performance, 32bit microprocessors. TS68040 virtual memory microprocessor employing multiple, concurrent execution units highly integrated architecture provide very high performance monolithic HCMOS device. single chip, TS68040 integrates 68030-compatible integer unit, IEEE 754-compatible floating-point unit (FPU), fully independent instruction data demand-paged memory management units (MMUs), including bytes independent instruction data caches. high degree instruction execution parallelism achieved through multiple independent execution pipelines, multiple internal buses, full internal Harvard architecture, including separate physical caches both instruction data accesses. TS68040 also directly supports cache coherency multimaster applications with dedicated on-chip snooping logic. TS68040 user-object-code compatible with previous members TS68000 Family specifically optimized reduce execution time compiler-generated code. 68040 HCMOS technology, provides ideal balance between speed, power, physical device size. Figure simplified block diagram TS68040. Instruction execution pipelined both integer unit FPU. Independent data instruction MMUs control main caches address translation caches (ATCs). ATCs speed logical-to-physical address translations storing recently used translations. snooper circuit ensures cache coherency multimaster multiprocessing applications.
Screening
MIL-STD-883 DESC. Drawing 5962-93143 Atmel Standards
Rev. 2116A-HIREL-09/02
suffix Ceramic Grid Array Cavity Down
suffix CQFP Gullwing Shape Lead Ceramic Quad Pack
Figure Block Diagram
INSTRUCTION DATA
INSTRUCTION
INSTRUCTION CACHE
INSTRUCTION ADDRESS
INSTRUCTION FETCH CONVERT DECODE EFFECTIVE ADDRESS CALCULATE EFFECTIVE ADDRESS FETCH EXECUTE WRITE BACK WRITE BACK
INSTRUCTION MMU/CACHE/SNOOP CONTROLLER
INSTRUCTION MEMORY UNIT
ADDRESS
EXECUTE
DATA
DATA MEMORY UNIT DATA MMU/CACHE/SNOOP CONTROLLER
DATA ADDRESS
CONTROL SIGNALS
FLOATINGPOINT UNIT
INTEGER UNIT
DATA
DATA CACHE
OPERAND DATA
TS68040
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TS68040
Introduction
TS68040 enhanced, 32-bit, HCMOS microprocessor that combines integer unit processing capabilities TS68030 microprocessor with independent bytes data instruction caches on-chip FPU. TS68040 maintains 32-bit registers available with entire TS68000 Family well 32-bit address data paths, rich instruction set, versatile addressing modes. Instruction execution proceeds parallel with accesses internal caches, operations, controller activity. Additionally, integer unit optimized high-level language environments. TS68040 user-object-code compatible with TS68882 floating-point coprocessor conforms ANSI/IEEE Standard binary floating-point arithmetic. been optimized execute most commonly used subset TS68882 instruction set, includes additional instruction formats single double-precision rounding results. Floating-point instructions execute concurrently with integer instructions integer unit. MMUs support multiprocessing, virtual memory systems translating logical addresses physical addresses using translation tables stored memory. MMUs store recently used address mappings separate ATCs-on-chip. When contains physical address cycle requested processor, translation table search avoided physical address supplied immediately, incurring delay address translation. Each transparent translation registers available that define one-to-one mapping address space segments ranging size from bytes bytes each. Each provides read-only supervisor-only protections page basis. Also, processes given isolated address spaces assigning each unique table structure updating root pointer upon task swap. Isolated address spaces protect integrity independent processes. instruction data caches operate independently from rest machine, storing information fast access execution units. Each cache resides internal address internal data bus, allowing simultaneous access both. data cache provides write through copyback write modes that configured page-by-page basis. TS68040 controller supports high-speed, multiplexed, synchronous external interface, which allows following transfer sizes: byte, word bytes), long word bytes), line bytes). Line accesses performed using burst transfers both reads writes provide high data transfer rates.
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Assignments
Figure Bottom View
Table Power Supply Affectation Body
Internal Logic Output Drivers C11,C13, K16, M16, R11, R13, S10, B10, B13, B15, B17, D17, F17, H17, L17, N17, Q17, S15, C10, C12, C14, H16, J16, L16, R12, B14, C17, G17, M17, R17,
TS68040
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TS68040
CQFP
Figure Assignments
Table Power Supply Affectation CQFP Body
Internal Logic Output Drivers 113, 119, 121, 122, 124, 125, 129, 130, 141, 159, 105, 106, 146, 147, 148, 149, 155, 162, 163, 169, 176, 182, 183, 189, 195, 114, 126, 137, 158, 173, 102, 152, 166, 179,
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Signal Description
Figure Table describe signals TS68040 indicate signal functions. test signals, TRST, TMS, TCK, TDI, TDO, comply with subset P-1149.1 IEEE testability standard.
Figure Functional Signal Groups
TS68040
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TS68040
Table Signal Index
Signal Name Address Data Transfer Type Transfer Modifier Transfer Line Number User Programmable Attributes Read Write Transfer Size Lock Lock Cache Inhibit Transfer Start Transfer Progress Transfer Acknowledge Transfer Error Acknowledge Transfer Cache Inhibit Transfer Burst Inhibit Data Latch Enable Snoop Control Memory Inhibit Request Grant Busy Cache Disable Disable Reset Reset Interrupt Priority Level Interrupt Pending Autovector Processor Status Mnemonic A31-A0 D31-D0 TT1, TM2, TLN1, TLN0 UPA1, UPA0 SIZ1, SIZ0 LOCK LOCKE CIOUT SC1, CDIS MDIS RSTI RSTO IPL2-IPL0 IPEND AVEC PST3-PST0 Function 32-bit address used address bytes 32-bit data used transfer bits data transfer Indicates general transfer type: normal, MOVE alternate logical function code, acknowledge Indicates supplemental information about access Indicates which cache line being pushed loaded current line transfer User-defined signals, controlled corresponding user attribute bits from address translation entry Identifies transfer read write Indicates data transfer size. These signals, together with define active sections data Indicates transfer part read-modify-write operation, that sequence transfers should interrupted Indicates current transfer last locked sequence transfer Indicates processor will cache current transfer Indicates beginning transfer Asserted duration transfer Asserted acknowledge transfer Indicates error condition exists transfer Indicates current transfer should cached Indicates slave cannot handle line burst access Alternate clock input used latch input data when processor operating mode Indicates snooping operation required during alternate master access Inhibits memory devices from responding alternate master access during snooping operations Asserted processor request mastership Asserted arbiter grant mastership processor Asserted current master indicate assumed ownership Dynamically disables internal caches assist emulator support Disables translation mechanism MMUs Processor reset Asserted during execution RESET instruction reset external devices Provides encoded interrupt level processor Indicates interrupt pending Used during interrupt acknowledge transfer request internal generation vector number Indicates internal processor status
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Table Signal Index (Continued)
Signal Name Clock Processor Clock Test Clock Test Mode Select Test Data Input Test Data Output Test Reset Power Supply Ground Mnemonic BCLK PCLK TRST Function Clock input used derive signal timing Clock input used internal logic timing. PCLK frequency exactly BCLK frequency Clock signal IEEE P1149.1 test access port (TAP) Selects principle operations test-support circuitry Serial data input Serial data output Provides asynchronous reset controller Power supply Ground connection
Scope
This drawing describes specific requirements microprocessor TS68040 MHz, compliance with MIL-STD-883 class Atmel standard screening.
Applicable Documents
MIL-STD-883
MIL-STD-883: test methods procedures electronics. MIL-I-38535: general specifications microcircuits. DESC 5962-93143.
Requirements
General Design Construction
Terminal Connections Lead Material Finish Figure Figure Lead material finish shall specified MIL-STD-883 (see enclosed "MIL-STD883 Internal Standard" page 46). macro circuits packaged hermetically sealed ceramic packages which conform case outlines MIL-STD-1835-or follow: CMGA 10-179-PAK grid array, "179 pins PGA" page Similar CQCC1-F196C-U6 ceramic uniform lead chip carrier package with ceramic nonconductive tie-bar Atmel's internal drawing, "196 pins CQFP Cavity request)" page Gullwing shape CQFP "196 pins Gullwing CQFP cavity page microcircuits accordance with applicable document specified herein.
Package
TS68040
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TS68040
precise case outlines described specification (See "Package Mechanical Data" page 43.) into MIL-STD-1835.
Electrical Characteristics
Absolute Maximum Ratings Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability.
Table Absolute Maximum Ratings
Symbol Tstg Note: Parameter Supply Voltage Range Input Voltage Range Large buffers enabled Power Dissipation Small buffers enabled Operating Temperature Storage Temperature Range Junction Temperature
Condition
-0.3 -0.3
Unit
+150 +125
Tlead Lead Temperature Max.10 soldering +300 This device tested +125°C. Testing performed setting junction temperature +125°C allowing case ambient temperatures rise fall necessary exceed maximum junction temperature.
Table Recommended Conditions Unless otherwise stated, voltages referenced reference terminal
Symbol Note: Case Operating Temperature Range Parameter Supply Voltage Range Logic Level Input Voltage Range Logic High Level Input Voltage Range High Level Output Voltage Level Output Voltage Clock Frequency Version Version
+4.75 +2.0
+5.25
Unit
TJmax +125
Maximum Operating Junction Temperature
This device tested +125°C. Testing performed setting junction temperature +125°C allowing case ambient temperatures rise fall necessary exceed maximum junction temperature.
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Thermal Considerations
General Thermal Considerations This section only given user information. microprocessors becoming more complex requiring more power, need efficiently cool device becomes increasingly more important. past, TS68000 Family, been able provide 0-70°C ambient temperature part speeds less than MHz. However, TS68040, which arithmetic logic unit (ALU) speed, specified with maximum power dissipation particular mode, maximum junction temperature, thermal resistance from junction case. This provides more accurate method evaluating environment, taking into consideration both air-flow ambient temperature available. This also allows user information design cooling method which meets both thermal performance requirements constraints board environment. This section discusses device characteristics thermal management, several methods thermal management, example method cooling TS68040. Thermal Device Characteristics TS68040 presents some inherent characteristics which should considered when evaluating method cooling device. following paragraphs discuss these die/package power considerations. TS68040 being placed cavity-down alumina-ceramic 179-pin that specified thermal resistance from junction case 1°C/W. This package differs from previous TS68000 Family packages which were cavity This cavity-down design allows attached surface package, which increases ability part dissipate heat through package surface attached heat sink. maximum perimeter that TS68040 allows heat sink surface without interfering with capacitor pads 1.48" 1.48". specific dimensions design particular heat sink will need determined system designer considering both thermal performance requirements size requirements. TS68040 maximum power rating, which varies depending operating frequency output buffer mode combination being used. large buffer output mode dissipates more power than small, higher frequencies operation dissipate more power than lower frequencies. following paragraphs discuss trade-offs using different output buffer modes, calculation specific maximum power dissipation different modes, relationship thermal resistances temperatures.
Package
Power Considerations
TS68040
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TS68040
Output Buffer Mode 68040 capable resetting enable combination either large buffers small buffers outputs miscellaneous control signals, data bus, address bus/transfer attribute pins. large buffers offer quicker output times, which allow easier logic design. However, they driving about times much current small buffers (refer TS68040 Electrical specifications current output). designer should consider whether quicker timings present enough advantage justify additional consideration individual signal terminations, power consumption, required cooling device. Since TS68040 powered-up eight output buffer modes upon reset, actual maximum power consumption TS68040 rated particular maximum operating frequency dependent upon power mode. Therefore, TS68040 rated maximum power dissipation either large buffers small buffers particular frequency (refer TS68040 Electrical specifications). This allows possibility some thermal management controlled upon reset. following equation provides rough method calculate maximum power consumption chosen output buffer mode: PDSB (PDLB PDSB) (PINSLB/PINSCLB) where: PDSB PDLB PINSLB Max. power dissipation output buffer mode selected Max. power dissipation small buffer mode (all outputs) Max. power dissipation large buffer mode (all outputs) Number pins large buffer mode
PINSCLB Number pins capable large buffer mode Table shows simplified relationship maximum power dissipation eight possible configurations output buffer modes. Table Maximum Power Dissipation Output Buffer Mode Configurations
Output Configuration Data Small Buffer Small Buffer Small Buffer Small Buffer Large Buffer Large Buffer Large Buffer Large Buffer Address Transfer Attrib. Small Buffer Small Buffer Large Buffer Large Buffer Small Buffer Small Buffer Large Buffer Large Buffer Misc. Control Signals Small Buffer Large Buffer Small Buffer Large Buffer Small Buffer Large Buffer Small Buffer Large Buffer Maximum Power Dissipation PDSB PDSB (PDLB DSB) PDSB (PDLB DSB) PDSB (PDLB DSB) PDSB (PDLB DSB) PDSB (PDLB DSB) PDSB (PDLB DSB) PDSB (PDLB PDSB) 100%
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calculate specific power dissipation specific design, termination method each signal must considered. example, signal output that connected would dissipate additional power were configured large buffer rather than small buffer mode. Relationships Between Thermal Resistances Temperatures Since maximum operating junction temperature been specified 125°C. maximum case temperature, obtained from: where: Maximum case temperature Maximum junction temperature Maximum power dissipation device Thermal resistance between junction case
general, ambient temperature, function following formula: Where thermal resistance from case ambient, only user-dependent parameter once buffer output configuration been determined. seen from equation (3), reducing case ambient thermal resistance increases maximum operating ambient temperature. Therefore, utilizing such methods heat sinks ambient cooling minimize higher ambient operating temperature and/or lower junction temperature achieved. However, easier approach thermal evaluation uses following formulas: alternatively, where: thermal resistance from junction ambient CA). This total thermal resistance package, combination components, These components represent barrier heat flow from semiconductor junction package (case) surface (JC) from case outside ambient (JC). Although device related cannot influenced user, user dependent. Thus, good thermal management user significantly reduce achieving either lower semiconductor junction temperature higher ambient operating temperature. Thermal Management Techniques attain reasonable maximum ambient operating temperature, user must reduce barrier heat flow from semiconductor junction outside ambient JA). only accomplish this significantly reduce applying such thermal management techniques heat sinks ambient cooling. following paragraphs discuss some results thermal study TS68040 device without using thermal management techniques; using only air-flow cooling, using only heat sink, using heat sink combined with air-flow cooling.
TS68040
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TS68040
Thermal Characteristics Still sample size three TS68040 packages tested free-air cooling with heat sink. Measurements showed that average 22.8°C/W with standard deviation 0.44°C/W. test performed with power being dissipated from within package. test determined that will decrease slightly increasing power dissipation range possible. Therefore, since variance within possible power dissipation range negligible, assumed calculation purposes that valid power levels. Using formulas introduced previously, Table shows results maximum power dissipation with heat sink air-flow (refer Table calculate other power dissipation values).
Table Thermal Parameters With Heat Sink Air-flow
Defined Parameters Watts Watts 125°C 125°C 1°C/W 1°C/W Measured 21.8°C/W 21.8°C/W 20.8°C/W 20.8°C/W Calculated 122°C 120°C 59.6°C 16°C
seen looking ambient temperature results, most users will want implement some type thermal management obtain more reasonable maximum ambient temperature. Thermal Characteristics Forced sample size three TS68040 packages tested forced cooling wind tunnel with heat sink. This test performed with power being dissipated from within package. previously mentioned, since variance within possible power range negligible, assumed calculation purposes that constant power levels. Using previous formulas, Table shows results maximum power dissipation with air-flow heat sink (refer Table calculate other power dissipation values).
Table Thermal Parameters With Forced Flow Heat Sink
Thermal Mgmt. Technique Air-flow velocity 1000 1000 Defined Parameters 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W Measured 11.7°C/W 10°C/W 8.9°C/W 8.5°C/W 8.3°C/W 11.7°C/W 10°C/W 8.9°C/W 8.5°C/W 8.3°C/W 10.7°C/W 9°C/W 7.9°C/W 7.5°C/W 7.3°C/W 10.7°C/W 9°C/W, 7.9°C/W 7.5°C/W 7.3°C/W Calculated 122°C 122°C 122°C 122°C 122°C 120°C 120°C 120°C 120°C 120°C 89.9°C 95°C 98.3°C 99.5°C 100.1°C 66.5°C 75°C 80.5°C 82.5°C 83.5°C
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reviewing maximum ambient operating temperatures, seen that using all-small-buffer configuration TS68040 with relatively small amount flow (100 LFM), 0-70°C ambient operating temperature achieved. However, depending output buffer configuration available forced-air cooling, additional thermal management techniques required. Thermal Characteristics with Heat Sink choosing heat sink designer must consider many factors: heat sink size composition, method attachment, choice connection. following paragraphs discuss relationship these decisions thermal performance design noticed during experimentation. heat sink size most significant parameters consider selection heat sink. Obviously larger heat sink will provide better cooling. However, less obvious that most benefit larger heat sink type used experimentation would still conditions. Under forced-air conditions LFM, difference between becomes very small (0.4°C/W less). This difference continues decrease forced flow increases. particular heat sink used testing perimeter package surface area available within capacitor pads TS68040 (1.48" 1.48") showed nice compromise between height thermal performance needs. heat sink base perimeter area 1.24" 1.30" height 0.49". pin-fin-type (i.e. nails) design composed alloy. heat sink shown Figure obtained through Thermalloy Inc. referencing part number 2338B. Figure Heat Sink Example
TS68040
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TS68040
heat sinks tested were made from extrusion products. planar face heat sink mating package should have good degree planarity; curvature, curvature should convex central region heat sink surface provide intimate physical contact surface. heat sinks tested this criteria. Nonplanar, concave curvature central regions heat sink will result poor thermal contact package. specification needs determined planarity surface part heat sink design. Although there several ways attach heat sink package, easiest demountable heat sink attach called "E-Z attach packages" developed Thermalloy (see Figure heat sink clamped package with help steel spring plastic frame plastic shoes Besides height heat sink plastic frame, additional height added package. interface between ceramic package heat sink evaluated both (i.e., thermal grease) interfaces still air. thermal grease reduced quite significantly (about °C/W) still air. Therefore, used other testing done with heat sink. According other testing, attachment with thermal grease provided about same thermal performance thermal epoxy were used. Figure Heat Sink with Attachment
sample size TS68040 package tested still with heat sink attachment method previously described. This test performed with power being dissipated from within package. Since variance within possible power range negligible, assumed calculation purposes that constant power levels. Table shows result assuming maximum power dissipation part (refer Table calculate other power dissipation values).
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Table Thermal Parameters With Heat Sink Flow
Thermal Mgmt. Technique Heat Sink 2338B 2338B Defined Parameters 125°C 125°C 1°C/W 1°C/W Measured 14°C/W 14°C/W 13°C/W 13°C/W Calculated 122°C 120°C 83°C 55°C
Thermal Characteristics with Heat Sink Forced
sample size three TS68040 packages tested forced-air cooling wind tunnel with heat sink. This test performed with power being dissipated from within package. mentioned previously, variance within possible power range negligible; assumed calculation purposes that valid power levels. Table shows results, assuming maximum power dissipation with flow heat sink thermal management (refer Table calculate other power dissipation values).
Table Thermal Parameters with Heat Sink Flow
Thermal Mgmt. Technique Air-flow 1000 1000 Heat sink 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B Defined Parameters 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 125°C 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W 1°C/W Measured 3.1°C/W 2.2°C/W 1.7°C/W 1.5°C/W 1.4°C/W 3.1°C/W 2.2°C/W 1.7°C/W 1.5°C/W 1.4°C/W 2.1°C/W 1.2°C/W 0.7°C/W 0.5°C/W 0.4°C/W 2.1°C/W 1.2°C/W 0.7°C/W 0.5°C/W 0.4°C/W Calculated 122°C 122°C 122°C 122°C 122°C 120°C 120°C 120°C 120°C 120°C 115.7°C 118.4°C 119.9°C 120.5°C 120.8°C 109.5°C 114°C 116.5°C 117.5°C 118°C
Thermal Testing Summary
Testing proved that heat sink combination with relatively small amount air-flow (100 less) will easily realize 0-70°C ambient operating temperature TS68040 with almost configuration output buffers. heat sink alone capable providing necessary cooling, depending particular heat sink height/size restraints, maximum ambient operating temperature required, output buffer configuration chosen. Also forced cooling alone attain 0-70°C ambient operating temperature. However this factor highly dependent output buffer configuration chosen available forced cooling. Figure summary test results relationship between air-flow TS68040.
TS68040
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TS68040
Figure Relationship Air-Flow
Table Characteristics Guaranteed
Package Symbol Parameter Thermal Resistance Junction-to-ambient Thermal Resistance Junction-to-case Thermal Resistance Junction-to-ambient Thermal Resistance Junction-to-case Value Figure Unit °C/W °C/W °C/W °C/W
CQFP
Mechanical Environment Marking
microcircuits shall meet mechanical environmental requirements either MILSTD-883 class devices Atmel standard screening. document where defined marking identified related reference documents. Each microcircuit legible permanently marked with following information minimum: Atmel Logo Manufacturer's Part Number Class Identification Date-code Inspection Identifier Available Country Manufacturing
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Quality Conformance Inspection
DESC/MIL-STD-883
accordance with MIL-M-38535 method 5005 MIL-STD-883. Group inspections performed each production lot. Groups inspection performed periodical basis.
Electrical Characteristics
General Requirements
static dynamic electrical characteristics specified inspection purposes relevant measurement conditions given below: Table Static electrical characteristics electrical variants. Table Dynamic electrical characteristics TS68040 MHz, MHz).
static characteristics (Table 12), test methods refer 748-2 method number, where existing. dynamic characteristics (Table 13), test methods refer clause "Static Characteristics" page this specification. Indication "min." "max." column means minimum maximum operating temperature defined sub-clause Table here above.
Static Characteristics
Table Electrical Characteristics -55°C TJmax; 4.75V 5.25V unless otherwise specified(1)(2)(3)(4)
Symbol Characteristic Input High Voltage Input Voltage Undershoot Input Leakage Current 0.5/2.4V Hi-z (Off-state) Leakage Current 0.5/2.4V Signal Input Current 0.8V Signal High Input Current 2.0V Output High Voltage Larger Buffers Small Buffers AVEC, BCLK CDIS, IPLn, MDIS, PCLK, RSTI, SCn, TBI, TCI, TCK, CIOUT, LOCK, LOCKE, R/W, SIZn, TDO, TIP, TLNn, TMn, TTn, UPAn TMS, TDI, TRST TMS, TDI, TRST Unit
ITSI
-1.1 -0.94
-0.18 -0.16
TS68040
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TS68040
Table Electrical Characteristics (Continued) -55°C TJmax; 4.75V 5.25V unless otherwise specified(1)(2)(3)(4)
Symbol Characteristic Output Voltage Larger buffers Small buffers Power Dissipation 125°C) Larger Buffers Enabled Small Buffers Enabled Unit
Notes:
Capacitance Note testing performed using worst-case test conditions unless otherwise specified. Maximum operating junction temperature (TJ) +125°. Minimum case operating temperature (TC) -55°. This device tested +125°. Testing performed setting junction temperature +125°and allowing case ambient temperatures rise fall necessary exceed maximum junction temperature. Capacitance periodically sampled rather than 100% tested. Power dissipation vary between limits depending application.
Dynamic Characteristics
Table Clock Timing Specifications (see Figure -55°C TJmax; 4.75V 5.25V unless otherwise specified(1)(2)(3)(4)
Frequency Operation PCLK Cycle Time PCLK Rise Time(4) PCLK Fall Time
(3)(4)
46.67 53.33 1000 Unit
Characteristic
PCLK Duty Cycle Measured 1.5V
47.5
52.5 10.5 10.5
PCLK Pulse Width High Measured 1.5V
PCLK Pulse Width Measured 1.5V(3)(4) BCLK Cycle Time BCLK Rise Fall Time BCLK Duty Cycle Measured 1.5V
1000
BCLK Pulse Width High Measured 1.5V BCLK Pulse Width Measured 1.5V PCLK, BCLK Frequency Stability
PCLK BCLK Skew Notes: testing performed using worst-case test conditions unless otherwise specified. Maximum operating junction temperature (TJ) +125°. Minimum case operating temperature (TC) -55°. This device tested +125°. Testing performed setting junction temperature +125°and allowing case ambient temperatures rise fall necessary exceed maximum junction temperature. Specification value maximum frequency operation. tested, shall guaranteed limits specified.
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Figure Clock Input Timing
Table Output Timing Specifications(1) (Figure Figure These output specifications only MHz. They must scaled lower operating frequencies. Refer TS6804DH/AD further information. -55°C TJmax; 4.75V 5.25V unless otherwise specified.(2)(3)(4)
Large Buffer(1) Characteristic BCLK address CIOUT, LOCK, LOCKE, R/W, SIZn, TLN, TMn, UPAn valid(5) BCLK output invalid (output hold) BCLK valid BCLK valid BCLK data-out valid(6) BCLK data-out invalid (output hold) BCLK output impedance
(5)(6)
Small Buffer(1) Large Buffer(1) 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 Small Buffer(1) 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 Unit
BCLK data-out high impedance BCLK multiplexed address valid(5) BCLK multiplexed address driven BCLK multiplexed address high impedance(5)(6) BCLK multiplexed data driven(6) BCLK multiplexed data valid
BCLK address CIOUT, LOCK, LOCKE, R/W, SIZn, TLNn, TMn, TTn, UPAn high impedance(5) BCLK high impedance BCLK valid BCLK valid BCLK valid BCLK IPEND, PSTn, RSTO valid
6.50 6.50 6.50 6.50
6.50 6.50 6.50 6.50
TS68040
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TS68040
Notes: Output timing specified valid signal measured pin. Large buffer timing specified driving transmission line with length characterized one-way propagation delay, terminated through 2.5V. Large buffer output impedance typically resulting incident wave switching this environment. Small buffer timing specified driving unterminated transmission line with length characterized one-way propagation delay. Small buffer output impedance typically small buffer specifications include approximately signal propagate length transmission line back. testing performed using worst-case test conditions unless otherwise specified. following pins active low: AVEC, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, RST0, RSTI, TBI, TCI, TEA, TIP, TRST, R/W. Maximum operating junction temperature (TJ) +125°. Minimum case operating temperature (TC) -55°. This device tested +125°. Testing performed setting junction temperature +125°and allowing case ambient temperatures rise fall necessary exceed maximum junction temperature. Timing specifications address output timing apply when normal operation selected. Specifications should used when multiplexed mode operation enabled. Timing specifications data output timing apply when normal operation selected. Specifications should used when multiplexed mode operation enabled.
Table Input Timing Specifications (Figure Figure -55°C TJmax; 4.75V 5.25V unless otherwise specified(1)(2)(3)(4)
Characteristic Data-in Valid BCLK (Setup) BCLK Data-in Invalid (Hold) BCLK Data-in High Impedance (Read Followed Write) Valid BCLK (Setup) Valid BCLK (Setup) Valid BCLK (Setup) Valid BCLK (Setup) BCLK TEA, TCI, Invalid (Hold) AVEC Valid BCLK (Setup) BCLK AVEC Invalid (Hold) Width High Data-in Valid (Setup) Data-in Invalid (Hold) BCLK Hold High BCLK Data-in Valid BCLK (DLE Mode Setup) BCLK Data-in Invalid (DLE Mode Hold) Valid BCLK (Setup) Valid BCLK (Setup) CDIS, MDIS Valid BCLK (Setup) IPLn Valid BCLK (Setup) BCLK CDIS, IPLn, MDIS Invalid (Hold) Address Valid BCLK (Setup) SIZn Valid BCLK (Setup) Min. Max. Min. 36.5 Max. Unit
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Table Input Timing Specifications (Figure Figure (Continued) -55°C TJmax; 4.75V 5.25V unless otherwise specified(1)(2)(3)(4)
Notes: Characteristic Valid BCLK (Setup) Valid BCLK (Setup) Valid BCLK (Setup) BCLK Address SIZn, TTn, R/W, Invalid (Hold) Valid BCLK (Setup) BCLK Invalid (Hold) BCLK High Impedance (68040 Assumes Mastership) RSTI Valid BCLK BCLK RSTI Invalid Mode Select Setup RSTI Negated
Min. Max. Unit
Min.
Max.
RSTI Negated Mode Selects Invalid testing performed using worst-case test conditions unless otherwise specified. following pins active low: AVEC, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, RST0, RSTI, TBI, TCI, TEA, TIP, TRST, R/W. Maximum operating junction temperature (TJ) +125°. Minimum case operating temperature (TC) -55°. This device tested +125°. Testing performed setting junction temperature +125°and allowing case ambient temperatures rise fall necessary exceed maximum junction temperature. levels CDIS, MDIS, IPL2-IPL0 signals enable disable multiplexed mode, data latch enable mode, driver impedance selection respectively.
TS68040
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TS68040
Figure Read/Write Timing
Note:
Transfer attribute signals UPAN, SIZN, TTN, TMN, TLNN, R/W, LOCK, LOCKE, CIOUT
Table JTAG Timing Application (Figure Figure -55°C TJmax; 4.75V 5.25V unless otherwise specified(1)(2)
Characteristic Frequency Cycle Time Clock Pulse Width Measured 1.5V Rise Fall Times TRST Setup Time Falling Edge TRST Assert Time Boundary Scan Input Data Setup Time Boundary Scan Input Data Hold Time Output Data Valid Output High Impedance TMS, Data Setup Time TMS, Data Hold Time Data Valid High Impedance Unit
2116A-HIREL-09/02
Notes:
testing performed using worst-case test conditions unless otherwise specified. Maximum operating junction temperature (TJ) +125°. Minimum case operating temperature (TC) -55°. This device tested +125°. Testing performed setting junction temperature +125° allowing case ambient temperatures rise fall necessary exceed maximum junction temperature.
Table Boundary Scan Instruction Codes
Instruction Selected Extest Highz Sample/Preload DRVCTLT Shutdown Private DRVCTLS Bypass Test Data Register Accessed Boundary Scan Bypass Boundary Scan Boundary Scan Bypass Bypass Boundary Scan Bypass
Switching Test Circuit Waveforms
Figure Address Data Timing Multiplexed Mode
TS68040
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TS68040
Figure Timing Burst Access
Figure Arbitration Timing
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Figure Snoop Timing
TS68040
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TS68040
Figure Snoop Miss Timing
Figure Other Signal Timing
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Figure Clock Input Timing Diagram
Figure TRST Timing Diagram
Figure Boundary Scan Timing Diagram
TS68040
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TS68040
Figure Test Access Port Timing Diagram
Functional Description
Programming Model
TS68040 integrates functions integer unit, MMU, FPU. shown Figure registers depicted programming model provide access control three units. registers partitioned into levels privilege: user supervisor. User programs, executing user mode, only resources user model. System software, executing supervisor mode, unrestricted access processor resources. integer portion user programming model, consisting general-purpose, 32-bit registers control registers, same user programming model TS68030. TS68040 user programming model also incorporates TS68882 programming model consisting eight, floating-point, 80-bit data registers, floatingpoint control register, floating-point status register, floating-point instruction address register. supervisor programming model used exclusively TS68040 system programmers implement operating system functions, control, memory management subsystems. This supervisor/user distinction TS68000 architecture carefully planned that application software written execute nonprivileged user mode migrate TS68040 from TS68000 platform without modification. Since system software usually modified system designers when porting design, control features properly placed supervisor programming model. example, transparent translation registers TS68040 only read written supervisor software; programming resources user application programs unaffected existence transparent translation registers Registers D0-D7 data registers containing operands field 32-bit), byte (8-bit), word (16-bit), long-word (32-bit), quad-word (64-bit) operations. Registers A0-A6 stack pointer registers (user, interrupt, master) address registers that used software stack pointers base address registers. Register user stack pointer user mode, either interrupt master stack pointer (A7' A7'') supervisor mode. supervisor mode, active stack pointer (interrupt master) selected based status register (SR). address
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registers used word long-word operations, general-purpose registers (D0-D7, A0-A7 Figure used index registers. eight, 80-bit, floating-point data registers (FP0-FP7) analogous integer data registers (D0-D7) TS68000 Family processors. Floating-point data registers always contain extended-precision numbers. external operands, regardless data format, converted extended-precision values before being used floating-point calculation stored floating-point data register. program counter (PC) usually contains address instruction being executed TS68040. During instruction execution exception processing, processor automatically increments contents places value appropriate. status register supervisor programming model) contains condition codes that reflect results previous operation used conditional instruction execution program. lower byte accessible user mode condition code register (CCR). Access upper byte restricted supervisor mode. part exception processing, vector number exception provides index into exception vector table. base address exception vector table stored vector base register (VBR). displacement exception vector added value when TS68040 accesses vector table during exception processing. Alternate function code registers, (source destination), contain 3-bit function codes. Function codes considered extensions 32-bit linear address. Function codes automatically generated processor select address spaces data program accesses user supervisor modes. alternate function code registers used certain instructions explicitly specify function codes various operations. cache control register (CACR) controls enabling on-chip instruction data caches TS68040. supervisor root pointer (SRP) user root pointer (URP) registers point root address translation table tree used supervisor mode user mode accesses. used logical address zero, used one. translation control register (TC) enables logical-to-physical address translation selects either page sizes. shown Figure there four transparent translation registers ITT0 ITT1 instruction accesses DTT0 DTT1 data accesses. These registers allow portions logical address space transparently mapped accessed without resident descriptors ATC. status register (MMUSR) contains status information from execution PTEST instruction. PTEST instruction searches translation tables logical address specified this instruction's effective address field DFC. 32-bit floating-point control register (FPCR) contains exception enable byte that enables disables traps each class floating-point exceptions mode byte that sets user-selectable modes. FPCR read written user cleared hardware reset restore operation null state. When cleared, FPCR provides IEEE standard defaults. floating-point status register (FPSR) contains condition code byte, quotient bits, exception status byte, accrued exception byte. bits FPSR read written user. Execution most floating-point instructions modifies this register.
TS68040
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TS68040
subset instructions that generate exception traps, 32-bit floatingpoint instruction address register (FPIAR) loaded with logical address instruction before instruction executed. This address then used floating-point exception handler locate floating-point instruction that caused exception. move floating-point data register (FMOVE) instruction from FPCR, FPSR, FPIAR) move multiple data registers (FMOVEN) instruction cannot generate floating-point exceptions; therefore, these instructions modify FPIAR. Thus, FMOVE FMOVEM instructions used read FPIAR trap handler without changing previous value. Figure Programming Model
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Data Types Addressing Modes
Table Data Types
Operand Data Type Field Byte Integer Word Integer Long-word Integer Quad-word Integer 16-byte Single-precision Real Double-precision Real Extended-precision Real Note: Integer Unit.
TS68040 supports basic data types shown Table Some data types apply only integer unit, some only FPU, some both integer unit FPU. addition, instruction supports operations other data types such memory addresses.
Execution Unit (IU(1), FPU) data registers Memory-only, aligned 16-byte boundary 1-bit sign, 8-bit exponent, 23-bit mantissa 1-bit sign, 11-bit exponent, 52-bit mantissa 1-bit sign, 15-bit exponent, 64-bit mantissa Field consecutive bits Packaged: digits byte Unpacked: digit byte
Size 1-bit 1-32 bits bits bits bits bits bits bits bits bits bits
Notes
three integer data formats that common both integer unit (byte, word, long word) standard twos-complement data formats defined TS68000 Family architecture. Whenever integer used floating-point operation, integer automatically converted extended-precision floatingpoint number before being used. ability effectively integers floating-point operations saves user memory because integer representation number usually requires fewer bits than equivalent floating-point representation. Single- double-precision floating-point data formats implemented defined IEEE standard. These data formats main floating-point formats should used most calculations involving real numbers. extended-precision data format also conformance with IEEE standard, standard does specify this format level does single- double-precision. memory format consists bits (three long words). Only bits actually used; other bits reserved future longword alignment floating-point data structures memory. extended-precision format 15-bit exponent, 64-bit mantissa, 1-bit mantissa sign. Extendedprecision numbers intended temporary variables, intermediate values, where extra precision needed. TS68040 addressing modes shown Table register indirect addressing modes support post-increment, predecrement, offset, indexing, which particularly useful handling data structures common sophisticated applications high-level languages. program counter indirect mode also indexing offset capabilities; this addressing mode typically required support positionindependent software. addition these addressing modes, TS68040 provides index sizing scaling features that enhance software performance. Data formats supported orthogonally arithmetic operations appropriate addressing modes.
TS68040
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TS68040
Table Addressing Modes
Addressing Modes Register Direct Date Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect With Postincrement Address Register Indirect With Predecrement Address Register Indirect With Displacement Register Indirect With Index Address Register Indirect With Index (8-bit Displacement) Address Register Indirect With Index (Base Displacement) Memory Indirect Memory Indirect Postincrement Memory Indirect Preindexed Program Counter Indirect With Displacement Program Counter Indirect With Index Indirect With Index (8-bit Displacement) Indirect With Index (Base Displacement Program Counter Memory Indirect Memory Indirect Postindexed Memory Indirect Preindexed Absolute Absolute Short Absolute Long Immediate Note: Syntax (An) (An) (An) (d16, (d8, (bd, ([bd, An], ([bd, Xn], (d16, (d8, (bd, ([bd, PC], ([bd, Xn], xxx.W xxx.L (data)
Data register, D0-D7 Address register, A0-A7 twos-complement sign-extended displacement; added part effective address calculation; size (d8) (d16) bits; when omitted, assemblers value zero. Address data register used index register; form SIZE*SCALE, where SIZE (indicates index register size) SCALE (index register multiplied SCALE); SIZE SCALE optional. twos-complement base displacement; when present, size bits. Outer displacement added part effective address calculation after memory indirection; optional with size bits. Program counter. Immediate value bits. Effective address. Used indirect address long-word address. Instruction Overview
(data)
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instruction provided TS68040 listed Table instruction been tailored support high-level languages optimized those instructions most commonly executed (however, instructions listed fully supported). Many instructions operate bytes, words, long words, most instructions addressing modes Table Table Instruction Summary
Mnemonic ABCD ADDA ADDI ADDQ ADDX ANDI ASL, BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BSET BTST CAS2 CHK2 CINV(1) CMPA CMPI CMPM CMP2 CPUSH(1) DBCC DIVS, DIVSL DIVU, DIVUL EORI EXT, EXTB Test Condition, Decrement Branch Signed Divide Unsigned Divide Logical Exclusive Logical Exclusive Immediate Exchange Registers Sign Extend Description Decimal With Extend Address Immediate Quick With Extend Logical Logical Immediate Arithmetic Shift Left Right Branch Conditionally Test Change Test Clear Test Field Change Test Field Clear Signed Field Extract Unsigned Field Extract Field Find First Field Insert Test Field Test Field Breakpoint Branch Test Branch Subroutine Test Compare Swap Operands Compare Swap Dual Operands Check Register Against Bounds Check Register Against Upper Lower Bounds Invalidate Cache Entries Clear Compare Compare Address Compare Immediate Compare Memory Memory Compare Register Against Upper Lower Bounds Push Then Invalidate Cache Entries
TS68040
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TS68040
Table Instruction Summary (Continued)
Mnemonic ILLEGAL LINK LSL, MOVE MOVE16(1) MOVEA MOVE MOVE MOVE MOVEC(1) MOVEM MOVEP MOVEQ MOVES(1) MULS MULU NBCD NEGX PACK PFLUSH(1) PTEST(1) RESET ROL, ROXL, ROXR Description Take Illegal Instruction Trap Jump Jump Subroutine Load Effective Address Link Allocate Logical Shift Left Right Move 16-byte Block Move Move Address Move Condition Code Register Move Status Register Move User Stack Pointer Move Control Register Move Peripheral Move Quick Move Alternate Address Space Move Multiply Signed Multiply Unsigned Multiply Negate decimal with extend Negate Negate with extend operation Logical complement Logical Inclusive Logical Inclusive Immediate Pack Push Effective Address Flush Entry(ies) ATCs Test Logical Address Reset External Devices Rotate Left Right Rotate With Extend Left Right Return Deallocate Return From Exception Return Restore Codes Return From Subroutine
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Table Instruction Summary (Continued)
Mnemonic SBCD STOP SUBA SUBI SUBQ SUBX SWAP TRAP TRAPcc TRAPV Description Substract Decimal With Extend Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract With Extend Swap Register Words Test Operand Trap Trap Conditionally Trap Overflow Trap Operand
UNLK Unlink UNPK Unpack Note: TS6840 additions alterations TS68030 TS68881/TS68882 instructions sets.
Table Floating-point instructions
Mnemonic FABS(1) FADD(1) FBcc FCMP FDBcc FDIV(1) FMOVE(1) FMOVEM FMUL(1) FNEG(1) FRESTORE FSAVE FScc FSQRT(1) FSUB(1) FTRAPcc FTST Note: Description Floating-point Absolute Value Floating-point Branch Floating-point Condition Floating-point Compare Floating-point Decrement Branch Floating-point Divide Move Floating-point Register Move Multiple Floating-point Registers Floating-point Multiply Floating-point Negate Restore Floating-point Internal State Save Floating-point Internal State According Floating-point Condition Floating-point Square Root Floating-point Substract Trap Floating-point Condition Floating-point Test
TS6840 additions alterations TS68030 TS68881/TS68882 instructions sets.
TS68040 floating-point instructions, commonly used subset TS68882 instruction set, implemented hardware. remaining unimplemented instructions less frequently used efficiently emulated software, maintaining compatibility with TS68881/TS68882 floating-point coprocessors. TS68040 instruction includes MOVE16, user instruction that allows highspeed transfers 16-byte blocks between external devices such memory memory coprocessor memory.
TS68040
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TS68040
Instruction Data Caches
Studies have shown that typical programs spend much their execution time main routines tight loops. Earlier members TS68000 Family took advantage this locality reference phenomenon varying degrees. TS68040 takes further advantage cache technology with two, independent, on-chip, physical address space caches, instructions data. caches reduce processor's external activity increase throughput lowering effective memory access time. typical system design, large caches TS68040 yield very high rate, providing substantial increase system performance. Additionally, caches automatically burstfilled from external whenever cache miss occurs. autonomous nature caches allows instruction-stream fetches, data-stream fetches, third external access occur simultaneously with instruction execution. example, TS68040 requires both instruction-stream access external peripheral access instruction resident on-chip cache, peripheral access proceeds unimpeded rather than being queued behind instruction fetch. data operand also required resident data cache, also accessed without hindering either instruction access from cache peripheral access external chip. parallelism inherent TS68040 also allows multiple instructions that require external accesses execute concurrently while processor performing external access previous instruction. Cache Organization instruction data caches four-way set-associative with sets four, 16byte lines total cache storage bytes each. shown Figure each 16byte line contains address state information. State information each entry consists valid flag entire line both instruction data caches write status each long word data cache. write status data cache signifies whether long-word data dirty (meaning that data cache been modified been written back external memory) data copyback pages.
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Figure Cache Organization Overview
caches accessed physical addresses from on-chip MMUs. translation upper bits logical address occurs concurrently with accesses into array cache lower address bits. output compared with field cache determine lines selected matches translated physical address. matches entry valid, then cache hit. cache hits access read, appropriate long word from cache line multiplexed onto appropriate internal bus. cache hits access write, data, regardless size, written appropriate portion corresponding longword entry cache. When data cache miss occurs previously valid cache line needed cache line, dirty data line will internally buffered copied back memory after cache line been loaded. Pushing dirty data forced CPUSH instruction.
TS68040
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TS68040
Cachability data each memory page controlled bits page descriptor each page. Cachable pages either write through copyback, with writeallocate misses write through pages. Non-cachable pages also specified non-cachable I/O, forcing accesses these pages occur order instruction execution. Cache Coherency TS68040 ability snoop external during accesses other masters maintain coherency between TS68040's caches external memory systems. External write cycles snooped both instruction cache data cache; whereas, external read cycles snooped only data cache. addition, external cycles flagged snoopable snoopable. When external cycle marked snoopable, snooper checks caches coherency conflict based state corresponding cache line type external cycle. Although internal execution units snooper circuit have access on-chip caches, snooper priority over execution units allow snooper resolve coherency discrepancies immediately. Cache Instructions TS68040 supports following instructions cache maintenance. Both instructions selectively operate data instruction cache. CINV: Invalidates single line, lines physical page, entire cache. CPUSH: Pushes selected dirty data cache lines memory, then invalidates selected lines.
Operand Transfer Mechanisms
Transfer Types
TS68040 external synchronous supports multiple masters overlaps arbitration with data transfers. optimized perform high-speed transfers from external cache memory. data address buses each bits wide. TS68040 provides signals (TT1-TT0) that define four types transfers: normal access, MOVE16 access, alternate access, interrupt acknowledge access. Normal accesses identify normal memory references: MOVE16 accesses memory accesses MOVE16 instruction; alternate accesses identify accesses undefined address spaces (function code values interrupt acknowledge access used fetch interrupt vector during interrupt exception processing. During burst read write cache transfers, values address transfer type signals change; they address first requested item cache line. When TS68040 request burst read transfer cache line, address indicates address long word line needed first, memory system expected provide data following order (modulo (long-word offsets). first address needed from offset nevertheless, four long words must transferred. Burst writes occur similar manner. snooping ensures that data main memory consistent with data on-chip caches. alternate master performing read transfer snooping enabled, snoop logic determines that on-chip data cache dirty data (data valid consistent with memory) this transfer, memory prevented from responding read request, TS68040 supplies data directly master. alternate master performing write transfer snooping enabled, snooper determines that on-chip caches valid line this request, then snooper either invalidate update line selected snoop control signals.
Burst Transfer Operation
Snooping
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Exception Processing
TS68040 provides same extensions exception stacking process TS68030. status register set, master stack pointer used task-related exceptions. When nontask-related exception occurs (i.e., interrupt), cleared, interrupt stack pointer used. This feature allows task's stack area carried within single processor control block, tasks initiated simply reloading master stack pointer setting bit. externally generated exceptions interrupts, errors, reset conditions. interrupts requests from external devices processor action; whereas, error reset signals used access control processor initialization. internally generated exceptions come from instructions, address errors, tracing, breakpoints. TRAP, TRAPcc, TRAPVcc, FTRAPcc, CHK, CHK2, instructions generate exceptions part their instruction execution. Tracing behaves like very high-priority, internally generated interrupt whenever processed. other internally generated exceptions caused unimplemented floating-point instructions, illegal instructions, instruction fetches from addresses, privilege violations. Finally, generate exceptions, access violations when invalid descriptors encountered during table searches. Exception processing TS68040 occurs following sequence: internal copy made status register, vector number exception determined, current processor status saved, exception vector offset determined multiplying vector number four. This offset then added contents determine memory address exception vector. instruction address given exception vector fetched, normal instruction decoding execution started.
Memory Management Units
full addressing range TS68040 bytes (4,294,967,296 bytes). However, most TS68040 systems implement much smaller physical memory. Nonetheless, using virtual memory techniques, system made appear have full bytes physical memory available each user program. independent instruction data MMUs fully support demand paged virtual-memory operating systems with either page sizes. addition main function memory management, each protects supervisor areas from accesses user programs also provides write protection page-by-page basis. maximum efficiency, each operates parallel with other processor activities. Because logical-to-physical address translation most frequently executed operations TS68040 MMUs, this task been optimized. Each initiates address translation searching descriptor containing address translation information ATC. descriptor does reside ATC, then performs external cycles controller search translation tables physical memory. After being located, page descriptor loaded into ATC, address correctly translated access, provided exception conditions encountered.
Translation Mechanism
TS68040
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TS68040
Address Translation Cache integral part translation function previously described dual cache memory that stores recently used logical-to-physical address translation information (page descriptors) instruction date accesses. These caches 64-entry, four-way, associative. Each compare logical address incoming access against entries. entries matches, there hit, sends physical address controller, which then starts external cycle (provided there corresponding cache access). translation tables TS68040 have three level tree structure reside main memory. Since only portion complete tree needs exist time, tree structure minimizes amount memory necessary tables most programs. shown Figure either user root pointer supervisor root pointer points first level table, depending values function code access. Table entries second level tree (pointer tables) contain pointers third level (page tables). Entries page tables contain either page descriptors indirect pointers page descriptors. mechanism performing table search operations uses portions logical address indices) each level search. addresses translation table entries physical addresses. Figure Translation Table Structure
Translation Tables
There variations table searches both page sizes: normal searches indirect searches. indirect search differs that entry third level page table contains pointer page descriptor rather than page descriptor itself. Entries translation tables contain control status information addition physical address information. Control bits specify write protection, limit access supervisor only, determine cachability data each memory page. Each page descriptor also user-programmable bits that appear UPA0 UPA1 signals during external access address modifier bits.
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global each page descriptor prevent flushing entry that page some PFLUSH instruction variants, allowing system entries remain resident during task swaps. these special PFLUSH instructions used, this user defined. MMUs automatically maintain access history information pages updating used modified status bits. Instructions instructions supported TS68040 follows: PFLUSH: Allows flushing either selected entries function code logical address entire ATCs. PTEST: Takes address function code searches translation tables corresponding entry, which then loaded into ATC. results search available status register often useful determining cause fault. TS68040 instructions privileged only executed from supervisor mode. Transparent Translation Four transparent translation registers, each instruction data accesses, have been provided TS68040 allow portions logical address space transparently mapped accessed without need corresponding entries resident ATC. Each register used define range logical addresses from bytes bytes with base address mask. addresses within these ranges mapped, optionally protected against user supervisor accesses write accesses. Logical addresses these areas become physical addresses memory access. transparent translation feature allows rapid movement large blocks data memory space without disturbing context on-chip ATCs incurring delays associated with translation table searches.
Preparation Delivery
Packaging
Microcircuits prepared delivery accordance with MIL-M-38510 Atmel standard.
Certificate Compliance Atmel offers certificate compliances with each shipment parts, affirming products compliance either with MIL-STD-883 Atmel standard guarantying parameters tested temperature extremes entire temperature range.
Handling
devices must handled with certain precautions avoid damage accumulation static charge. Input protection devices have been designed chip minimize effect this static buildup. However, following handling practices recommended: Devices should handled benches with conductive grounded surfaces. Ground test equipment, tools operator. handle devices leads. Store devices conductive foam carriers. Avoid plastic, rubber, silk areas. Maintain relative humidity above percent practical.
TS68040
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TS68040
Package Mechanical Data
pins
Millimeters
Inches 1.845 1.845 0.094 0.170 0.045 0.045 1.875 1.875 0.116 0.190 0.055 0.055
46.863 46.863 2.3876 4.318 1.143 1.143 2.54 0.432
47.625 47.625 1.875 4.826
0.100 0.483 0.017 0.019
Note:
untinned leads (gold)
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pins CQFP Cavity request)
Millimeters 3.30 0.23 +0.05 0.23 -0.038 0.635 typ. 33.91 0.25 0.89 0.13 63.5 0.51
Inches 0.130 0.009 +0.002 0.009 -0.015 .025 typ. 1.335 0.01 0.035 0.005 0.02
TS68040
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TS68040
pins Gullwing CQFP cavity
Reduce count shown clarity, pins side
Symbol Millimeters 4.19 0.673 0.23 +0.05 0.23 -0.038 0.127 +0.05 0.127 -0.025 HD/HE 33.91 ±0.25 .635 30.48 ±0.13 38.8 ±0.18 0.813 ±0.2 0.55 ±0.25 0.23 .005 -.001 1.335 ±.01 .025 ±.005 1.528 ±.007 .032 ±.008 .022 ±.01 .009 Inches 0.165 .0265 ±.008 .009 +.002 .009 -.0015 .005 +.002
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Ordering Information
MIL-STD-883 Internal Standard
TS68040
Device
Revision level Operating frequency: Screening level: B/C: MIL-STD-883, class D/T: Internal standard with burn-in Upscreening U/T: Upscreening burn-in Internal standard Lead finish: solder dip(1) Gold(2)
Temperature range: -55; +125°C -40; +110°C
Package: CQFP/Gullwing leads CQFP Flat tie-bar(3)
Standard lead finish Gold Gold Gold
Notes:
request. Standard process. request small quantity.
DESC Drawing 5962-93143
TS68040 DESC
Device
Revision level
DESC Screening
Lead finish: solder Gold
Speed:
Package: CQFP Flat tie-bar CQFP Gullwing leads
TS68040
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TS68040
Detailed TS68040 Part List
Hi-REL Product
Commercial Atmel Part Number TS68040MRB/C25A TS68040MRB/C33A TS68040MFB/C25A TS68040MFB/C33A TS68040DESC01XAA TS68040DESC02XAA TS68040DESC01XCA TS68040DESC02XCA TS68040DESC01YCA TS68040DESC02YCA TS68040DESC01ZAA TS68040DESC01ZCA TS68040DESC02ZAA TS68040DESC02ZCA TS68040MFB/C25A TS68040MFB/C33A TS68040MRD/T25A TS68040MRD/T33A TS68040MFD/T25A TS68040MFD/T33A Norms MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC MIL-STD-883 MIL-STD-883 BURN BURN BURN BURN Package CQFP CQFP gold gold CQFP gold CQFP gold CQFP gullwing CQFP gullwing gold CQFP gullwing CQFP gullwing gold CQFP CQFP CQFP CQFP Temperature range (°C) -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 -55/+TJ +125 Frequency (MHz) Drawing number Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet 5962-9314301MXA 5962-9314302MXA 5962-9314301MXC 5962-9314302MXC 5962-9314301MYC 5962-9314302MYC 5962-9314301MZA 5962-9314301MZC 5962-9314302MZA 5962-9314302MZC Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet
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Standard Product
Commercial Atmel Part Number TS68040VR25A TS68040VR33A TS68040MR25A TS68040MR33A TS68040VF25A TS68040VF33A TS68040MF25A TS68040MF33A Note: Norms Atmel standard Atmel standard Atmel standard Atmel standard Atmel standard Atmel standard Atmel standard Atmel standard Package CQFP CQFP CQFP CQFP Temperature Range (°C) -40/+TJ +110 -40/+TJ +110 -55/+TJ +125 -55/+TJ +125 -40/+TJ +110 -40/+TJ +110 -55/+TJ +125 -55/+TJ +125 Frequency (MHz) Drawing Number Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet
available request.
TS68040
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ThirdGeneration 32-bit Microprocessor TS68040 Description TS

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