The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

T6K53 Four-Grayscale Matrix Graphic Driver with Built-in T6K


Datasheet Thumbnail

  

Download PDF



Top Searches for this datasheet



T6K53
T6K53
Four-Grayscale Matrix Graphic Driver with Built-in
T6K53 single-chip, color driver with built-in which control 4096 colors. T6K53 Unit: output common drivers output segment drivers. Lead Pitch T6K53 capable driving graphics display with T6K53 colors dots. interface allows efficient command setting high-speed access display 16-bit parallel Please contact Toshiba authorized interface means High-Speed Write function. Toshiba dealer information package T6K53 grayscale modes: Fixed-Palette Mode (with dimensions. predetermined gray levels) Selected Palette Mode. Selected Palette Mode T6K53 enables high-quality display characteristics allowing selection gray levels from (Tape Carrier Package) LCD's available levels. T6K53 driver driven using single power supply, since incorporates voltage regulator, voltage-dividing resistance, driver op-amp, DC-DC converter (with holds) contrast (electronic volume) control circuit. Since T6K53 supports various display functions (e.g. partial display function Area Scroll Mode), suitable applications which require long battery lifetime, such Web-capable mobile phones.
Features
Driver output Display Grayscale function (384 outputs) 245,760 bits 4096 colors displayed with levels, levels levels grayscale system (with 16-level fixed palette) Word length Display modes bits/16 bits Normal Display Mode Partial Display Mode Standby Mode interfaces access cycle Oscillator Operating voltage Display operating voltage lower Built-in oscillator (with built-in oscillation CR). External clock pulses input. 20.0 VLC1, VLC2, VLC3 VLC4 Regulator 0.0%/°C 0.02% CMOS process Package power consumption 0.35 (typ.) target value Usage conditions display voltage 20.0 load, 25°C, fFrame fosc (with internal oscillator used), data access Full display Partial display Clock stopped
8-bit/16-bit switching, 68/80 Series parallel interface serial interface
Built-in display power supply circuits: DC-DC converter (max) booster
2001-11-07
T6K53
Assignment
COM80
COM159 SEGC127
SEGA0 COM79
COM0
(Input layout finalized.)
2001-11-07
T6K53
Functions
name SEGA0 SEGA127 SEGB0 SEGB127 SEGC0 SEGC127 COM0 COM159 DB15 /CS1 Functions drive segment signal output (red blue): selected using SWP. drive segment signal output (green) drive segment signal output (red blue): selected using SWP. drive common signal output Data Chip Select signal input Data write.Data written rising edge /CS1 Data read.Data read while /CS1 Low. Chip Select signal input Data write.Data written falling edge CS2. Data read.Data read while High. Register instruction data select signal input High, DB15 read register number. Low, DB15 read instruction data. Write Select signal input (Read/Write select signal input) Series selected, data written when Low. Series selected, whether Read Write effect indicated. Read Select signal input Series selected, data output while Low. Series selected, this used enable signal input (E). 68/80 Series parallel interface select signal input High, Series parallel interface selected. Low, Series parallel interface selected. Data Width Select signal input 8-Bit Mode Low. 16-Bit Mode High. Reset signal reset occurs /RST Low. Built-in oscillation monitoring Internal Oscillation Mode: Output External Oscillation Mode: Input External Power Supply Mode Internal Power Supply Mode Low. External Power Supply Mode High. External Power Supply Mode, DCDC will remain regardless command settings. Input Parallel/Serial Interface Select signal serial interface selected Low. parallel interface selected High. Serial interface clock input Serial interface data input Serial interface data output regulator output Booster capacitor connection Booster output. Usually connected VCC. Power supply drive voltage generation drive voltage output Supply voltage
(R/W)
/RST
OSC1
VREF VOUT VLC5, VLC4, VLC3, VLC2, VLC1 VDD,VSS
2001-11-07
T6K53
Power Supply Configuration
Draft power supply circuit (preliminary)
VLC0
VLC1 VOUT Contrast Control VLC2 BIAS VLC3 DC-DC
VLC4 Regulator VLC5
VREF
2001-11-07
T6K53
Signal Timing
interface
Series
/CS1 accessed with when /CS1 Low. /RD,
/CS1 accessed with /CS1 when Low. /RD,
DB15 (Write) (Read) DB15 (Command Read) Hi-Z
Series
D/I,
accessed with when High.
accessed with when High.
DB15 (Write) (Read) DB15 (Command Read) Hi-Z
2001-11-07
T6K53
Display Control Section Signal
Scanning period (frame period)
Alternating setting clock pulses)
Line
Line
Line
Line
Clock: Clock
Signal indicating frames Alternating signal. Display waveforms made alternate sync with this signal. Shift clock, used synchronize display data output with output. Minimum clock used reference driving LCD. used control pulse levels.
2001-11-07
T6K53
Functions
interfaces
interfaces connected directly data 8-bit/16-bit data transfer. used select either Series interface 8-bit/16-bit MPU.
type Series Series
/CS1
Data DB15 DB15
Data identification
contents data identified using combination signals.
Series Register Status read Display data read Command display data write
Series
Function
16-bit access display
T6K53 supports 16-bit data access. Data 16-bit data (DB0 DB15) used access display RAM. used specify 16-Bit Access Mode data mode.
Data width 16-Bit Access Mode 8-Bit Access Mode
DB15 DB15 High input
Note that even 16-Bit Access Mode, internal registers accessed 8-Bit Mode (DB0 DB7). Therefore, 16-Bit Access Mode only valid display access.
2001-11-07
T6K53
Data mode display address
sets display addresses using Y-addresses which pixel units. When data mode switched, address conversion handled automatically. following paragraphs describe display addresses each data mode. 8-Bit Mode this mode, single pixel's data transferred using 8-bit data accesses. Hence, 8-bit data accesses used. transfer format follows: first access sets low-order bits value low-order bits, second access sets high-order bits value high-order bits. example, data transfer interrupted after fifth access access another command register), access will resumed using high-order bits 002H (unless Y-Adr been reset). restart data access from point which interrupted, Y-Adr 002H.
Pixel Y-Adr Data Access
First pixel 000H
Second pixel 001H
Second First Fourth Third
Start Y-Adr: When 000H
Pixel Y-Adr Data Access Second First pixel 000H First Fourth Second pixel 001H Third Sixth Third pixel 002H Fifth Eighth Fourth pixel 003H Seventh Tenth Fifth pixel 004H Ninth
Start Y-Adr: When 002H
Pixel Y-Adr Data Access
Third pixel 002H Second First
Fourth pixel 003H Fourth Third
Fifth pixel 004H Sixth Fifth
Sixth pixel 005H Eighth Seventh
Seventh pixel 006H Tenth Ninth
Pixel Display pixel Y-Adr Y-Address Display data Data Data Access: Number accesses
2001-11-07
T6K53
16-Bit Mode This mode transfers one-pixel data with 16-bit data access. data access 16-bit used. low-order bits (D11 correspond bits.
Pixel Y-Adr Data Access
First pixel 000H
Second pixel 001H
First Second
Start Y-Adr: When 000H
Pixel Y-Adr Data Access
First pixel 000H First
Second pixel 001H Second
Third pixel 002H Third
Fourth pixel 003H Fourth
Fifth pixel 004H Fifth
Start Y-Adr: When 002H
Pixel Y-Adr Data Access
Third pixel 002H First
Fourth pixel 003H Second
Fifth pixel 004H Third
Sixth pixel 005H Fourth
Seventh pixel 006H Fifth
Pixel Display pixel Y-Adr Y-address Display data Data Data Access: Number accesses
2001-11-07
T6K53
Display
T6K53 incorporates bitmap display consisting pixels levels. display section consists bits 1536 bits) Y-address direction bits X-address direction. grayscale controlled 4-bit segment driver outputs which correspond grayscale levels. Hence, three segment driver outputs service pixel, using four bits each levels total bits supporting 4096 display colors levels levels levels). sets each address pixel units Y-address/X-address pairing, shown below:
SEGAi SEGBi SEGCi
Grayscale control
Grayscale control
Grayscale control
Y-adr X-adr X-adr X-adr
Y-adr
Y-adr
X-adr
2001-11-07
T6K53
Display Addresses
Data area accessed continuously. data access performed address area (X-address Y-address 7FH) Y-Address Count Mode, Y-address changes from 01H. data access performed while Y-address 7FH, Y-address will become X-address will incremented 01H. data access performed when Y-address X-address 9FH, Y-address X-address will both 00H. data access performed X-Address Count Mode, X-address will incremented from 01H. Every time data access performed when X-address 9FH, X-address will wrap around Y-address will 01H. data access performed when Y-address X-address 9FH, Y-address X-address will both 00H.
Y-Address Count Mode (Y-adr area X-adr area 9FH)
Y-address
X-address
X-Address Count Mode (Y-adr area X-adr area 9FH)
Y-address
X-address
2001-11-07
T6K53
Setting Display Access Area
Setting access area using Y-address control circuit X-address control circuit allows only part address area accessed.
Y-address area
X-address area
Y-address control circuit
Y-Address Count Mode, setting addresses Y-address area (Y-start Y-end) causes Y-address incremented from Y-start address Y-end address then wrap around back Y-start address. When Y-address wraps around, X-address also incremented one.
X-address control circuit
X-Address Count Mode, setting addresses X-address area (X-start X-end) causes X-address incremented from X-start address X-end address then wrap around back X-start address. When X-address wraps around, Y-address also incremented one.
2001-11-07
T6K53
Display Direction
used direction segment display. This implemented inverting Y-address when display data written.
SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA127 SEGB127 SEGC127
High
SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA127 SEGB127 SEGC127
used change direction scanning. scanning directions shown below.
1/144 duty
COM0 COM8 COM0 COM8
Display Area
Display Area
COM151 COM159
COM151 COM159
1/160 duty
COM0 COM0
Display Area
Display Area
COM160
COM160
2001-11-07
T6K53
used change assignments outputs (Ai, Ci). This function implements swapping grayscale control circuits.
SEGCi
SEGAi
SEGBi
SEGCi
SEGAi
SEGBi
Grayscale level control
Grayscale level control
Grayscale level control
Grayscale level control
Grayscale level control
Grayscale level control
data
SEGCi
SEGAi
SEGBi
SEGCi
SEGAi
SEGBi
Grayscale level control
Grayscale level control
Grayscale level control
Grayscale level control
Grayscale level control
Grayscale level control
data
SEGAi SWAP Blue SWAP
SEGBi Green Green
SEGCi Blue Color Corresponding bits Color Corresponding bits
2001-11-07
T6K53
Relationship between SDR-/SWP-based display output
Output Color Data Y-address
SEG0 Green Blue
SEG1 Green Blue
SEG127 Green Blue
Output Color Data Y-address Blue
SEG0 Green Blue
SEG1 Green Blue
SEG127 Green
Output Color Data Y-address Blue
SEG0 Green Blue
SEG1 Green Blue
SEG127 Green
Output Color Data Y-address
SEG0 Green Blue
SEG1 Green Blue
SEG127 Green Blue
2001-11-07
T6K53
Display Modes
following display modes supported. Mode Display Mode Mode Each mode described below.
Normal Mode
This mode which used normally. selected when reset occurs. start display practice, however, requires execution Display command. Normal Mode uses following settings: Display size Duty cycle setting Display bias Bias Contrast setting: Contrast
Display ON/OFF
Display
Once reset function executed, following settings must made before Display executed: Mode Executing Display sets /DOFF High takes circuit Display state, thus enabling display.
Display
Executing Display command causes following: outputs VLC2 VLC3 (inverted outputs VLC1 VLC4 (inverted
2001-11-07
T6K53
Partial Display Mode
this mode possible specify partial screen area display lines lines plus start block). This mode consumes little power compared with Full-Screen Display Mode thus suitable standby modes mobile phone. This mode valid when display partial display area, specify partial area start block (scanning start position) with block number every four lines shown below. partial area size selected either lines lines.
Partial start line
COM0 COM4 COM8 Display section lines (fixed) COM148 COM152 COM156
Block0 Block1 Block2
Block37 Block38 Block39
Non-display area
scanned (COM VLC1 VLC4)
Partial display section section that actually displayed
Switching from Normal Mode Partial Display Mode will occur start first frame after setting been completed.
Operation Partial Display Mode
Display duty cycle Display bias Contrast value Oscillation circuit output level output (partial display section) Common output (non-display area) 1/64 duty 1/32 duty Bias Contrast Automatic frequency switching Display data (VLC0, VLC2, VLC3, VLC5) Scanning (VLC0, VLC1, VLC4, VLC5) VLC1 VLC4 (inverted
2001-11-07
T6K53
Example
1/160 DutyCDR 0Mode Line)PDS
COM12 Display area COM75
1/160 DutyCDR 0Mode lines)PDS
COM127 Display area COM159
1/160 DutyCDR 0Mode lines)PDS
COM0 Display area COM31
COM127 Display area COM159
2001-11-07
T6K53
Area Scroll Function
possible scroll screen display partially specifying scroll area (start block, block number specific blocks). block consists lines. This mode valid after Display executed. Area scrolling supports four area modes.
Full-Screen
Upper-Screen Section
Lower-Screen Section
Middle-Screen Section
possible scroll screen display partially specifying scroll area (start block, block number specific blocks). size block must specified multiples lines. size display duty cycle block must also specified multiples lines.
Standby Mode
Standby Mode ON/OFF
Standby Mode
Standby command causes device enter Standby Mode. Standby Mode: outputs clock (FR, Stopped display power (VLC0 VLC5 fixed VSS) conversion operation display output output Standby Mode, possible access commands display data.
Exiting Standby Mode
When Standby Mode exited: outputs DOFF (VLC2 VLC3) outputs DOFF (VLC1 VLC4) (state before Standby Mode entered) (state before Standby Mode entered) (state before Standby Mode entered) states other than Display same before device entered Standby Mode. Therefore, after device exited Standby Mode, Display command must executed before data displayed on-screen.
2001-11-07
T6K53
Grayscale Control Circuit
grayscale
grayscale modes available selection T6K53. Fixed-Palette Mode predetermined grayscale levels) Palette Selection Mode (any grayscale levels selected from available levels.)
Fixed-Palette Mode
Fixed-Palette Mode selected. this mode, grayscale level output performed using predetermined 16-grayscale palette.
selection period (1CL period)
selection period GS10 GS11 GS12 GS13 GS14 GS15
2001-11-07
T6K53
Palette Selection Mode
Palette Selection Mode selected. this mode, selection period divided into parts enable selection grayscale levels from available levels (GL0 GL31) display grayscale output.
selection period GL10 GL11 GL12 GL13 GL14 GL15 GL16 GL17 GL18 GL19 GL20 GL21 GL22 GL23 GL24 GL25 GL26 GL27 GL28 GL29 GL30 GL31
2001-11-07
T6K53
Individual palettes selected separately. Three separate sets grayscale levels selected from grayscale levels shown above (for (GL0 GL31) GS15.
Gray Scale Level GL30 GL31 DB4/12 DB3/11 DB2/10 DB1/9 DB0/8
2001-11-07
T6K53
Normal/reverse display
this mode data output display reversed without alteration display image data. Turned data values i.e. VLC0 VLC5 selected output when data value Turned data values i.e. VLC0 VLC5 selected output when data value
Switching waveform output timing
Line Select Time GS10 GS11 GS12 GS13 GS14 GS15 Line Line Select Time Line
select waveform (SGM
waveform (SGM
2001-11-07
T6K53
Oscillation Circuit
oscillation circuit incorporates both capacitor resistor. When built-in oscillator used (EXT oscillation resistor incorporated oscillation circuit switched automatically device switched between Normal/Partial Display Mode Duty Cycle Setting Mode.
Oscillation frequencies when built-in oscillation circuit used
Display mode Duty cycle setting 1/160 duty Normal 1/144 duty 1/128 duty 1/64 duty Partial 1/32 duty 67.2 (divided give internal clock) Oscillation frequency (typical) 168.0 151.2 134.4 67.2
Frame period (typical) Calculation method: Fosc frame period (display line count) clock division number (15) partial display 1/32 Duty Mode, internal clock pulses generated frequency obtained dividing frequency partial display 1/64 Duty Mode
External Clock Mode selected external clock signal input pin. External Clock Mode, switching between Normal Partial Display Modes requires that clock frequency changed according display mode which selected.
2001-11-07
T6K53
Data Behavior When Data Accessed (example: i.e. device Mode)
Register
8-Bit Mode
/CS1
Command
16-Bit Mode
/CS1
Command
DB15
2001-11-07
T6K53
Command read (Status Read)
8-Bit Mode
/CS1
Status Read
16-Bit Mode
/CS1
Status Read
Hi-Z DB15
2001-11-07
T6K53
Command Data Write
8-Bit Mode
/CS1
low-order bits
high-order bits
DB15
16-Bit Mode
/CS1
DB15
DATA
2001-11-07
T6K53
Display Data Write
8-Bit Mode
/CS1
low-order bits
high-order bits
DB15
16-Bit Mode
/CS1
DB15
DATA
DATA
2001-11-07
T6K53
Display Data Read
8-Bit Mode
/CS1
low-order bits
high-order bits
DATA
Hi-Z DB15
16-Bit Mode
/CS1
DB15
DATA
DATA
DATA
2001-11-07
T6K53
Clock-Synchronous Serial Interface
Setting level enables data transferred clock-synchronous serial interface. When data transferred this way, synchronous clock input received pin, transfer data input output pin. Just with parallel interface, /CS1 pins used chip select signal. /CS1 used, example, data transfer begins when /CS1 changes from High ends when changes from High. fixed level. basic transfer data format uses bits total. first eight bits start byte other bits parameter data. start byte consists start bits (000110) followed bits.
Register Status Read
Function
Command Display Data Write Display Data Read
16-bit parameter data consists DB15 DB0. configuration same 16-bit parallel bus. During display data transfer, therefore, high-order bits (DB15 DB12) valid data. With Register Status Read, high-order bits valid data. This serial interface supports continuous transfer parallel data when display data read written. data format used continuous transfers made 8-bit start byte, first 16-bit parameter data item second 16-bit parameter data item, which transferred order. Within parameter data handled units bits. number consecutive parameter data items specified. data transfer ends when /CS1 goes High. first parameter data item bits) received during data read (Status Read Display Data Read) assumed dummy data. Normal data output begins with second parameter data item. transfer terminated middle start byte middle 16-bit parameter data items, previously transferred data nullified. this case, transfer should restarted.
When /CS1 Chip Select signal:
Transfer start /CS1
Transfer
Fixed High
Start (000110)
Start byte (start bits, R/W)
Parameter data (register number, command data display data)
Parameter data (Status Read Display Data Read/Write)
When Chip Select /CS1
Transfer start
Fixed Transfer
2001-11-07
T6K53
Register
/CS1 Start byte high-order bits (All "0") low-order bits (DB7 DB0)
Command Setting
/CS1 Start byte high-order bits (DB15 DB8) low-order bits (DB7 DB0)
Display Data Write
/CS1
Start byte high-order bits (DB15 DB8) low-order bits (DB7 DB0) high-order bits (DB15 DB8)
Display Data Read
/CS1 Start byte Dummy data Dummy data high-order bits (DB15 DB8) low-order bits (DB7 DB0)
Status Read
/CS1 Start byte high-order bits (All "0") low-order bits (DB7 DB0)
2001-11-07
T6K53
High-Speed Write function
T6K53 incorporates High-Speed Write function. This function enables T6K53 support applications, such animation software, which require high-speed rewriting display data.
Display Y-Adr 0000H 0001H 0002H 0003H 007CH 007DH 007EH 007FH
Reg.1
Reg.2
Reg.3
Reg.4
High-Speed Write selected writing display data (i.e. data received from stored Registers (each which consists word bits) then transferred display 4-word units. Thus, High-Speed Write Mode data access must performed 4-word units. Y-address area must 000H 0003H, 0004H 0007H, 0008H 000BH. 007CH 007FH. Y-address area cannot individual 4-address units (e.g. 003H 00FD). High-Speed Write Mode does support read functions. Example: Selecting rectangular display area SEG28 SEG99 COM40 COM119
Address area setting Y-adr: 1Ch, X-adr: 28h, 1C-1Fh
SEG28
SEG99
COM40
COM119
Y-Adr Count Mode
X-Adr Count Mode
When using High-Speed Write Mode, observe following precautions: Precautions: Conduct access count 4-word units. Otherwise, data transfer occur, resulting invalid data. Y-address area multiples address locations. X-Address Count Mode, count incremented every four accesses. After this mode been turned OFF, sure execute Y-Adr Area (31H) before beginning access display data. High-Speed Write Mode, Display Data Read cannot performed. perform read, first execute High-Speed Write Mode command (HRW then start access.
2001-11-07
T6K53
Command Setting
T6K53 both Register Status Read one-byte commands, while other instructions consist bytes. 16-Bit Mode both one-byte two-byte commands completed with single access. 8-Bit Mode, Register Status Read completed with single access. Other instructions with accesses first low-order bits accessed, then high-order bits. 8-Bit Mode, Register Status Read performed after first-byte access, access count will cleared that next access starts with first byte. Thus, when performing access 8-Bit Mode, perform Status Read regular intervals avoid crashes noise.
Instruction Name Register Status read Standby mode Display ON/OFF Function mode Function mode Contrast control Display mode N-line inversion Color palette (Red) Color palette (Green) Color palette (Blue) X-adr area Y-adr area Partial display mode Scroll mode area start Scroll area set. Scroll start block Display data write Display data read Toshiba test mode Reg. DB15 XAE7 DB14 BS22 XAE6 YAE6 DB13 DC21 BS21 XAE5 YAE5 PDS5 SAS5 SBN5 XAE4 YAE4 PDS4 SAS4 SBN4 DB12 DC20 BS20 DB11 DB10 BS12 DC11 BS11 DC10 BS10 REG7 NLI7 XAE0 YAE0 PDS0 SAS0 SBN0 XAS7 REG6 NLI6 XAS6 YAS6 REG5 NLI5 XAS5 YAS5 SAE5 SSB5 XAS4 YAS4 SAE4 SSB4 REG4 NLI4 REG3 NLI3 REG2 DCDC NLI2 REG1 DTY1 NLI1 REG0 DTY0 NLI0
GS1/GS3/GS5/GS7/GS9/ GS11/GS13/GS15 GS1/GS3/GS5/GS7/GS9/ GS11/GS13/GS15 GS1/GS3/GS5/GS7/GS9/ GS11/GS13/GS15 XAE3 YAE3 PDS3 SAS3 SBN3 DD11 DD11 XAE2 YAE2 PDS2 SAS2 SBN2 DD10 DD10 XAE1 YAE1 PDS1 SAS1 SBN1
GS0/GS2/GS4/GS6/GS8/ GS10/GS12/GS14 GS0/GS2/GS4/GS6/GS8/ GS10/GS12/GS14 GS0/GS2/GS4/GS6/GS8/ GS10/GS12/GS14 XAS3 YAS3 SAE3 SSB3 XAS2 YAS2 SAE2 SSB2 XAS1 YAS1 MODE SAE1 SSB1 XAS0 YAS0 SAE0 SSB0
2001-11-07
T6K53
Command Descriptions
Register set:
This command sets register address command which test commands Toshiba. Users should attempt access them.
Status read:
This command allows state each setting checked from low-order bits.
Function Standby Mode Standby Mode
Function Display Display
Function Read-Modify-Write Read-Modify-Write
Function Partial (Normal mode) Partial (Partial display mode)
Function Y-Adr Count Mode X-Adr Count Mode
Function Normal Mode OFF; ON.) Reverse Mode OFF.)
Standby Mode:
This command turns Standby Mode ON/OFF.
Function Standby Mode Standby Mode
2001-11-07
T6K53
Display ON/OFF:
This command turns display ON/OFF.
Function Display Display
Function mode (1):
This command sets operation each function.
OSC: Turns built-in oscillator ON/OFF.
Function Oscillator Oscillator
EXT: Selects either built-in oscillator external oscillator.
Function Built-in Oscillator Mode External Oscillator Mode
DCDC: Turns DC-DC conversion circuit ON/OFF.
DCDC Function DCDC DCDC
AMP: Turns operational amplifier ON/OFF.
Function
DC1x: Specifies number DC-DC conversion steps Normal Mode.
DC11 DC10 Function booster booster booster Cannot
DC2x: Specifies number DC-DC conversion steps Partial Display Mode.
DC21 DC20 Function booster booster booster booster
2001-11-07
T6K53
Function Mode (2):
This command sets display operation mode.
SDR: Specifies direction segment output.
Function Y-Adr SEG0 Y-Adr SEG127
CDR: Specifies direction output.
Function COM0 COM159 COM159 COM0
SWP: Changes assignments
Function
SGM: Specifies switching waveform output timing.
Function
REV: Specifies whether display output data will reversed.
Function Normal Mode ("0": OFF, Reverse Mode ("0": "1": "1": OFF)
Switches grayscale palette mode.
Function Fixed-Palette Mode Palette Selection Mode
X/Y: Selects address count mode.
Function Y-Adr Count Mode X-Adr Count Mode
2001-11-07
T6K53
RMW: Read-Modify-Write Mode ON/OFF
Function Read-Modify-Write Read-Modify-Write
Read-Modify-Write Mode function When Display Data Read executed, address count executed. address count executed only when display data written. Hence, example, after read data been changed, data written previous address without need specify address.
HRW: Turns High-Speed Write Mode ON/OFF.
Function High-Speed Write Mode High-Speed Write Mode
2001-11-07
T6K53
Contrast Control:
Normal Mode Contrast
VLCD0 voltage (typical) each Contrast setting
CONT (dec) CONT (Hex) VLC0 10.00 10.08 10.16 10.24 10.31 10.39 10.47 10.55 10.63 10.71 10.79 10.87 10.94 11.02 11.10 11.18 11.26 11.34 11.42 11.50 11.57 11.65 11.73 11.81 11.89 11.97 12.05 12.13 12.20 12.28 12.36 12.44 CONT (dec) CONT (Hex) VLC0 12.52 12.60 12.68 12.76 12.83 12.91 12.99 13.07 13.15 13.23 13.31 13.39 13.46 13.54 13.62 13.70 13.78 13.86 13.94 14.02 14.09 14.17 14.25 14.33 14.41 14.49 14.57 14.65 14.72 14.80 14.88 14.96 CONT (dec) CONT (Hex) VLC0 15.04 15.12 15.20 15.28 15.35 15.43 15.51 15.59 15.67 15.75 15.83 15.91 15.98 16.06 16.14 16.22 16.30 16.38 16.46 16.54 16.61 16.69 16.77 16.85 16.93 17.01 17.09 17.17 17.24 17.32 17.40 17.48 CONT (dec) CONT (Hex) VLC0 17.56 17.64 17.72 17.80 17.87 17.95 18.03 18.11 18.19 18.27 18.35 18.43 18.50 18.58 18.66 18.74 18.82 18.90 18.98 19.06 19.13 19.21 19.29 19.37 19.45 19.53 19.61 19.69 19.76 19.84 19.92 20.00
2001-11-07
T6K53
Partial Display Mode Contrast
VLC0 voltage (typical) each Contrast setting
CONT (dec) CONT (Hex) VLC0 5.00 5.08 5.16 5.24 5.31 5.39 5.47 5.55 5.63 5.71 5.79 5.87 5.94 6.02 6.10 6.18 6.26 6.34 6.42 6.50 6.57 6.65 6.73 6.81 6.89 6.97 7.05 7.13 7.20 7.28 7.36 7.44 CONT (dec) CONT (Hex) VLC0 7.52 7.60 7.68 7.76 7.83 7.91 7.99 8.07 8.15 8.23 8.31 8.39 8.46 8.54 8.62 8.70 8.78 8.86 8.94 9.02 9.09 9.17 9.25 9.33 9.41 9.49 9.57 9.65 9.72 9.80 9.88 9.96 CONT (dec) CONT (Hex) VLC0 10.04 10.12 10.20 10.28 10.35 10.43 10.51 10.59 10.67 10.75 10.83 10.91 10.98 11.06 11.14 11.22 11.30 11.38 11.46 11.54 11.61 11.69 11.77 11.85 11.93 12.01 12.09 12.17 12.24 12.32 12.40 12.48 CONT (dec) CONT (Hex) VLC0 12.56 12.64 12.72 12.80 12.87 12.95 13.03 13.11 13.19 13.27 13.35 13.43 13.50 13.58 13.66 13.74 13.82 13.90 13.98 14.06 14.13 14.21 14.29 14.37 14.45 14.53 14.61 14.69 14.76 14.84 14.92 15.00
2001-11-07
T6K53
Display Mode set:
Duty
This function sets display duty cycle Normal Mode.
DTY1
DTY0
Function 1/160 Duty.COM0 COM159 1/144 Duty.COM8 COM151 1/128 Duty.COM16 COM143 Cannot set.
Bias
This function specifies display bias ratio Normal Display Mode Partial Display Mode. display mode switched using Partial Display command, display bias ratio setting made using Bias will selected automatically. Normal Mode
BS12 BS11 BS10 Function 1/11 Bias 1/12 Bias 1/13 Bias 1/14 Bias 1/15 Bias
Partail Mode
BS22 BS21 BS20 Function Bias Bias Bias Bias 1/10 Bias
N-line Inversion:
Sets inversion period alternating signal (FR) arbitrary number display lines.
NLI7 NLI6 NLI5 NLI4 NLI3 NLI2 NLI1 NLI0
00H: Frame inverted 01H: Inverted every line 02H: Inverted every lines
9EH: Inverted every lines 9FH: Inverted every lines
2001-11-07
T6K53
Color Palette (Red/Green/Blue):
These registers which used setting grayscale levels Palette Selection Mode. Separate palettes selected individually grayscale levels selected from levels available (GL0 GL31) specified individually 5-bit values GS15. reset, GS15 values become 00H. When using this mode, sure these registers before executing Display
Color
DB15 DB14 DB13 DB12 DB11 DB10 GS11 GS13 GS15 GS11 GS13 GS15 GS11 GS13 GS15
GS10 GS12 GS14 GS10 GS12 GS14 GS10 GS12 GS14
Green
Blue
2001-11-07
T6K53
X-adr Area Set:
XASx: Sets start address display X-adr area.
XAS7 XAS6 XAS5 XAS4 XAS3 XAS2 XAS1 XAS0
specify address higher than 9FH.
XAEx: Sets address display X-adr area.
XAE7 XAE6 XAE5 XAE4 XAE3 XAE2 XAE1 XAE0
specify address higher than 9FH.
Y-adr Area Set:
YASx: Sets start address display Y-adr area.
YAS6 YAS5 YAS4 YAS3 YAS2 YAS1 YAS0
YAEx: Sets address display Y-adr area.
YAE6 YAE5 YAE4 YAE3 YAE2 YAE1 YAE0
Partial Display Mode:
This command turns Partial Display Mode ON/OFF sets display duty cycle Partial Display Mode.
Turns Partial Mode ON/OFF.
Function Partial (Normal mode) Partial (Partial display mode)
Mode: Selects display duty cycle Partial Display Mode.
Mode Function 1/32 Duty 1/64 Duty
PDSx: Specifies start block Partial Display Mode.
PDS5 PDS4 PDS3 PDS2 PDS1 PDS0
2001-11-07
T6K53
Scroll Mode Area Start:
Sets Area Scroll Mode.
Function Full-screen scroll Upper screen section scroll Lower screen section scroll Middle screen section scroll
SASx: Specifies start block number scroll area. 4-line block specified.
SAS5 SAS4 SAS3 SAS2 SAS1 SAS0
Scroll Area:
SAEx: Specifies block number scroll area. 4-line block specified. Setting total number blocks number lower fixed blocks
SAE5 SAE4 SAE3 SAE2 SAE1 SAE0
SBNx: Specifies number specific blocks. 4-line display duty blocks specified. Setting number display duty blocks number lower fixed blocks
SBN5 SBN4 SBN3 SBN2 SBN1 SBN0
block
Block start line Block Block start line Block Block start line Block
2001-11-07
T6K53
Scroll Start Block:
This command specifies scroll start block parameter. Executing this command causes specified scroll start block displayed first data item scroll display area. 4-line block specified.
SSB5 SSB4 SSB3 SSB2 SSB1 SSB0
Setting example
displays scrolled lines Middle Screen Section Mode when duty cycle 1/144 lines fixed: Mode Middle Screen Section Mode Scroll area start block Scroll area block Scroll start block
Display duty block Line Line Line Line Block Block Block Upper fixed area Xadr Xadr Xadr Xadr
Block Block Block Block Upper fixed area Line Line Line Line Display image Block Block Block
Number specific blocks
Scroll screen
Scroll area Line Line Line Line Line Block Block Block Block Xadr Lower fixed Xadr area Line Line Line Line Line Block Block Block Block
Block Block Background area
Xadr Xadr Xadr Xadr
Block Block Block
Block
Display Data:
DDxx: Accesses display RAM.
DD11 DD10
0000h 0FFFh
16-Bit Mode
DB11 DD11
8-Bit Mode
First access (DB7 DB0) DD11 Second access (DB3 DB0)
Toshiba Test Mode: (80h FFh)
user cannot access commands this area during normal use.
2001-11-07
T6K53
Post-Reset (Post-Initialization) States
Instruction Name Register Reg. DB15 DB14 DB13 DB12 DB11 DB10
REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0
Status read
Standby mode
Display ON/OFF
Function mode
DC21
DC20
DC11
DC10 BS10
DCDC
DTY1
DTY0 NLI0
Function mode
BS11
Contrast control
BS21
BS20
BS12
Display mode
BS22
N-line inversion
NLI7
NLI6
NLI5
NLI4
NLI3
NLI2
NLI1
Color palette (Red)
GS1/GS3/GS5/GS7/GS9/ GS11/GS13/GS15
GS0/GS2/GS4/GS6/GS8/ GS10/GS12/GS14
Color palette (Green)
GS1/GS3/GS5/GS7/GS9/ GS11/GS13/GS15
GS0/GS2/GS4/GS6/GS8/ GS10/GS12/GS14
Color palette (Blue)
GS1/GS3/GS5/GS7/GS9/ GS11/GS13/GS15
GS0/GS2/GS4/GS6/GS8/ GS10/GS12/GS14
XAE7 X-adr area Y-adr area
XAE6 YAE6
XAE5 YAE5 PDS5
XAE4 YAE4 PDS4 SAS4 SBN4
XAE3 YAE3 PDS3 SAS3 SBN3
XAE2 YAE2 PDS2 SAS2 SBN2
XAE1 YAE1 PDS1 SAS1 SBN1
XAE0 YAE0 PDS0 SAS0 SBN0
XAS7
XAS6 YAS6
XAS5 YAS5
XAS4 YAS4
XAS3 YAS3
XAS2 YAS2
XAS1 YAS1 MODE
XAS0 YAS0 SAE0 SSB0
Partial display mode
Scroll mode area start
SAS5
Scroll area
SBN5
SAE5
SAE4 SSB4
SAE3 SSB3
SAE2 SSB2
SAE1 SSB1
Scroll start block
SSB5
2001-11-07
T6K53
Summary Display Outputs Display Power Supply States Individual Operation Modes
After reset
(Standby Mode after DC-DC conversion: reset.) output output VLC0 VLC5 Standby Mode (Normally display OFF.) command required after initialization.)
DC-DC conversion: command required after initialization.) output output command required after initialization.) VLC2 VLC3 (Display OFF) VLC1 VLC4 (Display OFF) Display data output. Scanning performed. VLC2 VLC3 (Display OFF) VLC1 VLC4 (Display OFF)
Display (display output) Display (Display output stopped.) Standby Mode (Sleep state)
output output output output output output VLC0 VLC5
DC-DC conversion:
2001-11-07
T6K53
Command Execution State Transition
Reset (Initialize) Standby Mode Display
Power /RST input Power supply turn-on period: Period during which /RST Low: /RST input
Initialization been completed. Clear internal registers.
Execute Standby Mode command.
Execute Execute DC-DC conversion Execute Wait: Execute Display
Return from Standby Mode display mode
Execute Standby Mode command. Display Start DC-DC conversion Start Start
Wait: Execute Display
Display progress Display
Execute Display OFF.
Display OFF. output: VLC2 VLC3 output: VLC1 VLC4
Display Display
Execute Display
Display
2001-11-07
T6K53
Drive Waveform (Normal Display Mode)
COM0 COM1 COM160
drive timing chart (1/160 duty)
Maximum Ratings
Characteristics Supply voltage Supply Voltage Symbol VDD, (Note Rating -0.3 22.0 -0.3 Unit
VLC0, VLC1, VLC2, VLC3, VLC4, VLC5, VCC1, VCC2 Vinp (Note (Note
Input Voltage Operating Temperature Storage Temperature
Topr Tstg
Note Value with reference Note Does include VCC1, VCC2, VLC0, VLC1, VLC2, VLC3, VLC4 VLC5. This setting suitable inputs data bus.
2001-11-07
T6K53
(Conditions: Unless otherwise specified, 20.0 25°C)
Characteristics Operating voltage Operating voltage Normal display Operating voltage Partial display High level Input voltage level High level Output voltage level Segment driver on-resistance Common driver ON-resistance Normal display mode Normal display mode Rcol Rrow Symbol -400 Test Circuit Test Conditions Typ. 20.0 20.0 Unit DB15, DB15,D/I, /WR, /RD, /CS1, CS2, RSI, P/S, WLS, SCK, /RST, /STB DB15, D/I, /WR, /RD, /CS1, CS2, D/I, P/S, 68/80, SCK, /RST, /STB Applicable
Electrical Characteristics
(Note (Note
Input leakage current
Vinp
Operating frequency External clock input frequency External clock duty External clock rise/fall time Current consumption Current consumption Current consumption
fosc fduty tr/tf ISS1 ISS2 ISSSTB
(Note (Note
(Note (Note (Note
Note 10.0 Load current 1/11 bias Note 18.0 booster), data access, internal clock (OSC kHz), load, 1/14 bias, 1/160 duty, op-amp regulator Normal Display Mode, display pattern: all-white Note booster), data access, internal clock (OSC 67.2 kHz), load, bias, 1/64 duty, op-amp regulator Partial Display Mode, display pattern: all-white Note 22.0 /STB Note 1/160 duty,
2001-11-07
T6K53
Electrical Characteristics
(Conditions: Unless otherwise specified, 15.5 25°C)
Characteristics Output voltage booster) Output voltage booster) Output voltage booster) Output voltage booster) Output voltage booster) Output voltage booster) Symbol Test Circuit Test Conditions (Note (Note (Note (Note (Note (Note 11.6 14.5 17.4 18.3 20.0 Unit Applicable VOUT VOUT VOUT VOUT VOUT VOUT
Note (external power supply input), Cn+/Cn- VOUT 67.2 kHz, contrast max, 25°C, Iload Note 11.6 (external power supply input), Cn+/Cn- VOUT 67.2 kHz, contrast max, 25°C, Iload Note 14.5 (external power supply input), Cn+/Cn- VOUT 67.2 kHz, contrast max, 25°C, Iload Note 17.4 (external power supply input), Cn+/Cn- VOUT kHz, contrast max, 25°C, Iload Note 18.3 (external power supply input), Cn+/Cn- VOUT kHz, contrast max, 25°C, Iload Note 20.0 (external power supply input), Cn+/Cn- VOUT kHz, contrast max, 25°C, Iload
Electrical Characteristics
(Conditions: Unless otherwise specified, 15.5 25°C)
Characteristics Regulator reference high voltage Regulator reference high voltage Regulator reference high voltage Temperature gradient Regulator reference high voltage Temperature gradient variation Symbol VHR1 VHR2 VHRINC DVHRINC Test Circuit Test Conditions (Note14) (Note (Note 60°C (Note 60°C 19.95 14.95 -0.02 20.00 15.00 -0.00 20.05 15.05 0.02 Unit %/°C %/°C Applicable
Note (external supply), contrast max, display load, Normal Display Mode Note (external supply), contrast max, display load, Normal Display Mode
2001-11-07
T6K53
Electrical Characteristics
Characteristics Op-amp output voltage offset Op-amp output voltage offset Op-amp output voltage offset
(Conditions: Unless otherwise specified, 25°C)
Symbol Vopoff Vopoffs1 Vopoffs2 Test Circuit Test Conditions (Note (Note IIoad (Note Unit Applicable VLC0, VLC1, VLC2, VLC3, VLC4 VLC0, VLC1, VLC2, VLC3, VLC4 VLC0, VLC1, VLC2, VLC3, VLC4
Note 1/15 bias, 1/160 duty, 20.0 op-amp load VLC0: VLC0 Vopoff VLC1: (VLC0 14/15) VLC1 Vopoff VLC2: (VLC0 13/15) VLC2 Vopoff VLC3: (VLC0 2/15) VLC3 Vopoff VLC4: (VLC0 1/15) VLC4 Vopoff Note 1/15 bias, 1/160 duty, 20.0 op-amp load Vopoff1 (VLC1 VLC2) (VLC0 VLC1) (VLC3 VLC4) (VLC4 VLC5) Vopoff2 (VLC1 VLC2) (VLC0 VLC1) (VLC3 VLC4) (VLC4 VLC5)
2001-11-07
T6K53
Test Circuit
With booster
External input
67.2 Iload other pins left open
VOUT
Iload
External power supply
With booster
External input
67.2 Iload other pins left open
VOUT
Iload
External power supply
2001-11-07
T6K53
With booster
External input
VOUT
67.2 Iload other pins left open
Iload
External power supply
With booster
External input
VOUT
Iload other pins left open
Iload
External power supply
2001-11-07
T6K53
With booster
External input
VOUT
Iload other pins left open
Iload
External power supply
With booster
External input
VOUT
Iload other pins left open
Iload
External power supply
2001-11-07
T6K53
Switching Characteristics Series Parallel Interface)
/CS1 (CS2 Data Write Data Read Valid data tcycE Valid data PWEL
tDHW
tDHR
(Conditions: Unless Otherwise Specified, 25°C)
Characteristics Enable cycle time Enable pulse width Enable rise/fall time Address set-up time Address hold time Data set-up time Write data hold time Data delay time Read data hold time Symbol tcycE PWEL tEr, tDHW (Note tDHR (Note Unit Load Circuit
(including tool probe capacitances)
Note When load circuit shown figure connected
2001-11-07
T6K53
Switching Characteristics Series Parallel Interface)
(/WR) (/RD) PWEH tDHW Valid data tDHR Valid data tcycE
Data Write Data Read
(Conditions: Unless Otherwise Specified, 15.5 25°C)
Load circuit Characteristics Enable cycle time Enable pulse width Enable rise/fall time Address set-up time Address hold time Data set-up time Write data hold time Data delay time Read data hold time Symbol tcycE PWEH tEr, tDHW (Note tDHR (Note Unit (including tool probe capacitances)
Note When load circuit shown figure connected
2001-11-07
T6K53
Switching Characteristics (Serial Interface)
/CS1
tCSU tcycC tCSH
(Conditions: Unless Otherwise Specified, 25°C)
Characteristics Clock cycle time Clock pulse width Clock rise/fall time Chip select set-up time Chip select hold time Data set-up time Write data hold time Data output delay time Data output hold time Symbol tcycC PWCL, PWCH tCr, tSCU tCSH Unit
2001-11-07
T6K53
Switching Characteristics
VDST VRST RSTW /RST
(Conditions: Unless Otherwise Specified, 15.5 25°C)
Characteristics rise time Reset hold time Reset pulse width Symbol VDST VRST RSTW Unit
2001-11-07
T6K53
RESTRICTIONS PRODUCT
000707EBE
TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, comply with standards safety making safe design entire system, avoid situations which malfunction failure such TOSHIBA products could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent TOSHIBA products specifications. Also, please keep mind precautions conditions forth "Handling Guide Semiconductor Devices," "TOSHIBA Semiconductor Reliability Handbook" etc. TOSHIBA products listed this document intended usage general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products neither intended warranted usage equipment that requires extraordinarily high quality and/or reliability malfunction failure which cause loss human life bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, types safety devices, etc. Unintended Usage TOSHIBA products listed this document shall made customer's risk. Polyimide base film hard thin. careful injure yourself film scratch other parts with film. design manufacture products that there chance users touching film after assembly, they that there chance them injuring themselves. When cutting film, ensure that film shavings cause accidents. After use, treat leftover film reel spacers industrial waste. Light striking semiconductor device generates electromotive force photoelectric effects. some cases this cause device malfunction. This especially true devices which surface (back), side chip exposed. When designing circuits, make sure that devices protected against incident light from external sources. Exposure light both during regular operation during inspection must taken into account. products described this document subject foreign exchange foreign trade laws. information contained herein presented only guide applications products. responsibility assumed TOSHIBA CORPORATION infringements intellectual property other rights third parties which result from use. license granted implication otherwise under intellectual property other rights TOSHIBA CORPORATION others. information contained herein subject change without notice.
2001-11-07

Other recent searches


XZMDKVG45W - XZMDKVG45W   XZMDKVG45W Datasheet
UMZ8 - UMZ8   UMZ8 Datasheet
UGN5275K - UGN5275K   UGN5275K Datasheet
SK8509 - SK8509   SK8509 Datasheet
LT3479 - LT3479   LT3479 Datasheet
IXA17IF1200HJ - IXA17IF1200HJ   IXA17IF1200HJ Datasheet
GA3205 - GA3205   GA3205 Datasheet
CY7C265 - CY7C265   CY7C265 Datasheet
CY7C265W - CY7C265W   CY7C265W Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive