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TMS320VC5501/5502 Direct Memory Access (DMA) Controller Reference Guide
Literature Number: SPRU613E August 2004
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Preface
Read This First
About This Manual
This manual describes features operation direct memory access (DMA) controller that available TMS320VC5501 TMS320VC5502 digital signal processors (DSPs) TMS320C55x (C55x) generation. This controller allows movement data among internal memory, external memory, peripherals occur without intervention from background operation.
Notational Conventions
This document uses following conventions:
most cases, hexadecimal numbers shown with suffix
example, following number hexadecimal (decimal 64):
Similarly, binary numbers often shown with suffix example,
following number decimal number shown binary form: 0100b
Related Documentation From Texas Instruments
following documents describe C55x devices related support tools. Copies these documents available Internet www.ti.com. Tip: Enter literature number search provided www.ti.com. TMS320C55x Technical Overview (literature number SPRU393). This overview introduction TMS320C55x DSPs, latest generation fixed-point DSPs TMS320C5000 platform. Like previous generations, this processor optimized high performance low-power operation. This book describes architecture, low-power enhancements, embedded emulation features.
Related Documentation From Texas Instruments Trademarks Related Documentation From Texas Instruments
TMS320C55x Reference Guide (literature number SPRU371) describes architecture, registers, operation TMS320C55x DSPs. TMS320C55x Peripherals Reference Guide (literature number SPRU317) describes peripherals, interfaces, related hardware that available TMS320C55x DSPs. TMS320C55x Algebraic Instruction Reference Guide (literature number SPRU375) describes TMS320C55x algebraic instructions individually. Also includes summary instruction set, list instruction opcodes, cross-reference mnemonic instruction set. TMS320C55x Mnemonic Instruction Reference Guide (literature number SPRU374) describes TMS320C55x mnemonic instructions individually. Also includes summary instruction set, list instruction opcodes, cross-reference algebraic instruction set. TMS320C55x Optimizing C/C++ Compiler User's Guide (literature number SPRU281) describes TMS320C55x C/C++ Compiler. This C/C++ compiler accepts standard source code produces assembly language source code TMS320C55x devices. TMS320C55x Assembly Language Tools User's Guide (literature number SPRU280) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives TMS320C55x devices. TMS320C55x Programmer's Guide (literature number SPRU376) describes ways optimize assembly code TMS320C55x DSPs explains write code that uses special features instructions DSPs.
Trademarks
TMS320, TMS320C5000, TMS320C55x, C55x trademarks Texas Instruments. Trademarks property their respective owners.
Contents
Contents
Introduction Controller Features Controller Block Diagram Controller Requests Versus Requests Internal Memory
Channels Port Accesses Service Chain Service Chain Example Units Data: Byte, Element, Frame, Block 5Start Addresses Channel Start Address Memory Start Address Space Updating Addresses Channel Data Burst Capability Data Packing Write Posting: Buffering Writes Internal Memory
Synchronizing Channel Activity Event 10.1 Checking Synchronization Status 10.2 Dropped Synchronization Event Monitoring Channel Activity 11.1 Channel Interrupt 11.2 Time-Out Error Condition 11.3 Address Error Condition 11.4 Error Interrupt
Latency Transfers Power, Emulation, Reset Considerations 13.1 Reducing Power Consumed Controller (Idle Configurations) 13.2 Emulation Modes Controller
Contents
13.3
Controller after Reset
Controller Registers 14.1 Global Control Register (DMAGCR) 14.2 Global Time-Out Control Register (DMAGTCR) 14.3 Channel Control Register (DMACCR) 14.4 Interrupt Control Register (DMACICR) Status Register (DMACSR) 14.5 Source Destination Parameters Register (DMACSDP) 14.6 Source Start Address Registers (DMACSSAL DMACSSAU) 14.7 Destination Start Address Registers (DMACDSAL DMACDSAU) 14.8 Element Number Register (DMACEN) Frame Number Register (DMACFN) 14.9 Element Index Registers (DMACSEI, DMACDEI) Frame Index Registers (DMACSFI, DMACDFI) 14.10 Source Address Counter (DMACSAC) Destination Address Counter (DMACDAC) Revision History
Figures
Figures
Conceptual Block Diagram Controller Connections Parts Transfer Registers Controlling Channel's Context Possible Configuration Service Chains Service Chain Applied Three Ports High-Level Memory TMS320C55x DSPs High-Level TMS320C55x DSPs Triggering Channel Interrupt Request Global Control Register (DMAGCR) Global Time-Out Control Register (DMAGTCR) Channel Control Register (DMACCR) Interrupt Control Register (DMACICR) Status Register (DMACSR) Source Destination Parameters Register (DMACSDP) Source Start Address Registers (DMACSSAL DMACSSAU) Destination Start Address Registers (DMACDSAL DMACDSAU) Element Number Register (DMACEN) Frame Number Register (DMACFN) Element Index Registers (DMACSEI, DMACDEI) Frame Index Registers (DMACSFI, DMACDFI) Channel Source Address Counter (DMACSAC) Channel Destination Address Counter (DMACDAC)
Contents
Tables
Tables
Event Non-Event Driven Ports Activity Shown Figure Registers Used Define Start Addresses Transfer Data Packing Performed Controller 32-bit Data Packing Conditions 16-bit Data Packing Conditions Event Non-Event Driven Ports Controller Operational Events Their Associated Bits Interrupts Registers Controller DMAGCR FIeld Descriptions DMAGTCR Field Descriptions DMACCR Field Descriptions Synchronization Event Mapping TMS320VC5501/5502 DSPs DMACICR Field Descriptions DMACSR Field Descriptions DMACSDP Field Descriptions DMACSSAL Field Description DMACSSAU Field Description DMACDSAL Field Description DMACDSAU Field Description DMACEN Field Description DMACFN Field Description DMACSEI Field Description DMACSFI Field Description DMACDEI Field Description DMACDFI Field Description DMACSAC Field Description DMACDAC Field Description Document Revision History
Controller
This document describes direct memory access (DMA) controller TMS320VC5501/TMS320VC5502 digital signal processors (DSPs). This controller allows movement data among internal memory, external memory, peripherals without intervention from background operation.
Introduction Controller
Introduction Controller
Acting background operation, controller transfer data among internal memory, external memory, on-chip peripherals.
Features Controller
controller following important features:
Operation that independent CPU. Four standard ports: internal dual-access (DARAM),
external memory, peripherals.
channels, which allow controller keep track context
independent block transfers among standard ports.
Bits assigning each channel priority high priority. details,
Service Chain page
Event synchronization. transfers each channel made
dependent occurrence selected events. details, Synchronizing Channel Activity page
interrupt each channel. Each channel send interrupt
completion certain operational events. Monitoring Channel Activity page
Software-selectable options updating addresses sources
destinations data transfers.
dedicated idle domain. controller into low-power
state turning this domain. Each multichannel buffered serial port (McBSP) C55x ability temporarily take domain this idle state when McBSP needs controller. read about registers used program controller, section page
Block Diagram Controller
Figure conceptual diagram connections between controller other parts DSP. controller four ports:
ports internal dual-access (DARAM). ease reference,
these ports called internal memory port internal memory port throughout this document.
port external memory. external memory interface (EMIF)
connects port external memory.
port peripherals. peripheral controller connects port
peripherals.
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Introduction Controller
Data transfers among ports occur channels. (The channels described page 12.) possible multiple channels request access same port same time. arbitrate simultaneous requests, controller programmable service chain that used each ports. details service chain, page
Figure
Conceptual Block Diagram Controller Connections
TMS320VC5501/5502
Port DARAM Port controller Peripheral controller
Port Channels Port
Peripherals
EMIF
External memory
Requests Versus Requests Internal Memory
controller simultaneously request access same DARAM block internal memory, requests always have priority over requests. requests DARAM block will serviced when there more requests. Refer device-specific data manual specific information start addresses each DARAM block.
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Controller
Channels Port Accesses
Channels Port Accesses
controller paths, called channels, transfer data among four ports (two DARAM, external memory, peripherals). Each channel reads data from port (from source) writes data that same port another port destination). Each channel first first (FIFO) buffer that allows data transfer occur stages (see Figure Port read access Port write access Transfer data from source port channel FIFO buffer. Transfer data from channel FIFO buffer destination port.
FIFO buffer each channel eight 32-bit words deep.
Figure
Parts Transfer
Read access Source port Channel FIFO buffer Write access Destination port
different ports categorized event driven non-event driven (see Table This difference between ports significant when synchronization used transfer data, described section page
Table
Event Non-Event Driven Ports
Port DARAM External memory Peripheral Category Non-event driven Non-event driven Event driven
Controller
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Channels Port Accesses
conditions under which transfers occur channel called channel context. Each channels contains register structure programming updating channel context (see Figure Your code modifies configuration registers. When time data transferring, contents configuration registers copied working registers, controller uses working register values control channel activity. copy from configuration registers working registers occurs whenever your code enables channel DMACCR). addition, auto-initialization mode (AUTOINIT DMACCR), copy occurs between block transfers. more information about controller registers, page Some configuration registers programmed next block transfer while still running current context from working registers. next transfer will configuration without stopping DMA. configuration registers that should configured this manner DMAGCR, DMAGTCR, DMACSDP, DMACCR, DMACICR DMACSR. Modification these registers while channel running cause unpredictable operation channel.
Figure
Registers Controlling Channel's Context
Configuration registers (programmed code) DMACSDP DMACCR DMACICR DMACSR DMACSSAL DMACSSAU DMACDSAL DMACDSAU DMACEN DMACFN DMACSFI DMACSEI DMACSAC DMACDAC DMACDEI DMACDFI Automatically copied when channel enabled, between block transfers auto-initialization mode Working registers (used controller) DMACSDP copy DMACCR copy DMACICR copy DMACSR copy DMACSSAL copy DMACSSAU copy DMACDSAL copy DMACDSAU copy DMACEN copy DMACFN copy DMACSFI copy DMACSEI copy DMACSAC copy DMACDAC copy DMACDEI copy DMACDFI copy
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Controller
Service Chain
Service Chain
Each ports controller arbitrate simultaneous access requests sent channels. Each ports independently functioning service chain-a softwareand hardware-controlled scheme servicing access requests. Although four service chains function independently, they share common configuration. example, disable channel disabled four ports, make channel high-priority, high-priority four ports. possible configuration service chains shown Figure Important characteristics service chain listed after figure. Section contains example that shows service chain configuration applied three ports.
Figure
High Priority Channel
Possible Configuration Service Chains
High Priority Channel High Priority Channel
Channel Priority
Channel Priority
Channel Priority
channels have programmable priority level. Each channel
PRIO DMACCR selecting high priority priority. controller only services low-priority items when high-priority items done stalled. After reset, channels priority. figure, channels high-priority each these channels, PRIO channels priority each these channels, PRIO
channels have fixed positions service chain. Regardless
programmed priorities, port checks channels repeating circular sequence: each position service chain, port checks whether channel ready able serviced. serviced; otherwise, port skips next position. After reset, port restarts circular sequence, beginning with channel
Controller SPRU613E
Service Chain
channels individually connected disconnected from
service chain through software. channel enabled DMACCR), connected service chain; disabled disconnected. After reset, channels disconnected. figure, only channel disconnected. port checks channels repeating circular sequence, will keep skipping channel until channel reconnected.
channel tied synchronization event, channel does
generate request (and, therefore, cannot serviced) until synchronization event occurs.
Service Chain Example
Figure shows service chain applied DARAM port, external memory port, peripheral port. service chain following programmed characteristics.
Channels high-priority (PRIO DMACCR). Channels
low-priority (PRIO
Channels enabled DMACCR). Channels
disabled Table summarizes activity ports figure.
Table
Activity Shown Figure
Port DARAM External memory Peripheral This Port Arbitrates Write access requests from channel Read access requests from channel Write access requests from channel Write access requests from channel Read access requests from channel Read access requests from channel
Finally, notice that each port figure, there channel that connected service chain does port. example, peripheral port used channel channel were redefined include peripheral port source destination, port would handle channel according position priority service chain.
SPRU613E Controller
Service Chain
Figure
Service Chain Applied Three Ports
High-priority: Low-priority: Disabled: Enabled:
Configuration service chains
DARAM port: Only used channel channel
Write access Read access
Channel FIFO buffer External memory port: Only used channel channel Write access Channel FIFO buffer Write access
Channel FIFO buffer Peripheral port: Only used channel channel Read access
Read access
Controller
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Units Data: Byte, Element, Frame, Block
Units Data: Byte, Element, Frame, Block
This documentation controller refers data four levels granularity: Byte Element 8-bit value. byte smallest unit data transferred channel. more bytes transferred unit. Depending programmed data type, element 8-bit, 16-bit, 32-bit value. element transfer cannot interrupted; bytes transferred port before another channel take control port. more elements transferred unit. frame transfer interrupted between element transfers. more frames transferred unit. Each channel transfer block data (once multiple times). block transfer interrupted between frame transfers element transfers.
Frame Block
each channels, define number frames block (with DMACFN), number elements frame (with DMACEN), number bytes element (with DATATYPE bits DMACSDP). descriptions DMACFN, DMACEN, DMACSDP, other registers controller, section page
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Controller
Start Addresses Channel
Start Addresses Channel
During data transfer channel, first address which data read called source start address. first address which data written called destination start address. These byte addresses. From standpoint controller, every bits memory space address. Each channel contains following registers specifying start addresses:
Table
Registers Used Define Start Addresses Transfer
Register DMACSSAL DMACSSAU DMACDSAL DMACDSAU Load With Source start address (lower part) Source start address (upper part) Destination start address (lower part) Destination start address (upper part)
following sections explain load start address registers memory accesses accesses. controller access internal external memory space (which contains registers peripherals).
Start Address Memory
Figure high-level memory TMS320C55x DSPs. diagram shows both word addresses (23-bit addresses) used byte addresses (24-bit addresses) used controller. load source/destination start address registers: Identify correct start address. Check alignment constraint data type; description DATATYPE bits section 14.5 (page 50). have word address, shift left form byte address with bits. example, word address 4000h should converted byte address 8000h. Load least significant bits (LSBs) byte address into DMACSSAL (for source) DMACDSAL (for destination). Load most significant bits (MSBs) byte address into LSBs DMACSSAU (for source) DMACDSAU (for destination). Note: Word addresses 0000h-00 005Fh (which correspond byte addresses 0000h-00 00BFh) reserved memory-mapped registers (MMRs) CPU.
Controller
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Start Addresses Channel
Figure
High-Level Memory TMS320C55x DSPs
Word Addresses (Hexadecimal Ranges) MMRs 0000-00 005F Byte Addresses (Hexadecimal Ranges) 0000-00 00BF 00C0-01 FFFF 0000-03 FFFF
Memory
Main data page
0060-00 FFFF 0000-01 FFFF
Main data page
Main data page
0000-02 FFFF
0000-05 FFFF
Main data page
0000-7F FFFF
0000-FF FFFF
Start Address Space
Figure space TMS320C55x DSPs. diagram shows both word addresses (16-bit addresses) used byte addresses (17-bit addresses) used controller. load source/destination start address registers: Identify correct start address. Check alignment constraint data type; description DATATYPE bits section 14.5 (page 50). have word address, shift left form byte address with bits. example, word address 8000h should converted byte address 0000h. Load least significant bits (LSBs) byte address into DMACSSAL (for source) DMACDSAL (for destination). Load most significant (MSB) byte address into DMACSSAU (for source) DMACDSAU (for destination).
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Controller
Updating Addresses Channel
Figure
High-Level TMS320C55x DSPs
Word Addresses (Hexadecimal Range) 0000-FFFF Space Byte Addresses (Hexadecimal Range) 0000-1 FFFF
Updating Addresses Channel
During data transfers channel, controller begins read write accesses start addresses specify described section many cases, after data transfer begun, these addresses must updated that data read written consecutive indexed locations. configure address updates levels:
Block-level
address updates. auto-initialization mode (AUTOINIT DMACCR), block transfers occur after another until turn auto-initialization disable channel. want different start addresses block transfers, update start addresses between block transfers. source address and/or destination address after each element transfer. make sure source address points start next element, make sure element will precisely positioned destination. Choose addressing mode source with SRCAMODE bits DMACCR. Choose addressing mode destination with DSTAMODE bits DMACCR.
Element-level address updates. have controller update
Controller
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Data Burst Capability
Data Burst Capability
Data bursts used improve throughput both ports associated with channel support burst capability. When burst enabled, controller executes burst four elements each time channel serviced instead moving single element. DARAM ports support burst capability. EMIF port supports bursts only requested address range configured synchronous (burst) memory type. requested address configured asynchronous memory, will perform four single accesses move burst data. peripheral port does support burst capability. will perform four single peripheral-port accesses move burst data. burst used, start addresses source destination should aligned burst boundary. Burst boundaries correspond byte addresses with least significant byte. burst, following conditions should met:
start address port which burst enabled should
burst boundary.
element index should frame index should cause each burst access align burst
boundary.
(Element number Element size) should align burst boundary. This
means each frame address should aligned burst boundary. both source destination have burst enabled, source address does start burst boundary, source burst will automatically disabled internally. source will load channel FIFO and, when enough data available, destination burst will executed. destination does start burst boundary, destination accesses will performed single accesses. frame size multiple elements, remaining elements frame will transferred single (nonburst) accesses.
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Controller
Data Packing
Data Packing
controller perform data packing double quadruple amount data passed destination source single transfer. example, 8-bit data type selected destination port 32-bit data bus, four 8-bit pieces data packed into bits before being sent destination. resultant packed data depends size destination source port shown Table
Table
Port DARAM
Data Packing Performed Controller
Data Type 8-bit 16-bit Data Packing Four 8-bit data values packed into bits 16-bit data values packed into bits Four 8-bit data values packed into bits 16-bit data values packed into bits 8-bit data values packed into bits
EMIF
8-bit 16-bit
Peripheral
8-bit
addressing mode used destination source ports also affects whether controller tries pack data. conditions that have both 32-bit 16-bit data packing listed Table Table respectively.
Controller
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Data Packing
Table
32-bit Data Packing Conditions
Byte Address Lower Bits Addressing Mode Post Increment Single/Double Index Constant Other Single/Double Index Other Post Increment Single/Double Index Constant Other Single/Double Index Other Element Index Other Other Access Packed Packed Single Single Packed Single Single Packed Packed Single Single Packed Single Single
Data Type 8-bit
16-bit
Remaining bytes transferred greater than equal bytes.
Table
16-bit Data Packing Conditions
Byte Address Lower Bits Addressing Mode Post Increment Single/Double Index Constant Single/Double Index Other Element Index Other Access Packed Packed Single Single Packed Single
Data Type 8-bit
Remaining bytes transferred greater than equal bytes.
When using element synchronization, data packing performed when reading from source port that source port event driven (see section page 12). source port non-event driven, data packing will performed packing enabled source (SRCPACK regardless whether element synchronization used. However, only element will transferred destination every event.
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Write Posting: Buffering Writes Internal Memory
Write Posting: Buffering Writes Internal Memory
controller take advantage write-posting capability internal memory interface. When write posting DMACCR), controller initiate write then receive acknowledgement from internal memory interface before data actually written memory. controller free begin next operation while internal memory interface assumes control posted data. When write posting disabled controller waits internal memory interface finish memory access before continuing with next operation. might useful during debugging disable write posting.
Controller
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Synchronizing Channel Activity Event
Synchronizing Channel Activity Event
Activity channel synchronized event peripheral event signaled driving external interrupt pin. Using SYNC bits DMACCR, specify which synchronization event any) triggers activity. Each channel also DMACCR that allows choose among synchronization modes:
Element synchronization mode requires event element
transfer. When selected synchronization event occurs, element transferred from channel FIFO buffer destination port. When bytes current element transferred, channel makes more requests destination port until next occurrence synchronization event. channel will request data from source port described below.
Frame synchronization mode requires event trigger
entire frame elements. When event occurs, entire frame elements transferred from channel FIFO buffer destination port. When elements frame transferred, channel makes more requests destination port until next occurrence event. channel will request data from source port described below. synchronization event specified source port event driven (see Table channel will place access request source port until event occurs. When event occurs, channel will take data from source port, place FIFO buffer, place access request destination port. Requests received source destination ports handled according predefined position programmed priority channel service chain (see section page 14).
Table
Event Non-Event Driven Ports
Port DARAM External memory Peripheral Category Non-event driven Non-event driven Event driven
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Controller
Synchronizing Channel Activity Event
other hand, source port being used non-event driven, channel will place access request source port immediately after enabled DMACCR) without waiting event. remainder block, channel will continue make source read requests keep FIFO buffer filled. read requests from source will stop only when FIFO full when source data current block been moved into FIFO. channel will access more than block time. After event occurs, channel will transfer data from FIFO buffer destination port. amount data that transferred destination port each event depends frame element synchronization. channel will request more data from source port soon there space channel FIFO long entire block been completely copied channel FIFO. Read write requests different ports handled according predefined position programmed priority channel service chain (see page choose synchronize channel (SYNC 00000b), channel sends access request source port soon channel enabled DMACCR). Setting initiates transfer entire block defined channel.
10.1
Checking Synchronization Status
Each channel synchronization flag (SYNC) status register, DMACSR. When synchronization event occurs, controller sets flag (SYNC flag cleared (SYNC follows: source port event driven, SYNC cleared when source port initiates request placed channel. source port non-event driven, SYNC cleared when destination port initiates request placed channel.
10.2
Dropped Synchronization Event
synchronization event occurs before controller done servicing previous (before controller clears SYNC DMACSR), synchronization event been dropped. controller responds event drop following manner: After current element transfer, activity channel stops. corresponding interrupt enable (DROPIE DMACICR), controller also sets event drop status (DROP DMACSR) sends interrupt request CPU. more details, Monitoring Channel Activity page Before initiating next transfer, must clear error condition making DMACCR.
Controller
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Monitoring Channel Activity
Monitoring Channel Activity
controller send interrupt response operational events listed following table. Each channel interrupt enable (IE) bits interrupt control register (DMACICR) some corresponding status bits status register (DMACSR). (DMACICR DMACSR described section 14.4 page 44.) operational events table occurs, controller checks corresponding acts accordingly:
(the interrupt enabled), controller sets
corresponding status sends associated interrupt request CPU. DMACSR automatically cleared your program reads register.
controller sets corresponding status
does send interrupt CPU. DMACSR also SYNC that used choose synchronization event channel. SYNC indicates when selected synchronization event occurred (SYNC when been serviced (SYNC more details about synchronization events, Synchronizing Channel Activity page
Table
Controller Operational Events Their Associated Bits Interrupts
Interrupt Enable AERRIE BLOCKIE LASTIE FRAMEIE HALFIE DROPIE TIMEOUTIE Status AERR BLOCK LAST FRAME HALF DROP TIMEOUT Associated Interrupt Channel interrupt Channel interrupt Channel interrupt Channel interrupt Channel interrupt Channel interrupt Channel interrupt
Operational Event Address error occurred Block transfer complete Last frame transfer started Frame transfer complete First half current frame been transferred Synchronization event been dropped Time-out error occurred
frame with number elements, half-frame event occurs soon number elements transferred greater than number that remain transferred. example, frame five elements, half-frame event occurs when controller transferred three elements.
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Controller
Monitoring Channel Activity
11.1
Channel Interrupt
Each channels interrupt. shown Figure channel interrupt logical enabled operational events. choose combination these events setting clearing appropriate interrupt enable (IE) bits interrupt control register (DMACICR) channel. determine which event(s) caused interrupt reading bits status register (DMACSR) channel. read DMACSR clears status bits. DMACSR should read each time interrupt occurs clear pending status bits.
Figure
Triggering Channel Interrupt Request
AERRIE AERR event BLOCKIE BLOCK event LASTIE LAST event FRAMEIE FRAME event HALFIE HALF event DROPIE DROP event TIMEOUTIE TIMEOUT event Channel interrupt request
example using interrupt enable bits, suppose monitoring activity channel suppose that DMACICR: AERRIE BLOCKIE LASTIE FRAMEIE HALFIE DROPIE TIMEOUTIE
Controller SPRU613E
Monitoring Channel Activity
When current frame transfer done synchronization event dropped (see section 10.2 page 26), channel interrupt request sent CPU. other event generate channel interrupt. determine whether both events triggered interrupt, read DROP FRAME bits DMACSR. channel interrupt sets corresponding flag interrupt flag register CPU. respond interrupt ignore interrupt. more details about DMACICR DMACSR, section 14.4 page
11.2
Time-Out Error Condition
controller time-out counter each four ports (internal memory port internal memory port external memory port, peripheral port). clock that controls controller runs fast peripherals clock (SYSCLK1) that been programmed inside TMS320VC5501/5502 DSPs. Once transfer requested ports, corresponding time-out counter incremented every SYSCLK1 cycle. transfer been completed within SYSCLK1 cycles, time-out error signal generated. time-out counter four ports disabled default, enabled each individual port through DMAGTCR. response time-out error signal, activity affected channel stops. corresponding interrupt enable (TIMEOUTIE DMACICR), controller also sets time-out status (TIMEOUT DMACSR) sends channel interrupt request CPU. respond interrupt request ignore interrupt request. Before next transfer initiated, must clear time-out error condition making DMACCR.
11.3
Address Error Condition
controller accesses reserved address space DSP, address error signal generated controller. response, activity effected channel stops. corresponding interrupt enable (AERRIE DMACICR), controller also sets address error status (AERR DMACSR) sends channel interrupt request CPU. respond interrupt request ignore interrupt request. Before next transfer initiated, must clear address error condition making DMACCR.
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Controller
Monitoring Channel Activity
11.4
Error Interrupt
following actions will cause controller send error interrupt (BERRINT) request CPU. respond interrupt request ignore interrupt request.
attempts access reserved address register map. attempts write illegal/reserved value register
field inside register. Here important examples:
attempts load address register with unaligned address address that properly aligned according chosen data type). attempts load index register with index that would create unaligned address.
Controller
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Latency Transfers
Latency Transfers
Each element transfer channel composed read access transfer from source location channel buffer) write access transfer from channel buffer destination location). time complete this activity depends factors such
selected frequency fast peripherals clock (SYSCLK1) signal.
This signal, propagated controller, determines timing transfers.
Wait states other extra cycles added resulting from interface. Activity other channels. Since channels serviced sequential
order, number pending service requests other channels affects often given channel serviced. more details channels serviced, Service Chain page
timing synchronization events channel synchronized).
controller cannot service synchronized channel until synchronization event occurred. more details synchronization, Synchronizing Channel Activity page minimum (best-case) latency determined ports used. DARAM ports, access performed every cycle competing with access same memory block. best-case transfer rate channels using DARAM ports would cycle read source cycle write destination. minimum latency EMIF port determined EMIF settings, including memory type used, programmable timings, delays caused memory itself (such control ARDY pin). latency peripheral port dependent peripherals being accessed configuration fast slow peripheral clocks supplied those peripherals. explained section 1.3, page will always have higher priority than controller accesses same DARAM block internal memory.
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Controller
Power, Emulation, Reset Considerations
Power, Emulation, Reset Considerations
following sections describe controller into low-power state, program response controller debugger breakpoints, what values controller registers have after reset.
13.1
Reducing Power Consumed Controller (Idle Configurations)
divided into idle domains that programmed idle active. state domains called idle configuration. idle configuration that disables clock generator domain and/or domain stops clock and, therefore, stops activity controller. type channel synchronization any) determines quickly controller stops:
synchronization (SYNC 00000b DMACCR). controller
stops after entire block transfer completed.
Frame synchronization (SYNC nonzero DMACCR).
controller stops after current frame transfer completed.
Element synchronization (SYNC nonzero DMACCR).
controller stops after current element transfer completed. When domain idle, there case when temporarily reactivated without change idle configuration. multichannel buffered serial ports (McBSPs) needs controller data transfer, controller will leave idle state perform data transfer then enter idle state again.
13.2
Emulation Modes Controller
FREE DMAGCR controls behavior controller when emulation breakpoint encountered. FREE (the reset value), breakpoint suspends transfers. FREE transfers interrupted breakpoint.
13.3
Controller after Reset
reset resets controller configuration registers. register definitions that follow indicate effects reset register contents.
Controller
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Controller Registers
Controller Registers
Table lists types registers direct memory access (DMA) controller. There registers that affect channels: global control register (DMAGCR) global time-out control register (DMAGTCR). addition, each channels, there channel configuration registers. address each register, data manual your TMS320C55x DSP. attempts access reserved address register map, controller will send error interrupt (BERRINT) request CPU. respond interrupt request ignore interrupt request.
Table
Register DMAGCR DMAGTCR DMACCR DMACICR DMACSR DMACSDP
Registers Controller
Description Global control register (only one) Global time-out control register (only one) Channel control register (one each channel) Interrupt control register (one each channel) Status register (one each channel) Source destination parameters register (one each channel) Source start address (lower part) register (one each channel) Source start address (upper part) register (one each channel) Destination start address (lower part) register (one each channel) Destination start address (upper part) register (one each channel) Element number register (one each channel) Frame number register (one each channel) Details, Page Page Page Page Page Page Page Page Page Page Page Page
DMACSSAL DMACSSAU DMACDSAL DMACDSAU DMACEN DMACFN
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Table
Register DMACSEI DMACSFI DMACDEI DMACDFI DMACSAC DMACDAC
Registers Controller (Continued)
Description Source element index register (one each channel) Source frame index register (one each channel) Destination element index register (one each channel) Destination frame index register (one each channel) Source address counter register (one each channel) Destination address counter register (one each channel) Details, Page Page Page Page Page Page
14.1
Global Control Register (DMAGCR)
global control register (see Figure 16-bit I/O-mapped register used emulation mode controller.
Figure
Global Control Register (DMAGCR)
Reserved
Reserved
Legend: Read; Write; Value after reset
FREE R/W-0
Reserved
Controller
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Table DMAGCR FIeld Descriptions
15-3 Field Reserved FREE Reserved Value Description Writing these bits effect. Reading these bits returns Emulation mode bit. FREE controls behavior controller when emulation breakpoint encountered: breakpoint suspends transfers. transfers continue uninterrupted when breakpoint occurs. Writing these bits effect. Reading these bits returns
14.2
Global Time-Out Control Register (DMAGTCR)
global time-out control register 16-bit read/write register used enable disable time-out counters ports. time-out counters disabled, controller will never generate time-out error condition these ports. more details about time-out error condition, section 11.2 page
Figure
Global Time-Out Control Register (DMAGTCR)
Reserved
Reserved
Legend: Read; Write; Value after reset
R/W-0
R/W-0
ITE1 R/W-0
ITE0 R/W-0
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Table DMAGTCR Field Descriptions
15-4 Field Reserved Value Description Writing these bits effect. Reading these bits returns Peripheral port time-out counter enable bit. This enables/disables time-out counter used monitor delays requests peripheral port. Time-out counter disabled Time-out counter enabled External memory port time-out counter enable bit. This enables/disables time-out counter used monitor delays requests external memory port. ITE1 Time-out counter disabled Time-out counter enabled Internal memory port time-out counter enable bit. This enables/disables time-out counter used monitor delays requests DARAM internal memory port ITE0 Time-out counter disabled Time-out counter enabled Internal memory port time-out counter enable bit. This enables/disables time-out counter used monitor delays requests DARAM internal memory port Time-out counter disabled Time-out counter enabled
Controller
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14.3
Channel Control Register (DMACCR)
Each channel channel control register form shown following figure. This I/O-mapped register enables
Choose source destination addresses updated
(SRCAMODE DSTAMODE)
Enable control repeated transfers (AUTOINIT, REPEAT,
ENDPROG)
Enable disable write posting accesses internal memory (WP) Enable disable channel (EN) Choose high priority level channel (PRIO) Select element synchronization frame synchronization (FS) Determine what synchronization event any) initiates transfer
channel (SYNC)
Figure
Channel Control Register (DMACCR)
R/W-00 PRIO R/W-0 R/W-0 SYNC R/W-0 0000 ENDPROG R/W-0 R/W-0 REPEAT R/W-0 AUTOINIT R/W-0 SRCAMODE
DSTAMODE R/W-00 R/W-0
Legend: Read; Write; Value after reset
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Table DMACCR Field Descriptions
15-14 Field DSTAMODE Value Description Destination addressing mode. DSTAMODE determines addressing mode used controller when writes destination port channel: Constant address same address used each element transfer. Automatic post increment After each element transfer, address incremented according selected data type: data type 8-bit Address Address data type 16-bit Address Address data type 32-bit Address Address Single index After each element transfer, address incremented programmed element index amount: Address Address element index Double index (sort) After each element transfer, address incremented appropriate index amount: there more elements transfer current frame Address Address element index last element frame been transferred Address Address frame index
Controller
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Table DMACCR Field Descriptions (Continued)
13-12 Field SRCAMODE Value Description Source addressing mode. SRCAMODE determines addressing mode used controller when reads from source port channel: Constant address same address used each element transfer. Automatic post increment After each element transfer, address incremented according selected data type: data type 8-bit Address Address data type 16-bit Address Address data type 32-bit Address Address Single index After each element transfer, address incremented programmed element index amount: Address Address element index Double index (sort) After each element transfer, address incremented appropriate index amount: there more elements transfer current frame Address Address element index last element frame been transferred Address Address frame index
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Table DMACCR Field Descriptions (Continued)
Field ENDPROG Value Description End-of-programming bit. Each channel sets registers: configuration registers working registers. When block transfers occur repeatedly because auto-initialization (AUTOINIT change context next transfer writing configuration registers during current block transfer. current transfer, contents configuration registers copied into working registers, controller begins next transfer using context. proper auto-initialization, must finish programming configuration registers before controller copies their contents. controller automatically clears ENDPROG after copying configuration registers working registers. then program channel context next iteration transfer programming configuration registers. make sure auto-initialization waits CPU, follow this procedure: Make auto-initialization wait ENDPROG clearing REPEAT (REPEAT Poll ENDPROG which indicates that controller finished copying previous context. configuration registers programmed next iteration. Program configuration registers. ENDPROG (ENDPROG indicate register programming.
Configuration registers ready programming Programming progress programming Write posting bit. This enables disables write posting capability described page Write posting disabled. Write posting enabled. After initiating write, controller receive acknowledgement from internal memory interface before data actually written memory.
Controller
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Table DMACCR Field Descriptions (Continued)
Field REPEAT Value Description Repeat condition bit. auto-initialization selected channel (AUTOINIT REPEAT specifies special repeat conditions: Repeat only ENDPROG Once current transfer complete, auto-initialization only occurs end-of-programmation (ENDPROG) set. Repeat regardless ENDPROG Once current transfer complete, auto-initialization occurs regardless whether ENDPROG AUTOINIT Auto-initialization bit. controller supports auto-initialization, which automatic reinitialization channel between block transfers. AUTOINIT enable disable this feature: Auto-initialization disabled Activity channel stops current block transfer. stop transfer immediately, clear channel enable (EN). Auto-initialization enabled Once current block transfer complete, controller reinitializes channel starts block transfer. stop activity channel have options:
stop activity immediately, clear channel enable stop activity after current block transfer, clear AUTOINIT (AUTOINIT=
Channel enable bit. enable disable transfers channel. controller clears once block transfer channel complete. Note: attempts write same time that controller must clear controller given higher priority. cleared, value from discarded. Channel disabled channel cannot serviced controller. transfer already active channel, controller stops transfer resets channel. Channel enabled channel serviced controller next available time slot.
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Table DMACCR Field Descriptions (Continued)
Field PRIO Value Description Channel priority bit. channels given fixed position programmable priority level service chain controller. PRIO determines whether associated channel high priority priority. High-priority channels serviced before low-priority channels. priority High priority Frame/element synchronization bit. SYNC bits DMACCR specify synchronization event channel. determines whether synchronization event initiates transfer element entire frame data: Element synchronization When selected synchronization event occurs, element transferred channel. Each element transfer waits synchronization event. Frame synchronization When selected synchronization event occurs, entire frame transferred channel. Each frame transfer waits synchronization event. SYNC Table Synchronization control bits. SYNC DMACCR determines which event (for example, timer countdown) initiates transfer channel. Multiple channels have same SYNC value; other words, synchronization event initiate activity multiple channels. reset selects SYNC 00000b synchronization event). When SYNC 00000b, controller does wait synchronization event before beginning transfer channel; channel activity begins soon channel enabled attempts write reserved value SYNC bits, controller will send error interrupt (BERRINT) request CPU.
Controller
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Table Synchronization Event Mapping TMS320VC5501/5502 DSPs
SYNC Field DMACCR 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b
Synchronization Event Channel synchronization event McBSP receive event McBSP transmit event Reserved this value) Reserved this value) McBSP receive event McBSP transmit event Reserved this value) Reserved this value) Reserved/McBSP event Serial Port Mode Reserved Serial Port Mode McBSP receive event available TMS320VC5501
01010b
Reserved/McBSP event Serial Port Mode Reserved Serial Port Mode McBSP transmit event available TMS320VC5501
01011b
Reserved/UART event Serial Port Mode UART receive event Serial Port Mode Reserved Reserved/UART event Serial Port Mode UART transmit event Serial Port Mode Reserved Timer interrupt event Timer interrupt event External interrupt External interrupt External interrupt
01100b
01101b 01110b 01111b 10000b 10001b
details Serial Port Mode bit, device-specific data manual.
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Table Synchronization Event Mapping TMS320VC5501/5502 DSPs (Continued)
SYNC Field DMACCR 10010b 10011b 10100b Other values
Synchronization Event Channel External interrupt module receive event module transmit event Reserved these values)
details Serial Port Mode bit, device-specific data manual.
14.4
Interrupt Control Register (DMACICR) Status Register (DMACSR)
Each channel interrupt control register (DMACICR) status register (DMACSR). DMACICR DMACSR I/O-mapped registers. Their bits shown Figure described Table Table DMACICR specify that more operational events controller will trigger interrupt. operational event occurs interrupt enable (IE) interrupt request sent CPU, where serviced ignored. Each channel interrupt line flag enable bits CPU. which operational event events have occurred, your program read DMACSR. controller sets interrupt flag bits (bits 5-0) when operational event occurs. interrupt flag bits stay until your program reads DMACSR, which point bits cleared automatically. AERR, DROP, TIMEOUT bits indicate error conditions. Once error condition occurs, must cleared before next transfer initiated. clear error condition, must write DMACCR. SYNC (bit used detect when synchronization event occurred (SYNC when resulting access request been serviced (SYNC
Controller
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Figure
DMACICR
Interrupt Control Register (DMACICR) Status Register (DMACSR)
Reserved
Reserved R/W-1
AERRIE R/W-1 DMACSR
Reserved
BLOCKIE R/W-0
LASTIE R/W-0
FRAMEIE R/W-0
HALFIE R/W-0
DROPIE R/W-1
TIMEOUTIE R/W-1 Reserved
Reserved AERR SYNC BLOCK LAST FRAME HALF DROP
TIMEOUT
Legend: Read; Write; Value after reset; Value after reset defined
Always write DMACICR. After reset, change this from read state DMACSR defined.
Table DMACICR Field Descriptions
15-9 Field Reserved Reserved AERRIE Value Description Writing these bits effect. Reading these bits returns Always write this bit. After reset, change this from Address error interrupt enable bit. AERRIE determines controller responds address error source port destination port channel. address error condition described section 11.3 page send channel interrupt request when this error occurs. Send channel interrupt request when this error occurs.
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Table DMACICR Field Descriptions (Continued)
Field Reserved BLOCKIE Value Description Writing this effect. Reading this returns Whole block interrupt enable bit. BLOCKIE determines controller responds when current block been transferred destination port. LASTIE send channel interrupt request when this error occurs. Send channel interrupt request when this error occurs. Last frame interrupt enable bit. LASTIE determines controller responds last-frame event: peripheral port source, last-frame event occurs when first element last frame being read from source. external internal memory port source, last-frame event occurs when first element last frame being received destination. FRAMEIE send channel interrupt request when this error occurs. Send channel interrupt request when this error occurs. Whole frame interrupt enable bit. FRAMEIE determines controller responds when current frame been transferred destination port. send channel interrupt request when this error occurs. Send channel interrupt request when this error occurs.
Controller
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Table DMACICR Field Descriptions (Continued)
Field HALFIE Value Description Half frame interrupt enable bit. HALFIE determines controller responds when first half current frame been transferred destination port. frame with number elements, half-frame event occurs soon number elements transferred greater than number that remain transferred. example, frame five elements, half-frame event occurs when controller transferred three elements. DROPIE send channel interrupt request when this error occurs. Send channel interrupt request when this error occurs. Synchronization event drop interrupt enable bit. synchronization event occurs again before controller finished servicing previous request, error occurred-a synchronization event drop. DROPIE determines controller responds when synchronization event drop occurs channel. TIMEOUTIE send channel interrupt request when this error occurs. Send channel interrupt request when this error occurs. Time-out interrupt enable bit. TIMEOUTIE determines controller responds time-out error source port destination port channel. time-out error condition described section 11.2 page send channel interrupt request when this error occurs. Send channel interrupt request when this error occurs.
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Table DMACSR Field Descriptions
15-9 Field Reserved Reserved AERR Value Description Writing these bits effect. Reading these bits returns read state defined. Address error status bit. controller sets AERR when address error occurred source port destination port channel. address error condition described section 11.3 page SYNC address error occurred, AERR been cleared. address error occurred. channel interrupt request been sent CPU. Synchronization event status bit. controller updates SYNC indicate when synchronization event channel occurred when synchronized channel been serviced. controller finished servicing previous access request. synchronization event occurred. SYNC automatically cleared described section 10.1 page Note synchronization event occurs again before controller finished servicing previous request, error occurred- synchronization event drop. track this type error using DROPIE DROP bit. Note select synchronization event channel, SYNC bits DMACCR. SYNC SYNC bits DMACCR 00000b. BLOCK Whole block status bit. controller sets BLOCK when current block been transferred destination port. whole-block event occurred yet, BLOCK been cleared. whole block been transferred. channel interrupt request been sent CPU.
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Table DMACSR Field Descriptions (Continued)
Field LAST Value Description Last frame status bit. controller sets LAST when last-frame event occurs. peripheral port source, last-frame event occurs when first element last frame being read from source. external internal memory port source, last-frame event occurs when first element last frame being received destination. FRAME last-frame event occurred yet, LAST been cleared. controller started transferring last frame. channel interrupt request been sent CPU. Whole frame status bit. controller sets FRAME when current frame been transferred destination port. HALF whole-frame event occurred yet, FRAME been cleared. whole frame been transferred. channel interrupt request been sent CPU. Half frame status bit. controller sets HALF when first half current frame been transferred destination port. frame with number elements, half-frame event occurs soon number elements transferred greater than number that remain transferred. example, frame five elements, half-frame event occurs when controller transferred three elements. half-frame event occurred yet, HALF been cleared. first half frame been transferred. channel interrupt request been sent CPU.
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Table DMACSR Field Descriptions (Continued)
Field DROP Value Description Synchronization event drop status bit. synchronization event occurs again before controller finished servicing previous request, error occurred- synchronization event drop. controller sets DROP only DROPIE DMACICR synchronization event drop occurred channel. synchronization event drop occurred, DROP been cleared. synchronization event drop occurred. channel interrupt request been sent CPU. Note DROP cleared after DMACSR read. Note DROP SYNC bits DMACCR 00000b. TIMEOUT Time-out status bit. controller sets TIMEOUT only TIMEOUTIE DMACICR time-out error occurred source port destination port channel. time-out error condition described section 11.2 page time-out error occurred, TIMEOUT been cleared. time-out error occurred. channel interrupt request been sent CPU.
14.5
Source Destination Parameters Register (DMACSDP)
Each channel source destination parameters register form shown Figure This I/O-mapped register enables choose source port (SRC) destination port (DST), specify data type (DATATYPE) port accesses, enable disable data packing (SRCPACK DSTPACK), enable disable burst transfers (SRCBEN DSTBEN).
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Figure
Source Destination Parameters Register (DMACSDP)
DSTBEN R/W-00 DSTPACK R/W-0 SRCPACK R/W-0 R/W-0000 R/W-0000 R/W-00
SRCBEN R/W-00
DATATYPE
Legend: Read; Write; Value after reset
Table DMACSDP Field Descriptions
15-14 Field DSTBEN Value Description Destination burst enable bit. burst controller four consecutive 32-bit accesses port. DSTBEN determines whether controller performs burst destination port channel. DSTPACK Bursting disabled (single access enabled) destination Bursting disabled (single access enabled) destination Bursting enabled destination. When writing destination, controller performs four consecutive 32-bit accesses. Reserved. attempts write DSTBEN bits, controller will send error interrupt (BERRINT) request CPU. Destination packing enable bit. controller perform data packing double quadruple amount data passed destination single transfer. example, 8-bit data type selected destination port 32-bit data bus, four 8-bit pieces data packed into bits before being sent destination. DSTPACK determines whether data packing used destination port. Packing disabled destination Packing enabled destination. Where possible, controller packs data before each write destination. Section (page shows instances where data packing performed.
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Table DMACSDP Field Descriptions (Continued)
12-9 Field 0000b 0001b 0010b 0011b Other Value Description Destination selection bit. selects which port destination data transfers channel: DARAM internal memory port DARAM internal memory port External memory external memory interface (EMIF) Peripherals peripheral controller Reserved. attempts write reserved value bits, controller will send error interrupt (BERRINT) request CPU. Source burst enable bit. burst controller four consecutive 32-bit accesses port. SRCBEN determines whether controller performs burst source port channel. This field will ignored
SRCBEN
source port does support burst capability, constant address mode selected source port, channel element synchronized.
SRCPACK
Bursting disabled (single access enabled) source Bursting disabled (single access enabled) source Bursting enabled source. When reading from source, controller performs four consecutive 32-bit accesses. Reserved. attempts write SRCBEN bits, controller will send error interrupt (BERRINT) request CPU. Source packing enable bit. controller perform data packing double quadruple amount data gathered source before transfer. example, 8-bit data type selected source port 32-bit data bus, four 8-bit pieces data packed into bits before being sent through channel. SRCPACK determines whether data packing used source port.
Packing disabled source Packing enabled source. Where possible, controller packs data from source before beginning data transfer channel. Section (page shows instances where data packing performed.
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Table DMACSDP Field Descriptions (Continued)
Field 0000b 0001b 0010b 0011b Other Value Description Source selection bit. selects which port source data transfers channel: DARAM internal memory port DARAM internal memory port External memory external memory interface (EMIF) Peripherals peripheral controller Reserved. attempts write reserved value bits, controller will send error interrupt (BERRINT) request CPU.
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Table DMACSDP Field Descriptions (Continued)
Field DATATYPE Value Description Data type bit. DATATYPE indicates data accessed source destination channel. Note that controller uses byte addresses accesses; each byte data space space address. information addresses updated between element transfers, descriptions SRCAMODE bits DSTAMODE bits DMACCR (page 37). 8-bit controller makes 8-bit accesses source destination channel. source destination start addresses have alignment constraint: Start address: XXXX XXXX XXXX XXXXb choose automatic post increment addressing mode source destination, corresponding address updated increment after each element transfer. 16-bit controller makes 16-bit accesses source destination. source destination start addresses must each even 2-byte boundary; least significant (LSB) must Start address: XXXX XXXX XXXX XXX0b choose automatic post increment addressing mode source destination, address updated increment after each element transfer. 32-bit controller makes 32-bit accesses source destination. source destination start addresses must even 4-byte boundary; LSBs must Start address: XXXX XXXX XXXX XX00b choose automatic post increment addressing mode source destination, address updated increment after each element transfer. Reserved. attempts write DATATYPE bits, controller will send error interrupt (BERRINT) request CPU.
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14.6
Source Start Address Registers (DMACSSAL DMACSSAU)
Each channel source start address registers, which shown Figure described Table Table first access source port channel, controller generates byte address concatenating contents I/O-mapped registers. DMACSSAU supplies upper bits, DMACSSAL supplies lower bits: Source start address DMACSSAU:DMACSSAL
Notes: must load source start address registers with byte address. have word address, shift left before loading registers. have 16-bit 32-bit data type, start address must aligned properly. description DATATYPE bits DMACSDP (page 50). attempts write unaligned address, controller will send error interrupt (BERRINT) request CPU. programmer's responsibility ensure that start address, element index frame index will produce valid addresses within range port. invalid address generated, time-out error will occur.
destination start address supplied DMACDSAL DMACDSAU, which described section 14.7.
Figure
DMACSSAL
Source Start Address Registers (DMACSSAL DMACSSAU)
SSAL R/W-0
DMACSSAU SSAU R/W-0
Legend: Read; Write; Value after reset
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Table DMACSSAL Field Description
15-0 Field SSAL Value 0000h-FFFFh Description Lower part source start address (byte address)
Table DMACSSAU Field Description
15-0 Field SSAU Value 0000h-00FFh 0100h-FFFFh Description Upper part source start address (byte address) Reserved these values)
14.7
Destination Start Address Registers (DMACDSAL DMACDSAU)
Each channel destination start address registers, which shown Figure described Table Table first access destination port channel, controller generates byte address concatenating contents I/O-mapped registers. DMACDSAU supplies upper bits, DMACDSAL supplies lower bits: Destination start address DMACDSAU:DMACDSAL
Notes: must load destination start address registers with byte address. have word address, shift left before loading registers. have 16-bit 32-bit data type, start address must aligned properly. description DATATYPE bits DMACSDP (page 50). attempts write unaligned address, controller will send error interrupt (BERRINT) request CPU. programmer's responsibility ensure that start address, element index frame index will produce valid addresses within range port. invalid address generated, time-out error will occur.
source start address supplied DMACSSAL DMACSSAU, which described section 14.6.
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Figure
DMACDSAL
Destination Start Address Registers (DMACDSAL DMACDSAU)
DSAL R/W-0
DMACDSAU DSAU R/W-0
Legend: Read; Write; Value after reset
Table DMACDSAL Field Description
15-0 Field DSAL Value 0000h-FFFFh Description Lower part destination start address (byte address)
Table DMACDSAU Field Description
15-0 Field DSAU Value 0000h-00FFh 0100h-FFFFh Description Upper part destination start address (byte address) Reserved these values)
14.8
Element Number Register (DMACEN) Frame Number Register (DMACFN)
Each channel element number register frame number register, (see Figure Table Table 22). Load DMACFN with number frames want each block. Load DMACEN with number elements want each frame. must have least frame element, have many 65535 each: frame number 65535 element number 65535
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attempts write DMACEN DMACFN, controller will send error interrupt (BERRINT) request CPU.
Figure
DMACEN
Element Number Register (DMACEN) Frame Number Register (DMACFN)
ELEMENTNUM R/W-0001h
DMACFN FRAMENUM R/W-0001h
Legend: Read; Write; Value after reset
Table DMACEN Field Description
15-0 Field ELEMENTNUM Value 0000h Description Reserved. attempts write 0000h this field, controller will send error interrupt (BERRINT) request CPU. Number elements frame (1-65535)
0001h-FFFFh
Table DMACFN Field Description
15-0 Field FRAMENUM Value 0000h Description Reserved. attempts write 0000h this field, controller will send error interrupt (BERRINT) request CPU. Number frames block (1-65535)
0001h-FFFFh
Controller
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14.9
Element Index Registers (DMACSEI, DMACDEI) Frame Index Registers (DMACSFI, DMACDFI)
single- double-index addressing mode selected separately source destination ports using SRCAMODE bits DSTAMODE bits, respectively, DMACCR (page 37). support these index addressing modes, each channel element index registers frame index registers. These four registers shown Figure described tables that follow figure. controller uses following index registers control source port:
DMACSEI: Contains desired element index source single-
double-index addressing mode.
DMACSFI: Contains desired frame index source
double-index addressing mode. controller uses following index registers control destination port:
DMACDEI: Contains desired element index destination
single- double-index addressing mode.
DMACDFI: Contains desired frame index destination
double-index addressing mode. element frame indexes 16-bit signed numbers, providing following range: -32768 bytes frame index 32767 bytes -32768 bytes element index 32767 bytes After each transfer, source destination address registers contain address last byte element that transferred. example, consider case which channel reading 32-bit element byte address 0x2000. source address will 0x2003 after element read because channel will read total four bytes. channel reads 16-bit element, source address would 0x2001 after element read because only bytes read. byte read, source address would stay 0x2000 after byte read. When single index mode used, element index added source destination address each element transfer. modified address will then used beginning next element transfer.
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When double index mode used source destination address, element index added source destination address each element transferred described above, except last element frame. last element frame, frame index added source destination address instead element index. example, last element frame starts byte address 0x801E where data type 16-bit frame index 0x0003, will move first byte (0x801E) then second byte (0x801F) element. frame index will then added 0x801F create address first byte next element moved (0x801F 0x0003 0x8022). element index that added source destination address must produce aligned address according data type selected DATATYPE field DMACSDP. this reason only certain values valid element index. Valid values element index are:
(where data type 32-bit (where data type 16-bit value data type 8-bit
with element index, frame index must produce aligned address according data type selected DATATYPE field DMACSDP. Valid values frame index are:
(where data type 32-bit (where data type 16-bit value data type 8-bit
programmer's responsibility ensure that start address, element index, frame index will produce valid addresses within range port. invalid address generated, time-out error will occur. attempts write element frame index that would cause unaligned address, controller will send error interrupt (BERRINT) request CPU. This occurs even address indexing used.
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Figure
DMACSEI
Element Index Registers (DMACSEI, DMACDEI) Frame Index Registers (DMACSFI, DMACDFI)
ELEMENTNDX R/W-0
DMACSFI FRAMENDX R/W-0 DMACDEI ELEMENTNDX R/W-0 DMACDFI FRAMENDX R/W-0
Legend: Read; Write; Value after reset
Table DMACSEI Field Description
15-0 Field ELEMENTNDX Value -32768 32767 Description Source element index bytes)
Table DMACSFI Field Description
15-0 Field FRAMENDX Value -32768 32767 Description Source frame index bytes)
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Table DMACDEI Field Description
15-0 Field ELEMENTNDX Value -32768 32767 Description Destination element index bytes)
Table DMACDFI Field Description
15-0 Field FRAMENDX Value -32768 32767 Description Destination frame index bytes)
14.10 Source Address Counter (DMACSAC) Destination Address Counter (DMACDAC)
progress each channel monitored reading source destination address counters (DMACSAC DMACDAC). DMACSAC shows bits current source address. DMACDAC shows bits current destination address.
Figure
DMACSAC
Channel Source Address Counter (DMACSAC) Channel Destination Address Counter (DMACDAC)
R/W-0
DMACDAC R/W-0
Legend: Read; Write; Value after reset
Table DMACSAC Field Description
15-0 Field Value 0000h-FFFFh Description Current channel source address
Table DMACDAC Field Description
15-0 Field Value 0000h-FFFFh Description Current channel destination address
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Revision History
Table Document Revision History
Page Changed Figure SYNC field range. Changed Figure fields range.
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Index
Index
address counters (DMACSAC DMACDAC) address error condition address error interrupt enable (AERRIE) address error status (AERR) address updating channel AERR DMACSR AERRIE DMACICR AUTOINIT (autoinitialization bit) DMACCR channel synchronized event channels port accesses checking synchronization status CONFIG register used priority configuration versus working registers (figure) requests versus request internal memory
data burst capability DATATYPE bits DMACSDP destination address counter (DMACDAC) destination addressing mode bits (DSTAMODE) destination burst enable bits (DSTBEN) destination packing enable (DSTPACK) destination selection bits (DST) destination start address registers (DMACDSAL DMACDSAU) channel channel address updating channel enable (EN) channel interrupt channel monitoring channel priority (PRIO) channel start addresses channel synchronized event controller connections (figure) requests versus requests internal memory service chain service chain example transfer latency transfer's parts (figure) DMACCR DMACDAC
BLOCK DMACSR block diagram controller connections block interrupt enable (BLOCKIE) block data block status (BLOCK) BLOCKIE DMACICR buffering writes internal memory burst capability error interrupt
channel channel address updating channel context channel control register (DMACCR) channel enable (EN) channel interrupt channel monitoring channel priority (PRIO) channel start addresses
Index
DMACDEI DMACDFI DMACDSAL DMACDSAU DMACEN DMACFN DMACICR DMACSAC DMACSDP DMACSEI DMACSFI DMACSR DMACSSAL DMACSSAU DMAGCR DMAGTCR DROP DMACSR DROPIE DMACICR dropped synchronization event reset effects controller bits DMACSDP DSTAMODE bits DMACCR DSTBEN bits DMACSDP DSTPACK DMACSDP
external memory port time-out counter enable (ETE)
features controller FRAME DMACSR frame index registers (DMACSFI DMACDFI) frame interrupt enable (FRAMEIE) frame number register (DMACFN) frame data frame status (FRAME) frame synchronization mode fram-lement synchronization (FS) FRAMEIE DMACICR FREE DMAGCR DMACCR
global control register (DMAGCR) global time-out control register (DMAGTCR)
HALF DMACSR half frame interrupt enable (HALFIE) half frame status (HALF) HALFIE DMACICR
element index registers (DMACSEI DMACDEI) element number register (DMACEN) element data element synchronization mode emulation mode (FREE) emulation modes DMACCR end-of-programmation (ENDPROG) end-of-programming (ENDPROG) described table ENDPROG DMACCR described table errors address error error time-out error DMAGTCR event drop interrupt enable (DROPIE) event drop status (DROP)
idle configurations effects controller index registers (DMACSEI DMACDEI DMACSFI DMACDFI) internal memory access priority (DMA requests requests) internal memory port time-out counter enable (ITE0) internal memory port time-out counter enable (ITE1) internal memory write posting interrupt control register (DMACICR) interrupts monitoring channel activity introduction controller ITE0 DMAGTCR ITE1 DMAGTCR
Index
features controller
registers controller REPEAT DMACCR repeat condition (REPEAT) reset effects controller
LAST DMACSR last frame interrupt enable (LASTIE) last frame status (LAST) LASTIE DMACICR latency transfers
service chain service chain example source address counter (DMACSAC) source addressing mode bits (SRCAMODE) source destination parameters register (DMACSDP) source burst enable bits (SRCBEN) source packing enable (SRCPACK) source selection bits (SRC) source start address registers (DMACSSAL DMACSSAU) bits DMACSDP SRCAMODE bits DMACCR SRCBEN bits DMACSDP SRCPACK DMACSDP start address registers destination channel source channel start addresses channel status register (DMACSR) SYNC DMACSR SYNC bits DMACCR synchronization control bits (SYNC DMACCR) synchronization event drop interrupt enable (DROPIE) synchronization event drop status (DROP) synchronization event status (SYNC DMACSR) synchronization modes (element frame) synchronization status checking synchronizing channel activity event system configuration register (CONFIG) used priority
monitoring channel activity
number elements DMACEN number frames DMACFN
peripheral port time-out counter enable (PTE) port read access port write access ports controller (figure) position service chain power reduction PRIO DMACCR PRIODMA CONFIG used priority priority channel (PRIO) priority service chain DMAGTCR
reducing power consumed
Index
time-out counter enable bits (PTE ITE1 ITE0) time-out error condition time-out interrupt enable (TIMEOUTIE) time-out status (TIMEOUT) TIMEOUT DMACSR TIMEOUTIE DMACICR transfer latency parts transfer (figure)
whole block interrupt enable (BLOCKIE) whole block status (BLOCK) whole frame interrupt enable (FRAMEIE) whole frame status (FRAME) working registers versus configuration registers (figure) DMACCR
units data
write posting (WP) write posting internal memory

Literature Number: SPRU613E August 2004 IMPORTANT NOTICE Texas In

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