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TMS320VC5503/5507/5509/5510 Direct Memory Access (DMA) Controller Reference Guide
Literature Number: SPRU587B June 2004
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Preface
Read This First
About This Manual
This manual describes features operation direct memory access (DMA) controller that available TMS320VC5503, TMS320VC5507, TMS320VC5509 TMS320VC5510 digital signal processors (DSPs) TMS320C55x (C55x) generation.
Notational Conventions
This document uses following conventions:
most cases, hexadecimal numbers shown with suffix
example, following number hexadecimal (decimal 64):
Similarly, binary numbers often shown with suffix example,
following number decimal number shown binary form: 0100b
Related Documentation From Texas Instruments
following documents describe C55x devices related support tools. Copies these documents available Internet www.ti.com. Tip: Enter literature number search provided www.ti.com. TMS320VC5503 Fixed-Point Digital Signal Processor Data Manual (literature number SPRS245) describes features TMS320VC5503 fixed-point provides signal descriptions, pinouts, electrical specifications, timings device. TMS320VC5507 Fixed-Point Digital Signal Processor Data Manual (literature number SPRS244) describes features TMS320VC5507 fixed-point provides signal descriptions, pinouts, electrical specifications, timings device. TMS320VC5509 Fixed-Point Digital Signal Processor Data Manual (literature number SPRS163) describes features TMS320VC5509 fixed-point provides signal descriptions, pinouts, electrical specifications, timings device.
SPRU587B Direct Memory Access (DMA) Controller
Related Documentation From Texas Instruments
TMS320VC5509A Fixed-Point Digital Signal Processor Data Manual (literature number SPRS205) describes features TMS320VC5509A fixed-point provides signal descriptions, pinouts, electrical specifications, timings device. TMS320VC5510 Fixed-Point Digital Signal Processor Data Manual (literature number SPRS076) describes features TMS320VC5510 fixed-point provides signal descriptions, pinouts, electrical specifications, timings device. TMS320C55x Technical Overview (literature number SPRU393) introduces TMS320C55x DSPs, latest generation fixed-point DSPs TMS320C5000 platform. Like previous generations, this processor optimized high performance low-power operation. This book describes architecture, low-power enhancements, embedded emulation features. TMS320C55x Reference Guide (literature number SPRU371) describes architecture, registers, operation TMS320C55x DSPs. TMS320C55x Peripherals Overview Reference Guide (literature number SPRU317) introduces peripherals, interfaces, related hardware that available TMS320C55x DSPs. TMS320C55x Algebraic Instruction Reference Guide (literature number SPRU375) describes TMS320C55x algebraic instructions individually. Also includes summary instruction set, list instruction opcodes, cross-reference mnemonic instruction set. TMS320C55x Mnemonic Instruction Reference Guide (literature number SPRU374) describes TMS320C55x mnemonic instructions individually. Also includes summary instruction set, list instruction opcodes, cross-reference algebraic instruction set. TMS320C55x Optimizing C/C++ Compiler User's Guide (literature number SPRU281) describes TMS320C55x C/C++ Compiler. This C/C++ compiler accepts standard source code produces assembly language source code TMS320C55x devices. TMS320C55x Assembly Language Tools User's Guide (literature number SPRU280) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives TMS320C55x devices.
Direct Memory Access (DMA) Controller SPRU587B
Trademarks
TMS320C55x Programmer's Guide (literature number SPRU376) describes ways optimize assembly code TMS320C55x DSPs explains write code that uses special features instructions DSPs.
Trademarks
TMS320, TMS320C5000, TMS320C55x, C55x trademarks Texas Instruments. Trademarks property their respective owners.
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Direct Memory Access (DMA) Controller
Contents
Contents
Introduction Controller Features Controller Block Diagram Controller Channels Port Accesses Access Configurations Service Chain Service Chain Example Units Data: Byte, Element, Frame, Block Start Addresses Channel Start Address Memory Start Address Space Updating Addresses Channel Data Burst Capability Synchronizing Channel Activity Checking Synchronization Status Dropped Synchronization Events
Monitoring Channel Activity 10.1 Channel Interrupt 10.2 Time-Out Error Conditions Latency Transfers Power, Emulation, Reset Considerations 12.1 Reducing Power Consumed Controller 12.2 Emulation Modes Controller 12.3 Controller after Reset
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Contents
Controller Registers 13.1 Global Control Register (DMAGCR) 13.2 Global Software Compatibility Register (DMAGSCR) 13.3 Global Time-Out Control Register (DMAGTCR) 13.4 Channel Control Register (DMACCR) 13.5 Interrupt Control Register (DMACICR) Status Register (DMACSR) 13.6 Source Destination Parameters Register (DMACSDP) 13.7 Source Start Address Registers (DMACSSAL DMACSSAU) 13.8 Destination Start Address Registers (DMACDSAL DMACDSAU) 13.9 Element Number Register (DMACEN) Frame Number Register (DMACFN) 13.10 Element Index Registers (DMACEI/DMACSEI, DMACDEI) Frame Index Registers (DMACFI/DMACSFI, DMACDFI) 13.11 Source Address Counter (DMACSAC) Destination Address Counter (DMACDAC)
Revision History
Direct Memory Access (DMA) Controller
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Figures
Figures
Conceptual Block Diagram Controller Connections Parts Transfer Registers Controlling Context Channel Access Configurations Possible Configuration Service Chains Service Chain Applied Three Ports High-Level Memory TMS320C55x DSPs High-Level TMS320C55x DSPs Triggering Channel Interrupt Request Global Control Register (DMAGCR) Global Software Compatibility Register (DMAGSCR) Global Time-Out Control Register (DMAGTCR) Channel Control Register (DMACCR) Interrupt Control Register (DMACICR) Status Register (DMACSR) Source Destination Parameters Register (DMACSDP) Source Start Address Registers (DMACSSAL DMACSSAU) Destination Start Address Registers (DMACDSAL DMACDSAU) Element Number Register (DMACEN) Frame Number Register (DMACFN) Element Index Registers (DMACSEI, DMACDEI) Frame Index Registers (DMACSFI, DMACDFI) Source Address Counter (DMACSAC) Destination Address Counter (DMACDAC)
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Tables
Tables
Activity Shown Registers Used Define Start Addresses Transfer Controller Operational Events Their Associated Bits Interrupts Registers Controller Global Control Register (DMAGCR) Field Descriptions Global Software Compatibility Register (DMAGSCR) Field Descriptions Global Time-Out Control Register (DMAGTCR) Field Descriptions Channel Control Register (DMACCR) Field Descriptions Interrupt Control Register (DMACICR) Field Descriptions Status Register (DMACSR) Field Descriptions Source Destination Parameters Register (DMACSDP) Field Descriptions Data Packing Performed Controller Source Start Address Register Lower Part (DMACSSAL) Field Description Source Start Address Register Upper Part (DMACSSAU) Field Description Destination Start Address Register Lower Part (DMACDSAL) Field Description Destination Start Address Register Upper Part (DMACDSAU) Field Description Element Number Register (DMACEN) Field Description Frame Number Register (DMACFN) Field Description Source Element Index Register (DMACSEI DMACEI) Field Description Source Frame Index Register (DMACSFI DMACFI) Field Description Destination Element Index Register (DMACDEI) Field Description Destination Frame Index Register (DMACDFI) Field Description Source Address Counter (DMACSAC) Field Description Destination Address Counter (DMACDAC) Field Description
Direct Memory Access (DMA) Controller
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Direct Memory Access (DMA) Controller
This document describes features operation controller that available TMS320VC5503, TMS320VC5507, TMS320VC5509, TMS320VC5509A, TMS320VC5510 DSPs. This controller allows movement data among internal memory, external memory, peripherals, host port interface (HPI) occur without intervention from background operation.
Introduction Controller
Acting background operation, controller can:
Transfer data among internal memory, external memory, on-chip
peripherals.
Transfer data between host port interface (HPI) memory.
Features Controller
controller following important features:
Operation that independent CPU. Four standard ports, each data resource: internal dual-access
(DARAM), internal single-access (SARAM), external memory, peripherals.
auxiliary port enable certain transfers between host port interface
(HPI) memory.
channels, which allow controller keep track context
independent block transfers among standard ports.
Bits assigning each channel priority high priority. details,
Service Chain page
Event synchronization. transfers each channel made
dependent occurrence selected events. details, Synchronizing Channel Activity page
interrupt each channel. Each channel send interrupt
completion certain operational events. Monitoring Channel Activity page
Introduction Controller
Software-selectable options updating addresses sources
destinations data transfers.
dedicated idle domain. controller into low-power
state turning this domain. Each multichannel buffered serial port (McBSP) C55x ability temporarily take domain this idle state when McBSP needs controller. Reducing Power Consumed Controller page read about registers used program controller, section page
Block Diagram Controller
Figure conceptual diagram connections between controller other parts DSP. controller ports diagram are:
Four standard ports. controller standard port each
following resources: internal dual-access (DARAM), internal single-access (SARAM), external memory, peripherals. Data transfers among standard ports occur channels. (The channels described page 14.)
Auxiliary port. fifth port supports data transfers between memory
host port interface (HPI). cannot access peripheral port. want transfer data from peripheral port, must data memory temporary buffer. Transfers between memory ports channel. TMS320VC5507/5509 DSPs, shares auxiliary port with module. module given higher priority port. possible multiple channels more channels HPI) request access same standard port same time. arbitrate simultaneous requests, controller programmable service chain that used each standard ports. details service chain, page
Direct Memory Access (DMA) Controller
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Introduction Controller
Figure
Host
Conceptual Block Diagram Controller Connections
Port Port DARAM
Port controller
SARAM
Port Channels Port
Peripheral controller
Peripherals
EMIF
External memory
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Direct Memory Access (DMA) Controller
Channels Port Accesses
Channels Port Accesses
controller paths, called channels, transfer data among four standard ports (for DARAM, SARAM, external memory, peripherals). Each channel reads data from port (from source) writes data that same port another port destination). Each channel first first (FIFO) buffer that allows data transfer occur stages (see Figure Port read access Port write access Transfer data from source port channel FIFO buffer. Transfer data from channel FIFO buffer destination port.
Figure
Parts Transfer
Read access Source port Channel FIFO buffer Write access Destination port
conditions under which transfers occur channel called channel context. Each channels contains register structure programming updating channel context (see Figure Your code modifies configuration registers. When time data transferring, contents configuration registers copied working registers, controller uses working register values control channel activity. copy from configuration registers working registers occurs whenever your code enables channel DMACCR). addition, auto-initialization mode (AUTOINIT DMACCR), copy occurs between block transfers. more information about controller registers, page Some configuration registers programmed next block transfer while controller still running current context from working registers. next transfer will configuration without stopping controller. registers that should configured this manner DMACSDP, DMACCR, DMACICR, DMACSR, DMAGCR, DMAGSCR, DMAGTCR. Modification these registers while channel running cause unpredictable operation channel.
Direct Memory Access (DMA) Controller SPRU587B
Channels Port Accesses
Figure
Registers Controlling Context Channel
Configuration registers (programmed code) DMACSDP DMACCR DMACICR DMACSR DMACSSAL DMACSSAU DMACDSAL DMACDSAU DMACEN DMACFN DMACFI/DMACSFI DMACEI/DMACSEI DMACSAC DMACDAC DMACDEI DMACDFI Automatically copied when channel enabled, between block transfers auto-initialization mode Working registers (used controller) DMACSDP copy DMACCR copy DMACICR copy DMACSR copy DMACSSAL copy DMACSSAU copy DMACDSAL copy DMACDSAU copy DMACEN copy DMACFN copy DMACFI/DMACSFI copy DMACEI/DMACSEI copy DMACSAC copy DMACDAC copy DMACDEI copy DMACDFI copy
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Access Configurations
Access Configurations
shown Figure EHPIEXCL DMAGCR determines relationship between channels:
When EHPIEXCL shares memory with channels. When EHPIEXCL cannot access external memory,
access internal without interruptions from channels. DARAM port SARAM port operate channels were disconnected from service chain. (The service chain described section
Figure
Access Configurations
EHPIEXCL Port read/write requests Port read/write requests DARAM port channels
SARAM port
External memory port
Peripheral port
EHPIEXCL Port read/write requests DARAM port Port read/write requests channels
SARAM port
External memory port
Peripheral port
Direct Memory Access (DMA) Controller
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Service Chain
Service Chain
Each standard ports arbitrate simultaneous access requests sent channels host port interface (HPI). Each standard ports independently functioning service chain-a software hardware controlled scheme servicing access requests. Although four service chains function independently, they share common configuration. example, disable channel disabled four ports, make channel high-priority, high-priority four ports. possible configuration service chains shown Figure Important characteristics service chain listed after figure. Section contains example that shows service chain configuration applied three ports.
Figure
High priority Channel
Possible Configuration Service Chains
High priority Channel High priority Channel
Channel priority
Channel priority
Channel priority
priority EHPIEXCL
channels have programmable priority level. Each
channel PRIO DMACCR selecting high priority priority. assign high priority priority with EHPIPRIO DMAGCR. controller only services low-priority items when high-priority items done stalled. After reset, channels priority. figure, channels high-priority each these channels, PRIO channels priority each these channels, PRIO HPI, EHPIPRIO
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Direct Memory Access (DMA) Controller
Service Chain
channels have fixed positions service chain.
port checks channels repeating circular sequence: HPI, HPI, each position service chain, port checks whether channel/HPI ready able serviced. channel ready serviced higher priority request pending another channel, serviced; otherwise, port skips next position. After reset, port restarts circular sequence, beginning with channel
channels individually connected disconnected from
service chain through software. channel enabled DMACCR), connected service chain; disabled disconnected. After reset, channels disconnected. figure, only channel disconnected. port checks channels repeating circular sequence, will keep skipping channel until channel reconnected.
cannot access peripheral port. peripheral port operates
disconnected from service chain.
writing EHPIEXCL DMAGCR, give
exclusive access DARAM SARAM ports. Then DARAM SARAM ports operate only connected service chain none channels connected, regardless whether channels enabled). more details, Access Configurations page figure, EHPIEXCL shares ports with channels.
channel tied synchronization event, channel does
generate request (and, therefore, cannot serviced) until synchronization event occurs.
Service Chain Example
Figure shows service chain applied DARAM port, external memory port, peripheral port. This service chain following programmed characteristics.
Channels high-priority (PRIO DMACCR). Channels
low-priority (PRIO
Channels enabled DMACCR). Channels
disabled
Direct Memory Access (DMA) Controller SPRU587B
Service Chain
sharing internal memory with channels (EHPIEXCL
DMAGCR) treated like low-priority channel (EHPIPRIO DMAGCR). Notice that shown disconnected peripheral port. This because cannot access peripheral port. Table summarizes activity ports Figure
Table
Activity Shown Figure
Port DARAM This Port Arbitrates Write access requests from channel Read access requests from channel Read write access requests from Write access requests from channel Write access requests from channel Read write access request from Read access requests from channel Read access requests from channel
External memory
Peripheral
Finally, notice that each port figure, there channel that connected service chain does port. example, peripheral port used channel channel were redefined include peripheral port source destination, port would handle channel according position priority service chain.
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Direct Memory Access (DMA) Controller
Service Chain
Figure
Service Chain Applied Three Ports
High-priority: Low-priority: Disabled: Enabled: shares with channels
Configuration service chains
DARAM port: Only used channel channel
Write access Read access
Channel FIFO buffer External memory port: Only used channel channel Write access Channel FIFO buffer Write access
Channel FIFO buffer Peripheral port: Only used channel channel Read access
Read access
Note: never access peripheral port.
Direct Memory Access (DMA) Controller
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Units Data: Byte, Element, Frame, Block
Units Data: Byte, Element, Frame, Block
This documentation controller refers data four levels granularity: Byte Element 8-bit value. byte smallest unit data transferred channel. more bytes transferred unit. Depending programmed data type, element 8-bit, 16-bit, 32-bit value. element transfer cannot interrupted; bytes transferred port before another channel take control port. more elements transferred unit. frame transfer interrupted between element transfers. more frames transferred unit. Each channel transfer block data (once multiple times). block transfer interrupted between frame transfers element transfers.
Frame Block
each channels, define number frames block (with DMACFN), number elements frame (with DMACEN), number bytes element (with DATATYPE bits DMACSDP). descriptions DMACFN, DMACEN, DMACSDP, other registers controller, section page
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Direct Memory Access (DMA) Controller
Start Addresses Channel
Start Addresses Channel
During data transfer channel, first address which data read called source start address. first address which data written called destination start address. These byte addresses. From standpoint controller, every bits memory space address. Each channel contains following registers specifying start addresses:
Table
Registers Used Define Start Addresses Transfer
Register DMACSSAL DMACSSAU DMACDSAL DMACDSAU Load With Source start address (lower part) Source start address (upper part) Destination start address (lower part) Destination start address (upper part)
following sections explain load start address registers memory accesses accesses. controller access internal external memory space (which contains registers peripherals).
Start Address Memory
Figure high-level memory TMS320C55x DSPs. diagram shows both word addresses (23-bit addresses) used byte addresses (24-bit addresses) used controller. load source/destination start address registers: Identify correct start address. Check alignment constraint data type; description DATATYPE bits DMACSDP (page 53). have word address, shift left form byte address with bits. example, word address 4000h should converted byte address 8000h. Load least significant bits (LSBs) byte address into DMACSSAL (for source) DMACDSAL (for destination). Load most significant bits (MSBs) byte address into LSBs DMACSSAU (for source) DMACDSAU (for destination). Note: Word addresses 0000h-00 005Fh (which correspond byte addresses 0000h-00 00BFh) reserved memory-mapped registers (MMRs) CPU.
Direct Memory Access (DMA) Controller
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Start Addresses Channel
Figure
High-Level Memory TMS320C55x DSPs
Word Addresses (Hexadecimal Ranges) MMRs 0000-00 005F Byte Addresses (Hexadecimal Ranges) 0000-00 00BF 00C0-01 FFFF 0000-03 FFFF
Memory
Main data page
0060-00 FFFF 0000-01 FFFF
Main data page
Main data page
0000-02 FFFF
0000-05 FFFF
Main data page
0000-7F FFFF
0000-FF FFFF
Start Address Space
Figure space TMS320C55x DSPs. diagram shows both word addresses (16-bit addresses) used byte addresses (17-bit addresses) used controller. load source/destination start address registers: Identify correct start address. Check alignment constraint data type; description DATATYPE bits DMACSDP (page 53). have word address, shift left form byte address with bits. example, word address 8000h should converted byte address 0000h. Load least significant bits (LSBs) byte address into DMACSSAL (for source) DMACDSAL (for destination). Load most significant (MSB) byte address into DMACSSAU (for source) DMACDSAU (for destination).
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Updating Addresses Channel Start Address Channel Updating Addresses Channel
Figure
High-Level TMS320C55x DSPs
Word Addresses (Hexadecimal Range) 0000-FFFF Space Byte Addresses (Hexadecimal Range) 0000-1 FFFF
Updating Addresses Channel
During data transfers channel, controller begins read write accesses start addresses specify described section many cases, after data transfer begun, these addresses must updated that data read written consecutive indexed locations. configure address updates levels:
Block-level
address updates. auto-initialization mode (AUTOINIT DMACCR), block transfers occur after another until turn auto-initialization disable channel. want different start addresses block transfers, update start addresses between block transfers.
Element-level address updates. have controller update
source address and/or destination address after each element transfer. element transfer, source address held controller address last byte that read from source. Likewise, after transfer, destination address held controller address last byte that modified destination. Through software control, make sure source address points start next element, make sure element will precisely positioned destination. Choose addressing mode source with SRCAMODE bits DMACCR. Choose addressing mode destination with DSTAMODE bits DMACCR. choose single-index double-index addressing mode, must load appropriate index register registers (see section 13.10 page 58).
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Data Burst Capability
Data Burst Capability
Data bursts used improve throughput both ports associated with channel support burst capability. When burst enabled, controller executes burst four elements each time channel serviced instead moving single element. SARAM DARAM ports support burst capability. EMIF port supports bursts only requested address range configured synchronous (burst) memory type. requested address configured asynchronous memory, controller will perform four single accesses move burst data. peripheral port does support burst capability; therefore, controller will perform four single peripheral port accesses move burst data. burst used, start addresses source destination should aligned burst boundary. Burst boundaries correspond byte addresses with least significant byte. burst, following conditions should met:
start address port which burst enabled should
burst boundary.
element index should frame index should cause each burst access align burst
boundary.
(Element number Element size) should align burst boundary. This
means each frame address should aligned burst boundary. both source destination have burst enabled, source address does start burst boundary, source burst will automatically disabled internally. source will load channel FIFO and, when enough data available, destination burst will executed. destination does start burst boundary, destination accesses will performed single accesses. frame size multiple elements, remaining elements frame will transferred single (nonburst) accesses. Burst mode supported when source destination both configured EMIF port.
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Synchronizing Channel Activity
Synchronizing Channel Activity
Activity channel synchronized event peripheral event signaled driving external interrupt pin. Using SYNC bits DMACCR, specify which synchronization event any) triggers activity. Each channel also DMACCR that allows choose among synchronization modes:
Element synchronization mode requires event element
transfer. When selected synchronization event occurs, read access request sent source port then write access request sent destination port. When bytes current element transferred, channel makes more requests until next occurrence synchronization event.
Frame synchronization mode requires event trigger
entire frame elements. When event occurs, channel sends read access request write access request each element frame. When elements transferred, channel makes more requests until next occurrence event. specify synchronization event, source port does receive access request until event occurs. Once request received, handled according predefined position programmed priority channel service chain (see page 17). choose synchronize channel (SYNC 00000b), channel sends access request source port soon channel enabled DMACCR). Setting initiates transfer entire block defined channel.
Checking Synchronization Status
Each channel synchronization flag (SYNC) status register, DMACSR. When synchronization event occurs, controller sets flag (SYNC flag cleared (SYNC when controller completed first read access (transfer from source port channel buffer) after receiving synchronization.
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Synchronizing Channel Activity Monitoring Channel Activity
Dropped Synchronization Events
synchronization event occurs before controller done servicing previous (before controller clears SYNC DMACSR), synchronization event been dropped. controller responds event drop following manner:
After current element transfer, controller disables channel
DMACCR) activity channel stops.
corresponding interrupt enable (DROPIE DMACICR),
controller also sets event drop status (DROP DMACSR) sends interrupt request CPU. more details, Monitoring Channel Activity page
Monitoring Channel Activity
controller send interrupt response operational events listed Table Each channel interrupt enable (IE) bits interrupt control register (DMACICR) some corresponding status bits status register (DMACSR). (DMACICR DMACSR described section 13.5 page 45.) operational events table occurs, controller checks corresponding acts accordingly:
(the interrupt enabled), controller sets
corresponding status sends associated interrupt request CPU. DMACSR automatically cleared your program reads register.
interrupt sent status affected.
DMACSR also SYNC that used choose synchronization event channel. SYNC indicates when selected synchronization event occurred (SYNC when been serviced (SYNC more details about synchronization events, Synchronizing Channel Activity page
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Monitoring Channel Activity
Table
Controller Operational Events Their Associated Bits Interrupts
Interrupt Enable BLOCKIE LASTIE FRAMEIE HALFIE Status BLOCK LAST FRAME HALF Associated Interrupt Channel interrupt Channel interrupt Channel interrupt Channel interrupt
Operational Event Block transfer complete Last frame transfer started Frame transfer complete First half current frame been transferred Synchronization event been dropped Time-out error occurred
DROPIE
DROP
Channel interrupt
TIMEOUTIE
TIMEOUT
Bus-error interrupt
frame with number elements, half-frame event occurs soon number elements transferred greater than number that remain transferred. example, frame five elements, half-frame event occurs when controller transferred three elements.
10.1
Channel Interrupt
Each channels interrupt. shown Figure channel interrupt logical enabled operational events except time-out event (the time-out event generates bus-error interrupt request). choose combination these five events setting clearing appropriate interrupt enable (IE) bits interrupt control register (DMACICR) channel. determine which event(s) caused interrupt reading bits status register (DMACSR) channel. bits DMACSR automatically cleared. read DMACSR clears status bits. DMACSR should read each time interrupt occurs clear pending status bits.
Figure
Triggering Channel Interrupt Request
BLOCK event LASTIE LAST event FRAMEIE FRAME event HALFIE HALF event DROPIE DROP event
Direct Memory Access (DMA) Controller
BLOCKIE
Channel interrupt
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Monitoring Channel Activity
example using interrupt enable bits, suppose monitoring activity channel suppose that DMACICR: BLOCKIE LASTIE FRAMEIE HALFIE DROPIE When current frame transfer done synchronization event dropped (see page 27), channel interrupt request sent CPU. other event generate channel interrupt. determine whether both events triggered interrupt, read FRAME DROP bits DMACSR. channel interrupt sets corresponding flag interrupt flag register CPU. respond interrupt ignore interrupt. more details about DMACICR DMACSR, section 13.5 page
10.2
Time-Out Error Conditions
time-out error condition exists when memory access been stalled many cycles. Each four standard ports controller supported hardware detect time-out error:
DARAM port: time-out counter DARAM port keeps track
many cycles have passed since request made access DARAM. When counter reaches time-out value clock cycles, DARAM port generates internal time-out signal. This counter enabled disabled writing DARAM time-out counter enable (DTCE DMAGTCR). time-out error DARAM port occur because using port preventing access controller, because address specified that does exist DARAM DSP.
SARAM port: time-out counter SARAM port keeps track
many cycles have passed since request made access SARAM. When counter reaches time-out value clock cycles, SARAM port generates time-out signal. This counter enabled disabled writing SARAM time-out counter enable (STCE DMAGTCR). time-out error SARAM port occur because using port preventing access controller, because address specified that does exist SARAM DSP.
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Monitoring Channel Activity
External memory port: time-out counter external memory interface
(EMIF) keeps track many cycles external ready (ARDY) been sampled low. When counter reaches programmed time-out value, EMIF sends time-out signal controller. external memory divided into four memory spaces, each which programmable time-out value cycles.
Peripheral port: time-out counter peripheral controller counts
many cycles have passed since request made access peripheral. When counter reaches time-out value clock cycles, peripheral controller sends time-out signal controller. time-out error peripheral port occur because address specified that does exist space DSP. response time-out signal, controller disables channel DMACCR); activity channel stops. corresponding interrupt enable (TIMEOUTIE DMACICR), controller also sets time-out status (TIMEOUT DMACSR) sends time-out signal interrupt request. interrupt request sets bus-error interrupt (BERRINT) flag CPU. respond interrupt request ignore interrupt request.
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Latency Transfers
Latency Transfers
Each element transfer channel composed read access transfer from source location channel buffer) write access transfer from channel buffer destination location). time complete this activity depends factors such
selected frequency clock signal. This signal,
propagated controller, determines timing transfers. Wait states other extra cycles added resulting from interface. Activity other channels. Since channels serviced sequential order, number pending service requests other channels affects often given channel serviced. more details channels serviced, Service Chain page Competition from host port interface (HPI). sharing internal with channels, controller allocates cycles like does channels. give exclusive access internal RAM, channels access internal until change access configuration (see section page 16). Competition from CPU. controller request access same internal memory block same cycle memory block cannot service both requests same time, request higher priority. request serviced soon there pending requests. timing synchronization events channel synchronized). controller cannot service synchronized channel until synchronization event occurred. more details synchronization, Synchronizing Channel Activity page
minimum (best-case) latency determined ports used. SARAM DARAM ports, controller initiate access cycle, controller competing with access same memory block. SARAM memory support access cycle memory block from either CPU. access same SARAM block used same cycle) will cause stalls access. DARAM memory support accesses cycle memory block from either CPU. More than access same DARAM block used will cause stalls access. best-case transfer rate channels using these ports would cycle read source cycle write destination. minimum latency EMIF port determined EMIF settings, including memory type used, programmed timings, delays caused memory itself (such control ARDY pin). minimum latency peripheral port approximately cycles access.
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Power, Emulation, Reset Considerations
Power, Emulation, Reset Considerations
following sections describe controller into low-power state, program response controller emulation breakpoints, effect reset controller.
12.1
Reducing Power Consumed Controller
divided into idle domains that programmed idle active. state domains called idle configuration. idle configuration that disables clock generator domain and/or domain stops clock and, therefore, stops activity controller. type channel synchronization any) determines quickly controller stops:
synchronization (SYNC 00000b DMACCR). controller
stops after entire block transfer completed.
Frame synchronization (SYNC nonzero DMACCR).
controller stops after current frame transfer completed.
Element synchronization (SYNC nonzero DMACCR).
controller stops after current element transfer completed. When domain idle, there case when temporarily reactivated without change idle configuration. multichannel buffered serial ports (McBSPs) needs controller data transfer, controller will leave idle state perform data transfer then enter idle state again.
12.2
Emulation Modes Controller
FREE DMAGCR controls behavior controller when emulation breakpoint encountered. FREE (the reset value), breakpoint suspends transfers. FREE transfers interrupted breakpoint.
12.3
Controller after Reset
reset resets controller configuration registers. Some registers initialized after reset some not. register definitions that follow indicate effects reset register contents.
Direct Memory Access (DMA) Controller
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Controller Registers
Controller Registers
Table lists types registers direct memory access (DMA) controller. There three global control registers (DMAGCR, DMAGSCR, DMAGTCR) that affect channel activity. addition, each channels, there channel configuration registers. address each register, data manual your TMS320C55x DSP.
Table
Register DMAGCR DMAGSCR DMAGTCR DMACCR DMACICR DMACSR DMACSDP DMACSSAL DMACSSAU DMACDSAL DMACDSAU DMACEN DMACFN
Registers Controller
Description Global control register (only one) Global software compatibility register (only one) Global time-out control register (only one) Channel control register (one each channel) Interrupt control register (one each channel) Status register (one each channel) Source destination parameters register (one each channel) Source start address (lower part) register (one each channel) Source start address (upper part) register (one each channel) Destination start address (lower part) register (one each channel) Destination start address (upper part) register (one each channel) Element number register (one each channel) Frame number register (one each channel) Details, Page Page Page Page Page Page Page Page Page Page Page Page Page
This register associated function supported TMS320VC5509 DSP, supported TMS320VC5503/5507/5509A/5510 DSPs.
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Table
Register DMACEI/ DMACSEI DMACFI/ DMACSFI DMACDEI DMACDFI DMACSAC DMACDAC
Registers Controller (Continued)
Description Element index register/ Source element index register (one each channel) Frame index register/ Source frame index register (one each channel) Destination element index register (one each channel) Destination frame index register (one each channel) Source address counter register (one each channel) Destination address counter register (one each channel) Details, Page
Page
Page Page Page Page
This register associated function supported TMS320VC5509 DSP, supported TMS320VC5503/5507/5509A/5510 DSPs.
Direct Memory Access (DMA) Controller
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13.1
Global Control Register (DMAGCR)
global control register (see Figure Table 16-bit read/write register. this I/O-mapped register emulation mode controller (FREE) define controller treats host port interface (EHPIEXCL EHPIPRIO).
Figure
Global Control Register (DMAGCR)
Reserved
Reserved
Reserved R/W-1
FREE R/W-0
EHPIEXCL R/W-0
EHPIPRIO R/W-0
Legend: Read; Write; Value after reset
Always write this reserved bit.
Table
15-4 Field
Global Control Register (DMAGCR) Field Descriptions
Value Description These read-only bits return when read. Always write this reserved bit. Emulation mode bit. FREE controls behavior controller when emulation breakpoint encountered: breakpoint suspends transfers. transfers continue uninterrupted when breakpoint occurs. exclusive access bit. EHPIEXCL determines whether host port interface (HPI) exclusive access internal DSP. Note: Regardless value EHPIEXCL, cannot access peripheral port. shares internal with channels. access internal external memory address reach. exclusive access internal RAM. channels must access DARAM port SARAM port, activity these channels suspended. this access configuration, only access DARAM port SARAM port. cannot access external memory port.
Reserved Reserved FREE
EHPIEXCL
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Table
Field
Global Control Register (DMAGCR) Field Descriptions (Continued)
Value Description priority bit. EHPIPRIO assigns high priority level service chain controller: Note: When exclusive access DARAM SARAM ports (EHPIEXCL priority irrelevant these ports because none channels access DARAM SARAM ports. priority level. High priority level.
EHPIPRIO
13.2
Global Software Compatibility Register (DMAGSCR)
global software compatibility register 16-bit read/write register used control controller gets destination element index destination frame index. original controller design used same element index register (DMACEI) both source destination, same frame index register (DMACFI) both source destination. Later designs were enhanced allow separate source destination indexes. enhanced mode:
DMACEI DMACSEI, source element index register. DMACFI
DMACSFI, source frame index register.
destination element index stored separate destination element
index register (DMACDEI) destination frame index stored separate destination frame index register (DMACDEI). DMAGSCR provides ability choose either original method indexing maintain software compatibility with code written original design) enhanced method indexing. DMAGSCR summarized Figure Table Note: DMAGSCR associated function supported TMS320VC5509 DSP, they supported TMS320VC5503/5507/5509A/5510 DSPs.
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Figure
Global Software Compatibility Register (DMAGSCR)
Reserved
Reserved
Legend: Read; Write; Value after reset
DINDXMD R/W-0
Table
15-1
Global Software Compatibility Register (DMAGSCR) Field Descriptions
Field Reserved DINDXMD Value Description These read-only bits return when read. Destination element frame index mode bit. This determines which registers will used indicate destination element frame indexes. Compatibility mode. element index both source destination stored channel source element index register (DMACSEI). frame index both source destination stored channel source frame index register (DMACSEI). Enhanced mode. source element index stored channel source element index register (DMACSEI). destination element index stored channel destination element index register (DMACDEI). source frame index stored channel source frame index register (DMACSFI). destination frame index stored channel destination frame index register (DMACDFI).
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Controller Registers
13.3
Global Time-Out Control Register (DMAGTCR)
global time-out control register (see Figure Table 16-bit read/write register used enable disable time-out counters SARAM DARAM ports. time-out counters disabled, controller will never generate time-out error these ports. details about time-out error conditions, section 10.2 (page 29). Note: DMAGTCR associated function supported TMS320VC5509 DSP, they supported TMS320VC5503/5507/5509A/5510 DSPs.
Figure
Global Time-Out Control Register (DMAGTCR)
Reserved
Reserved
Legend: Read; Write; Value after reset
DTCE R/W-0
STCE R/W-0
Direct Memory Access (DMA) Controller
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Table
15-2
Global Time-Out Control Register (DMAGTCR) Field Descriptions
Field Reserved DTCE Value Description These read-only bits return when read. DARAM time-out counter enable bit. This enables/disables time-out counter used monitor delays requests DARAM port. DARAM time-out counter disabled. DARAM time-out counter enabled. SARAM time-out counter enable bit. This enables/disables time-out counter used monitor delays requests SARAM port. SARAM time-out counter disabled. SARAM time-out counter enabled.
STCE
13.4
Channel Control Register (DMACCR)
Each channel channel control register form shown Figure This I/O-mapped register enables
Choose source destination addresses updated
(SRCAMODE DSTAMODE)
Enable control repeated transfers (AUTOINIT, REPEAT,
ENDPROG)
Enable disable channel (EN) Choose high priority level channel (PRIO) Select element synchronization frame synchronization (FS) Determine what synchronization event any) initiates transfer
channel (SYNC) Table describes fields this register.
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Controller Registers
Figure
Channel Control Register (DMACCR)
R/W-0 PRIO R/W-0 R/W-0 SYNC R/W-0 ENDPROG R/W-0 Reserved R/W-0 REPEAT R/W-0 AUTOINIT R/W-0 SRCAMODE
DSTAMODE R/W-0 R/W-0
Legend: Read; Write; Value after reset
must kept proper operation controller.
Table
15-14
Channel Control Register (DMACCR) Field Descriptions
Field DSTAMODE Value Description Destination addressing mode bits. DSTAMODE determines addressing mode used controller when writes destination port channel. transfer before incrementing, destination address address last byte that modified destination. Constant address. same address used each element transfer. Automatic post increment. After each element transfer, address incremented according selected data type: data type 8-bit Address Address data type 16-bit Address Address data type 32-bit Address Address Single index. After each element transfer, address incremented programmed element index amount: Address Address element index Double index (sort). After each element transfer, address incremented appropriate index amount: there more elements transfer current frame Address Address element index last element frame been transferred Address Address frame index
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Table
13-12
Channel Control Register (DMACCR) Field Descriptions (Continued)
Field SRCAMODE Value Description Source addressing mode bits. SRCAMODE determines addressing mode used controller when reads from source port channel. transfer before incrementing, source address address last byte that read from source. Constant address. same address used each element transfer. Automatic post increment. After each element transfer, address incremented according selected data type: data type 8-bit Address Address data type 16-bit Address Address data type 32-bit Address Address Single index. After each element transfer, address incremented programmed element index amount: Address Address element index Double index (sort). After each element transfer, address incremented appropriate index amount: there more elements transfer current frame Address Address element index last element frame been transferred Address Address frame index
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Table
Channel Control Register (DMACCR) Field Descriptions (Continued)
Field ENDPROG Value Description End-of-programming bit. Each channel sets registers: configuration registers working registers. When block transfers occur repeatedly because auto-initialization (AUTOINIT change context next transfer writing configuration registers during current block transfer. current transfer, contents configuration registers copied into working registers, controller begins next transfer using context. proper auto-initialization, must finish programming configuration registers before controller copies their contents. controller automatically clears ENDPROG after copying configuration registers working registers. then program channel context next iteration transfer programming configuration registers. make sure auto-initialization waits CPU, follow this procedure: Make auto-initialization wait ENDPROG clearing REPEAT (REPEAT Poll ENDPROG which indicates that controller finished copying previous context. configuration registers programmed next iteration. Program configuration registers. ENDPROG (ENDPROG indicate register programming.
Reserved
Configuration registers ready programming Programming progress. programming. This reserved must kept Make sure that whenever your program modifies DMACCR, writes
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Table
Channel Control Register (DMACCR) Field Descriptions (Continued)
Field REPEAT Value Description Repeat condition bit. auto-initialization selected channel (AUTOINIT REPEAT specifies special repeat conditions: Repeat only ENDPROG Once current transfer complete, auto-initialization will wait end-of-programming (ENDPROG) set. Repeat regardless ENDPROG. Once current transfer complete, auto-initialization occurs regardless whether ENDPROG
AUTOINIT
Auto-initialization bit. controller supports auto-initialization, which automatic reinitialization channel between block transfers. AUTOINIT enable disable this feature. Auto-initialization disabled. Activity channel stops current block transfer. stop transfer immediately, clear channel enable (EN). Auto-initialization enabled. Once current block transfer complete, controller reinitializes channel starts block transfer. stop activity channel have options:
stop activity immediately, clear channel enable stop activity after current block transfer, clear AUTOINIT (AUTOINIT=
Channel enable bit. enable disable transfers channel. controller clears once block transfer channel complete. Note: attempts write same time that controller must clear controller given higher priority. cleared, value from discarded. channel disabled. channel cannot serviced controller. transfer already active channel, controller stops transfer resets channel. channel enabled. channel serviced controller next available time slot.
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Table
Channel Control Register (DMACCR) Field Descriptions (Continued)
Field PRIO Value Description Channel priority bit. channels given fixed position programmable priority level service chain controller. PRIO determines whether associated channel high priority priority. High-priority channels serviced before low-priority channels. priority. High priority. Frame/element synchronization bit. SYNC bits DMACCR specify synchronization event channel. determines whether synchronization event initiates transfer element entire frame data: Element synchronization. When selected synchronization event occurs, element transferred channel. Each element transfer waits synchronization event. Frame synchronization. When selected synchronization event occurs, entire frame transferred channel. Each frame transfer waits synchronization event.
SYNC
(See data Synchronization control bits. SYNC DMACCR determines manual) which event (for example, timer countdown) initiates transfer channel. Multiple channels have same SYNC value; other words, synchronization event initiate activity multiple channels. reset selects SYNC 00000b synchronization event). When SYNC 00000b, controller does wait synchronization event before beginning transfer channel; channel activity begins soon channel enabled available SYNC events each TMS320C55x documented device-specific data manuals.
Direct Memory Access (DMA) Controller
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Controller Registers
13.5
Interrupt Control Register (DMACICR) Status Register (DMACSR)
Each channel interrupt control register (DMACICR) status register (DMACSR). DMACICR DMACSR I/O-mapped registers. Their bits shown Figure described Table Table DMACICR specify that more operational events controller will trigger interrupt. operational event occurs interrupt enable (IE) interrupt request sent CPU, where serviced ignored. Each channel interrupt line flag enable bits CPU. addition controller send bus-error interrupt request response time-out error. bus-error interrupt also flag enable bits CPU. which operational event events have occurred controller, your program read DMACSR. controller sets interrupt flag bits (bits 5-0) only operational event occurs associated interrupt enable DMACICR. After your program reads DMACSR, bits cleared automatically. SYNC (bit DMACSR used detect when synchronization event occurred (SYNC when resulting access request been serviced (SYNC
Figure
DMACICR
Interrupt Control Register (DMACICR) Status Register (DMACSR)
Reserved
Reserved DMACSR
BLOCKIE R/W-0
LASTIE R/W-0
FRAMEIE R/W-0
HALFIE R/W-0
DROPIE R/W-1
TIMEOUTIE R/W-1
Reserved Reserved SYNC BLOCK LAST FRAME HALF DROP TIMEOUT
Legend: Read; Write; Value after reset
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Controller Registers
Table
15-6
Interrupt Control Register (DMACICR) Field Descriptions
Field Reserved BLOCKIE Value Description These read-only bits return when read. Whole block interrupt enable bit. BLOCKIE determines controller responds when current block been transferred from source port destination port. record event. BLOCK send channel interrupt request CPU. Last frame interrupt enable bit. LASTIE determines controller responds when controller starts transferring last frame from source port destination port. record event. LAST send channel interrupt request CPU. Whole frame interrupt enable bit. FRAMEIE determines controller responds when current frame been transferred from source port destination port. record event. FRAME send channel interrupt request CPU. Half frame interrupt enable bit. HALFIE determines controller responds when first half current frame been transferred from source port destination port. frame with number elements, half-frame event occurs soon number elements transferred greater than number that remain transferred. example, frame five elements, half-frame event occurs when controller transferred three elements. record event. HALF send channel interrupt request CPU.
LASTIE
FRAMEIE
HALFIE
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Table
Interrupt Control Register (DMACICR) Field Descriptions (Continued)
Field DROPIE Value Description Synchronization event drop interrupt enable bit. synchronization event occurs again before controller finished servicing previous request, error occurred-a synchronization event drop. DROPIE determines controller responds when synchronization event drop occurs channel. record drop. DROP send channel interrupt request CPU. Time-out interrupt enable bit. TIMEOUTIE determines controller responds time-out error source port destination port channel. time-out error conditions described section 10.2 (page 29). record time-out error. TIMEOUT send bus-error interrupt request CPU.
TIMEOUTIE
Table Status Register (DMACSR) Field Descriptions
15-7 Field Reserved SYNC Value Description These read-only bits return when read. Synchronization event status bit. controller updates SYNC indicate when synchronization event channel occurred when synchronized channel been serviced: controller finished servicing previous access request. synchronization event occurred. response event, synchronized channel submits access request source port. Note synchronization event occurs again before controller finished servicing previous request, error occurred-a synchronization event drop. track this type error using DROPIE DROP bit. Note select synchronization event channel, SYNC bits DMACCR.
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Controller Registers
Table Status Register (DMACSR) Field Descriptions (Continued)
Field BLOCK Value Description Whole block status bit. controller sets BLOCK only BLOCKIE DMACICR current block been transferred from source port destination port: whole-block event occurred yet, BLOCK been cleared. whole block been transferred. channel interrupt request been sent CPU. Last frame status bit. controller sets LAST only LASTIE DMACICR controller started transferring last frame from source port destination port: last-frame event occurred yet, LAST been cleared. controller started transferring last frame. channel interrupt request been sent CPU. Whole frame status bit. controller sets FRAME only FRAMEIE DMACICR current frame been transferred from source port destination port: whole-frame event occurred yet, FRAME been cleared. whole frame been transferred. channel interrupt request been sent CPU. Half frame status bit. controller sets HALF only HALFIE DMACICR first half current frame been transferred from source port destination port. frame with number elements, half-frame event occurs soon number elements transferred greater than number that remain transferred. example, frame five elements, half-frame event occurs when controller transferred three elements. half-frame event occurred yet, HALF been cleared. first half frame been transferred. channel interrupt request been sent CPU.
LAST
FRAME
HALF
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Table Status Register (DMACSR) Field Descriptions (Continued)
Field DROP Value Description Synchronization event drop status bit. synchronization event occurs again before controller done servicing previous request, error occurred-a synchronization event drop. controller sets DROP only DROPIE DMACICR synchronization event drop occurred channel. synchronization event drop occurred, DROP been cleared. synchronization event drop occurred. channel interrupt request been sent CPU. Time-out status bit. controller sets TIMEOUT only TIMEOUTIE DMACICR time-out error occurred source port destination port channel. time-out error conditions described section 10.2 (page 29). time-out error occurred, TIMEOUT been cleared. time-out error occurred. bus-error interrupt request been sent CPU.
TIMEOUT
13.6
Source Destination Parameters Register (DMACSDP)
Each channel source destination parameters register form shown Figure This I/O-mapped register enables choose source port (SRC) destination port (DST), specify data type (DATATYPE) port accesses, enable disable data packing (SRCPACK DSTPACK), enable disable burst transfers (SRCBEN DSTBEN). Table describes fields this register.
Figure
Source Destination Parameters Register (DMACSDP)
DSTBEN R/W-0 DSTPACK R/W-0 SRCPACK R/W-0 R/W-0 R/W-0
SRCBEN R/W-0
DATATYPE R/W-0
Legend: Read; Write; Value after reset
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Table Source Destination Parameters Register (DMACSDP) Field Descriptions
15-14 Field DSTBEN Value Description Destination burst enable bits. burst controller four consecutive 32-bit accesses port. DSTBEN determines whether controller performs burst destination port channel. Burst supported when both source destination configured EMIF port (SRC XX10b). Bursting disabled (single access enabled) destination. Bursting disabled (single access enabled) destination. Bursting enabled destination. When writing destination, controller performs four consecutive 32-bit accesses. Reserved use). Destination packing enable bit. controller perform data packing double quadruple amount data passed destination single transfer. example, 8-bit data type selected destination port 32-bit data bus, four 8-bit pieces data packed into bits before being sent destination. DSTPACK determines whether data packing used destination port. Packing disabled destination. Packing enabled destination. Where possible, controller packs data before each write destination. Table (page shows instances where data packing performed.
DSTPACK
Refer device specific data manuals available ports each TMS320C55x DSP.
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Table Source Destination Parameters Register (DMACSDP) Field Descriptions (Continued)
12-9 Field Value Description Destination selection bits. selects which port destination data transfers channel shown 0000b 0001b 0010b 0011b SARAM (single-access inside DSP). DARAM (dual-access inside DSP). External memory (via external memory interface, EMIF). Peripherals (via peripheral controller). Connection channel configured have 8-bit data type peripheral port supported. Others SRCBEN Reserved. Source burst enable bits. burst controller four consecutive 32-bit accesses port. SRCBEN determines whether controller performs burst source port channel. This field will ignored
source port does support burst capability, constant address mode selected source port, channel element synchronized.
Burst supported when both source destination configured EMIF port (SRC XX10b). Bursting disabled (single access enabled) source. Bursting disabled (single access enabled) source. Bursting enabled source. When reading from source, controller performs four consecutive 32-bit accesses. Reserved use).
Refer device specific data manuals available ports each TMS320C55x DSP.
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Table Source Destination Parameters Register (DMACSDP) Field Descriptions (Continued)
Field SRCPACK Value Description Source packing enable bit. controller perform data packing double quadruple amount data gathered source before transfer. example, 8-bit data type selected source port 32-bit data bus, four 8-bit pieces data packed into bits before being sent through channel. SRCPACK determines whether data packing used source port. Packing disabled source. Packing enabled source. Where possible, controller packs data from source before beginning data transfer channel. Table (page shows instances where data packing performed. Source selection bits. selects which port source data transfers channel shown 0000b 0001b 0010b 0011b SARAM (single-access inside DSP). DARAM (dual-access inside DSP). External memory (via external memory interface, EMIF). Peripherals (via peripheral controller). Connection channel configured have 8-bit data type peripheral port supported. Others
Reserved.
Refer device specific data manuals available ports each TMS320C55x DSP.
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Table Source Destination Parameters Register (DMACSDP) Field Descriptions (Continued)
Field DATATYPE Value Description Data type bit. DATATYPE indicates data accessed source destination channel. Note that controller uses byte addresses accesses; each byte data space space address. information addresses updated between element transfers, descriptions DSTAMODE bits SRCAMODE bits DMACCR (see pages 41). 8-bit. controller makes 8-bit accesses source destination channel. source destination start addresses have alignment constraint: Start address: XXXX XXXX XXXX XXXXb choose automatic post increment addressing mode source destination, corresponding address updated increment after each element transfer. Connection channel configured 8-bit data type peripheral port supported. 16-bit. controller makes 16-bit accesses source destination. source destination start addresses must each even 2-byte boundary; least significant (LSB) must Start address: XXXX XXXX XXXX XXX0b choose automatic post increment addressing mode source destination, address updated increment after each element transfer. 32-bit. controller makes 32-bit accesses source destination. source destination start addresses must even 4-byte boundary; LSBs must Start address: XXXX XXXX XXXX XX00b choose automatic post increment addressing mode source destination, address updated increment after each element transfer.
Reserved use).
Refer device specific data manuals available ports each TMS320C55x DSP.
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Controller Registers
Table Data Packing Performed Controller
Data Type 8-bit 8-bit 16-bit Port Size 16-bit 32-bit 32-bit Data Packing data values packed into bits Four data values packed into bits data values packed into bits
SARAM, DARAM, EMIF ports have 32-bit internal buses. peripheral port 16-bit internal bus.
13.7
Source Start Address Registers (DMACSSAL DMACSSAU)
Each channel source start address registers, which shown Figure described Table Table first access source port channel, controller generates byte address concatenating contents I/O-mapped registers. DMACSSAU supplies upper bits, DMACSSAL supplies lower bits: Source start address DMACSSAU:DMACSSAL Notes: must load source start address registers with byte address. have word address, shift left before loading registers. have 16-bit 32-bit data type, start address must aligned properly. description DATATYPE bits DMACSDP (page 53). Make sure that start address, element index, frame index will produce valid addresses within range port. invalid address generated, time-out error will occur. destination start address supplied DMACDSAL DMACDSAU, which described section 13.8.
Direct Memory Access (DMA) Controller
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Figure
DMACSSAL
Source Start Address Registers (DMACSSAL DMACSSAU)
SSAL R/W-x
DMACSSAU SSAU R/W-x
Legend: Read; Write; Value after reset defined
Table Source Start Address Register Lower Part (DMACSSAL) Field Description
15-0 Field SSAL Value 0000h-FFFFh Description Lower part source start address (byte address).
Table Source Start Address Register Upper Part (DMACSSAU) Field Description
15-0 Field SSAU Value 0000h-00FFh 0100h-FFFFh Description Upper part source start address (byte address). Reserved use).
13.8
Destination Start Address Registers (DMACDSAL DMACDSAU)
Each channel destination start address registers, which shown Figure described Table Table first access destination port channel, controller generates byte address concatenating contents I/O-mapped registers. DMACDSAU supplies upper bits, DMACDSAL supplies lower bits: Destination start address DMACDSAU:DMACDSAL
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Notes: must load destination start address registers with byte address. have word address, shift left before loading registers. have 16-bit 32-bit data type, start address must aligned properly. description DATATYPE bits DMACSDP (page 53). Make sure that start address, element index, frame index will produce valid addresses within range port. invalid address generated, time-out error will occur. source start address supplied DMACSSAL DMACSSAU, which described section 13.7.
Figure
DMACDSAL
Destination Start Address Registers (DMACDSAL DMACDSAU)
DSAL R/W-x
DMACDSAU DSAU R/W-x
Legend: Read; Write; Value after reset defined
Direct Memory Access (DMA) Controller
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Table Destination Start Address Register Lower Part (DMACDSAL) Field Description
15-0 Field DSAL Value 0000h-FFFFh Description Lower part destination start address (byte address).
Table Destination Start Address Register Upper Part (DMACDSAU) Field Description
15-0 Field DSAU Value 0000h-00FFh 0100h-FFFFh Description Upper part destination start address (byte address). Reserved use).
13.9
Element Number Register (DMACEN) Frame Number Register (DMACFN)
Each channel element number register frame number register, (see Figure Table Table 18). Load DMACFN with number frames want each block. Load DMACEN with number elements want each frame. must have least frame element, have many 65535 each: frame number 65535 element number 65535 DMACEN DMACFN uninitialized after reset.
Figure
Element Number Register (DMACEN) Frame Number Register (DMACFN)
DMACEN ELEMENTNUM R/W-x DMACFN FRAMENUM R/W-x
Legend: Read; Write; Value after reset defined
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Table Element Number Register (DMACEN) Field Description
15-0 Field ELEMENTNUM Value 0000h 0001h-FFFFh Description Reserved use). Number elements frame (1-65535).
Table Frame Number Register (DMACFN) Field Description
15-0 Field FRAMENUM Value 0000h 0001h-FFFFh Description Reserved use). Number frames block (1-65535).
13.10
Element Index Registers (DMACEI/DMACSEI, DMACDEI) Frame Index Registers (DMACFI/DMACSFI, DMACDFI)
single- double-index addressing mode selected separately source destination ports using SRCAMODE bits DSTAMODE bits, respectively, DMACCR (see pages 41). support index addressing modes, there four index registers: source index registers (DMACSEI DMACSFI) destination index registers (DMACDEI DMACDFI). these registers used depends destination index mode chosen with DINDXMD DMAGSCR. When DINDXMD (the default forced reset), compatibility mode selected. original controller design, source destination shared element index register called DMACEI frame index register called DMACFI. When DINDXMD compatible behavior enabled; DMACSEI used DMACEI, DMACSFI used DMACFI. destination index registers used.
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When DINDXMD=1, enhanced mode selected. this mode, source index registers used only source, destination index registers used destination. element frame indexes 16-bit signed numbers, providing following range: -32768 bytes frame index 32767 bytes -32768 bytes element index 32767 bytes element and/or frame index must produce aligned address according data type selected DATATYPE field DMACSDP. data type 32-bit, element/frame index must (where 2,.). data type 16-bit, element/frame index must (where 2,.). type 8-bit, element/frame have value. attempts write index that would cause unaligned address, controller will send error interrupt (BERRINT) request CPU. This occurs even address indexing used. Notes: DMACDEI, DMACDFI, their associated functions supported TMS320VC5509 DSP, they supported TMS320VC5503/5507/5509A/5510 DSPs. Make sure that start address, element index, frame index will produce valid addresses within range port. invalid address generated, time-out error will occur. index addressing mode, make sure that addresses computed controller will match alignment constraint chosen data type. more details, description DATATYPE bits DMACSDP (see page 53). index registers summarized Figure tables that follow figure. element index frame index registers uninitialized after reset.
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Figure
Element Index Registers (DMACSEI, DMACDEI) Frame Index Registers (DMACSFI, DMACDFI)
DMACEI DMACSEI ELEMENTNDX R/W-x DMACFI DMACSFI FRAMENDX R/W-x DMACDEI ELEMENTNDX R/W-x DMACDFI FRAMENDX R/W-x
Legend: Read; Write; Value after reset defined
Table Source Element Index Register (DMACSEI DMACEI) Field Description
15-0 Field ELEMENTNDX Value -32768 32767 Description When DINDXMD DMACSEI used DMACEI; contains element index bytes) both source destination. When DINDXMD DMACSEI contains source element index bytes).
Table Source Frame Index Register (DMACSFI DMACFI) Field Description
15-0 Field FRAMENDX Value -32768 32767 Description When DINDXMD DMACSFI used DMACFI; contains frame index bytes) both source destination. When DINDXMD DMACSFI contains source frame index bytes).
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Table Destination Element Index Register (DMACDEI) Field Description
15-0 Field ELEMENTNDX Value -32768 32767 Description When DINDXMD DMACDEI contains destination element index bytes).
Table Destination Frame Index Register (DMACDFI) Field Description
15-0 Field FRAMENDX Value -32768 32767 Description When DINDXMD DMACDFI contains destination frame index bytes).
13.11
Source Address Counter (DMACSAC) Destination Address Counter (DMACDAC)
progress each channel monitored reading source destination address counters (DMACSAC DMACDAC). DMACSAC shows bits current source address. DMACDAC shows bits current destination address. address counters summarized Figure Table Table DMACSAC DMACDAC uninitialized after reset. Note: DMACSAC, DMACDAC, their associated functions supported TMS320VC5509 DSP, they supported TMS320VC5503/5507/5509A/5510 DSPs.
Figure
DMACSAC
Source Address Counter (DMACSAC) Destination Address Counter (DMACDAC)
R/W-x
DMACDAC R/W-x
Legend: Read; Write; Value after reset defined
SPRU587B
Direct Memory Access (DMA) Controller
Controller Registers
Table Source Address Counter (DMACSAC) Field Description
15-0 Field Value 0000h-FFFFh Description bits current source address.
Table Destination Address Counter (DMACDAC) Field Description
15-0 Field Value 0000h-FFFFh Description bits current destination address.
Direct Memory Access (DMA) Controller
SPRU587B
Revision History
Revision History
This document revised SPRU587B from SPRU587A, which released October 2003. scope this revision limited adding support TMS320VC5503/5507 devices. following changes were made this revision:
Page Global
Added TMS320VC5503/5507 devices.
SPRU587B
Direct Memory Access (DMA) Controller
Index
Index
address counters (DMACSAC, DMACDAC) address updating channel AUTOINIT (auto-initialization bit) DMACCR described table shown figure
DARAM time-out counter enable (DTCE) described table shown figure data burst capability DATATYPE bits DMACSDP described table shown figure destination address counter (DMACDAC) destination addressing mode bits (DSTAMODE) described table shown figure destination burst enable bits (DSTBEN) described table shown figure destination element frame index mode (DINDXMD) described table shown figure destination element index register (DMACDEI) destination frame index register (DMACDFI) destination packing enable (DSTPACK) described table shown figure destination selection bits (DST) described table shown figure destination start address registers (DMACDSAL/U) diagram controller DINDXMD DMAGSCR described table shown figure channel enable (EN) described table shown figure channel start addresses SPRU587B
BLOCK DMACSR described table shown figure block diagram controller block data BLOCKIE DMACICR described table shown figure burst capability
channel context channel control register (DMACCR) channel enable (EN) described table shown figure channel priority (PRIO) described table shown figure channels definition interrupt monitoring start addresses synchronizing updating addresses channels port accesses configuration working registers Direct Memory Access (DMA) Controller
Index
channels definition interrupt monitoring start addresses synchronizing updating addresses DMACCR DMACDAC DMACDEI DMACDFI DMACDSAL DMACDSAU DMACEI DMACEN DMACFI DMACFN DMACICR DMACSAC DMACSDP DMACSEI DMACSFI DMACSR DMACSSAL DMACSSAU DMAGCR DMAGSCR DMAGTCR DROP DMACSR described table shown figure DROPIE DMACICR described table shown figure dropped synchronization events reset, effects controller bits DMACSDP described table shown figure DSTAMODE bits DMACCR described table shown figure DSTBEN bits DMACSDP described table shown figure
DSTPACK DMACSDP described table shown figure DTCE DMAGTCR described table shown figure
effects reset EHPIEXCL DMAGCR described table shown figure EHPIPRIO DMAGCR described table shown figure element index registers (DMACEI/DMACSEI, DMACDEI) element number register (DMACEN) element data emulation mode (FREE) described table shown figure emulation modes DMACCR described table shown figure end-of-programming (ENDPROG) described table shown figure ENDPROG DMACCR described table shown figure event drop interrupt enable (DROPIE) described table shown figure event drop status (DROP) described table shown figure exclusive access (EHPIEXCL) described table shown figure
SPRU587B
Direct Memory Access (DMA) Controller
Index
FRAME DMACSR described table shown figure frame index registers (DMACFI/DMACSFI, DMACDFI) frame number register (DMACFN) frame data frame/element synchronization (FS) described table shown figure FRAMEIE DMACICR described table shown figure FREE DMAGCR described table shown figure DMACCR described table shown figure
index registers interrupt control register (DMACICR) interrupts monitoring channel activity introduction controller
LAST DMACSR described table shown figure last frame interrupt enable (LASTIE) described table shown figure last frame status (LAST) described table shown figure LASTIE DMACICR described table shown figure latency transfers
global control register (DMAGCR) global software compatibility register (DMAGSCR) global time-out control register (DMAGTCR)
monitoring channel activity
HALF DMACSR described table shown figure half frame interrupt enable (HALFIE) described table shown figure half frame status (HALF) described table shown figure HALFIE DMACICR described table shown figure access configurations exclusive access (EHPIEXCL) described table shown figure priority (EHPIPRIO) described table shown figure Direct Memory Access (DMA) Controller
number elements DMACEN number frames DMACFN
ports port accesses position service chain power reduction PRIO DMACCR described table shown figure priority channel (PRIO) described table shown figure priority (EHPIPRIO) described table shown figure priority service chain SPRU587B
Index
reducing power consumed register structure controller registers controller REPEAT (repeat condition) DMACCR described table shown figure reset, effects controller
SRCPACK DMACSDP described table shown figure start address registers destination channel source channel start addresses channel status register (DMACSR) STCE DMAGTCR described table shown figure SYNC DMACSR described table shown figure SYNC bits DMACCR described table shown figure synchronization control bits (SYNC DMACCR) described table shown figure synchronization event drop interrupt enable (DROPIE) described table shown figure synchronization event drop status (DROP) described table shown figure synchronization event status (SYNC DMACSR) described table shown figure synchronization events
SARAM time-out counter enable (STCE) described table shown figure service chain service chain example source address counter (DMACSAC) source addressing mode bits (SRCAMODE) described table shown figure source destination parameters register (DMACSDP) source burst enable bits (SRCBEN) described table shown figure source element index register (DMACSEI) source frame index register (DMACSFI) source packing enable (SRCPACK) described table shown figure source selection bits (SRC) described table shown figure source start address registers (DMACSSAL/U) bits DMACSDP described table shown figure SRCAMODE bits DMACCR described table shown figure SRCBEN bits DMACSDP described table shown figure
time-out error conditions TIMEOUT (time-out status) DMACSR described table shown figure TIMEOUTIE (time-out interrupt enable) DMACICR described table shown figure
SPRU587B
Direct Memory Access (DMA) Controller
Index
units data updating addresses channel
whole block status (BLOCK) described table shown figure whole frame interrupt enable (FRAMEIE) described table shown figure whole frame status (FRAME) described table shown figure
whole block interrupt enable (BLOCKIE) described table shown figure
Direct Memory Access (DMA) Controller
SPRU587B
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