Brian Carlson Vassos Soteriou ABSTRACT This application note describes

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TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
Brian Carlson Vassos Soteriou ABSTRACT This application note describes multimedia audio codec interfaced TMS320C6201/C6701 DSPs. Although this application report uses CS4231A audio codec example, part that obsolete, this application note used reference guide interfacing similar audio codecs TMS320C6000 McBSP. Cirrus Logic offers CS4235 CrystalClear audio device that provides similar functionality CS4231A. Specifically, this application report addresses digital interface between these devices TMS320C6000 DSP, using serial interface audio data transfer parallel interface control status access, referencing CS4231A example device. CS4231A codec's digital audio data directly interfaced DSP's McBSP efficient data transfers that contend DSP's EMIF. codec controlled monitored codec's parallel interface which memory-mapped directly EMIF's asynchronous interface with glue logic. EMIF access codec allows external processor also control monitor DSP's host port interface. application note also identifies other codec digital interface signals that useful some applications. Introduction Serial Interface Timing Codec Registers Registers Parallel Interface Other Interface Signals References List Figures Figure Figure Figure Figure Figure Figure Figure Figure TMS320C6000 Interface CS4231A Multimedia Audio Codec CS4231A 64-bit Enhanced Mode Serial Timing Receive Control Register (RCR) Transmit Control Register (XCR) Sample Rate Generator Register (SRGR) Contrl Register (PCR) Serial Port Control Register (SPCR) CS4231A Parallel Interface Read Timing Enterprises, Inc. Texas Instruments
Trademarks property their respective owners.
SPRA477A
Figure CS4231A Parallel Interface Write Timing Figure EMIF Space Control Register Diagram List Tables Table TMS320C6201 Serial Port CS4231A Codec Timing Analysis Table CS4231A Digital Audio Format Selection Table CS4231A Parallel Interface Parametric Timing
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
SPRA477A
Introduction
TMS320C6000 interface CS4231A multimedia audio codec several ways since codec provides both parallell, serial, interrupt support. most efficient interface method takes advantage CS4231A's serial audio data port which compatible with TMS320C6000 multichannel buffered serial port (McBSP). This interface method provides dedicated path serial audio data that does continuously contend bandwidth DSP's parallel, external memory interface (EMIF). codec's parallel control interface memory-mapped into DSP's EMIF control status access, which used during initialization infrequently during normal operation. separate control interface codec simplifies software driver support. codec driver does have deal with complexities additional memory requirements associated with data control/status information multiplexed single stream. added benefit, memory-mapped codec interface enables external processor control monitor codec through DSP's host port interface (HPI). This direct access codec from host processor provides flexibility that could useful some applications. This application note specifically addresses digital interfaces between codec using serial interface audio data parallel interface control status. Other parallel interface methods possible, they optimal TMS320C6000. analog interface CS4231A, other functional aspects directly related digital interface DSP, within scope this application note. CS4231A data sheet[4] provides extensive information about device should referenced further details. Figure shows digital interfaces between TMS320C6000 CS4231A codec.
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
SPRA477A
CS4231A AUDIO CODEC Serial Interface
SCLK FSYNC SDOUT SDIN A[1:0]
SN74CBTD3384 BUFFER McBSP
TMS320C6000
CLKS CLKR CLKX EXT_INTx
VOLTAGE TRANSLATION
ADDRESS
EA[3:2]
Parallel Interface
D[7:0]
DATA
EMIF VOLTAGE TRANSLATION SN74CBTD3384 BUFFER
3.3V DATA
ED[7:0]
Figure TMS320C6000 Interface CS4231A Multimedia Audio Codec digital interfaces between codec consist serial interface that connects codec DSP's McBSP parallel interface that connects codec EMIF's asynchronous mode. important note that CS4231A device, signals that provides 3.3V must translated using devices such SN74CBTD3384 switches. Signals originating from need translated since their values compatible with codec. codec always generates serial data clock frame sync signals. After voltage translation, serial data clock connected three DSP's McBSP clock pins, which should programmed inputs. Similarly, frame sync signal connected both FSX, which should also programmed inputs. This configuration means that both transmit receive data synchronized with phase alignment.
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
SPRA477A
codec's parallel interface consists 8-bit data bus, 2-bit address bus, chip select, read strobe, write strobe. EMIF's lower eight bits (ED[7:0]) connected codec's data using voltage translation buffer. DSP's EA[3:2] address signals mapped directly codec's A[1:0] address signals, codec registers mapped 32-bit word boundaries with only lower eight data bits being valid. EMIF asynchronous control signals directly connected codec's chip select read/write strobes since EMIF memory space control register programmed with timing characteristics that match requirements codec. optional interrupt connection shown Figure This interrupt connection independent both serial parallel interfaces required codec operation. codec supports active, high-interrupt output that driven from internal 16-bit timer. This interrupt useful some applications independent watchdog timer that connected DSP's EXT_INTx inputs. this interrupt used, DSP's default rising-edge interrupt polarity should used.
Serial Interface
Timing
codec's serial port timing directly compatible with TMS320C6000 McBSP. McBSP designed directly interface with devices such CS4231A audio codec that present serial clock, frame sync data. codec generates serial data clock that operates rate times sample rate. maximum sample rate 48KHz, serial clock 3.072 MHz, which below maximum DSP. codec transitions SDOUT data rising edge SCLK samples SDIN data falling edge, which default operation McBSP. serial data streams, codec's left channel data always before right channel data, most-significant each element transmitted first which compatible with McBSP. Both left right channels' elements always bits wide with actual audio data being left justified element. example, 8-bit companded data would occupy first eight bits. Unused bits output zeros after least-significant bit. codec supports three types serial data formats that used with flexible McBSP. However, codec's default 64-bit enhanced mode serial format recommended, since provides most flexibility without incurring additional overhead. 64-bit enhanced mode serial format directly compatible with McBSP, configured positive frame sync pulses with 1-bit data delay. this mode, each frame data bits. first bits data represent left channel second bits represent right channel. last bits optionally used monitor codec's interrupt, capture enable, playback enable, over-range indicators. application does need extra status information, then number elements phase (frame) just 32-bit word. mono applications, number elements could just 16-bit word. status information needed, 32-bit mode serial format could used. this mode, clock still runs times sample rate, frame consists bits times. However, SCLK SDOUT held during last bits frame. Stopping SCLK compatible with McBSP since clock stopped after bits already transferred. 32-bit mode used example applications TMS320C6201/C6701 EVMs since additional status information required.
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
SPRA477A
serial port timing requirements orders magnitude parameters maximum sample rate (3.072 SCLK), there critical timing parameters serial interface. timing analysis shown Table Table TMS320C6201 Serial Port CS4231A Codec Timing Analysis
CS4231A Timing Requirements (min) SDIN valid SCLK falling (min) SDIN hold after SCLK falling McBSP Timing Requirements tsu(DRV-CKRL)min Setup Time, valid before CLKR(ext) th(CKXL-DRV)min Hold Time, valid after CLKR(ext) tsu(FRH-CKRL)min Setup Time, ext. high before CLKR(ext) th(CKRL-FRH)min Hold Time, ext. high after CLKR(ext) tsu(FXH-CKXL)min Setup Time, ext. high before CLKX(ext) th(CKXL-FXH)min Hold Time, ext. high after CLKX(ext) McBSP Switching Characteristics (tSCLK/2) td(CKXH-DXV)max= (tSCLK/2) td(CKXH-DXV)min= CS4231A Switching Characteristics (tSCLK/2) tPD1(max)= (tSCLK/2) tPD1(min)= tpD1(min) available (tSCLK/2) tPD2(max)= (tSCLK/2) tPD2(min)= (-20) (tSCLK/2) tPD2(max)= (tSCLK/2) tPD2(min)= (-20) UNIT
Figure shows codec's 64-bit enhanced mode serial format.
FSYNC
SCLK SDOUT
zeros
zeros
zeros
Bits Left Data SDIN
Bits Right Data
Bits
Figure CS4231A 64-bit Enhanced Mode Serial Timing
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
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Codec Registers
CS4231A includes four direct access (R0-R3) indirect access (I0-I31) registers that used initialize, control, monitor codec. Only register bits must initialized certain manner order support digital serial interface between codec DSP. following paragraphs this section highlight these specific register bits. Refer CS4231A data sheet details registers them. enable CS4231A codec's serial interface, which expanded mode features, MODE2 MODE register (I12) must initialized This allows access indirect registers 16-31, that required enable configure serial interface. Alternate Feature Enable register (I16) must initialized enable serial port select serial data format. Serial Port Enable (SPE) must enable serial interface. When serial port enabled, digital audio data from ADCs sent SDOUT, audio data from SDIN sent DACs. Serial Format bits (SF1, SF0) should both select default, 64-bit enhanced serial data format. Index Address Register (R0) must before SPE, register bits changed. Playback Data Format (I8) Capture Data Format (I28) registers used select digital audio data format. these registers selects either Mono Stereo data streams. mono mode, left right channels have same data. stereo mode, alternating samples represent left right audio channels. C/L, FMT1 FMT0 bits audio data format shown Table data formats, data always sent first, left-justified each 16-bit element. example, 4-bit ADPCM data would occupy first four bits would followed zeros. Index Address Register (R0) must before C/L, FMT1 FMT1 register bits changed. playback capture bits (PEN/PPIO/CEN/CPIO) Interface Configuration (I9) register should enable codec operation. Other codec registers initialized needed particular application. Table CS4231A Digital Audio Format Selection
FMT1
FMT0
Data Format
Linear, 8-bit unsigned µ-Law, 8-bit companded Linear, 16-bit, comp. A-Law, 8-bit companded RESERVED ADPCM, 4-bit RESERVED RESERVED
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
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Registers
McBSP configuration registers must initialized support serial interface with CS4231A audio codec. There several McBSP register bits, this section only addresses ones that directly related serial interface codec. following serial interface characteristics, relative DSP, must addressed McBSP register bits initialization:
External frame syncs (FSXM=FSRM=0) External serial clocks (CLKRM=CLKXM=0) Positive frame sync polarities (FSXP=FSRP=0) Positive serial clock polarities (CLKXP=0, CLKRP=1) Single phase frames (RPHASE=XPHASE=0) element phase (RFRLEN1=XFRLEN1=0000000b) bits audio channel Most significant first Left-justified with right zero fill (RJUST=10b) 16-bit (Mono) 32-bit (Stereo) element length (For 16-bit mono, RWDLEN1=010b, XWDLEN1=010b; 32-bit stereo, RWDLEN1=101b, XWDLEN1=101b) Companding match selected codec data format (RCOMPAND, XCOMPAND) 1-bit data delay (RDATDLY=01b, XDATDLY=01b)
following steps describe setup DMA, McBSP, interrupts required order. McBSP initialization procedure that uses also discussed application report literature number SPRA488, TMS320C6000 McBSP Initialization. McBSP C6000 should properly initialized before enabled. McBSP already reset state, /XRST /RRST SPCR should equal McBSP configuration registers XCR, RCR, SRGR, PCR, SPCR should then initialized with required parameters shown bulleted points above. Serial Port Control Register (SPCR) should initialized disable frame sync sample rate generators (/FRST=/GRST=0) since these provided codec. channels should hooked interrupt service routines. channel should configured transfer data from codec McBSP. second channel should data transfers from McBSP codec. interrupts that correspond channels that will used service McBSP should then enabled. default mapping channel-complete interrupts following:
channel interrupt channel interrupt channel interrupt channel interrupt
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
SPRA477A
Either should followed: This step should performed used service McBSP. XRST RRST signals should enable serial port. Note that value written SPCR this time should only have reset bits changed remaining fields should have same value Step above. used perform data transfers, should first initialized with appropriate read/write syncs, src/dst addresses their update modes, transfer complete interrupt, other feature suitable application. Lastly, START should set. START state waits synchronization events occur. Then, McBSP should pulled reset. details initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (literature number SPRA488) TMS320C6000 Applications (literature number SPRA529). McBSP transmitter receiver should then enabled (/RRST=/XRST=1) order McBSP reinitialize. above McBSP registers their bit-field values shown Figure through Figure
RPHASE
RFRLEN2
RWDLEN2
RCOMPAND
RFIG
RDATDLY
reserved
RFRLEN1
RWDLEN1
RWDREVRS
reserved
Figure Receive Control Register (RCR)
XPHASE
XFRLEN2
XWDLEN2
XCOMPAND
XFIG
XDATDLY
reserved
XFRLEN1
XWDLEN1
XWDREVRS
reserved
Figure Transmit Control Register (XCR)
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
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GSYNC CLKSP CLKSM FSGM FPER FPER
FWID
CLKGDV
Figure Sample Rate Generator Register (SRGR)
reserved 0x0000 XIOEN RIOEN RSXM FSRM CLKXM CLKRM
CLKS_STAT
DX_STAT
DR_STAT
FSRP
CLKXP
CLKRP
Figure Contrl Register (PCR)
0x00
FRST
GRST-
XIN0
XSYNCERR
XEMPTY-
XRDY
XRST
DXENA
RIN0
RSYNCERR
RFULL0
RRDY
RRST
RJUST
CLKSTP
Figure Serial Port Control Register (SPCR)
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
SPRA477A
Parallel Interface
codec's parallel interface directly compatible with EMIF's asynchronous mode. When EMIF's space configured asynchronous operation, provides high degree programmability shaping accesses. programmable parameters include setup, strobe, hold times. Setup time time between beginning memory cycle activation read (ARE) write (AWE) strobe. Strobe time time between activation deactivation read write strobe. Hold time time between deactivation read write strobe cycle. codec's parallel interface timing defined read cycle timing diagram shown Figure write cycle timing diagram shown Figure Table provides parametric timing indicated timing diagrams.
tCSSU
tCSHD
tRDDV D[7:0] ED[7:0] A[1:0] EA[3:2] tADSU
tDHD1
tADHD
Figure CS4231A Parallel Interface Read Timing
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
SPRA477A
tCSSU
tCSHD
tRDDV D[7:0] ED[7:0] A[1:0] EA[3:2] tADSU
WDSU
tDHD2
tADHD
Figure CS4231A Parallel Interface Write Timing
Table CS4231A Parallel Interface Parametric Timing
Parameter setup falling edge hold from rising edge strobe width falling edge data valid Data hold from rising edge Data valid rising edge Data hold from rising edge Address setup falling edge Address hold from rising edge Symbol tCSSU tCSHD tSTW tRDDV tDHD1 tWDSU tDHD2 tADSU tADHD (ns) (ns)
WRITE SETUP 0101
WRITE STROBE 10010 10010
READ SETUP 0101
WRITE HOLD MTYPE010
reserved
READ STROBE 10010
READ HOLD
Figure EMIF Space Control Register Diagram
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
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start asynchronous EMIF access codec's parallel interface begins with asserting chip enable (CE0#) memory space. codec setup requirements prior falling edge read write data strobe. chip select must least address must setup least before data strobe's falling edge. Since EMIF CE0# address signals transition same CLKOUT1 edge, worst case setup time that This time period defines asynchronous setup time that should programmed CE0# memory space control register which located address 0x01800008. Assuming clock MHz, with CLKOUT1 period read write setup fields this control register should codec requires minimum read write data strobe period least This means that read write strobe fields control register should 0x12 (10010b). During read access, codec register data available after maximum into strobe period. This means that there data setup DSP, which easily meets setup requirement. codec's data hold time minimum after rising edge read strobe. Since rising edge read strobe after edge that samples data, this problem. During write access, codec requires that data least before rising edge write strobe. Since provides valid data beginning memory cycle writes, there approximately setup time. codec requires that write data held least after rising edge write strobe. Since holds data valid until hold period, length hold period must least codec's chip select does have held past rising edge read write data strobe. However, address signals must held least after data strobe's rising edge. worst-case hold time therefore, defined write data hold time MHz, this means that read write hold fields control register should (011b). codec timing parameter, shown timing diagrams important note, that there must least between rising edge read write strobe next falling edge read write strobe. This means that codec accesses need controlled, either hardware software, application would ever attempt perform sequential register accesses codec. hardware approach simple increasing setup strobe periods EMIF memory space control register clocks respectively. MHz, this total clocks between data strobe beginning next would meet requirement. more elaborate solution would programmable logic manage codec interface signals ensure that back-to-back accesses meet minimum time period. This solution required anyway, additional asynchronous devices were required same memory space. software approach would require delay inserted between codec accesses ensure that requirement met. codec cannot allocated asynchronous EMIF memory space, such CE0#, coexist with other asynchronous devices using programmable logic, which manages codec interface signal timing provides required ready (ARDY) signal generation. This approach taken TMS320C6201/6701 since multiple devices, including daughter board interface, coexist asynchronous interface. When multiple asynchronous devices with different timing requirements design, programmable logic required handle these timing differences through ARDY signal.
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
SPRA477A
Other Interface Signals
There other codec signals independent from serial parallel interfaces that could interfaced some applications. mentioned previously, codec's interrupt output interfaced DSP's external interrupt inputs. codec provides on-chip timer that used independent timing source watchdog timer. codec's power-down (/PDWN) input controlled disable device into low-power mode. codec provides general-purpose output signals (XCTL1/XCTL0) that controlled writes codec's Control (I10) register.
References
TMS320C6201 Data Sheet, Texas Instruments, SPRS051G January 1997, revised November 2000. TMS320C6000 Peripherals Reference Guide, Literature Number SPRU190D, February 2001. CS4231A Parallel Interface, Multimedia Audio Codec Data Sheet, Crystal Semiconductor, September 1994. TMS320C6201/C6701 Evaluation Module Reference Guide, SPRU269D, December 1998.
TMS320C6201/6701 EVM: TMS320C6000 McBSP Multimedia Audio Codec Interface
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Brian Carlson Vassos Soteriou ABSTRACT This application note describes

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