Clay Turner Muhammad Haque ABSTRACT This document describes features o
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Using Bootloader
Clay Turner Muhammad Haque ABSTRACT This document describes features on-chip bootloader provided with digital signal processor (DSP). Included descriptions each available boot modes interfacing requirements associated with them well instructions generating boot table. C5000 Applications
Contents Introduction Bootloader Features On-Chip Description Bootloader Operation Bootloader Initialization Boot Mode Selection Boot Mode Options 2.3.1 Direct Execution From External Asynchronous Memory 2.3.2 Parallel EMIF Boot Mode 2.3.3 EHPI Boot Mode 2.3.4 Standard Serial Boot Mode 2.3.5 EEPROM Boot Mode 2.3.6 EEPROM Boot Mode (VC5503/VC5507/VC5509/VC5509A Only) 2.3.7 Boot Mode Behavior Boot Table 2.5.1 Resources Used Bootloader 2.5.2 Boot Table Structure 2.5.3 Register Configuration Delay During Boot 2.5.4 Code Data Sections Boot Table 2.5.5 Creating Boot Table References List Figures Figure Figure Figure Figure EHPI Wait Flag Entry-Point Address McBSP0 Receive Data Format Bootload (16-bit shown) Latency Boot Table Programmed Delays Signal Connections EEPROM Boot Mode
Trademarks property their respective owners.
SPRA375D
Figure EEPROM Mode Transfer Protocol With 16-Bit Addresses Figure EEPROM Mode Transfer Protocol With 24-Bit Addresses Figure Signal Connections EEPROM Boot Mode Figure Reading First Byte 64Kbyte Block Figure Current Address Read Command Figure Boot Table Structure List Tables Table Table Table Table Memory Bootloader Initialization Boot Mode Selection Options Boot Mode Types Conversion Utility List Examples Example Example Creating Boot Table Application my_app.out Boot From 16-Bit External Asynchronous Memory Creating Boot Table Application my_app.out Boot From 8-Bit Standard Serial Mode
Introduction
This section provides description features on-chip bootloader provided with digital signal processor (DSP). references this document VC5503/VC5507/VC5509/VC5509A refer both unless otherwise specified.
Bootloader Features
VC5503/VC5507/VC5509/VC5509A bootloader used transfer code from external source into internal external program memory following power-up. This allows code reside slow non-volatile memory externally, transferred high-speed memory executed. accommodate different system requirements, VC5503/VC5507/VC5509/VC5509A offers variety different boot modes. following list different boot modes implemented bootloader, summary their functional operation:
Boot from Enhanced Host Port Interface (EHPI) code executed loaded into on-chip memory external host processor EHPI following reset. Code execution begins when host indicates that application been loaded. EHPI boot performed with EHPI, configured multiplexed non-multiplexed. operation this mode described section 2.3.3.
Parallel EMIF boot from 16-bit external asynchronous memory
Using Bootloader
SPRA375D
bootloader reads boot table from external memory interface (EMIF), configured asynchronous memory. boot table contains code data sections loaded, destination addresses each sections, execution address once loading completed, other configuration information. operation this mode described section 2.3.2.
Standard serial boot through McBSP0 16-bit supported) bootloader receives boot table from McBSP0, operating standard mode, loads code according information specified boot table. operation this mode described section 2.3.4.
EEPROM serial boot though McBSP0 bootloader receives boot table from McBSP0 operating mode, loads code according information specified boot table. data received from SPI-format serial EEPROM, from another SPI-compliant serial port. bootloader supports EEPROMs based 24-bit addresses. operation this mode described section 2.3.5.
Universal Serial (USB) boot bootloader receives boot table through on-chip peripheral. protocol supported conforms standard data loaded bulk end-point. operation this mode described section 2.3.7.
Bootloading from interface boot loader reads boot table from slave device (EEPROM) loads code according information specified boot table.
bootloader also offers following features:
Pin-controlled boot mode selection subset general-purpose input/output (I/O) pins used select boot mode. boot mode selection process discussed section 2.2.
Selectable entry point desired entry point (the first address execution after boot load complete) programmable, stored boot table. boot table discussed section 2.5.
Port-addressed register configuration during boot Port-addressed registers (such those used control peripherals) configured during boot load, providing ability modify clock generator, reconfigure EMIF strobe timings, preset peripheral register values. address contents register modified contained boot table. This capability discussed section 2.5.3.
Programmable delay during boot Programmable delays 65535 clock cycles added during register configuration process, ensure that configurations complete before boot process continues. This capability discussed section 2.5.3.
Using Bootloader
SPRA375D
On-Chip Description
VC5503/VC5507/VC5509/VC5509A, on-chip contains several factory-programmed sections including:
Bootloader program (described this document) 256-word sine look-up table, consisting signed integers representing degrees. Factory test code, used testing device. Interrupt vector table.
memory shown Table Table Memory
Starting Byte Address FF_0000h FF_8000h FF_FA00h FF_FC00h FF_FF00h FF_FFFCh
Contents bootloader components Main bootloader code Sine table Factory test code Interrupt vector table code
bootmode option available VC5503
Bootloader Operation
following sections describe structure operation production VC5503/VC5507/VC5509/VC5509A bootloader.
Bootloader Initialization
When VC5503/VC5507/VC5509/VC5509A bootloader begins execution, program performs some initialization VC5503/VC5507/VC5509/VC5509A prior loading code. VC5503/VC5507/VC5509/VC5509A resources that configured bootloader described Table
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SPRA375D
Table Bootloader Initialization
Resource Stack registers Initialization Value data stack register (SP) initialized address 000090h, system stack register (SSP) initialized address 000080h. stack configuration default mode 32-bit stack, with slow return. INbit Status Register (ST1_55) default value disable interrupts. words reserved temporary storage entry-point address 000060h 000061h. SXMD Status Register (ST1_55) cleared disable sign-extension mode. After bootloader copies sections, SXMD back before execution transferred application. 54CM Status Register (ST1_55) enable compatibility mode during after bootload.
Stack configuration Interrupts
Memory-mapped registers Sign extension
Compatibility mode
After initialization performed, bootloader loads on-chip according boot mode selected, then causes VC5503/VC5507/VC5509/VC5509A begin execution loaded code. that point, bootload process complete. Whenever system reset, VC5503/VC5507/VC5509/VC5509A starts execution bootloader again, entire bootload process repeated. remaining sections this document describe various boot modes boot tables detail.
Boot Mode Selection
desired boot mode selected setting four boot mode select pins BOOTM[0:3]. These pins sampled after reset when bootloader program begins execution. BOOpins shared with general-purpose (GPIO) pins.
BOOTM3 shared with IO0. BOOTM2 shared with IO3. BOOTM1 shared with IO2. BOOTM0 shared with IO1.
Another GPIO pin, IO4, used output handshaking purposes some boot modes. Although this involved boot-mode selection, should aware that this will become active output during bootload process, should design accordingly. After bootload complete, loaded application change function IO[4:0] pins. available boot mode options their corresponding BOOpin configurations shown Table Some configurations reserved addition future boot modes, should selected.
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SPRA375D
Table Boot Mode Selection Options
BOOTM[3:0] IO.0 IO.3 IO.2 IO.1 VC5503 Device(s) VC5507/ VC5509A VC5509 Boot Source Reserved Serial EEPROM (SPI 24-bit address) boot from McBSP0 EEPROM Reserved EHPI (multiplexed mode) boot EHPI (non-multiplexed mode) boot Reserved Execute from 16-bit external asynchronous memory Serial EEPROM (SPI 16-bit address) boot from McBSP0 Parallel EMIF boot (8-bit asynchronous memory) Parallel EMIF boot (16-bit asynchronous memory) Reserved Reserved Standard serial (16-bit data) boot from McBSP0 Standard serial (8-bit data) boot from McBSP0 2.3.4 2.3.4 2.3.1 2.3.5 2.3.2 2.3.2 2.3.3 2.3.3 2.3.5 2.3.7 2.3.7 Section
NOTE: boot mode selections that require BOOTM3 (IO0) reset, will configure external parallel port EHPI mode, EMIF mode. boot external memory desired these modes, external parallel port mode must back Full EMIF mode during bootload. This achieved using register configuration capability bootloader (see section 2.5.3). this capability configure External Selection Register (EBSR). following statement added conversion utility command line command file: -reg_config 0x6C00, 0x0001 Also include other register configurations required EMIF mode desired. also necessary insert delay (using -delay statement) allow EMIF configuration become active before bootloader begins writing Refer section 2.5.3 more information.
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SPRA375D
2.3.1
Boot Mode Options Direct Execution From External Asynchronous Memory
When BOOTM[3:0] 1000b reset, direct execution option selected. this mode, bootloader configures EMIF 16-bit asynchronous memory then transfers control external code beginning byte (program) address 0x400000. code this location should executable code, boot table. accommodate slow memory, bootloader configures EMIF maximum timings READ SETUP, READ STROBE, READ HOLD, READ EXTENDED HOLD parameters.
2.3.2
Parallel EMIF Boot Mode
Parallel EMIF Boot Mode selected when BOOTM[3:0] 1010b 1011b after reset. this mode bootloader reads boot table from 16-bit external asynchronous memory. 8-bit 16-bit data width configured based selected mode, cannot changed during boot process. Parallel EMIF mode begins reading boot table word address 200000h, which located space. external memory containing boot table must start this location. execution entry point contained boot table programmable. When this boot mode initiated, programmable timings EMIF following:
READ SETUP cycles (1111b). READ STROBE cycles (111111b). READ HOLD cycles (11b). READ EXTENDED HOLD cycle (01b).
READ SETUP, READ STROBE, READ HOLD their most conservative setting assure interface wide range memory speeds. However, this default setting proves slow cycles access), these EMIF timings modified using port-addressed register configuration feature discussed section 2.3.2. These timing parameters controlled EMIF Space Control Register (CE1_1). more information EMIF effects these parameters, TMS320C55x Peripherals Reference Guide (SPRU317). aware that changing timing parameters EMIF during boot process cause bootload fail. external space must maintained asynchronous memory, with same data width original boot mode chosen. When reconfiguring CE1_1, write value MTYPE that matches original boot mode selected. Modifications EMIF control registers also have some latency before becoming active. bootloader should make read requests EMIF while configuration changing, entry boot table that reconfigures EMIF should followed delay less than cycles, allow EMIF configuration complete. Also, remember that using register configuration feature change clock generator frequency will change memory timings generated EMIF, since they cycle-based. Carefully verify that clock EMIF configurations being programmed will produce memory timings compatible with external memory used.
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SPRA375D
During this boot mode, will beginning boot process. will high during execution programmable delay feature boot table. When delay completed, will again. bootload, will high will begin execution entry-point address. necessary memories, used handshaking signal some other source generating data EMIF. ARDY goes during bootload, will stall until ARDY high (ready) again. target system does drive ARDY, should pulled high.
2.3.3
EHPI Boot Mode
description this section assumes familiarity with VC5503/VC5507/VC5509/VC5509A EHPI. detailed information TMS320C55x EHPI refer TMS320C55x Peripherals Reference Guide (SPRU317) application report Using TMS320VC5509/VC5510 Enhanced (SPRA741). EHPI boot multiplexed mode selected when BOOTM[3:0] 0101b reset. EHPI boot non-multiplexed mode selected when BOOTM[3:0] 0110b reset. After reset, bootloader will configure VC5503/VC5507/VC5509/VC5509A support EHPI boot multiplexed non-multiplexed mode depending state BOOpins. When EHPI configured, goes indicate that device ready receive data from host. lieu monitoring IO4, host wait cycles after reset released, before beginning transfers through EHPI. EHPI boot mode, external host load code data directly into memory while waits. EHPI boot does boot table. code and/or data sections directly loaded desired locations host. When EHPI finished loading application, signals begin execution, begins executing specified entry point. During normal operation VC5503/VC5507/VC5509/VC5509A, host access area memory below word address 004000h. This space includes internal DARAM blocks 0-3. Because some DARAM memory used bootloader code itself, recommended that memory image loaded through EHPI limited word-address range 000100h-003FFFh (16,128 bytes total). entry point byte address where execution application will begin. entry point stored DARAM word addresses 0060h 0061h, shown Figure most significant word stored 0060h, least significant word stored 0061h. least significant bits form byte address entry point. most significant bits used signal when start executing entry-point specified bits. will continue loop, monitoring high bits, long they remain zeroes. This allows EHPI time load desired code data sections. When host completed loading application, writes entry point byte address non-zero wait flag value word addresses 0060h 0061h, shown Figure When non-zero value detected wait flag, will branch byte address specified bits, begin execution loaded application. Remember that EHPI host addresses word-addressed, while program fetches byte-addressed. example, load section code executed from byte address 2000h, EHPI will load section word address 1000h.
TMS320C55x trademark Texas Instruments.
Using Bootloader
SPRA375D Word address 0060h Word address 0061h
8-bit wait flag
24-bit entry point address
Figure EHPI Wait Flag Entry-Point Address Since will transfer control application soon detects non-zero value wait flag, address 0060h (the MSW) should written after address 0061h (the LSW). general procedure boot loading using EHPI
RESET released (low-to-high transition) with BOOTM[3:0] 0101b 0110b selecting desired mode. host loads desired code data sections into internal memory within address limits mentioned above. host writes word address 0061h, with least significant bits desired 24-bit entry-point address. host writes word address 0060h, with most significant bits desired 24-bit entry-point address bits 7-0, non-zero value bits 15-8. will then transfer execution (branch) previously specified entry-point address, begin running application.
event that application been previously loaded another reset necessary (warm boot), necessary host reload application. host simply rewrite entry point wait flag after bootloader begins execution (IO4 goes low). peripheral register reconfiguration delay features available during EHPI since these features associated with boot table.
2.3.4
Standard Serial Boot Mode
description this section assumes familiarity with McBSP. detailed information C55x McBSP refer TMS320C55x Peripherals Reference Guide (SPRU317). Standard serial boot mode loads boot table from McBSP0 either 8-bit 16-bit mode, selected BOOpins. McBSP0 receiver configured bootloader, with following parameters:
Single phase (RPHASE= word frame (RFRLEN1 0000000b) Word length bits (RWDLEN1 000b 8-bit mode, 010b 16-bit mode). Data right-justified (RJUST 00b), with cycle delay (RDATDLY 01b) first relative FSR.
C55x trademark Texas Instruments.
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SPRA375D
Receive clock (CLKR0) receive frame sync (FSR0) generated externally.
expected receive data format implied this configuration shown Figure (16-bit shown). serial port sending data must conform this data format.
CLKR0 FSR0
Figure McBSP0 Receive Data Format Bootload (16-bit shown) When standard serial boot mode selected, bootloader configures McBSP0 described above, then drives low, indicate sender that ready receive (approximately cycles after bootloader begins execution). frame sync associated with each word byte) exchanged. following conditions must order insure proper operation:
serial port receive clock externally supplied CLKR0 should exceed frequency VC5503/VC5507/VC5509/VC5509A clock. Appropriate delay should provided between transmission each word, prevent receiver overflow. This achieved either slowing down receive clock frequency, providing additional serial port clock cycles between transmitted words.
sender provides words boot table McBSP0, responds handshaking signal indicate state boot. When serial port ready receive another word, goes low. When serial port process copying received word memory when programmed delay progress, high, only goes again when serial port ready receive another word. overflow receiver will cause bootload fail. There basic options managing rate words sent serial port prevent overflow: handshaking signal, allow sufficient time between transmissions prevent overflow. 2.3.4.1 Using Prevent Receiver Overflow
mentioned previously, goes when receiver ready receive word goes high when some other transaction progress. This signal polled indicator when serial port ready and, therefore, used directly prevent overflow. There some latency response after word been received, shown Figure latency associated with interaction serial port bootloader code that interprets boot table, copies data initiates delays. From point view sender, will respond indicate delay progress approximately cycles after last word received. This latency accounted automatically serial port clock operated clock frequency slower.
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SPRA375D
does high after every word received. 8-bit mode, will high after every four bytes, depending whether part boot table being received 16-bit 32-bit object. 16-bit mode, will high after each word (for 16-bit objects) after every words (for 32-bit objects). Polling provides automatic method account delays bootload process programmed delays access delays associated with EMIF (such programmed strobe timings ARDY delays).
FSR0 response latency cycles Receiver ready cycles* cycles Receiver ready
Figure Latency Boot Table Programmed Delays 2.3.4.2 Preventing Receiver Overflow Without Polling
monitored, then appropriate delays must inserted between transmitted words prevent receiver overflow. When destination boot table contents internal memory, time when receiver ready approximately cycles after reception word shown Figure sender should allow least this much time between transmitted words destined internal memory DSP. programmed delay feature used, additional time must included accommodate extra delay. Similarly, destination code data external memory, sender must allow additional time allow memory conditions. example, assume destination section code external asynchronous memory with following conditions:
WRITE SETUP cycles. WRITE STROBE cycles. WRITE HOLD cycles. WRITE EXTENDED HOLD cycle.
additional cycles (2+5+2+1) will necessary each word moved. time between transmission words should less than cycles. Since delay terms cycles (not serial port clock cycles), required timing inserting additional serial port clock cycles between transmitted words, slowing down serial port clock relative clock, both. Since delay after reception each word byte) same, must select word byte) rate that accommodates worst-case delay. When boot table received, will driven high, will branch execution entry point specified boot table, begin execution.
Using Bootloader
SPRA375D
2.3.5
EEPROM Boot Mode
description this section assumes familiarity with McBSP operation using clock-stop mode. detailed information C55x McBSP, refer TMS320C55x Peripherals Reference Guide (SPRU317). VC5503/VC5507/VC5509/VC5509A bootloader supports boot from EEPROMs device operating slave that emulates appropriate format. bootloader supports EEPROMs based 16-bit byte addresses bytes) mode BOO= 1001b. bootloader supports EEPROMs based 24-bit byte addresses bytes) mode BOO= 0001b. EEPROM boot mode, acts master, memory acts slave. minimum connection required between McBSP0 EEPROM shown Figure CLKX0 master clock driving EEPROM signal. EEPROM boot mode, CLKX0 period (DSP input clock period). transmits data EEPROM serial data input (SI) signal. receives data from EEPROM serial data output (SO) signal. used operate EEPROM chip select (CS) signal. will automatically enable EEPROM when bootload ready begin, will disable EEPROM when bootload complete. Some serial EEPROMs additionally provide write-protect (WP) HOLD signals. Write-protect prevents external device from writing internal memory registers EEPROM. Since bootloader only performs reads EEPROM, state writeprotect function relevant. used, pulled inactive (high). HOLD input used suspend serial input EEPROM. Having this active will prevent bootloader from operating correctly. HOLD present) should pulled inactive (high).
TMS320VC5503/V C5507/VC5509/ VC5509A CLKX0 EPROM
HOLD
High High
present
Figure Signal Connections EEPROM Boot Mode bootloader reads boot table from EEPROM sequential block data. does perform random accesses. 16-bit EEPROM mode, format beginning transfer shown Figure
Using Bootloader
SPRA375D IO4/CS CLKX0/CLK DX/SI DR/SO
READ instruction (03h)
Byte address
Data
Figure EEPROM Mode Transfer Protocol With 16-Bit Addresses process begins with driving (EEPROM CS). Then issues READ instruction (03h) EEPROM, followed starting byte address, which will always address zero. EEPROM responds sending data bytes back DSP. does resend address each byte, depends ability serial EEPROM automatically increment address internally. continues read bytes sequentially from EEPROM until entire boot table been transferred. Then drives high, disable EEPROM chip select, bootloader branches beginning loaded application, begin execution. process identical 24-bit address mode except initial address transmitted EEPROM bits instead shown Figure either these modes, boot table must programmed into EEPROM single, continuous image starting EEPROM address zero.
IO4/CS CLKX0/CLK DX/SI DR/SO
READ instruction (03h)
Byte address
Data
Figure EEPROM Mode Transfer Protocol With 24-Bit Addresses Although Figure Figure show address data being continuous, there gaps between READ instruction, address, subsequent data bytes. Since master, will only operate clock when ready next byte, user intervention required accommodate delays during bootload.
Using Bootloader
SPRA375D
2.3.6
EEPROM Boot Mode (VC5503/VC5507/VC5509/VC5509A Only)
description this section assumes familiarity with operation using master receiver master transmitter modes. detailed information I2C, consult TMS320VC5501/VC5502/VC5509 Inter-Integrated (I2C) Module Reference Guide (SPRU146). VC5503/VC5507/VC5509/VC5509A bootloader supports boot from EEPROM Slave devices emulating EEPROM behavior. bootloader following requirements EEPROM:
memory device complies with Philips Specification v2.1 responds slave address 50h. memory device uses bytes bytes) internal addressing. memory device capability auto-increment internal address counter such that contents memory device read sequentially.
boot mode, acts master EEPROM acts slave. connection required between VC5503/VC5507/VC5509/VC5509A EEPROM shown Figure required pull-ups depends number devices sharing bus. Consult Philips Specification details pull-ups requirements. Normally shared only EEPROM, pull-ups should work.
Pull-up VC5503/VC5507/ VC5509/VC5509A EEPROM High
Address
Present
Figure Signal Connections EEPROM Boot Mode Some EEPROMS have write-protect (WP) feature that prevents unauthorized writes memory. This feature neded bootloading purposes since only reads data from EEPROM. write-protect feature enabled disabled without impacting bootloader operation. VC5503/VC5507/VC5509/VC5509A operating frequency calculated using following formula: (High) (DSP input clock period) (Low) (DSP input clock period) CLKIN frequency less should chosen that frequency greater than since that maximum speed supported module.
Using Bootloader
SPRA375D
boot process begins with using random read command read address zero EEPROM. random read command, shown Figure consists dummy write command with address zero, immediately followed current address read command. EEPROM responds sending data byte DSP. depends ability EEPROM automatically increment address internally read subsequent bytes. subsequent bytes read using current address read command shown Figure
Activity: Line Activity: EEPROM Start Slave Address Word Address Word Address Start Slave Address Stop
Data
Figure Reading First Byte 64Kbyte Block
Start Slave Address Data Stop
Figure Current Address Read Command stops requesting data when first zero-length memroy section encountered boot table. data bytes will processed accordance with boot table description given later this document. bootloader flags start boot mode setting GPIO4 during random read operation. GPIO4 then high during rest read operations. module remains enabled (but activities) boot process, until user's application turns module off.
2.3.7
Boot Mode
boot mode selected when BOOTM[3:0] 0010b after reset. Detailed information boot mode available Using TMS320VC5507/VC5509/VC5509A Bootloader (SPRA840).
Behavior
VC5503/VC5507/VC5509/VC5509A bootloader, configured output used multiple functions, depending boot mode selected indicated below:
standard serial-boot-mode modes, used indicate that serial port ready receive data. programmed delay occurs, ready (high) until delay completed, then ready (low) when serial port ready receive again. also
Using Bootloader
SPRA375D
goes ready while data being moved. used handshaking signal prevent receiver overflow.
external asynchronous memory boot modes, goes beginning boot process only goes high during programmed delays, indication delay. When bootload complete, goes high. serial EEPROM boot modes, used chip select (CS) signal serial EEPROM. goes beginning boot process, goes high when boot process complete. does change during delays this mode, since master, delays handled automatically. EEPROM boot mode, toggled indicate beginning activity.
Boot Table
boot table block data that contains code data sections loaded bootloader well other information including entry point address, register configurations, programmable delays. boot table created conversion utility standard component TMS320C55x Assembly Language Tools), based common object file format (COFF) output linker application code. conversion utility provides several output options, such industry-standard ASCII formats that used program parallel serial EEPROMs, formats that used code host transmit boot table DSP. more detailed description role hex-conversion utility creating boot table covered later.
2.5.1
Resources Used Bootloader
bootloader program uses several internal resources during entire boot process. These resources reserved bootloader should altered until bootload completed, bootloader passed control loaded application code. following resources used bootloader:
Accumulators: Auxiliary registers: Temporary registers:
AC0, AC1, AC2, XAR5, XAR6
entry-point address stored word addresses 0060h 0061h. stack pointer (SP) located word address 0090h. system stack pointer (SSP) located word address 0080h.
avoid corruption these memory locations, sections contained boot table should contain destinations lower than word address 0100h (byte address 0200h).
2.5.2
Boot Table Structure
boot table specific format that independent boot mode chosen contains information relating program sections, data sections other information used bootloader. components boot table shown Figure
Using Bootloader
SPRA375D Byte address Byte address Byte address Byte address
32-bit entry point address Byte address Byte address 32-bit register configuration count 16-bit register address 16-bit delay indicator 16-bit register contents 16-bit delay count Repeated according count Repeated according count
32-bit section byte count 32-bit section byte start address Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Repeated each section
32-bit zero byte count (end boot table)
Figure Boot Table Structure description each component boot table given below:
32-bit Entry-Point Byte Address address where bootloader will begin execution after application loaded. 32-bit Register Configuration Count number registers configured, delays implemented, during bootload process (see section 2.5.3). following four components only included boot table register configuration count non-zero. 16-bit Register Address, register configured 16-bit Register Contents contains value programmed above register. 16-bit Delay Indicator (FFFFh) indicates delay will implemented. 16-bit Delay Count contains number cycles delay.
2.5.3
32-bit Section Byte Count contains number bytes copied current section. 32-bit Section Start Byte Address destination address current section. Data Bytes actual data section copied. 32-bit Zero Byte Count (00000000h) indicates boot table.
Register Configuration Delay During Boot
VC5503/VC5507/VC5509/VC5509A bootloader supports feature that allows peripheral port-addressed registers configured during boot process before code data sections copied. This feature provides capability change device mode specific purposes, such changing clock generator frequency speed boot process) configuring EMIF external memory spaces. register configuration entry will added boot table when option "-reg_config address, data" added command line conversion utility when boot table created. this option, address port address register configured, data data that will written register. example, program VC5503/VC5507/VC5509/VC5509A clock mode register (CLKMD port address 1C00h) with value following option would added utility command line: -reg_config 0x1C00, 0x0000 ;write 0000h port address 1C00h
Using Bootloader
SPRA375D
conversion utility will 32-bit entry boot table containing this information. first bits port address, second bits contents written that address. Multiple register configurations included boot table, will added each -reg_config reference command line command file). Since some configurations device have some latency before becoming active, delay feature also available that delay boot process until configuration changes valid. delay implemented similar manner. option "-delay_count" added utility command line generate delay. delay_count value between 65535, represents number cycles wait before bootloader proceeds with boot process. delay option will 32-bit entry boot table, which first bits FFFFh, second bits delay count. Since this same format register configuration feature, bootloader will always interpret reference port address FFFFh request delay, next bits delay count. Some examples where inserting delays useful are:
Changing clock generator delay stall boot process until clock generator locked frequency running appropriate speed.
Configuring EMIF memory type timings necessary change configuration EMIF external spaces, delay used wait until changes have become valid, EMIF ready operate.
bootloader reserved port address FFFFh delay feature, reserved port addresses FFF0h-FFFEh future features. These port addresses cannot used register configuration feature. port address FFFFh used, will interpreted delay. Only port addresses below FFEFh will interpreted register configurations. Note that bootloader provides protection with regard programmed register contents specified these features. responsibility user configure register values correctly. Altering peripheral registers that associated with bootloader cause bootload fail. Some guidelines register configuration during boot given below:
serial boot modes used, alter configuration registers associated with McBSP0. EMIF boot modes used, alter configuration registers associated with EMIF space. This space where boot table located, reconfigured, ability bootloader read rest boot table fail. programmable memory timings space altered, should carefully consider effect changes memory timing ability bootloader continue read memory. Changing memory timing space speed boot process, also cause boot fail changed incorrectly. MTYPE space should never changed. clock generator reconfigured, think carefully about timing effects boot process. Changing clock frequency will change EMIF timings (since EMIF timings relative clock), cause interface timings that incompatible with external memory used. Frequency changes also affect whether serial port timing
Using Bootloader
SPRA375D
provided externally still meets data sheet bootloader requirements. Consider these issues very carefully before making changes. conversion utility will automatically count number register configurations delays specified command line command file), will insert this information boot table. register configurations delays will inserted boot table (and executed bootloader) order they specified conversion utility command line command file. Once configurations have been completed during bootload, bootloader will proceed copying code data sections.
2.5.4
Code Data Sections Boot Table
Code data sections inserted into boot table automatically conversion utility. conversion utility uses information embedded linker .out file, determine each section's destination address length. Adding these sections boot table requires special intervention user. conversion utility will initialized sections application boot table. remaining information included this section describes format sections boot table. C55x architecture, program sections byte-addressed, have variable widths bytes), start and/or byte boundaries. Data sections word-addressed, always start word boundaries. accommodate these types sections, boot table will program sections temporarily align sections start word boundaries. This structure causes bootloader code simpler execute more quickly. These added "pad bytes" affect content sections, their address alignments, because bootloader code strips bytes before writing sections their destinations. However, user reads output conversion utility, bytes will present. program section starts even byte address, byte added beginning section. program section starts byte address, byte added beginning section. program section ends even byte address, byte added section. program section ends byte address, byte added beginning section. Because this structure boot table, sections included boot table must contain least bytes. Each section added boot table with same format. first entry 32-bit count representing length section bytes. next entry 32-bit destination address. This address where first byte section will copied. Although these entries reserve bits boot table alignment, destination address byte count will exceed bits, since address range VC5503/VC5507/VC5509/VC5509A limited bits. remainder section boot table contains actual program data information that section. bootloader will continue read copy these sections until encounters section whose byte count zero. This indication boot table, bootloader will branch entry-point address (specified beginning boot table), begin execution application.
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SPRA375D
2.5.5
Creating Boot Table
create boot table, proceed through following steps: conversion utility (HEX55.exe) revision 2.10 later. Earlier versions support boot table features correctly. -boot option, cause conversion utility create boot table. -v5510:2 option. Even though this option refers TMS320C5510, applies VC5503/VC5507/VC5509/VC5509A also. This option very important since some early versions C55x conversion utility supported different boot table format. wrong boot table format will cause bootloader fail. Specify boot type -parallel8, -parallel16, -serial16 -serial8. Table shows correct option select each supported boot mode. EHPI boot mode does require boot table. Specify entry point using entry_point_address option. entry point address which bootloader will transfer execution when boot load complete. Specify desired output format. TMS320C55x Assembly Language Tools User's Guide (SPRU280) detailed information available conversion utility output formats. Specify output filename using output_filename option. specify output filename, conversion utility will create default filename based output format. Table Boot Mode Types Conversion Utility
BOOTM[3:0] 0001 0010 1001 1011 1110 1111
Boot Mode Source Serial EEPROM (SPI) Boot from McBSP0 supporting 24-bit address Serial EEPROM (SPI) Boot from McBSP0 supporting 16-bit address External Asynchronous Memory (16-bit) Standard Serial Boot from McBSP0 (16-bit) Standard Serial Boot from McBSP0 (8-bit)
Include this option -serial8 -serial8 -serial8 -parallel16 -serial16 -serial8
Example Example showing conversion utility options create boot table, shown below.
Using Bootloader
SPRA375D
Example
Creating Boot Table Application my_app.out Boot From 16-Bit External Asynchronous Memory
create boot table application my_app.out with following conditions:
Desired boot mode from 16-bit external asynchronous memory. registers will configured during boot. programmed delays will occur during boot. Desired output TI-Tagged format, file called my_app.hex.
following options conversion utility command line command file:
-boot -v5510:2 -parallel16 my_app.hex my_app.out Option create boot table C55x boot table format TMS320VC5509 Boot mode 16-bit external asynchronous memory Desired output format TI-Tagged Specify output filename Specify input file
Example
Creating Boot Table Application my_app.out Boot Mode From 8-Bit Standard Serial Mode
create boot table application my_app.out with following conditions:
Desired boot mode from 8-bit standard serial boot Configure CLKMD register (port address 0x1C00) with value 0x2180 After CLKMD register configured, wait cycles before continuing boot Desired output Intel format file called my_app.io.
following options conversion utility command line command file:
-boot -v5510:2 -serial8 -reg_config 0x1c00, 0x2180 -delay 0x100 my_app.io my_app.out Option create boot table C55x boot table format TMS320VC5509 Boot mode 8-bit standard serial boot Write 0x2180 register address 0x1C00 Delay clock cycles Desired output format Intel format Specify output filename Specify input file
detailed information about C55x conversion utility, TMS320C55x Assembly Language Tools User's Guide (SPRU280).
Using Bootloader
SPRA375D
References
TMS320C55x Peripherals Reference Guide (SPRU317). Using TMS320VC5509/VC5510 Enhanced (SPRA741). TMS320C55x Assembly Language Tools User's Guide (SPRU280). TMS320VC5509 Fixed-Point Digital Signal Processor (SPRS163). Using TMS320VC5507/VC5509/VC5509A Bootloader (SPRA840).
Using Bootloader
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