Kimberly Daniel ABSTRACT Development begin Texas Instruments TMS320C64

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Kimberly Daniel ABSTRACT Development begin Texas Instruments TMS320C64

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Begin Development Today With TMS320C6411
Kimberly Daniel ABSTRACT Development begin Texas Instruments TMS320C6411 high-performance digital signal processor (DSP) systems. Because compatibility between TMS320C6000 generation devices, existing C6000 software tools development platforms used develop code C6411 other future devices. This capability allows systems running when silicon becomes available. C6000 Applications Team
Contents Introduction TMS320C60000 Compatibility C64x Advanced Core Difference Between C6411 C6211 DSPs Similarities Between C6411 C6415 DSPs Differences Between C6411 C6415 DSPs
Highest-Performance Begin Writing Code C6411 Today C6000 Tools Support References List Figures
Figure TMS320C6000 Highest-Performance Fixed-Point Roadmap Figure TMS320C6411 Block Diagram List Tables Table Comparisons Between C6211, C6411, C6415 DSPs
TMS320C6000 C6000 trademarks Texas Instruments. Trademarks property their respective owners.
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Introduction
Texas Instruments TMS320C6000 generation high-performance digital signal processors (DSPs) includes TMS320C6411. TMS320C64x brings highest level performance C6000 generation fixed-point DSPs. clock rates MHz, C6411 provides low-cost, high-performance solution process information rate 2400 MIPS (million instructions second) core voltage. Introduced February 1997, C6000 generation based TI's VelociTI architecture, advanced very long instruction word (VLIW) architecture DSPs. Advanced features VelociTI architecture include instruction packing, conditional branching, pre-fetched branching, which overcome problems that were associated with previous VLIW implementations. architecture highly deterministic, with restrictions when instructions fetched, executed, stored. This architectural flexibility breakthrough efficiency levels C6000 compiler. C64x employs VelociTI.2 extension VelociTI architecture. VelociTI.2 extension significantly improves performance with increased parallelism, orthogonality, packed data processing, instructions accelerate performance applications. roadmap fixed-point C6000 platform, shown Figure demonstrates TI's commitment present highest-performance DSPs.
C6414 4800 MIPS
C6415 4800 MIPS
C6416 4800 MIPS
MIPS
C6203 2400 MIPS C6202 2000 MIPS C6201 1600 MIPS C6211 1333 MIPS Software compatible C6204 1600 MIPS C6205 1600 MIPS
C6411 2400 MIPS
Figure TMS320C6000 Highest-Performance Fixed-Point Roadmap
TMS320C64x, VelociTI, C64x, VelociTI.2 trademarks Texas Instruments.
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TMS320C60000 Compatibility
C6000 generation devices code-compatible with another, with exception that there some floating-point instructions that only valid floating-point (TMS320C67x) members. C64x core enhanced over TMS320C62x core designed achieve high performance through increased instruction-level parallelism. Surpassing throughput traditional superscalar designs, VelociTI.2 provides eight execution units, including multipliers arithmetic logic units (ALUs). These units operate parallel perform eight instructions during single clock cycle-up 2400 MIPS 300MHz initial-device clock speed. This common architecture allows designers begin development with existing C6000 software tools those devices currently development. This also allows migration from C6000 processor another, design specifications require. addition core, many on-chip peripherals common between C6000 devices. Figure shows block diagram C6411. Most these blocks reflect enhancements made over C6211. section details.
EMIF McBSP1 McBSP0 Timer Timer Timer Enhanced Controller Channels Cache/ SRAM 256K Bytes C6411 Digital Signal Processor
Cache Direct Mapped Bytes C64x Core Instruction Fetch Instruction Dispatch Instruction Decode Data Path Register File Data Path Register File
Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
GPIO
Interrupt Selector Boot Configuration Power Down Logic
Cache 2-Way Associative Bytes
Figure TMS320C6411 Block Diagram
TMS320C67x TMS320C62x trademarks Texas Instruments.
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C64x Advanced Core
C64x core offers several enhancements over C62x core. They include: Register file enhancement register files have doubled size. C62x 32-bit general-purpose registers, C64x 32-bit general-purpose registers. Register used condition registers C64x addition condition registers available C62x. C62x register file supports packed 16-, 32-, 40-bit data types. C64x register file extends this also supporting packed 64-bit data types. Data path extensions Each unit load store doublewords bits) with single instruction. unit C62x cannot load store 64-bit values with single instruction. unit, well functional units, access operands data cross-path. C62x, only address cross-paths unit supported. C64x pipelines data cross path accesses. This allows same register used data cross-path operand multiple functional units same execute packet. C62x, only cross operand allowed side.
Advanced instruction packing C62x VelociTI architecture contains instruction packing. Eight instructions fetched every clock cycle. these instructions, any, some, executed parallel. allow maximum usage parallel instructions, VelociTI architecture does allow execute packets cross-fetch packet boundaries. code generation tools handled this limitation padding fetch packets with instructions. C64x VelociTI.2 architecture extensions eliminate this limitation including advanced instruction packing instruction dispatch unit. This improvement removes execute packet boundary restrictions, thereby eliminating NOPs added fetch packets, helps reduce code size. Packed data processing Instructions have been added that operate directly packed data streamline data flow increase instruction efficiency. C64x comprehensive collection quad 8-bit dual 16-bit instruction extensions. Extensive collection pack unpack instructions simplifies manipulation packed data types. Additional functional unit hardware Each unit perform 16-bit multiplies four 8-bit multiplies every clock cycle. units access words doublewords byte boundary using non-aligned load store instructions. C62x only provides aligned load store instructions. units perform byte shifts, units perform bidirectional variable shifts, addition unit's ability shifts. bidirectional shifts directly assist voice-compression codecs (vocoders).
C62x trademark Texas Instruments.
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units perform quad 8-bit subtracts with absolute value. This absolute difference instruction greatly aids motion-estimation algorithms. Special communications-specific instructions, such SHFL, DEAL GMPY4 have been added unit address common operations error-correcting codes. Bit-count Rotate hardware unit extends support bit-level algorithms such binary morphology, image-metric calculations encryption algorithms. unit perform 32-bit logical instructions addition units. unit directly supports load store instructions doubleword data values. C62x does directly support loads stores doublewords, C67x only directly supports loads doublewords. units used load 5-bit constants addition unit's ability load 16-bit constants. C62x, long source long result data path could occur every cycle. C64x, long sources long results accessed each data path every cycle.
Increased orthogonality
Difference Between C6411 C6211 DSPs
Significant enhancements have been made C6411 over C6211, allow C6411 low-cost, high-performance DSP. These include:
core: C6411 features C64x core, while C6211 C62x core. Core supply voltage: C6211 requires core supply voltage. C6411 requires only core-supply voltage. Core frequency: C6211 runs MHz, while C6411 will MHz. Phase-Lock Loop (PLL): circuitry C6211 supports clock multiplier factors while C6411, multiplier factors supported. Internal memory: support high performance core, L1/L2 caches C6411 have been increased four times size over C6211, with each caches, unified cache/SRAM. Enhanced Direct Memory Access (EDMA): C6211 independent EDMA channels. C6411 improves EDMA independent channels. External Memory Interface (EMIF): C6211 C6411 both have 32-bit wide EMIF. addition, C6411 EMIF offers additional flexibility replacing SBSRAM mode with programmable synchronous interface mode, which supports glueless interfaces following: Zero turnaround (ZBT) SRAM Synchronous FIFOs Pipeline flow-thru SBSRAM
C67x trademark Texas Instruments.
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Timers: C6211 Timers. 32-bit timer been added C6411, bringing total three. Multichannel Buffered Serial Port (McBSP): Additional features C6411 include: Enhanced multichannel selection capability allows McBSP independently select channels phase frame. Enhanced sample rate generator.
Host Port Interface (HPI): C6211 16-bit HPI. advanced 32-bit available C6411 allows 16-bit mode operation. Peripheral Component Interconnect (PCI): C6211 does have PCI. C6411 supports 32-bit interface MHz. General-Purpose Input/Output (GPIO): C6211, GPIO pins shared with timers McBSP pins. C6411 extends this capability adding dedicated GPIO module, with GPIO pins. GPIO peripheral programmed generate different interrupts EDMA events. Device boot configurations: C6211 uses pullup/down resistors pins determine boot process device configurations reset. C6411, pullup/down resistors dedicated pins determine boot process device configurations. Package technology: C6211 based 0.18 µm/5-level metal process technology 256-pin package. C6411 based 0.13 mm/6-level metal-process technology 532-pin package.
Similarities Between C6411 C6415 DSPs
following device components identical between three devices:
C64x fixed-point core Enhanced (EDMA) controller: independent channels Host port interface (HPI): 32-bit-wide data bus, capable 16-bit modes operation Peripheral component interconnect (PCI): 32-bit, General-purpose input/output (GPIO) Timer: three 32-bit general-purpose timers Power-down logic
Differences Between C6411 C6415 DSPs
low-cost C6411 viewed subset C6415. following list differences between C6411 C6415 DSPs:
internal memory: C6415 1024 memory. memory C6411 reduced EMIF: There 64-bit EMIF, 16-bit EMIF C6415. low-cost C6411 32-bit EMIF. mode: C6415 device supports multiplier mode. C6411 device, modes supported
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Core frequency: C6415 device runs MHz, whereas C6411 runs MHz. Core supply voltage: C6415 operates core voltages volts. C6411, core supply voltage Universal tests operations interface A(UTOPIA): This peripheral exists only C6415. McBSP: C6415 three McBSPs. C6411 two.
summarize these differences, Table compares C6411 with C6211 C6415 DSPs. Gray cells indicate C6411 enhancements over C6211 DSP. section details. Table Comparisons Between C6211, C6411, C6415 DSPs
C6211 core EMIF C62x 32-bit C6411 C64x 32-bit C6415 C64x 1024 64-bit 16-bit channels 32-/16-bit 32-bit transmit receive 1.2, 532-pin suffix 0.13
EDMA
channels 16-bit
channels 32-/16-bit 32-bit
McBSP UTOPIA
Timer GPIO Core frequency Core voltage modes Package
256-pin suffix 0.18
532-pin suffix 0.13
Process technology
detailed information about device configurations peripherals selection C6411, TMS320C6411 Fixed-Point Digital Signal Processor (SPRS196).
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Highest-Performance
TMS320C64x core scales operating speeds beyond achieves performance improvements over industry's previous performance leader, TMS320C62x DSP. Chips development couple this processing performance, with memory peripheral systems designed accelerate real-time throughput higher system performance. efficient on-chip cache architecture C641x allows system designers slower, cheaper external-memory devices data program storage, while keeping high performance capabilities device. addition, cache helps programmers achieve their performance goals faster, shortening code development accelerating time market. enhanced direct-memory access (EDMA) controller allows designers optimize data organization their systems. Capable accessing location C641x memory map, EDMA controller transfers data background core operation. EDMA controller handle multiple transfers simultaneously interleave bursts. EDMA controller offers independent channels, with separate space hold additional transfer configurations. Each EDMA controller channel synchronized event allow minimal intervention core. on-chip memory organized allow design flexibility ensure efficient memory usage. C641x 288K bytes on-chip memory, with bytes serving level-one (L1) cache that core directly access. cache divided into bytes program (L1P) bytes data (L1D) cache memory. remaining 256K bytes on-chip memory unified program data memory space. serve level-two (L2) cache, directly mapped internal memory, serve combination these functions. direct-mapped, that each instruction byte occupies unique location cache. 256-bit-wide data path core, that core fetch eight instructions (one fetch packet) every cycle. two-way associative, that hold different sets information with independent address ranges. cache dual-ported memory that allows simultaneous accesses from both core data ports, that core load store 64-bit values single data cycle. cache uses least-recently-used (LRU) replacement scheme select between possible cache locations cache miss. 256K bytes memory configured memory-mapped SRAM, combination SRAM 4-way associative cache. memory programmed 32-, 64-, 128-, 256K-byte 4-way associative cache, with remaining memory-mapped SRAM. Blocks that selected cache included C6411 memory map. mapability blocks, addressable locations, allows critical code data locked into internal memory. extensive tests this L1/L2 architecture determine performs with enhanced full-rate vocoder, system-level applications ADSL, V.90 modems, other commonly used algorithms. both data program, TI's tests indicate cache rates greater than percent. other words, only instruction data word fifty needs fetched from external memory.
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high rate, combined with flexibility memory organization, means that this architecture operate more than percent cycle performance more expensive device, with traditional memory organization where system memory chip. This high degree efficiency allows systems rely inexpensive external memory program data storage, while same time performing high-speed, number-crunching routines real time.
Begin Writing Code C6411 Today
Full object-code compatibility with existing C6000 DSPs allows system developers begin development C64x systems today. code-compatible, fixed-point cores C620x, C6211, C641x devices allow code written C6411 using existing C6000 tools. taking advantage C6000 software hardware tools currently available, C6411 systems have running start when silicon becomes available. C6000 compiler used members C6000 device platform. Fixed-point devices object code compatible, C64x code written C62x. C6000 simulator used provide cycle-accurate account device performance provide good environment learn C6000 VLIW architecture. available C6415 configuration simulator closest configuration model C6411 device. EMIF configurations need adjusted reflect C6411 model. C6415 configuration also models cache performance device. Using this configuration, possible optimize code structure data organization take advantage C6411 cache structure. C6411 designs worked detail simulator prior purchasing actual silicon. development start hardware, C6416 Test Evaluation Board (TEB) used understand C6411 functionality. this environment, code debugged while core peripherals running real time. C6411 considered subset C6416, therefore making best tool understand incorporate peripherals into real-time system. Applications running C6416 with C6411 configuration will 100% cycle accurate C6411 system. identical architectures C6416 C6411 devices allow many system-level issues resolved prior obtaining C6411 silicon. Using these development platforms, well C6000 literature currently available, will enable C6411 systems completed soon after C6411 silicon made available.
C6000 Tools Support
C6000 tools available C6000 designs. C6000 development tools available today C6411 are:
C6000 simulator software C6000 Optimizing Compiler/Assembler TMDX3260E6416 C6416 test evaluation board (TEB), bundled with Code Composer Studio Spectrum Digital 510PP+
Code Composer Studio trademark Texas Instruments.
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TMDX3260E6416E C6416 test evaluation board (TEB), bundled with Code Composer Studio Spectrum Digital 510PP+ with European power cord XDS510 C6000 Source Debugger Software XDS510 Emulator Hardware with JTAG Emulation Cable
latest information available tools, site http://www.ti.com
Literature Available
great deal literature available today C6000 devices. TMS320C6411 Fixed-Point Digital Signal Processor (SPRS196). TMS320C6000 Instruction Reference Guide (SPRU189). Manual Update Sheet TMS320C6000 Instruction Reference Guide (SPRZ168). TMS320C6000 Peripherals Reference Guide (SPRU190). TMS320C64x Technical Overview (SPRU395). Code Composer Studio User's Guide (SPRU328). TMS320C6000 Code Composer Studio Tutorial (SPRU301). TMS320C6000 Programmer's Guide (SPRU198). TMS320C64x Image/Video Processing Library Programmer's Reference (SPRU023). TMS320C64x Library Programmer's Reference (SPRU565). TMS320C6000 Chip Support Library Reference Guide (SPRU401). TMS320C6000 Assembly Language Tools User's Guide (SPRU186). TMS320C6000 Optimizing Compiler User's Guide (SPRU187). TMS320C6x Source Debugger User's Guide (SPRU188). TMS320C6x Source Debugger SPARC (SPRU224). TMS320C6000 DSP/BIOS User's Guide (SPRU303). TMS320C6000 DSP/BIOS Application Programming Interface (API) Reference Guide (SPRU403). TMS320 Algorithm Standard Rules Guidelines (SPRU352). TMS320 Product Family Glossary (SPRU258). TMS320 Algorithm Standard Developer's Guide (SPRU424).
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Many application reports also exist assistance with C6411 applications. Here just few: Guidelines Software Development Efficiency TMS320C6000 VelociTI Architecture (SPRA434). Getting Most Performance When Porting TMS320C62x Code TMS320C64x Platform (SPRA678). Reed Solomon Decoder: TMS320C64x Implementation (SPRA686). Cache Usage High Performance Applications with TMS320C64x (SPRA756). TMS320C6414/15/16 Power Consumption Summary (SPRA811). TMS320C6411 Power Consumption Summary (SPRA373). TMS320C6000 EMIF-to-External SDRAM Interface (SPRA433). TMS320C6000 Manufacturing Considerations (SPRA429). TMS320C6000 Board Design: Considerations Debug (SPRA523). TMS320C6x Thermal Design Considerations (SPRA432). Using TMS320C6000 McBSP High Speed Communication Port (SPRA455). TMS320C6000 Simulator User's Guide (SPRU546). more information, site http://www.ti.com
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Kimberly Daniel ABSTRACT Development begin Texas Instruments TMS320C64

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