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Frequently Asked Questions about FIFOs Dual Ports
following questions frequently asked customers evaluating using Cypress FIFOs Dual Ports. These answers will serve introduction each topic. Separate application notes cover these topics more complete detail.
Frequently Asked Questions about FIFOs
does retransmit work? Retransmit allows user re-read block information that previously read from FIFO. This feature commonly used serial transmission applications. serial data corrupted during transmission, retransmit allows easy resend that data packet. FIFOs have also been used hold instruction code processors. Once processor read last instruction pulse retransmit line FIFO re-execute same code. Retransmit also allows FIFOs data pattern generators. retransmit feature effectively FIFO must first reset. resetting device read write pointers moved location zero. device empty ready receive data. Once packet data written into device write pointer sits data packet. Once packet read read pointer moves packet well. Pulsing Retransmit (RT*) simply moves read pointer back location zero. flags will updated reflect number words device packet ready re-read. Care should taken ensure that reads writes performed device during pulsing signal. Refer data sheet complete description requirements perform valid retransmit. reset device? After power-up FIFO must given reset pulse which empties device sets flags represent empty state. Reads writes must performed during reset pulse except with some devices when programming flags. Giving device reset pulse includes both assertion deassertion edge reset pin. What advantage Synchronous flags? tying SMODE CY7C42x5 FIFOs flags will synchronous. flag synchronized read clock, synchronized write clock. When flags synchronous there need synchronize them externally (double triple registering flag avoid metastability concerns.) avoiding external synchronization system respond much faster flag assertion. Synchronized flags also guaranteed asserted minimum clock cycle. This ensures that flag transition visible synchronous environment. CY7C42x1 FIFOs have synchronous flags times. What flag update cycle with respect Synchronous Clocked FIFO? flag update cycle (otherwise known boundary latency cycle) refers clock cycle which updates synchronous flags boundary. When starting with empty FIFO essentially takes read clocks read first word from device. first read clock rising edge updates Empty Flag (assuming write been performed). This update cycle occurs whether read clock enabled not. second read clock rising edge (enabled) will read first word from device. Without asserting read enable (REN) read will performed. Similarly, when device full, write clock needed update full flag (FF). this case takes write cycles write into device which just became full. This type flag operation necessary ensure that empty full flags will valid usable minimum clock cycle. This architecture eliminates short flag pulses characteristic asynchronous FIFO. there concerns with width expansion? Many applications require that multiple FIFOs used parallel generate wider data path. Such applications should external logic generate composite empty full flags. When using FIFOs that have active flags, ANDing EMPTY full flags each device will ensure that FIFOs sync. application note "Understanding Synchronous FIFOs" full description which circumstances allow devices sync. other operations FIFOs will occur just single device. Cypress Semiconductor Corporation 3901 North First Street Jose 95134 408-943-2600 November 1997
Frequently Asked Questions About FIFOs Dual Port RAMs
there concerns with depth expansion? Many FIFOs have expansion logic which allows cascading multiple devices create logically deeper FIFO. Such cascading does slow overall FIFO operation, does limit usability PAE, PAF, flags. Such flags generated subtracting value read write pointers FIFO. Each device will generate flags which accurately represent state that device. However, individual flag used determine overall state system. (For instance: device just over half full other device close empty. FIFOs which make system less than half full.)
What Minimum Pulse Width Violation with respect Asynchronous FIFOs? When using Asynchronous FIFO, users must attempt write full device read from empty device (only when performing simultaneous reads writes.) When asynchronous FIFO full device disables input. does this internally asserting signal inactive state. read pulse occurred during attempted write full device following occurs: 1.The read operation brings device state full 2.Write operations then enabled Internally after signal enabled, pulse which given device truncated (since part pulse disabled). width truncated pulse depends phase relationship between pulse pulse. Under certain phase conditions effective pulse width shorter than allowed. phenomenon therefore called "minimum pulse width violation" Such "runt" pulses irritate flag state machines cause them reflect incorrect values. Likewise same phenomenon occur empty boundary. avoid minimum pulse width violation attempt write full device read from empty device applications which allow simultaneous read write operations.
Frequently Asked Questions about Dual Ports
What difference between Master Slave device? When multiple dual ports used width expansion, typically device master rest devices slaves. master device performs arbitration between ports. slave device does have chip arbiter must told which port BUSY case address collision. Typically BUSY signals connected between master slave devices. This procedure ensures that devices will arbitrate differently. BUSY driven directly slave device cases where user wants perform arbitration externally. What difference between CY7Bxxx device CY7Cxxx device? CY7B designator used describe BiCMOS dual port. CY7C designator used describe CMOS device. Some Dual Ports were originally built using BiCMOS process achieve faster access times. More recent CMOS devices just fast have replaced BiCMOS parts. CMOS dual ports with same part number extensions functionally identical their BiCMOS predecessors (i.e., CY7C135 functionally identical CY7B135). CMOS dual ports typically consume much less power than BiCMOS dual ports. What Semaphore latches for? Semaphore latches used "reserve" certain portions memory space particular port. port requires particular port writes semaphore latch which represents that address space. Once written, that port will read same latch determine gained access. that port reads attempt successful that port access. represents failed attempt. effectively utilize semaphores, both ports must semaphores friendly fashion. dual port does "enforce" semaphores active state since part does know which portion memory being allocated. Each port must monitor semaphores make them effective. What interrupts for? port generate interrupt other port writing designated address. Once receiving port serviced that interrupt reads same address clear interrupt. Such interrupt passing useful notifying port that block data been written ready use.
Cypress Semiconductor Corporation, 1997. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

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