Military Operating Temperature Range: 55°C 125°C Processed MIL-PR

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Military Operating Temperature Range: 55°C 125°C Processed MIL-PR

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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
Military Operating Temperature Range:
55°C 125°C Processed MIL-PRF-38535 Fast Instruction Cycle Time Source-Code Compatible With Devices RAM-Based Operation 16-Bit Single-Cycle On-Chip Program/Data 1056 16-Bit Dual-Access On-Chip Data 16-Bit On-Chip Boot 224K 16-Bit Maximum Addressable External Memory Space (64K Program, Data, I/O, Global) 32-Bit Arithmetic Logic Unit (ALU) 32-bit Accumulator (ACC) 32-Bit Accumulator Buffer (ACCB) 16-Bit Parallel Logic Unit (PLU) 16-Bit Multiplier, 32-Bit Product Context-Switch Registers Buffers Circular Addressing Full-Duplex Synchronous Serial Port Time-Division Multiplexed Serial Port (TDM) Timer With Control Counter Registers Software Programmable Wait-State Generators Divide-by-One Clock Option IEEE 1149.1 Boundary Scan Logic Operations Fully Static Enhanced Performance Implanted CMOS (EPIC) Technology Fabricated Texas Instruments Packaging 141-Pin Ceramic Grid Array (GFA Suffix) 132-Lead Ceramic Quad Flat Package (HFG Suffix) 132-Lead Plastic Quad Flat Package Suffix)
PACKAGE (TOP VIEW)
PACKAGE (TOP VIEW)
PACKAGE (TOP VIEW)
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. IEEE Standard 1149.1-1990 Standard-Test-Access Port Boundary Scan Architecture EPIC trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1998, Texas Instruments Incorporated
products compliant 883, Class parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
description
SMJ320C50 digital signal processor (DSP) high-performance, 16-bit, fixed-point processor manufactured 0.72-µm double-level metal CMOS technology. SMJ320C50 first from designed fully static device. Full-static CMOS design contributes power consumption while maintaining high performance, making ideal applications such battery-operated communications systems, satellite systems, advanced control algorithms. number enhancements basic SMJ320C2x architecture give minimum performance over previous generation. four-deep instruction pipeline, that incorporates delayed branching, delayed call subroutine, delayed return from subroutine, allows perform instructions fewer cycles. addition parallel logic unit (PLU) gives method manipulating bits data memory without using accumulator ALU. additional shifting scaling capability proper alignment multiplicands storage values data memory. achieves low-power consumption through IDLE2 instruction. IDLE2 removes functional clock from internal hardware C50, which puts into total-sleep mode that uses only low-logic level external interrupt with duration least five clock cycles ends IDLE2 mode. available with clock speeds. clock frequencies MHz, providing 40-ns cycle time, MHz, providing 30-ns cycle time. available options listed Table Table Available Options
PART NUMBER SMJ320C50GFAM66 SMJ320C50HFGM66 SMJ320C50GFAM50 SMJ320C50HFGM50 SMQ320C50PQM66 SPEED 30-ns cycle time 30-ns cycle time cycle time cycle time cycle time SUPPLY VOLTAGE TOLERANCE PACKAGE grid array Quad flat package grid array Quad flat package Plastic Quad flat package
When ordering, DESC 5962-9455804NZD
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
functional block diagram
Program (Address) Program (Data)
IPTR BMAR
INT#
IN
PC(16) PASR BRAF MP/MC PAER
Compare Stack
Program Memory
BRCR
Data (Data)
TREG2 TREG1 TREG0
Multiplier COUNT PREG(32) Prescaler P-Scaler
ALU(32) ACCB(32) ACC(32)
Post-Scaler
DBMR
PLU(16) Data (Data)
CBER
INDX
ARCR
AUXREGS
CBSR DP(9) dma(7)
CBCR
ARAU(16) Data (Address) Data Memory OVLY GREG
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
terminal assignments
NAME VSS3 VSS4 D0(LSB) VDD3 VDD4 VSS5 VSS6 INT1 INT2 INT3 INT4 CLKR VDD5 VDD6 VSS7 VSS8 NAME VDD7 VDD8 VSS9 VSS10 CLKMD1 A15(MSB) VDD9 VDD10 VSS11 VSS12 STRB CLKIN2
internal connection Package additional connections: VDD: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, VSS: T14, C17, C19, D14, D16, D18, F16, H16, K16, M16,
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
terminal assignments (continued)
NAME X2/CLKIN VDD11 VDD12 VSS13 VSS14 CLKMD2 TFSX/TFRM HOLDA CLKOUT1 IACK VDD13 VDD14 EMU0 EMU1/OFF VSS15 VSS16 TOUT NAME TCLKX CLKX TFSR/TADD TCLKR READY HOLD VDD15 VDD16 TRST VSS1 VSS2 MP/MC D15(MSB) VDD1 VDD2
internal connection Package additional connections: VDD: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, VSS: T14, C17, C19, D14, D16, D18, F16, H16, K16, M16,
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
Terminal Functions
TERMINAL NAME (MSB) (LSB) (MSB) (LSB) TYPE DESCRIPTION ADDRESS DATA BUSES
I/O/Z
Parallel address bus. Multiplexed address external data, program memory, I/O. A0-A15 high-impedance state hold mode when active (low). These signals used inputs external access on-chip single-access RAM. They become inputs while HOLDA active (low) driven externally.
I/O/Z
Parallel data bus. Multiplexed transfer data between core external data, program memory, devices. D0-D15 high-impedance state when outputting data, when HOLD asserted, when active (low). These signals also used external access on-chip single-access RAM.
MEMORY CONTROL SIGNALS READY Data, program, space select signals. Always high unless asserted communicating particular external space. high-impedance state hold mode when active (low). Data ready input. Indicates that external device prepared transaction completed. device ready (READY low), processor waits cycle checks READY again. READY also indicates grant external device after (bus request) signal. Read/write. indicates transfer direction during communication external device normally read mode (high) unless asserted performing write operation. high-impedance state hold mode when active (low). Used external access cell, this signal indicates direction data reads (high) writes (low) when HOLDA active (low). Strobe. Always high unless asserted indicate external cycle, STRB high-impedance state hold mode when active (low). Used external access on-chip single-access while HOLDA active (low), STRB used select memory access. Read select. indicates active external read cycle connect directly output enable (OE) external devices. This signal active external program, data, reads. high-impedance state hold mode when active (low).
I/O/Z
STRB
I/O/Z
Input, Output, High-Impedance NOTE: input pins that unused should connected external pullup resistor. internal pullup performing on-chip RAM. emulation, TRST internal pulldown, TMS, TCK, have internal pullups. EMU0 EMU1 require external pullups support emulation.
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
TERMINAL NAME TYPE DESCRIPTION MEMORY CONTROL SIGNALS (CONTINUED) Write enable. falling edge indicates that device driving external data (D15-D0). Data latched external device rising edge This signal active external program, data, writes. high-impedance state hold mode when active (low). MULTIPROCESSING SIGNALS HOLD Hold. HOLD asserted request control address, data, control lines. When acknowledged C50, these lines high-impedance state. Hold acknowledge. HOLDA indicates external circuitry that processor hold state that address, data, memory control lines high-impedance state that they available external circuitry access local memory. This signal also goes high-impedance state when active (low). request. asserted during access external global data memory space. READY asserted when global data memory available transaction. used extend data memory address space words. goes high-impedance state when active low. used external access on-chip single-access RAM. While HOLDA active (low), externally driven (low) request access on-chip single-access RAM. Instruction acquisition. Asserted (active) when there instruction address address bus; goes into high-impedance state when active (low). also used external access on-chip single-access RAM. While HOLDA active (low), acknowledges request access on-chip single-access stops indicating instruction acquisition. Branch control. samples condition and, low, causes device execute conditional instruction. must active during fetch conditional instruction. External flag (latched software-programmable signal). high specific instruction loading status register (ST1). Used signaling other processors multiprocessor configurations general-purpose output. goes high-impedance state when active (low) high reset. Interrupt acknowledge. Indicates receipt interrupt that program counter fetching interrupt vector location designated A15-A0. IACK goes high-impedance state when active (low). INITIALIZATION, INTERRUPT, RESET OPERATIONS INT4 INT3 INT2 INT1 External interrupts. INT1-INT4 prioritized maskable interrupt mask register (IMR) interrupt mode (INTM, status register These signals polled reset using interrupt flag register. Nonmaskable interrupt. external interrupt that cannot masked INor IMR. When activated, processor traps appropriate vector location. Reset. causes device terminate execution forces program counter zero. When brought high level, execution begins location zero program memory. Microprocessor/microcomputer select. active (low) reset (microcomputer mode), signal causes internal program mapped into program memory space. microprocessor mode, program memory mapped externally. This signal sampled only during reset, mode that reset overridden software control MP/MC PMST register. OSCILLATOR/TIMER SIGNALS CLKOUT1 Master clock CLKIN2 frequency). CLKOUT1 cycles machine-cycle rate CPU. internal machine cycle bounded rising edges this signal. This signal goes high-impedance state when active (low).
HOLDA
I/O/Z
IACK
MP/MC
Input, Output, High-Impedance
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
TERMINAL NAME TYPE CLKMD1 CLKMD1 CLKMD2 CLKMD2 DESCRIPTION OSCILLATOR/TIMER SIGNALS (CONTINUED) Clock mode External clock with divide-by-two option. Input clock provided X2/CLKIN1. Internal oscillator disabled. Reserved test purposes External divide-by-one option. Input clock provided CLKIN2. Internal oscillator disabled internal enabled. Internal external divide-by-two option. Input clock provided X2/CLKIN1. Internal oscillator enabled internal disabled.
X2/CLKIN CLKIN2 TOUT
Input internal oscillator from crystal. internal oscillator being used, clock input device X2/CLKIN. internal machine cycle half this clock rate. Output from internal oscillator crystal. internal oscillator used, must left unconnected. This signal does high-impedance state when active (low). Divide-by-one input clock driving internal machine rate. Timer output. TOUT signals pulse when on-chip timer counts down past zero. pulse CLKOUT1 cycle wide. SUPPLY PINS
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12
Power supply data
Power supply address Power supply inputs internal logic Power supply address Power supply memory control signals Power supply inputs internal logic Power supply memory control signals Ground memory control signals
Ground data
Ground address
Ground memory control signals
VSS13 VSS14 Ground inputs internal logic VSS15 VSS16 Input, Output, High-Impedance
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
TERMINAL NAME TYPE DESCRIPTION SERIAL PORT SIGNALS CLKR TCLKR Receive clock. External clock signal clocking data from (data receive) (TDM data receive) into (serial port receive shift register). Must present during serial port transfers. serial port being used, these signals sampled input serial port control (SPC) serial port control (TSPC) registers. Transmit clock. Clock signal clocking data from (data transmit) (TDM data transmit pins). CLKX input serial port control register also driven device CLKOUT1 frequency when serial port being used, this sampled input TSPC register. This signal goes into high-impedance state when active (low). Serial data receive. Serial data received (serial port receive shift register) TDR. Serial port transmit. Serial data transmitted from (serial port transmit shift register) TDX. This signal high-impedance state when transmitting when active (low). Frame synchronization pulse receive. falling edge TFSR initiates data receive process, which begins clocking RSR. TFSR becomes input/output (TADD) when serial port operating mode (TDM mode, this used input/output address port. This signal goes into high-impedance state when active (low). Frame synchronization pulse transmit. falling edge FSX/TFSX initiates data transmit process, which begins clocking XSR. Following reset, default operating condition FSX/TFSX input. This selected software output when serial control register This signal goes high-impedance state when active (low). When operating mode (TDM TFSX becomes TFRM, frame-synchronization pulse. TEST SIGNALS Boundary scan test clock. This normally free-running clock with duty cycle. changes (test access port) input signals (TMS TDI) clocked into controller, instruction register, selected test data register rising edge TCK. Changes output signal (TDO) occur falling edge TCK. Boundary scan test data input. clocked into selected register (instruction data) rising edge TCK. Boundary scan test data output. contents selected register (instruction data) shifted falling edge TCK. high-impedance state except when scanning data progress. This signal also goes high-impedance state when active (low). Boundary scan test mode select. This serial control input clocked into test access port (TAP) controller rising edge TCK. Boundary scan test reset. Asserting this signal gives JTAG scan system control operations device. this signal connected driven low, device operates functional mode boundary scan signals ignored. Emulator When TRST driven low, EMU0 must high activation condition (see EMU1/OFF). When TRST driven high, EMU0 used interrupt from emulator system defined input/output boundary scan. Emulator 1/OFF. When TRST driven high, EMU1/OFF used interrupt from emulator system defined input/output boundary scan. When TRST driven low, EMU1/OFF configured OFF. When signal active (low), output drivers high-impedance state. used exclusively testing emulation purposes (not multiprocessing applications). condition, following conditions apply: TRST EMU0 High EMU1/OFF
CLKX TCLKX
I/O/Z
TFSR/TADD
I/O/Z
TFSX/TFRM
I/O/Z
TRST
EMU0
I/O/Z
EMU1/OFF
I/O/Z
RESERVED Reserved. This must left unconnected. Input, Output, High-Impedance Quad flat pack only
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, (see Note Input voltage range Output voltage range Operating case temperature range, 55°C 125°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect VSS.
recommended operating conditions
Supply voltage Supply voltage CLKIN, CLKIN2 High level input High-level voltage Low-level input voltage High-level output current CLKX, CLKR, TCLKX, TCLKR others 4.75 5.25 UNIT
Low-level output current Operating case temperature (see Note This exceeded when using pulldown resistor serial port TADD output; however, this output still meets specifications under these conditions. NOTE maximum rated operating conditions point case. initial (time zero) power
electrical characteristics over recommended ranges supply voltage operating case temperature (unless otherwise noted)
PARAMETER High-level output voltage# Low-level output High edance High-impedance output current (VDD MAX) (with internal pullup) others TRST (with internal pulldown) Input current VDD) Supply current, core Supply current, pins Supply current, standby rrent standb Input capacitance TMS, TCK, (with internal pullups) X2/CLKIN other inputs IDDC IDDP Operating, Operating, IDLE instruction, 25°C, 25°C, 5.25 5.25 5.25 =5.25 TEST UNIT
125°C, IDLE2 instruction, Clocks shut off, =125°C,
Output capacitance conditions shown MIN/MAX, appropriate value specified under recommended operating conditions. typical nominal values (ambient temperature)= 25°C. input output voltage levels TTL-compatible. Figure shows test load circuit; Figure Figure show voltage reference levels. These values specified pending detailed characterization.
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
Tester Electronics VLOAD Output Under Test
Where: VLOAD (all outputs) (all outputs) typical load circuit capacitance
Figure Test Load Circuit
signal transition levels
Transistor-to-transistor logic (TTL) output levels driven minimum logic-high level maximum logic-low level Figure shows TTL-level outputs.
Figure TTL-Level Outputs TTL-output transition times specified follows:
high-to-low transition, level which output said longer high level
which output said low-to-high transition, level which output said longer level which output said high
Figure shows TTL-level inputs.
Figure TTL-Level Inputs TTL-compatible input transition times specified follows:
high-to-low transition input signal, level which input said longer high
level which input said
high transisiton input signal, level which input said longer
level which input said high
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
CLOCK CHARACTERISTICS TIMING
either internal oscillator external frequency source clock. clock mode determined CLKMD1 CLKMD2 pins. Table outlines selection clock mode these pins. Table Clock Mode Selection
CLKMD1 CLKMD2 CLOCK SOURCE External divide-by-one clock option Reserved test purposes External divide-by-two option internal divide-by-two clock option with external crystal External divide-by-two option with internal oscillator disabled
internal divide-by-two clock option with external crystal
internal oscillator enabled connecting crystal across X2/CLKIN. frequency CLKOUT1 one-half crystal's oscillating frequency. crystal should either fundamental overtone operation parallel resonant, with effective series resistance power dissipation should specified load capacitance Overtone crystals require additional tuned circuit. Figure shows external crystal (fundamental frequency) connected on-chip oscillator.
recommended operating conditions internal divide-by-two clock option
'320C50-50 '320C50-66 UNIT
Input clock frequency Load capacitance This device uses fully static design and, therefore, operate with tc(CI) approaching device characterized frequencies approaching tested minimum meet device test time requirements.
Crystal
X2/CLKIN
Figure Internal Clock Option
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
external divide-by-two clock option
external frequency source used injecting frequency directly into X2/CLKIN with left unconnected, CLKMD1 high, CLKMD2 high. external frequency divided generate internal machine cycle. external frequency injected must conform specifications listed timing requirements table.
switching characteristics over recommended operating conditions tc(CO)]
'320C50-50 PARAMETER tc(CO) td(CIH-COH/L) tf(CO) tr(CO) Cycle time, CLKOUT1 Delay time, X2/CLKIN high CLKOUT1 high/low Fall time, CLKOUT1 Rise time, CLKOUT1 2tc(CI) '320C50-66 2tc(CI) UNIT
tw(COL) Pulse duration, CLKOUT1 tw(COH) Pulse duration, CLKOUT1 high This device uses fully static design and, therefore, operate with tc(CI) approaching device characterized frequencies approaching tested minimum meet device test time requirements.
timing requirements
'320C50-50 tc(CI) tf(CI) tr(CI) tw(CIL) Cycle time, X2/CLKIN Fall time, X2/CLKIN Rise time, X2/CLKIN Pulse duration, X2/CLKIN '320C50-66 UNIT
tw(CIH) Pulse duration, X2/CLKIN high This device uses fully static design and, therefore, operate with tc(CI) approaching device characterized frequencies approaching tested minimum meet device test time requirements. This parameter production tested. tw(CIH) tr(CI) tw(CIL) tf(CI)
tc(CI) CLKIN tc(CO) td(CIH-COH/L) tw(COH) CLKOUT1
tf(CO) tr(CO) tw(COL)
Figure External Divide-by-Two Clock Timing
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
external divide-by-one clock option
external frequency source used injecting frequency directly into CLKIN2 with left unconnected connected VDD. This external frequency divided generate internal machine cycle. divide-by-one option used when CLKMD1 strapped high CLKMD2 strapped low. external frequency injected must conform specifications listed timing requirements table (see Figure more details).
switching characteristics over recommended operating conditions tc(CO)]
'320C50-50 PARAMETER tc(CO) td(C2H-COH) tf(CO) tr(CO) tw(COL) tw(COH) td(TP) Cycle time, CLKOUT1 Delay time, CLKIN2 high CLKOUT1 high Fall time, CLKOUT1 Rise time, CLKOUT1 Pulse duration, CLKOUT1 Pulse duration, CLKOUT1 high Delay time, transitory phase-PLL synchronized after CLKIN2 supplied tc(CI) 1000tc(C2)* '320C50-66 tc(CI) 1000tc(C2)* UNIT
This parameter production tested.
timing requirements over recommended ranges supply voltage operating case temperature
'320C50-50 tc(C2) tf(C2) tr(C2) tw(C2L) Cycle time, CLKIN2 Fall time, CLKIN2 Rise time, CLKIN2 '320C50-66 UNIT UNIT
Pulse duration, CLKIN2 tc(C2)-11 tc(C2)-9 tw(C2H) Pulse duration, CLKIN2 high tc(C2)-11 tc(C2)-9 This parameter production tested. Clocks stopped only while device executes IDLE2 when using external divide-by-one clock option. Note that (the transitory phase) occurs when restarting clock from IDLE2 this mode. tw(C2H) tc(C2) CLKIN2 td(C2H-COH) tc(CO) td(TP) CLKOUT1 Unstable tw(COH) tf(CO) tw(COL) tr(CO) tw(C2L) tr(C2) tf(C2)
Figure External Divide-by-One Clock Timing
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
MEMORY PARALLEL INTERFACE READ
Memory parallel interface read timings illustrated Figure
switching characteristics over recommended operating conditions 0.5tc(CO)]
PARAMETER tsu(AV-RDL) th(RDH-AV) tw(RDL) tw(RDH) Setup time, address valid before Hold time, address valid after high Pulse duration, Pulse duration, high H-10 UNIT
td(RDH-WEL) Delay time, high 2H-5 A15-A0, R/W, timings included timings referenced address. Figure address-bus timing variation with load capacitance. STRB timing 3/+5 from CLKOUT1 timing read cycles, following first cycle after reset, which always seven wait-state cycle. This parameter production tested.
timing requirements
ta(RDAV) ta(RDL-RD) Access time, read data valid from address valid Access time, read data valid after 2H-15 H-10 UNIT
tsu(RD-RDH) Setup time, read data valid before high th(RDH-RD) Hold time, read data valid after high Figure address-bus timing variation with load capacitance.
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
MEMORY PARALLEL INTERFACE WRITE
Memory parallel interface read timings illustrated Figure
switching characteristics over recommended operating conditions 0.5tc(CO)]
PARAMETER tsu(AV-WEL) th(WEH-AV) tw(WEL) tw(WEH) td(WEH-RDL) tsu(WDV-WEH) Setup time, address valid before Hold time, address valid after high Pulse duration, Pulse duration, high Delay time, high Setup time, write data valid before high UNIT
th(WEH-WDV) Hold time, write data valid after high ten(WE-BUd) Enable time, data driven A15-A0,PS, R/W, timings included timings referenced address. Figure address timing variation with load capacitance. STRB edges from CLKOUT1 edges writes. Rising falling edges these signals track each other; tolerance resulting pulse durations This value holds true zero wait state only. This parameter production tested. ADDRESS th(WEH-AV) tsu(AV-WEL) ta(RDAV) th(RDH-RD) ta(RDL-RD) tsu(RD-RDH) DATA tsu(AV-RDL) tw(RDH) tw(RDL) tw(WEH) STRB NOTE timings wait states. However, external writes always require cycles prevent external conflicts. above diagram illustrates one-cycle read two-cycle write drawn scale. external writes immediately preceded external read immediately followed external read require three machine cycles. td(RDH-WEL) td(WEH-RDL) th(RDH-AV) tsu(WDV-WEH) ten(WE-BUd) th(WEH-WDV)
tw(WEL)
Figure Memory Parallel Interface Read Write Timing
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
MEMORY PARALLEL INTERFACE WRITE (CONTINUED)
Change Address Timing 1.75 1.50 1.25 0.75 0.50 0.25
Change Load Capacitance
Figure Address Timing Variation With Load Capacitance
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
READY TIMING EXTERNALLY GENERATED WAIT STATES timing requirements
tsu(RY-COH) th(CO-RYH) tsu(RY-RDL) th(RDL-RY) tv(WEL-RY) th(WEL-RY) Setup time, READY before CLKOUT1 rises Hold time, READY after CLKOUT1 rises Setup time, READY before falls Hold time, READY after falls Valid time, READY after falls Hold time, READY after falls UNIT
CLKOUT1 tsu(RY-COH) ADDRESS th(CO-RYH) READY tsu(RY-RDL) th(RDL-RY) Wait State Generated Internally Wait State Generated READY
Figure Ready Timing Externally Generated Wait States During External Read Cycle
CLKOUT1 th(CO-RYH) ADDRESS tsu(RY-COH) READY tv(WEL-RY) th(WEL-RY)
Wait State Generated READY
Figure Ready Timing Externally Generated Wait States During External Write Cycle
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
RESET, INTERRUPT, timing requirements
tsu(IN-COL) th(COL-IN) tw(INL)SYN tw(INH)SYN tw(INL)ASY tw(INH)ASY tsu(RS-X2L) tw(RSL) td(RSH) tw(BIL)SYN tw(BIL)ASY tsu(BI-COL) Setup time, INT1-INT4, NMI, before CLKOUT1 Hold time, INT1-INT4, NMI, after CLKOUT1 Pulse duration, INT1-INT4, low, synchronous Pulse duration, INT1-INT4, high, synchronous Pulse duration, INT1-INT4, low, asynchronous Pulse duration, INT1-INT4, high, asynchronous Setup time, before X2/CLKIN Pulse duration, Delay time, high reset vector fetch Pulse duration, low, synchronous Pulse duration, low, asynchronous Setup time, before CLKOUT1 4H+15 2H+15* 6H+15* 4H+15* H+15* UNIT
th(COL-BI) Hold time, after CLKOUT1 These parameters must synchronous timings. Both reset interrupts operate asynchronously. pulse durations require extra half-cycle assure internal synchronization. IDLE2, these timings. *This parameter production tested. X2/CLKIN tsu(RS-X2L) CLKOUT1 tw(BIL)SYN A15-A0 INT4- INT1 tsu(IN-COL) tw(INH)SYN th(COL-BI) tw(RSL) tsu(BI-COL) tsu(IN-COL) td(RSH)
tsu(IN-COL) tw(INL)SYN
th(COL-IN)
Figure Reset, Interrupt, Timings
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK), EXTERNAL FLAG (XF), TOUT switching characteristics over recommended operating conditions 0.5tc(CO)]
tsu(AV-IQL) th(IQL-AV) tw(IQL) td(CO-TU) tsu(AV-IKL) th(IKH-AV) tw(IKL) tw(TUH) PARAMETER Setup time, address valid before Hold time, address valid after Pulse duration, Delay time, CLKOUT1 falling TOUT Setup time, address valid before IACK Hold time, address valid after IACK high Pulse duration, IACK Pulse duration, TOUT high H-12 H-10 H-10 H-12 H-10 H-10 2H-12 UNIT
td(CO-XFV) Delay time, valid after CLKOUT1 goes during instruction acquisition. goes only first cycle read when wait states used. falling edge should used latch valid address. AVIS PMST register must zero address valid when instruction being addressed resides on-chip memory. Valid only external address reflects current instruction activity (that code executing chip with external cycles AVIS code executing off-chip) IACK goes during fetch first word interrupt vector. goes only first cycle read when wait states used. Address pins decoded falling edge identify interrupt being acknowledged. AVIS PMST register must zero address valid when vectors reside on-chip memory. th(IQL-AV) ADDRESS tsu(AV-IQL) tw(IQL) tsu(AV-IKL) IACK tw(IKL) STRB CLKOUT1 td(CO-TU) td(CO-XFV) th(IKH-AV)
td(CO-TU)
TOUT tw(TUH) NOTE: IACK affected wait states.
Figure IAQ, IACK, Timings Example With External Wait States
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
EXTERNAL TIMING switching characteristics over recommended operating conditions 0.5tc(CO)] (see Note
PARAMETER td(HOL-HAL) td(HOH-HAH) tdis(AZ-HAL) ten(HAH-Ad) td(XBL-IQL) td(XBH-IQH) td(XSL-RDV) th(XSH-RD) ten(IQL-RDd) tdis(W) Delay time, HOLD HOLDA Delay time, HOLD high before HOLDA high Disable time, address high-impedance state before HOLDA Enable time, HOLDA high address driven Delay time, Delay time, high high Delay time, read data valid after XSTRB Hold time, read data after XSTRB high Enable time, read data driven Disable time, XR/W data high-impedance state H-15* H-5* UNIT
tdis(I-D) Disable time, high data high-impedance state ten(D-XRH) Enable time, data from XR/W going high HOLD acknowledged until current external access request complete. This parameter includes memory control lines. This parameter refers delay between time condition (IAQ XR/W satisfied time that SMJ320C50x data lines become valid. This parameter production tested. NOTE preceding name refers external drive signal.
timing requirements
td(HAL-XBL) td(IQL-XSL) tsu(AV-XSL) tsu(DV-XSL) th(XSL-D) th(XSL-WA) tw(XSL) tw(XSH) Delay time, HOLDA Delay time, XSTRB Setup time, Xaddress valid before XSTRB Setup time, Xdata valid before XSTRB Hold time, Xdata hold after XSTRB Hold time, write Xaddress hold after XSTRB Pulse duration, XSTRB Pulse duration, XSTRB high UNIT
tsu(RW-XSL) Setup time, valid before XSTRB th(XSH-RA) Hold time, read Xaddress after XSTRB high XBR, XR/W, XSTRB lines should pulled with 10-k resistor assure that they inactive (high) state during transition period between SMJ320C50x driving them external circuit driving them. NOTE preceding name refers external drive signal.
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EXTERNAL TIMING (CONTINUED)
HOLD td(HOL-HAL) HOLDA Address Bus/ Control Signals td(XBL-IQL) td(IQL-XSL) XSTRB tw(XSH) tw(XSL) XR/W tsu(AV-XSL) th(XSH-RD) th(XSH-RA) ten(IQL-RDd) XADDRESS td(XSL-RDV) tsu(AV-XSL) th(XSL-WA) tdis(I-D) DATA(RD) ten(IQL-RDd) th(XSL-D) tsu(DV-XSL) XDATA(WR) A15-A0, R/W, timings included timings referenced address bus/control signals. ten(D-XRH) tdis(W) tsu(RW-XSL) td(XBH-IQH) tdis(AZ-HAL) ten(HAH-Ad) td(HOH-HAH)
td(HAL-XBL)
ten(I-B)
Figure External Timing
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
SERIAL-PORT RECEIVE timing requirements
tc(SCK) tf(SCK) tr(SCK) tw(SCK) tsu(FS-CK) th(CK-FS) Cycle time, serial-port clock Fall time, serial-port clock Rise time, serial-port clock Pulse duration, serial-port clock low/high Setup time, before CLKR falling edge Hold time, after CLKR falling edge 2.1H 5.2H UNIT
tsu(DR-CK) Setup time, before CLKR falling edge th(CK-DR) Hold time, after CLKR falling edge serial-port design fully static and, therefore, operate with tc(SCK) approaching characterized approaching input frequency tested much higher frequency minimize test time. This parameter production tested. tc(SCK) tw(SCK) CLKR th(CK-FS) tw(SCK) tsu(FS-CK) tsu(DR-CK) th(CK-DR) (see Note (see Note tr(SCK) tf(SCK)
NOTE Depending whether information sent 8-bit 16-bit packet.
Figure Serial-Port Receive Timing
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SERIAL-PORT TRANSMIT, EXTERNAL CLOCKS EXTERNAL FRAMES switching characteristics over recommended operating conditions (see Note
PARAMETER td(CXH-DXV) tdis(CXH-DX) Delay time, valid after CLKX high Disable time, valid after CLKX high UNIT
th(CXH-DXV) Hold time, valid after CLKX high This parameter production tested.
timing requirements
tc(SCK) tf(SCK) tr(SCK) tw(SCK) td(CXH-FXH) th(CXL-FXL) Cycle time, serial-port clock Fall time, serial-port clock Rise time, serial-port clock Pulse duration, serial-port clock low/high Delay time, after CLKX high edge 2.1H 2H-8 5.2H UNIT
Hold time, after CLKX falling edge th(CXH-FXL) Hold time, after CLKX high edge 2H-8* serial-port design fully static therefore operate with tc(SCK) approaching characterized approaching input frequency tested much higher frequency minimize test time. pulse does meet this specification, first serial data driven until falling edge FSX. After falling edge FSX, data shifted pin. transmit-buffer-empty interrupt generated when th(FS) th(FS)H specification met. NOTE Internal clock with external vice versa also allowable. However, timings CLKX always defined depending source FSX, CLKX timings always dependent upon source CLKX. Specifically, relationship CLKX independent source CLKX. This parameter production tested. tc(SCK) CLKX td(CXH-FXH)) th(CXL-FXL) td(CXH-DXV) th(CXH-DXV) (see Note (see Note th(CXH-FXL) tw(SCK) tdis(CXH-DX) tr(SCK) tw(SCK) tf(SCK)
NOTE Depending whether information sent 8-bit 16-bit packet
Figure Serial-Port Transmit Timing External Clocks External Frames
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SERIAL-PORT TRANSMIT, INTERNAL CLOCKS INTERNAL FRAMES switching characteristics over recommended operating conditions 0.5tc(CO)] (see Note
PARAMETER td(CX-FX) td(CX-DX) tdis(CX-DX) tc(SCK) tf(SCK) tr(SCK) tw(SCK) th(CXH-DXV) Delay time, CLKX rising Delay time, CLKX rising Disable time, CLKX rising Cycle time, serial-port clock Fall time, serial-port clock Rise time, serial-port clock Pulse duration, serial-port clock low/high Hold time, valid after CLKX high UNIT
This parameter production tested. NOTE Internal clock with external vice versa also allowable. However, timings CLKX always defined depending source FSX, CLKX timings always dependent upon source CLKX. Specifically, relationship CLKX independent source CLKX. tc(SCK) tw(SCK) CLKX td(CX-FX) td(CX-FX) td(CX-DX) tdis(CX-DX) th(CXH-DXV) (see Note (see Note tw(SCK) tr(SCK) tf(SCK)
NOTE Depending whether information sent 8-bit 16-bit packet
Figure Serial-Port Transmit Timing Internal Clocks Internal Frames
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SERIAL-PORT RECEIVE TIMING MODE timing requirements
tc(SCK) tf(SCK) tr(SCK) tw(SCK) tsu(TD-TCH) th(TCH-TD) tsu(TA-TCH) th(TCH-TA) Cycle time, serial-port clock Fall time, serial-port clock Rise time, serial-port clock Pulse duration, serial-port clock low/high Setup time, TDAT/TADD before TCLK rising Hold time, TDAT/TADD after TCLK rising Setup time, TDAT/TADD before TCLK rising Hold time, TDAT/TADD after TCLK rising 2.1H 5.2H UNIT
tsu(TF-TCH) Setup time, TRFM before TCLK rising th(TCH-TF) Hold time, TRFM after TCLK rising serial-port design fully static therefore operate with tc(SCK) approaching characterized approaching input frequency tested much higher frequency minimize test time. These parameters apply only first bits serial string. TFRM timing waveforms shown Figure external TFRM. TFRM also configured internal. TFRM internal case illustrated transmit timing diagram Figure This parameter production tested. tf(SCK) TCLK tc(SCK) TDAT th(TCH-TA) tsu(TF-TCH) TADD th(TCH-TF) TFRM th(TCH-TA) tsu(TA-TCH) tsu(TD-TCH) th(TCH-TD) tr(SCK) tw(SCK) tw(SCK)
Figure Serial-Port Receive Timing Mode
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SERIAL-PORT TRANSMIT TIMING MODE switching characteristics over recommended operating conditions 0.5tc(CO)]
PARAMETER th(TCH-TDV) td(TCH-TFV) Hold time, TDAT/TADD valid after TCLK rising Delay time, TFRM valid after TCLK rising 3H+10 UNIT
td(TC-TDV) Delay time, TCLK valid TDAT/TADD TFRM timing waveforms shown Figure internal TFRM. TFRM also configured external, TFRM external case illustrated receive timing diagram Figure
timing requirements
tc(SCK) tf(SCK) Cycle time, serial-port clock Fall time, serial-port clock 5.2H UNIT
tr(SCK) Rise time, serial-port clock tw(SCK) Pulse duration, serial-port clock low/high 2.1H When generated internally. serial-port design fully static therefore operate with tc(SCK) approaching characterized approaching input frequency tested much higher frequency minimize test time. This parameter production tested. tf(SCK) tr(SCK) TCLK tc(SCK) TDAT th(TCH-TDV) TADD td(TCH-TFV) td(TCH-TFV) TFRM th(TCH-TDV) td(TC-TDV) td(TCV-TDV) tw(SCK)
tw(SCK)
Figure Serial-Port Transmit Timing Mode
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MECHANICAL DATA
(S-CQFP-F132) CERAMIC QUAD FLATPACK WITH TIE-BAR
0.960 (24,38) 0.945 (24,00) 0.800 (20,32) 0.225 (5,72) Width 0.175 (4,45)
1.210 (30,73) 2.015 (51,18) 1.990 (50,55)
2.025 (51,44)
0.061 (1,55) 0.059 (1,50) 0.013 (0,33) 0.006 (0,15) Braze
0.040 (1,02) 0.030 (0,76) 0.025 (0,64) DETAIL 0.020 (0,51) DETAIL
0.010 (0,25) 0.005 (0,12)
0.014 (0,36) 0.002 (0,05)
0.116 (2,95) DETAIL 4040231-8/F 04/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Ceramic quad flatpack with flat leads brazed non-conductive carrier. This package hermetically sealed with metal lid. terminals will gold plated.
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SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR
MECHANICAL DATA
(S-CPGA-P141)
1.080 (27,43) 1.040 (26,42)
CERAMIC GRID ARRAY PACKAGE
0.900 (22,86) 0.100 (2,54) 0.050 (1,27)
0.026 (0,66) 0.006 (0,15) 0.145 (3,68) 0.105 (2,67)
0.034 (0,86) 0.022 (0,56) 0.016 (0,41) 0.048 (1,22) Places 4040133/D 04/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MO-128 0.140 (3,56) 0.120 (3,05)
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MECHANICAL DATA
(S-PQFP-G***)
LEAD SHOWN
PLASTIC QUAD FLATPACK
0.012 (0,30) 0.008 (0,20)
0.006 (0,15)
"D3"
0.025 (0,635) 0.006 (0,16) 0.150 (3,81) 0.130 (3,30) "D1" "D2" 0.020 (0,51) 0°-8° 0.046 (1,17) 0.036 (0,91) Seating Plane 0.180 (4,57) LEADS 0.890 (22,61) 0.870 (22,10) 0.766 (19,46) 0.734 (18,64) 0.912 (23,16) 0.888 (22,56) 0.600 (15,24) 0.004 (0,10) 0.010 (0,25) Gage Plane
1.090 (27,69) 1.070 (27,18) 0.966 (24,54) 0.934 (23,72) 1.112 (28,25) 1.088 (27,64) 0.800 (20,32) 4040045/C 11/95
"D1"
"D2" "D3"
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MO-069
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device 5962-9455803QXA 5962-9455803QYA 5962-9455804NZB 5962-9455804QXA 5962-9455804QYA SM320C50GFAM50 SM320C50GFAM66 SM320C50HFGM50 SMJ320C50GFAM50 SMJ320C50GFAM66 SMJ320C50HFGM50 SMJ320C50HFGM66
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CPGA BQFP CPGA CPGA CPGA CPGA CPGA
Package Drawing
Pins Package Plan
Lead/Ball Finish Call Call Call Call Call Call Call Call Call Call Call Call
Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-4-220C-72 Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MBQF001A NOVEMBER 1995
(S-PQFP-G***)
LEAD SHOWN
PLASTIC QUAD FLATPACK
0.012 (0,30) 0.008 (0,20)
0.006 (0,15)
"D3"
0.025 (0,635) 0.006 (0,16) 0.150 (3,81) 0.130 (3,30) "D1" "D2" 0.020 (0,51) 0.046 (1,17) 0.036 (0,91) Seating Plane 0.180 (4,57) LEADS 0.890 (22,61) 0.870 (22,10) 0.766 (19,46) 0.734 (18,64) 0.912 (23,16) 0.888 (22,56) 0.600 (15,24) 0.004 (0,10) 0.010 (0,25) Gage Plane
1.090 (27,69) 1.070 (27,18) 0.966 (24,54) 0.934 (23,72) 1.112 (28,25) 1.088 (27,64) 0.800 (20,32) 4040045 11/95
"D1"
"D2" "D3"
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MO-069
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MECHANICAL DATA
MCFP019C JANUARY 1995 REVISED JUNE 1999
(S-CQFP-F132)
0.960 (24,38) 0.940 (23,88) 0.800 (20,32)
CERAMIC QUAD FLATPACK WITH NCTB
0.375 (9,53) Width 0.325 (8,26)
1.520 (38,61) 1.480 (37,59) 2.505 (63,63) 2.485 (63,12)
1.150 (29,21) Places 0.061 (1,55) Places 0.059 (1,50) 0.013 (0,33) 0.006 (0,15) BRAZE
0.105 (2,67) 0.018 (0,46)
0.040 (1,02) 0.030 (0,76) 0.025 (0,64) DETAIL 0.020 (0,51) DETAIL
0.009 (0,23) 0.004 (0,10)
0.014 (0,36) 0.002 (0,05) 0.130 (3,30)
DETAIL 4040231-4/J 01/99
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Ceramic quad flatpack with flat leads brazed non-conductive carrier This package hermetically sealed with metal lid. leads gold-plated solder-dipped. Leads shown clarity purposes Falls within JEDEC MO-113AC
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MECHANICAL DATA
MCPG015B FEBRUARY 1996 REVISED DECEMBER 2001
(S-CPGA-P141)
1.080 (27,43) 1.040 (26,42)
CERAMIC GRID ARRAY
0.900 (22,86) 0.100 (2,54) 0.050 (1,27)
Corner 0.026 (0,66) 0.006 (0,15) 0.145 (3,68) 0.105 (2,67)
Bottom View
0.034 (0,86) 0.022 (0,56) 0.016 (0,41) 0.048 (1,22) Places 4040133/E 11/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Index mark appear bottom, depending package vendor. Pins located within 0.010 (0,25) diameter true position relative each other maximum material condition within 0.030 (0,76) diameter relative edge ceramic. This package hermetically sealed with metal lids with ceramic lids using glass frit. pins gold-plated solder-dipped. Falls within JEDEC MO-128AB 0.140 (3,56) 0.120 (3,05)
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MECHANICAL DATA
MCQF004C FEBRUARY 1996 REVISED JUNE 1999
(S-CQFP-F132)
0.960 (24,38) 0.945 (24,00) 0.800 (20,32)
CERAMIC QUAD FLATPACK WITH NCTB
0.225 (5,72) 0.175 (4,45)
Width
1.222 (31,04) 1.198 (30,43) 2.015 (51,18) 1.990 (50,55)
2.025 (51,44)
0.900 (22,86) Places 0.062 (1,57) 0.058 (1,47)
0.091 (2,31) 0.013 (0,33) 0.006 (0,15) Braze 0.014 (0,36) 0.002 (0,05) 0.115 (2,92) DETAIL 4040231-8/J 01/99 0.018 (0,46)
0.040 (1,02) 0.030 (0,76) 0.025 (0,64) DETAIL 0.020 (0,51) DETAIL
0.009 (0,23) 0.004 (0,10)
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Ceramic quad flatpack with flat leads brazed non-conductive carrier This package hermetically sealed with metal lid. leads gold-plated solder-dipped. Leads shown clarity purposes
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Military Operating Temperature Range: 55°C 125°C Processed MIL-PR

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