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Signal Processing Codec Filter SICOFI®, SICOFI®-2

PEB 2060 PEB 2260 Revision History: Previous Releases: Page

ICs for Communications
Signal Processing Codec Filter SICOFI®, SICOFI®-2
PEB 2060 PEB 2260 Revision History: Previous Releases: Page
Original Version 03.92
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Semiconductor Group
Contents
Detailed Description of Hardware Tools.................................... 326 SICOFI® Test Board STUT 2060........................................... 326 SICOFI®-2 Module for the Siemens ISDN PC User Board (SIPB 5135) .............. 358 SLIC Babyboard STUS 5502 for HARRIS SLIC HC 5502......................... 386 SLIC Babyboard STUS 5509 for HARRIS SLIC HC 5509......................... 398 SLIC Babyboard STUS 3762 for ERICSSON SLIC PBL 3736 ..................... 411 SLIC Babyboard STUS 3762 for ERICSSON SLIC PBL 3762 / 64 ................... 423 SLIC Babyboard STUS 3030 for S SLIC L3000 / L3030 ....................... 437 SLIC Babyboard STUS 3090 for S SLIC L3000 / L3090 ....................... 453 SLIC Babyboard STUS 1001 for Transformer SLIC ............................. 466 Application Notes ...................................................... 475 I II III IV V VI VII VIII IX X SICOFI® Application Together with HARRIS-SLIC HC 5502 .............. 475 SICOFI® Application Together with ERICSSON SLIC PBL 3762........... 502 SICOFI® Application Together with S SLIC L3000 / L3030.............. 548 SICOFI® Application Together with S SLIC L3000 / L3090.............. 594 SICOFI® Application Together with Transformer SLIC with Series Feeding.................................................. 629 SICOFI® Application Together with Transformer SLIC with Transverse Feeding .......................................... 658 SICOFI® Application Together with Transformer SLIC for USA Specification............................................. 710 SICOFI® Layout Recommendation for Analog Line-Card Applications ....... 723 Using SICOFI®-2 (PEB 2260) in IOM®-2 Mode ......................... 728 DAML Simulation Using the SIPB 5000 Userboard System................ 744
Semiconductor Group
Contents
Semiconductor Group
General Information
Type-Designation Code for ICs
IC type designations are based on the European Pro Electron system. The code system is explained in the Pro Electron brochure D 15), edition 1988. ) Available from Pro Electron Avenue Louise, 430 (B.12) B -1050 Bruxelles, Belgium 2 Mounting Instructions Plastic Packages for Insertion The pins of the packages are bent downwards by an angle of 90° and fit into holes on a grid of 2.54 mm and with diameters of between 0.7 and 0.9 mm. The dimension x is shown in the corresponding drawing of the package. The bottom of the package will not touch the circuit board after insertion because the pins have shoulders just below the package (see figure 1). After insertion of a package on a board it is advisable to bend the ends of two pins at an angle of approx. 30° to the board so that the package does not have to be pressed down during soldering. Plastic packages are soldered on the board on the side facing away from the package. The maximum permissible soldering temperature is 260 °C (max.10 s) when using a solder bath, e.g. wave soldering, and 350 °C (max. 3 s) when using a soldering iron. ws
Figure 1 Plastic Packages (P-DSO and P-LCC) for Surface Mounting (SMD) Reflow soldering: Wave soldering: for a device temperature of 215 °C max. soldering time 2 x 40 s (typical figure for vapor-phase soldering) soldering temperature 260 °C, soldering time max. 10 s. the minimum thermal stress, based on experience, is at a soldering temperature of 350 °C (soldering time 3 s)
Soldering iron:
Semiconductor Group
General Information
Storage and Pretreatment of SMD ICs The components should be stored in a dry place. Some large and specially identified plastic ICs have to be processed in a dry condition. This is produced by dry packing or by means of a separate drying process shortly before they are processed (e.g. 16 h at 125 °C)
All in all this means that ICs call for special handling, because uncontrolled charges, voltages from ungrounded equipment or persons, surge voltage spikes and similar influences can destroy a device. Even if devices have protective circuits (e.g. protective diodes) on their inputs, the following guidelines for their handling should nevertheless be observed. Identification The packing of ESS devices is provided with the following label by the manufacturer:
Scope The guidelines apply to the storage, transport, testing, and processing of all kinds of ICs, equipped and soldered circuit boards that comprise such components.
Semiconductor Group
General Information
Semiconductor Group
General Information
Material and Mounting 1 The drive belts of machines used for the processing of the devices, in as much as they come into contact with them (e.g. bending and cutting machines, conveyor belts), should be treated with anti-static spray (e.g. anti-static spray 100 from Kontaktchemie). It is better, however, to avoid the contact completely. If ESS devices have to be soldered or desoldered manually, soldering irons with thyristor control may not be used. Siemens EMI-suppression capacitors of the type B 81711-B31..-B36 have been proven very effective against line transients. Circuit boards fitted and soldered with ESS devices are always to be considered as endangered.
Semiconductor Group
General Information
Electrical Tests and Application Circuit 1 2 The devices should be processed with observation of these guidelines. Before assembled and soldered circuit boards are tested, remove any shorting rings. The sockets or integrated circuits must not be conducting any voltage when individual devices or assembled circuit boards are inserted or withdrawn, unless works specifications state otherwise. Ensure that the test devices and power supplies do not produce any voltage spikes, either when being turned on and off in normal operation or if the power fuse blows or other fuses respond. When supplying bipolar integrated circuits with current, the negative voltage (-V S or GND) has first to be connected. In general, an interruption of this potential during operation is not permissible. Signal voltages may only be applied to the inputs of ICs when or better after the supply voltage is turned on. They must be disconnected when or better before the supply voltage is turned off. Power supplies of integrated circuits are to be blocked as near as possible at the supply terminals of the IC. With bipolar ICs it is recommended to use a low-inductance electrolytic capacitor or at least a paralleled ceramic capacitor of 100 nF to 470 nF for example. Using ICs with high output currents, the necessary value of the electrolytic capacitor must be adapted to the test or application circuit. Transient behavior and dynamic output resistance of the power supplies, line inductances in the supply and load circuit and in particular inductive loads or motors have to be considered. When switching off line inductances of inducitve loads, the stored power has to be consumed externally, unless otherwise specified (e.g. by an electrolytic capacitor, diodes, Z-diodes or the power supply). Also a switching off of the supply voltage prior to the load rejection should be taken into account. ICs with low-pass character of the output stages (e.g. PNP drivers or PNP / NPN endstages), normally need an additional external compensation at the output. This applies particularly to complex loads. The output of AF power amplifiers is compensated by the Boucherot element. In individual cases, bridge circuits only need a capacitance for bypassing the load. Depending on the application it is, however, also recommended to connect one capacitor from each output to ground. Observe any notes and instructions in the respective data books.
Semiconductor Group
General Information
Semiconductor Group
General Information
Operating Range In the operating range the functions given in the circuit description are fulfilled.
Quality Assurance Quality Assurance System The high quality and reliability of integrated circuits from Siemens are the results of carefully managed design and production which is systematically checked and controlled at each stage. The procedures are subject to a quality assurance system full details are given in the brochure "Quality Assurance - Integrated Circuits". Figure 1 and 2 show the most important stages of Quality Assurance (QA) system. QA departments independent of production and development are responsible for the selected measures, acceptance procedures and information feedback loops. Operating QA departments have state-of-the-art test and measuring equipment at their disposal, work according to approved methods of statistical quality control, and are provided with facilities for accelerate life and environmental tests used for both qualification and routine monitoring tests. The latest methods and equipment for preparation and analysis are employed to achieve continuity of quality and reliability. Conformance Each integrated circuit is subjected to a final test at the end of the production process. These are carried out by computer-controlled, automatic test systems because hundreds of thousands of operating conditions as well as a large number of static and dynamic parameters have to be considered. Moreover, the test systems are extremely reliable and reproducible. The QA department carries out a final check in the form of a lot-by-lot sampling inspection to additionally ensure this minimum percent defectives to ensure statistically that the PDA of released lots is less than the AQL agreed. Sampling inspection is performed in accordance with the inspection plans of DIN 40 080, as well as of the identical MIL-STD-105 or IEC 410.
Semiconductor Group
General Information
Figure 2 Semiconductor Group 13
General Information
Figure 3 Reliability Measures Taken During Development The reliability of ICs is already considerably influenced at the development stage. Siemens has, therefore, fixed certain design standards for the development of circuit and layout, e.g. specifying minimum width and spacing of conductive layers on a chip, dimensions and electrical parameters of protective circuits for electrostatic charge, etc. An examination with the aid of carefully arranged programs operated on large-scale computers, guarantees the immediate identification and elimination of unintentional violations of these designs standards. Semiconductor Group 14
General Information
In-Process Control During Production The manufacturing of integrated circuits comprises several hundred production steps. As each step is to be executed with utmost accuracy, the in-procress control is of outstanding importance. Some processes require more than a hundred different test measures. The tests have been arranged in a manner that the individual steps of the process can be reproduced continuously. The decreasing failure rates reflect the persistent effort in this direction in the course of the years they have been reduced considerably despite an immense rise in IC complexity.
Semiconductor Group
Overview on Architecture and Devices
General Exchange Architecture
Semiconductor Group
Overview on Architecture and Devices
Analog Line Cards
In a digital exchange system the subscriber line boards provide the link between the subscriber and the switching network. The basic functions of analog line boards are known under the acronym BORSHT (battery, overvoltage, ringing, supervision, hybrid, testing). Moreover, further important tasks are voice frequency band limitation, analog to digital conversion into time discrete digital equivalents, time-slot assignment on the PCM highways and handling of signaling and control information. Usual implementation uses two PCM ports and one µP interface per subscriber line leading to a large amount of wiring and, thus, problems such as crosstalk and large board size. Usual implementation is also characterized by fixed adjustment of line interface conditions although telephone line conditions vary considerably with national standards and even with subscriber line installations. Under adverse conditions telecommunication equipment must match the subscriber line and termination impedances while suppressing return echoes in the two- to four-wire hybrid network. Compensating for line attenuation is just as critical for balancing the voice signals in the transmission and reception paths. To improve voice quality, subscriber line boards have to be matched to different line conditions by means of interchangeable discrete components. This approach is very costly regarding line board design and manufacturing. Furthermore, the reliability of a board filled with parts, wires and connections will decrease rapidly. The subscriber line board architecture proposed by Siemens Semiconductor is geared to eliminate many of these line board trouble spots.
Semiconductor Group
Overview on Architecture and Devices
General Line Board Structure and Functions
General Line Card Function Component SLIC (Subscriber line interface circuit) Function
realisation of the BORSHT function B battery feed O overvoltage protection R ringing S supervision H hybrid T testing analog network Z matching of input and line impedance R, X frequency response correction B hybrid balancing G gain adjustment CODEC / Filter coding, A / D and D / A conversion according to A-law and µ-law, voice band limitation according to CCITT and LSSGR PCM time-slot assignment, PCM data rate
Semiconductor Group
Overview on Architecture and Devices
Optimized Line Board Architecture
The Siemens Semiconductor concept is characterized by a centralized PCM interface controller device providing the variable Time-Slot Assignment (TSA), the communication with up to 64 subscriber line devices such as signal processing codec / filter (SICOFI®) or ISDN devices via the SLD (Subscriber Line Data) or IOM®-2 (ISDN Oriented Modular) interface, and the interface with a microprocessor. As a characteristic architectural feature, for test, monitring and control purposes, the device permits efficient switching of data streams between all these interfaces and, therefore, ensures transparency between the PCM channels and control or signaling data. This opens up attractive possibilities such as common-channel signaling and microprocessor access to PCM data. The use of the signal processing codec / filter (SICOFI) avoids the analog network which has to be matched to different requirements by interchanging its discrete components. Based on Digital Signal Processing (DSP) methods the SICOFI allows the complete control of the line conditions by software. The all-over flexibility of the unique device concept gives the user the capability for designing a standard line card which can be customized for each application under software control. The SLD / IOM-2 architecture leads to a highly modular line board configuration with low wiring, reduced board area and, depending only on the SLIC to be used, very few discrete elements.
Siemens ICs for Analog Subscriber Lines
Semiconductor Group
Overview on Architecture and Devices
The SLD / IOM®-2 Interface
The SLD bus is used by the PBC / PIC to interface with the subscriber line devices. A Serial Interface Port (SIP) is used for the transfer of all digital voice and data, feature control and signaling information between the individual subscriber line devices, the PCM highways and the control backplane. The SLD approach provides a common interface for analog or digital per-line components. Through the PBC / PIC, which is the key device in the SLD architecture, the PCM data is transparently switched onto the PCM highways. The PBC will make analog and digital subscriber line boards plug-compatible in a line equipment rack. There are three leads connecting each subscriber line device and the PBC / PIC: two common clock signals shared among all devices, and a unique bidirectional data lead for each of the eight SIP lines. The Direction signal (DIR) is an 8-kHz clock output from the PBC (master) that serves as a frame sync to the subscriber line devices (slave) as well as a transfer indicator. The data are transferred at a 512-kHz rate, clocked by the Subscriber Clock (SCLK). When DIR is high (first half of the SLD 125 µs frame), four bytes of digital data are transmitted on the SLD bus from the PBC / PIC to the slave (receive direction). During the second half of the frame when DIR is low, four bytes of data are transferred from the slave back to the PBC / PIC (transmit direction). Channel A and B are 64-kbit / s channels reserved for voice or data to be routed to and from the PCM highways. In an application where one SICOFI is connected to a SIP, voice is received on channel A and transmitted on channel A and B. For a three-party conference, channel B is the third-party voice channel. If two SICOFIs are connected to one SIP, channel A is assigned to one and channel B to the other SICOFI. Conferencing is not possible in this configuration. With digital subscriber line devices the two bytes can be used to carry 64-kbit / s data channels. The third and sixth byte locations are used to transmit and receive control information for programming the slave devices. The last byte in each direction is reserved for signaling data.
Semiconductor Group
Overview on Architecture and Devices
Frame Structure of the SLD Interface
Because of the unique requirements of ISDN systems, Siemens developed an interchip interface especially for these applications. As part of their joint definition of ISDN components, the "Group of Four" (ALCATEL, Siemens, Plessey and ITALTEL systems houses) adapted this Siemens Semiconductor interface and suggested some compatible additional features. The resulting IOM-2 interface has become the standard for interchip communication in ISDN terminals, terminal adaptors, network terminations, transmission repeaters and line cards for digital exchange systems. The IOM-2 interface is a four wire interface with: a bit clock, a frame clock and one data line per direction. It has a flexible data clock. In this way, data transmission requirements are optimized for different applications.
Semiconductor Group
Overview on Architecture and Devices
On line cards, a 4096-kHz clock has been selected so that up to eight IOM channels and thus, eight ISDN or 16 analog subscribers can be multiplexed over a single IOM-2 bus. The channel structure of the IOM-2 interface is as follows: The first two octets constitute the two 64 kbit / s B channels. q The third octet is the MONITOR channel. It is used for the exchange of data between devices using the IOM-2 MONITOR channel protocol.
The fourth octet (control channel) contains - two bits for the 16 kbit / s D channel - a four-bit command / indication channel, in ISDN applications or - a six bit command / indication channel for analog subscriber applications - two bits MR and MX for supporting the MONITOR channel protocol.
Multiplexed Frame Structure of the IOM®-2 Interface
Semiconductor Group
Overview on Architecture and Devices
Device Overview PCM Interface Controller (PBC / PIC / EPIC®)
Semiconductor Group
Overview on Architecture and Devices
The Extended PCM Interface Controller (EPIC) PEB 2055 is intended to be used as central PCM processor in the IOM architecture. The CMOS device can be programmed to operate at different data rates between 128 and 8192 kbit / s. The system interface consists of up to four duplex ports with a tristate indication signal for each output line. The configurable interface can be selected to incorporate either four duplex (IOM) or eight bidirectional I / O ports (SLD). The EPIC can therefore be programmed to communicate either with SLD or with IOM (ISDN Oriented Modular) and IOM®-2 compatible devices. In both cases the device handles the layer1 functions of buffering the C / I and MONITOR channels for IOM-compatible devices and the feature control and signaling channels for SLD compatible devices. The EPIC can handle up to 32 ISDN subscribers with their 2B + D channel structure or 64 analog subscribers in IOM configuration or up to 16 subscribers in SLD configuration. Since its interfaces can operate at different data rates, the EPIC is an ideal device for data rate adaptation. Moreover, the EPIC is one of the fundamental building blocks for networks with either central, decentral or mixed signaling and packet data handling architectures. The EPIC-2 PEB 2056 is a smaller version of the EPIC. The functions that are performed remain essentially the same but the EPIC-2 PEB 2056 has been optimized for time-slot assignment and switching functions on line cards with up to 8 ISDN or 16 analog subscriber lines. Siemens Semiconductor therefore offers the optimal solution of PCM Interface Controller for every application. - PBC PEB 2050: - PIC PEB 2052: - EPIC PEB 2055: for up to eight ISDN and 16 analog subscribers. Especially suitable for powerful PABX. for up to eight ISDN and 16 analog subscribers. Ideal for price sensitive systems, e.g. small PABX and public exchanges (CO). for up to 32 ISDN and 64 analog subscribers. Suitable as the central PCM processor in IOM architectures.
- EPIC-2 PEB 2056: for up to 8 ISDN or 16 analog subscribers in IOM architectures. 2.2 Signal Processing Codec / Filter (SICOFI® / SICOFI®-2)
The Codec / Filter used in the advantageous analog line board architecture is the programmable Signal Processing Codec Filter (SICOFI) PEB 2060, fabricated in advanced CMOS technology. Based on Digital Signal Processing (DSP) methods, in addition to the standard functions of PCM coding and voice-band limitation that any codec filter features, the SICOFI provides a variety of user-programmable filters for impedance matching, 2 / 4-wire hybrid balancing, analog and digital gain adjustment as well as frequency response correction.
Semiconductor Group
Overview on Architecture and Devices
Semiconductor Group
Overview on Architecture and Devices
In addition, the DSP technique allows a better and easier shrinking of the device and the implementation of codec / filter functions for two and more subscribers on one chip, which is not economic or completely impossible with switched capacitor methods. The next development stage has produced a Dual Channel Codec Filter (SICOFI-2) PEB 2260 that performs the functions of the SICOFI-1 PEB 2060 for two subscribers in one chip. The sharing of the same digital signal processor part allows a reduced die size per line and leads to reduced line-card costs. Moreover the CMOS device can be programmed to communicate either with SLD (PBC / PIC) or with IOM-2 (EPIC) compatible PCM interface controller. As shown with the SICOFI the DSP approach, in a cost-saving and programmable manner, allows the realization of new functions which would be very expensive or impractical in the analog domain. Optimized Board Controller Concept Circuit Interface SLD SLD Controller PEB 2050 (PCB) with HDLC controller PEB 2052 (PIC) low cost PBC for analog line cards with SICOFI PEB 2055 (EPIC-1) key device for mixed ISDN / Analog systems PEB 2056 (EPIC-2) low cost EPIC Max. Subscriber 16 analog or 8 ISDN 16 analog or 8 ISDN Highways 2 PCM (4 Mbit / s) 1 HDLC 2 PCM (4 Mbit / s)
IOM-2 / (SLD) IOM-2
64 analog or 32 ISDN 16 analog or 8 ISDN
4 PCM (8 Mbit / s)
2 PCM (4 Mbit / s)
Semiconductor Group
Overview on Architecture and Devices
Optimal Solutions for Every Application
Semiconductor Group
Overview on Architecture and Devices
Mixed Use of ISDN and Analog Subscribers with EPIC®
Semiconductor Group
Overview on Architecture and Devices
Advantages of Siemens Semiconductor Analog Line Card Concept
Advanced Signal Processing Codec Filter SICOFI family based on DSP technique. Matching to different line conditions under complete software control (global line-card solution). Modular architecture (IOM-2 / SLD compatible). Reduced line card wiring, per line structure avoids cross wiring. Optimized board controller family. Cost optimized design / high volume production. Effective application support tools (hardware / software).
Semiconductor Group
Signal Processing Codec Filter (SICOFI®)
Features
PEB 2060
CMOS IC
P-LCC-28-R
P-DIP-22
Type PEB 2060-N PEB 2060-P
Version V 4.4 V 4.4
Ordering Code Q67100-H8393 Q67100-Z170
Package P-LCC-28-R (SMD) P-DIP-22
Semiconductor Group
PEB 2060
General Description The Signal Processing Codec Filter (SICOFI) PEB 2060 is a fully integrated PCM codec (coder / decoder) and transmit / receive filter fabricated in advanced CMOS technology for applications in digital telecommunication systems. Based on a digital filter concept, the PEB 2060 provides improved transmission performance and high flexibility. The digital signal processing approach supports software controlled adjustment of the analog behavior, including attractive features such as programmable transhybrid balancing, impedance matching, gain and frequency response correction.
Pin Configuration (top view)
P-LCC-28-R
P-DIP-22
Semiconductor Group
PEB 2060
Pin Definitions and Functions Pin No. P-LCC-28-R P-DIP-22 1 6 5 1 4 3 Symbol V DD V SS GNDA Input (I) Function Output (O) I I I + 5 V power supply - 5 V power supply Ground analog, not internally connected to GNDD All analog signals are referred to this pin Ground digital, not internally connected to GNDA All digital signals are referred to this pin Analog voice input to transmit path Analog voice output of the received digital voice Slave clock Frame synchronisation signal (direction signal) Serial interface port, bidirectional serial data port Reset input, RS forces the SICOFI I to power down mode and initializes the configuration registers I I I I I O O O I / O I / O I / O I / O Test input, normally connected to GNDD Clock selection (see Appendix A) Signaling inputs. Data present at SI is sampled and transmitted via the serial interface Signaling outputs. Data received via the serial interface is latched and fed to these outputs Programmable I / O signaling pins. Each of these pins may be declared input individually with adequate SICOFI status settings. If 2 SICOFIs are connected to 1 serial interface, pin SA (high / low) assigns voice, control and signaling bytes
VIN VOUT SCLK DIR SIP RS
TEST PLL SI1 SI2 SI3 SO1 SO2 SO3 SA SB SC SD
Semiconductor Group
PEB 2060
SICOFI® Principles The SICOFI codec filter solution is a highly digital approach utilizing the advantages of digital signal processing such as excellent performance, high flexibility, easy testing, no sensitivity to fabrication and temperature variations, no problems with crosstalk and power supply rejection.
SICOFI® Signal Flow Graph Transmit Direction The analog input signal is A / D converted, digitally filtered and transmitted either PCM-encoded or linear. Antialiasing is done with a 2nd order Sallen-Key prefilter (PREFI). The A / D Converter (ADC) is a modified slopeadaptive interpolative sigmadelta modulator with a sampling rate of 128 kHz. Digital downsampling to 8 kHz is done by subsequent decimation filters D1 and D2 together with the PCM bandpass filter (BP). Receive Direction The digital input signal is received PCM-encoded or linear, digitally filtered and D / A converted to generate the analog output signal. Digital interpolation up to 128 kHz is done by the PCM lowpass filter (LP) and the interpolation filters I1 and I2. The D / A Converter (DAC) output is fed to the 2nd order Sallen-Key postfilter (POFI). Programmable Functions The high flexibility of the SICOFI is based on a variety of user programmable filters, which are analog gain adjustment AGR and AGX, digital gain adjustment GR and GX, frequency response adjustment R and X, impedance matching filter Z and the transhybrid balancing filter B.
Semiconductor Group
PEB 2060
Signaling SA..SD SI SO 4 PREFI A 3 3 DIR D Interface SCLK SIP S L D B U S
Coeff. RAM VOUT POFI D A
ITB00635
SICOFI® Block Diagram
The SICOFI bridges the gap between analog and digital voice signal transmission in modern telecommunication systems. High performance oversampling Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) provide the conversion accuracy required. An analog antialiasing prefilter (PREFI) and smoothing postfilter (POFI) is included. The dedicated on chip Digital Signal Processor (DSP) handles all the algorithms necessary, e.g. PCM bandpass filtering, sample rate conversion and PCM companding. The three pin serial SLD-Bus interface handles digital voice transmission and SICOFI feature control. Specific filter programming is done by downloading coefficients to the coefficient ram (CRAM). The ten pin parallel Signaling Interface provides for a powerful per line SLIC control.
Semiconductor Group
PEB 2060
Serial Line Data Interface (SLD Interface) The exchange of data on the SLD-Bus is based on a bidirectional, bitserial interface consisting of three pins: SIP, DIR and SCLK. Data is written or read out on the Serial Interface Port SIP under control of the frame synchronization signal DIR with a period of 125 µs). The interface clock frequency supplied at the Slave CLock pin SCLK is 512 kHz). The rate of the serial data stream on the SIP pin is 512 kbit / s, that is 64 bits per each 8 kHz frame). Starting with the rising edge of DIR, four bytes of information are transferred on the SLD-Bus to the SICOFI, followed by four bytes from the SICOFI to the SLD-Bus. Bit 7 (MSB) is the first bit transferred and bit 0 (LSB) is the last one of each byte.
DIR SLD-Bus SIP SIP SIP Channel A Channel A
Receive SICOFI
Transmit SICOFI Signaling Signaling Signaling 125 µ s Channel A Channel A
SLD-Bus Control Signaling
Channel B Channel B
Control Control Control
Channel B Channel B
LIO 00 01 10
Linear Voice Control Signaling
Linear Voice
DIR SCLK SIP Bit 00 Bit 63 Bit 62
LIO : Field LIO (Linear Operating Mode) in CR 3
ITD00636
Byte Sequence and Timing at Serial Interface Port SIP
for applications with other clock rates see Appendix A
Semiconductor Group
PEB 2060
Programming A message-orientated byte transfer is used, due to the fact that the SICOFI needs extended control information. One control byte per frame and direction is transferred. With the appropriate received commands, data can be written to the SICOFI or read from the SICOFI onto the SLD-bus. Data transfer to the SICOFI starts with a write command, followed by up to 8 bytes of data. The SICOFI responds to a read command with the requested information, starting at the next transmission period. If no status modification or data exchange is required a NOP byte is transferred (see Programming Procedure). Control Bytes The 8-bit control bytes consist of either commands, status information or data. There are three different classes of SICOFI commands: NOP SOP COP NO OPERATION: no status modification or data exchange STATUS OPERATION: SICOFI status setting / monitoring COEFFICIENT OPERATION: filter coefficient setting / monitoring
The class of command is selected by Bit 2 and 3 of the control byte as shown below. Due to the extended SICOFI feature control facilities, SOP- and COP-commands contain additional information.
NOP SOP COP
NOP Command If no status modification of the SICOFI or control data exchange is required, a No Operation Byte NOP is transferred.
Semiconductor Group
PEB 2060
SOP Command To modify or evaluate the SICOFI status, the contents of up to four configuration registers CR1, CR2, CR3 and CR4 may be transferred to or from the SICOFI. This is done by a SOPCommand (Status Operation Command).
Address Information
A-SICOFI addressed B-SICOFI addressed This bit is evaluated if two SICOFIs are connected to one SLD-port. A SICOFI is accessed, if AD is consistent with the level at pin SA (see Signaling Byte, Programming Procedure). Write to SICOFI Read from SICOFI Enables reading from the SICOFI or writing information to the SICOFI. sets the SICOFI to power-up mode (operating) resets the SICOFI to power-down (standby mode)
Read / Write Information
Power Up / Power Down (see also CR3) Three Party Conference
The received voice bytes of channel A and channel B are added (A + B). The result is filtered, D / A converted and transferred to analog output VOUT (see also CR3).
Semiconductor Group
PEB 2060
CR1 Configuration Register 1 This configuration register is used for enabling / disabling the programmable digital filters (DB .. RG) and for accessing testmodes (TM1).
Disable B-Filter
B-Filter enabled B-Filter disabled Z-Filter disabled Z-Filter enabled X-Filter disabled X-Filter enabled R-Filter disabled R-Filter enabled GX-GR-Filter disabled GX-GR-Filter enabled
Restore Z-Filter
Restore X-Filter
Restore R-Filter
Restore GX-GR-Filter
Other codes are reserved for future use.
Semiconductor Group
PEB 2060
CR2 Configuration Register 2
Address Mode
Receive (SLD-Bus SICOFI) AM 0 0 1 1 µ / A PCS
SICOFI A channel A channel B channel A channel A + B2)
SICOFI B channel B channel A ------
PCM-law B-Filter Coefficients
A-law µ-law (µ255 PCM) Programmed coefficients Fixed coefficients
The SICOFI transmits the same byte in channel A and B. Three Party Conference.
Semiconductor Group
PEB 2060
CR3 Configuration Register 3
TR LIO
(Change of linear mode becomes valid in the next DIR-cycle).
Semiconductor Group
PEB 2060
CR4 Configuration Register 4
TEST MODES No test mode Additional + 6 dB digital gain in transmit direction (GX) Additional + 12 dB digital gain in transmit direction (GX) Enable on chip tone generation1) Far analog loop back2)
Other codes are reserved for future use.
With the R-filter disabled a 2 kHz, 0 dBm0 sinusoidal signal is fed to the input of the receive Lowpass Filter LP (other frequencies see Appendix B). The output of the X-filter is fed to the input of the R-filter (8 kHz, 16 bit linear).
Semiconductor Group
PEB 2060
COP Command
CODE 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 B-Filter coefficients part 1 B-Filter coefficients part 2 Z-Filter coefficients B-Filter delay coefficients X-Filter coefficients R-Filter coefficients GX- and GR-Filter coefficients) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 4 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 4 bytes of data)
Other codes are reserved for future use.
In the range - 8 dB to 8 dB gain adjustment is possible in steps 0.25 dB
Semiconductor Group
PEB 2060
Signaling Byte The signaling interface of the SICOFI consists of 10 pins. 3 transmit signaling inputs: SI1, SI2 and SI3 3 receive signaling outputs: SO1, SO2 and SO3 4 bidirectional programmable signaling pins: SA, SB, SC and SD Data present at SI1 .. SI3 and possibly at some or all of SA .. SD (if programmed as inputs) are sampled and transferred serially on SIP onto the SLD-bus. Data received serially on SIP from the SLD-Bus are latched and fed to SO1 .. SO3 and possibly to some of SA .. SD if programmed as output. The signaling field format is generally: in receive direction:
SO1 in transmit direction:
SO1 SO2 SO3 X SO1 SO2 SO3 X
SI1 SI2 SI3 SD Z SI1 SI2 SI3 0 Z
SI1 SI2 SI3 SD SI1 SI2 SI3 0
SO1 SO2 SO3 SD X
Semiconductor Group
PEB 2060
Semiconductor Group
PEB 2060
Programming Procedure The following table shows some control byte sequences. If the SICOFI has to be configured completely during initialization, up to 60 bytes will be transferred.
Receive
Transmit
Receive
Transmit
Receive
Transmit
Receive
Transmit
Receive
Transmit
Receive
ITD02445
DB1, DB2 .. DB8 .. coefficient Data Byte 1 .. 8
Semiconductor Group
PEB 2060
Semiconductor Group
PEB 2060
Limit Values typ. max.
dB dB dBm0p dBrnc dBm0p dBrnc
Semiconductor Group
PEB 2060
Attenuation Distortion Attenuation deviations stay within the limits in the figures below.
2.0 dB 1.5
ITD00637
Attenuation
Receive: Reference frequency 1 kHz, input signal level 0 dBm0
Transmit: Reference frequency 1 kHz, input signal level 0 dBm0
Semiconductor Group
PEB 2060
500 µs
ITD00639
70 0.7 0 0.5 1.0 1.5 2.0 2.5 2.8 3.1 3.0 kHz 3.5
Semiconductor Group
PEB 2060
Out-of-Band Signals at Analog Input With an out-of-band sine wave signal with frequency f and level A applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X dB below level A.
ITD00640
Attenuation
ITD00641
Attenuation
Out-of-Band Signals at Analog Output With a 0 dBm0 sine wave of frequency f applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output.
ITD00642
Attenuation
Semiconductor Group
PEB 2060
Gain Tracking (Receive and Transmit) The gain deviations stay within the limits in the figures below
ITD00643
dB 0.5 0.4 0.2 0 0.2 -0.5 0.4 0.25 0.25
-35 -30 -20 -10 0 dBm0 10
Input Level
ITD00644
1.4 0.5 0.2 -0.2 -0.5 -1.4 -55 3 -50 -40 -30 -20 -10 0 dBm0 10 Input Level
Semiconductor Group
PEB 2060
Total Distortion The signal-to-distortion ratio exceeds the limits in the following figures.
ITD00645
20 14.7 10 -55 0 -60 -50 -40 -34 -27 -24 -30 -20 Input Level -6 -3 -10 dBm0 0
Receive: Measured with noise signal according to CCITT recommendations
ITD00646
20 13.7 10 -55 0 -60 -50 -40 -34 -27 -24 -30 -20 -6 -3 -10 dBm0 0
Input Level
Transmit: Measured with noise signal according to CCITT recommendations
Semiconductor Group
PEB 2060
The signal to distortion ratio exceeds the limits in the following figures.
ITD00647
29.5 A - LAW
10 -45 0 -60 -50 -40 -28 -30 -20 Input Level -10 dBm0 0
Receive & Transmit: Measured with sine wave in the range 700 to 1100 Hz excluding submultiples of 8 kHz
Signal to Total Distortion CCITT Noise Signal Digital-Digital (A-law and µ-law) Parameter Input Level Unit Digital Loop Back via B-Filter or Digital Loop Back via Analog port 0 - 30 - 40 - 45 dBm0 dBm0 dBm0 dBm0 Total Distortion min. 31 31 25 20 Unit dB dB dB dB
Semiconductor Group
PEB 2060
Parameter Transhybrid loss at 500 Hz Transhybrid loss at 2500 Hz Transhybrid loss at 3000 Hz Transhybrid loss at 500 Hz Transhybrid loss at 2500 Hz Transhybrid loss at 3000 Hz Transhybrid loss at 500 Hz Transhybrid loss at 2500 Hz Transhybrid loss at 3000 Hz
Symbol THL500 THL2500 THL3000 THL500 THL2500 THL3000 THL500 THL2500 THL3000
Limit Values min. 33 29 27 29 27 25 27 25 23 typ. 45 40 35 40 35 30 40 35 30
Unit dB dB dB dB dB dB dB dB dB
Semiconductor Group
PEB 2060
Semiconductor Group
PEB 2060
Limit Values min. - 0.3 2.0 0.45 1 max. 0.8
Test Condition
Limit Values min. 10 10
Test Condition
Semiconductor Group
PEB 2060
t SCLK
t DIRxS
t DIRxH
t SCLK 2 t DINxS
SIP Data IN SIP Data OUT
t SCLK 2 t DINxH
t dOUT
t dDHZ
High Imp.
ITT00649
Unit max.
Semiconductor Group
PEB 2060
SCLK SIP Data IN
Last Signaling Bit IN
t dSIG OUT
SIG OUT SIP Data IN
Last Control Bit IN
t dSIGZ
SIG OUT
t SIG INxS
SIG IN SIP Data IN
t SIG INxH
Last Control Bit OUT
First Signaling Bit OUT
ITD02446
Pins SO1 .. SO3 Pins SA .. SD as output Pins SI1 .. SI3 Pins SA .. SD as input SICOFI is ready to accept SOP / COP commands in the next DIR Cycle. Spikes shorter than 244 ns will be ignored.
Semiconductor Group
PEB 2060
Appendix A Specific Interface Types The SICOFI can be used with three different SLD-bus type interfaces. A specific interface type is selected with three pins: TEST, SI3 and PLL.
TEST 0
DIR SCLK MCLK SIP Data
ITD00651
1) SLD-Bus Interface1)
TEST 1
SI3) 0
SI3 cannot be used as Signaling Pin
DIR SCLK MCLK SIP Data
ITD00652
2) SLD-Bus Interface with Variable Clock Frequencies 2)
Semiconductor Group
PEB 2060
TEST 1
SI3) 0
SI3 cannot be used as Signaling Pin
DIR SCLK MCLK SIP Data
ITD00653
3) Burst Mode Interface1)
Semiconductor Group
PEB 2060
In burst-mode 8- or 16-bit bursts are received or transmitted, depending on the linear mode selected (see field LIO in CR3).
Voice A
Voice B
Control
Signaling
Voice A
Voice B
Control
Signaling
MSB + LSB Detail A
MSB + LSB
ITD00654
ITD00655
Detail A A.. B.. MSB .. LSB .. voice A C .. control voice B S .. signaling bit 15-8 of linear in- or output bit 7-0 of linear in- or output
Semiconductor Group
PEB 2060
ITD00656
Semiconductor Group
Dual Channel Codec Filter (SICOFI®-2)
PEB 2260 PEF 2260
CMOS IC
Features
Dual channel single chip codec and filter Band limitation according to all CCITT and AT&T recommendations Digital signal processing techniques PCM encoded digital voice transmission (A-law or µ-law) Programmable digital filters for - impedance matching - transhybrid balancing - gain - frequency response correction Two digital Interfaces - three pin serial SLD Interface (eg. to PEB 2050 / 52) - four pin serial IOM®-2 Interface with two different clock-frequencies and time-slot assignment (e.g. to PEB 2055 / 56)
P-LCC-28-R
Programmable signaling interface to peripherals (e.g. SLIC) q High performance A / D and D / A conversion q Programmable analog gain adjustment q Advanced test capabilities - three digital loop back modes - two analog loop back modes - two programmable tone generators
No trimming or adjustments No external components Advanced low power 2µCMOS technology Power supply + / - 5 V Meets or exceeds CCITT and LSSGR recommendations Two types are available: - PEB 2260 with standard temperature range 0..70oC - PEF 2260 with extended temperature range -40..85oC
Type PEB 2260-N PEF 2260-N
Version V 2.0 V 2.0
Ordering Code Q67100-H6191 Q67100-H6261
Package P-LCC-28-R (SMD) P-LCC-28-R (SMD)
Semiconductor Group
PEB 2260 PEF 2260
General Description The Dual Channel Codec Filter PEB 2260 (SICOFI®-2) is a fully integrated PCM codec and filter fabricated in low power 2µCMOS technology for applications in digital communication systems. Based on an advanced digital filter concept, the PEB 2260 provides excellent transmission performance and high flexibility. The digital signal processing approach includes attractive programmable features such as transhybrid balancing, impedance matching, gain and frequency response correction.
Pin Configuration for SLD Mode (top view)
Pin Configuration for IOM®-2 Mode (top view)
Semiconductor Group
PEB 2260 PEF 2260
VINA VOUTA VINB VOUTB MODE SCLK DIR SIP RS SI1A SI2A SI3A SI1B SI2B SI3B
Signaling inputs: data present at SI1A .. SI3B are sampled and transmitted via the serial interface
Semiconductor Group
PEB 2260 PEF 2260
Pin Definitions and Functions for SLD Interface Mode (continued) Pin No. Symbol 5 6 7 11 10 9 4 12 SO1A SO2A SO3A SO1B SO2B SO3B SBA SBB Input (I) Output (O) O O O O O O I / O I / O Bidirectional signaling pins: SBA, SBB pins may be programmed as input or output individually with adequate SICOFI-2 status settings Signaling outputs: data received via the serial interface are latched and fed to SO1A .. SO3B Function
VINA VOUTA VINB VOUTB MODE
Semiconductor Group
PEB 2260 PEF 2260
Pin Definitions and Functions for IOM®2 Interface Mode (continued) Pin No. Symbol 21 20 19 18 23 28 16 5 6 26 11 10 2 4 14 12 7 9 DCL FSC DU DD RS I1A I1B C1A C2A C3A C1B C2B CI1A CI2A CI1B CI2B TS1 TS2 Input (I) Output (O) I I O I I I I O O O O O I / O I / O I / O I / O I I Time-slot selection pins 1 .. 2 with ternary logic Bidirectional command / indication pins: CI1A .. CI2B may be programmed as input or output individually with adequate SICOFI-2 status settings Command outputs: data received via the serial interface are latched and fed to C1A .. C3A and C1B .. C2B Function Data clock, 512 kHz or 4096 kHz Frame synchronisation clock, 8 kHz Data upstream Data downstream Reset input, RS forces the SICOFI-2 to basic setting mode Indication inputs: data present at I1A .. I1B are sampled and transmitted via the serial interface
Semiconductor Group
PEB 2260 PEF 2260
SICOFI®-2 Principles The SICOFI-2 codec filter solution is a highly digital approach utilizing the advantages of digital signal processing such as excellent performance, high flexibility, easy testing, no sensitivity to fabrication and temperature variations, no problems with crosstalk and power supply rejection.
PREFI
PCMOUT
Transmit
Receive
PCMIN
ITS02447
SICOFI®-2 Signal Flow Graph (for either channel) Transmit Direction The analog input signal is A / D converted, digitally filtered and transmitted PCM-encoded. Antialiasing is done with a 2nd order Sallen-Key prefilter (PREFI). The A / D Converter (ADC) is a modified slopeadaptive interpolative sigma-delta modulator with a sampling rate of 128 kHz. Digital downsampling to 8 kHz is done by subsequent decimation filters D1 and D2 together with the transmit PCM lowpass filter (LPX). Receive Direction The digital input signal is received PCM-encoded, digitally filtered and D / A converted to generate the analog output signal. Digital interpolation up to 128 kHz is done by the receive PCM lowpass filter (LPR) and the interpolation filters I1 and I2. The D / A Converter (DAC) output is fed to the 2nd order Sallen-Key postfilter (POFI). Programmable Functions The high flexibility of the SICOFI-2 is based on a variety of user programmable filters, which are analog gain adjustment AGR and AGX, digital gain adjustment GR and GX, frequency response adjustment R and X, impedance matching filter Z and the transhybrid balancing filter B.
Semiconductor Group
PEB 2260 PEF 2260
SLIC-Interface DIR / FSC VIN A Channel A VOUT A POFI DAC DSP VIN B Channel B VOUT B POFI DAC
ITB00659
PREFI
ADC SLD / IOM -2 Interface
SCL / DCL SIP / DU DD
PREFI
ADC Coeff. RAM
SICOFI®-2 Block Diagram
The SICOFI-2 bridges the gap between analog and digital voice signal transmission in modern telecommunication systems. High performance oversampling Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) provide the conversion accuracy required. Analog antialiasing prefilters (PREFI) and smoothing postfilters (POFI) are included. The dedicated on chip Digital Signal Processor (DSP) handles all the algorithms necessary, e.g. PCM bandpass filtering, sample rate conversion and PCM companding. The SLD or IOM-2 Interface handles digital voice transmission, SICOFI-2 feature control and access to the SICOFI-2 signaling pins. Specific filter programming is done by downloading coefficients to the coefficient ram (CRAM).
Semiconductor Group
PEB 2260 PEF 2260
DIR SCLK SIP Channel A
Receive SLD - Bus Channel B SICOFI - 2 Control Signaling Channel A
Transmit SICOFI - 2 Channel B
SLD - Bus Control Signaling
DIR SCLK
Bit 00
Bit 63
Bit 62
ITD02448
Semiconductor Group
PEB 2260 PEF 2260
IOM®-2 Interface The IOM-2 interface consists of two data lines and two clock lines. DU (data upstream) carries data from the SICOFI-2 to a master device. DD (data downstream) carries data from the master device to the SICOFI-2. A 8 kHz FSC (frame synchronization clock) signal as well as a 512 kHz or 4096 kHz DCL (data clock) signal is supplied. The SICOFI-2 implements all functions for analogue devices as described in the IOM-2 specification.
125 µ s FSC DCL 512 kHz DD DU Detail A B1 B1 B2 B2 MONITOR Data MONITOR Data C / I 6:1 C / I 6:1 MM R X MM R X
ITD02449
125 µ s FSC DCL 4096 kHz DD DU CH0 CH0 Detail A CH1 CH1 CH2 CH2 Detail B CH3 CH3 CH4 CH4 CH5 CH5 CH6 CH6 CH7 CH7
ITD02450
Semiconductor Group
PEB 2260 PEF 2260
ITD02451
Detail A
MONITOR Data
ITD02452
Detail B
Semiconductor Group
PEB 2260 PEF 2260
IOM®-2 MONITOR Channel Data Structure The MONITOR channel is used for the transfer of maintenance information between two functional blocks. By use of two MONITOR control bits (MR and MX) per direction, the data are transferred in a complete handshake procedure. The messages transmitted in the MONITOR channel may have different kinds of data structures. Therefore, the first byte of the message is used to indicate the structure of the following data. Messages to and from the SICOFI-2 are started with the following byte:
Thus providing information for two analog lines, the SICOFI-2 is one device on one IOM-2 channel. MONITOR data for a specific analog channel is selected by the SICOFI-2 specific command following. For more details on IOM-2 MONITOR channel data structure, and an IOM-2 specific identification command see Appendix B.
Semiconductor Group
PEB 2260 PEF 2260
Programming A message oriented byte transfer is used, due to the fact that the SICOFI-2 needs extended control information. With the appropriate commands, data can be written to the SICOFI-2 or read from the SICOFI-2 via the SLD or via the IOM-2 interface monitor channel. Data transfer to the SICOFI-2 starts with a write command, followed by up to 8 bytes of data. The SICOFI-2 responds to a read command with the requested information, that is up to 8 bytes of data. (see Programming procedure). The same command structure is used both in SLD and IOM-2 interface mode. If the SICOFI2 is operating in IOM-2 interface mode, any new command sequence starts with a SICOFI-2 specific address-byte. The following command is the same in SLD and IOM-2 mode. If the command requests an answer, in SLD mode the SICOFI-2 will start immediately (next transmission period) with the requested data. In IOM-2 mode the SICOFI-2 specific address byte will be sent first, followed by the requested data. Attention: In IOM-2 mode, each byte on the monitor channel, is sent twice at least.
Example for a programming sequence in SLD and IOM-2 interface mode: SLD Interface Receive SOP-Write CR2 CR1 SOP-Read Transmit Receive Address SOP-Write CR2 CR1 SOP-Read Address CR2 CR1 IOM-2 Interface Transmit
CR2 CR1
Semiconductor Group
PEB 2260 PEF 2260
Control Bytes The 8-bit control bytes consist of either commands, status information or data. There are three different classes of SICOFI-2 commands: NOP SOP COP NO OPERATION: STATUS OPERATION: COEFFICIENT OPERATION: no status modification or data exchange SICOFI-2 status setting / monitoring filter coefficient setting / monitoring
The class of command is selected by bit 3 and 2 of the control byte as shown below.
NOP SOP COP
Due to the extended SICOFI-2 feature control facilities, SOP and COP commands contain additional information for programming and verifying the SICOFI-2.
Programmable Devices 3 configuration registers per channel: 1 coefficient ram per channel: 1 common configuration register: CR1, CR2, CR3 CRAM CR4 is only available in IOM-2 mode the contents of CR4 is valid for both channels
To obtain more clarity, bit fields containing different informations for SLD and IOM-2 interface are high lighted in subsequent chapters.
Semiconductor Group
PEB 2260 PEF 2260
NOP Command If no status modification of the SICOFI-2 is required, a no operation byte NOP may be transferred.
NOP receive, not useful in IOM-2 interface mode
NOP transmit, only available in SLD interface mode
VERSION
PDA PDB VERSION
if channel A is in power-down mode if channel A is in power-up mode if channel B is in power-down mode if channel B is in power-up mode
Semiconductor Group
PEB 2260 PEF 2260
SOP Command To modify or evaluate the SICOFI-2 status, the contents of up to three (four) configuration registers CR1, CR2, CR3 (and CR4) may be transferred to or from the SICOFI-2. This is done by a SOP-Command (status operation command). In SLD interface mode three configuration registers per channel are accessible. If the SICOFI-2 is operating with IOM-2 interface an additional fourth configuration register (CR4) can be written or read.
forces SICOFI-2 to enter the Basic Setting Mode (see Operating Modes).
Commands concerning CR4 are independent of bit AD in SOP command.
Semiconductor Group
PEB 2260 PEF 2260
CR1 Configuration Register 1 Configuration register CR1 defines the basic SICOFI-2 settings, which are: enabling / disabling the programmable digital filters, programming of signaling pins, and selection of the PCM companding characteristics.
Semiconductor Group
PEB 2260 PEF 2260
CR2 Configuration Register 2 Configuration register CR2 sets analog gain control and enables two on-chip tone- generators. In IOM-2 operating mode two bidirectional command / indication pins are controlled.
Semiconductor Group
PEB 2260 PEF 2260
CR3 Configuration Register 3 This register is for accessing testmodes only
Semiconductor Group
PEB 2260 PEF 2260
CR4 Configuration Register 4 (available in IOM®-2 interface mode only) Register CR4 configures the data-upstream command / indication channel. The content of CR4 is valid for both channels A and B.
Update Interval Time Persistance checking is disabled Upstream transmission after 1 ms Upstream transmission after 2 ms . . Upstream transmission after 14 ms Upstream transmission after 15 ms
Semiconductor Group
PEB 2260 PEF 2260
Detector Select Sampling Interval T SLICs with multiplexed loop- and ground-key-status, which have a single status output pin for carrying the loop- and ground-key-status information, need a special detector select input .
C / I 1 2 3 SLIC Detector Select Control C3A Indication Upstream
Loop / GND Key Input from SLIC
CI2A SLIC-A
SLIC-B Programmable T ) I1B Loop / GND Key Input from SLIC
CI2B -
SICOFI -2 ) Connection available with 512-kHz IOM -2 Interface only
ITS02453
Semiconductor Group
PEB 2260 PEF 2260
Semiconductor Group
PEB 2260 PEF 2260
COP Command With a COP Command coefficients for the programmable filters can be written to the SICOFI-2 coefficient ram or transmitted on the SLD or IOM-2 interface for verification
CODE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 0 B-Filter coefficients part 1 B-Filter coefficients part 2 Z-Filter coefficients B-Filter delay coefficients X-Filter coefficients R-Filter coefficients GX-Filter coefficients GR-Filter coefficients (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 4 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 4 bytes of data)) (followed by 2 bytes of data))
All other codes are reserved for future use.
) In the range of 0 to 8 dB (0 to - 8 dB) gain adjustment is possible in steps 0.25 dB
Semiconductor Group
PEB 2260 PEF 2260
SLIC Interface The connection between SICOFI-2 and a SLIC is performed by the SICOFI-2 signaling and command / indication pins. In SLD interface mode, the receive signaling byte is transferred to the signaling output pins. Data present at signaling input pins are transferred to the transmit signaling byte. Operating the SICOFI-2 with IOM-2 interface, data received from the downstream C / I byte are transferred to command output pins (C, C / I). Data on input pins (I, C / I) are transferred to the upstream C / I-byte. SLD Interface Signaling Byte The SICOFI-2 offers a 7 pin parallel signaling interface per channel. Channel A: SI1A, SI2A, SI3A SO1A, SO2A, SO3A SBA SI1B, SI2B, SI3B SO1B, SO2B, SO3B SBB signaling input pins signaling output pins programmable bidirectional signaling pin. signaling input pins signaling output pins programmable bidirectional signaling pin.
Channel B:
Data present at SI1A .. SI3B and SBA, SBB (if programmed as input) are sampled and transferred to the SLD bus. Data received from the SLD bus are latched and fed to SO1A .. SO3B and SBA, SBB (if programmed as output). Signaling byte format in receive direction:
SBB1)
SBA1)
Signaling byte format in transmit direction:
SBB2)
SBA2)
Semiconductor Group
PEB 2260 PEF 2260
The four possible cases of the signaling byte format are listed below. Case 1 2 3 4 Receive Signaling Byte 7 SBB X SBB X 6 SO3B SO3B SO3B SO3B 5 SO2B SO2B SO2B SO2B 4 SO1B SO1B SO1B SO1B 3 SBA SBA X X 2 SO3A SO3A SO3A SO3A 1 SO2A SO2A SO2A