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Operating Range 5.5-V EPIC (Enhanced-Performance Implanted CMOS) Proce


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SN54AHC244, SN74AHC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Operating Range 5.5-V EPIC (Enhanced-Performance Implanted CMOS) Process High Latch-Up Immunity Exceeds JESD Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), Ceramic Flat Packages, Ceramic Chip Carriers (FK), Standard Plastic Ceramic 300-mil DIPs
SN54AHC244 PACKAGE SN74AHC244 DGV, PACKAGE (TOP VIEW)
description
These octal buffers/drivers designed specifically improve performance density 3-state memory-address drivers, clock drivers, bus-oriented receivers transmitters. 'AHC244 organized 4-bit buffers/line drivers with separate output-enable (OE) inputs. When low, device passes data from inputs outputs. When high, outputs high-impedance state. SN54AHC244 characterized operation over full military temperature range -55°C 125°C. SN74AHC244 characterized operation from -40°C 85°C.
FUNCTION TABLE (each buffer) INPUTS OUTPUT SN54AHC244 PACKAGE (TOP VIEW)
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC244, SN74AHC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
logic symbol
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
logic diagram (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Note -0.5 Input clamp current, Output clamp current, VCC) Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 115°C/W package 146°C/W package 97°C/W package 67°C/W package 128°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD except through-hole packages, which trace length zero.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC244, SN74AHC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54AHC244 Supply voltage High-level input voltage High Low-level input voltage Input voltage Output voltage High-level output current High Low-level output current 3.85 1.65 SN74AHC244 3.85 1.65 UNIT
ns/V
Input transition rise fall rate
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS Data inputs Control inputs GND, (OE) GND, 25°C 2.58 3.94 0.36 0.36 ±0.1 ±0.1 ±0.25 SN54AHC244 2.48 ±2.5 SN74AHC244 2.48 0.44 0.44 ±2.5 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC244, SN74AHC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
SN54AHC244 PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 10.3 10.3 10.6 10.6 11.9 11.9 14.1 14.1 12.5 12.5 13.5 13.5 UNIT
products compliant MIL-PRF-38535, this parameter ensured production tested.
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
SN74AHC244 PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 10.3 10.3 10.6 10.6 11.9 11.9 14.1 14.1 12.5 12.5 13.5 13.5 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC244, SN74AHC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
SN54AHC244 PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 10.5 10.5 10.5 10.5 UNIT
products compliant MIL-PRF-38535, this parameter ensured production tested.
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
SN74AHC244 PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 10.5 10.5 10.5 10.5 UNIT
output-skew characteristics, (see Note
SN74AHC244 PARAMETER 25°C UNIT
tsk(o)
Output skew
NOTE Characteristics determined during product characterization ensured design.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC244, SN74AHC244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
noise characteristics, 25°C (see Note
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic Quiet output, minimum dynamic Quiet output, minimum dynamic High-level dynamic input voltage SN74AHC244 -0.2 UNIT
VIL(D) Low-level dynamic input voltage NOTE Characteristics determined during product characterization ensured design surface-mount packages only.
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load, UNIT
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open
LOAD CIRCUIT Input tPLH In-Phase Output tPHL Out-of-Phase Output VOLTAGE WAVEFORMS DELAY TIMES tPHL tPLH Output Waveform (see Note Output Control (low-level enabling) Output Waveform (see Note tPZL tPZH tPLZ tPHZ
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated

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