SCEA003 Application Report GTL/BTL: Low-Swing Solution High-

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SCEA003 Application Report GTL/BTL: Low-Swing Solution High-

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Printed U.S.A. 1096-CP
SCEA003
Application Report
GTL/BTL: Low-Swing Solution High-Speed Digital Logic
SCEA003 September 1996
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated
Contents
Title Page Introduction Test Setup Advantages Over CMOS/TTL Family Input Output Structure Family Input Output Structure Power Consumption Simultaneous Switching Output Capacitance Slew Rate Signal Integrity Design Considerations Summary References
List Illustrations
Figure Title Page Backplane Model With Four Boards Connected Point-to-Point Model With Only Driver Receiver Connected Typical Input Output Cells Typical Input Output Cells FB1650 GTL16612 Power Consumption With Outputs Switching FB1650 High Output Voltage Peak Valley Noise Unswitched Output GTL16612 High Output Voltage Peak Valley Noise Unswitched Output FB1650 Output Voltage Peak Valley Noise Unswitched Output GTL16612 Output Voltage Peak Valley Noise Unswitched Output Capacitance Variation Across Process FB1650 Fall Time Measured Between GTL16612 Fall Time Measured Between FB1650 Rise Time Measured Between GTL16612 Rise Time Measured Between FB1650 Signal Integrity Receiver Input Using Different-Length Cables GTL16612 Signal Integrity Receiver Input Using Different-Length Cables Proposed Circuit Generate
Introduction
This application report examines requirements low-swing interface high-speed digital systems well this need addressed interface standards: backplane transceiver logic (BTL) Gunning transceiver logic (GTL). Both interface standards attempt improve performance high-speed digital systems reducing difference between logic high-voltage level logic low-voltage level. comparison various performance criteria, such power consumption, noise immunity, capacitive loading, speed, packaging, shows that provide compelling solution both point-to-point backplane environments. Guidelines system designs using Texas Instruments (TI) products addressed, including associated voltage supplies proper termination techniques.
Test Setup
GTL16612 FB1650 were used study various performance levels. backplane-like design been established perform laboratory work supporting this application report. Four boards with 2-in. stubs interconnecting transmission lines were used simulate backplane environment. 50-MHz frequency used unless otherwise noted. output supply voltage (VTT) supplied through resistor each backplane (50- BTL) both families specified both IEEE (BTL) JEDEC (GTL) standards. Figure shows backplane model with four boards connected.
Receiver Driver Receiver Receiver
3-Bit
Figure Backplane Model With Four Boards Connected Another design been used simulate transmission-environment effect when transferring data across longer point-to-point transmission line. Figure shows same backplane model with only driver receiver used transfer data across 12-in., 28-in., 48-in. transmission lines.
Driver Receiver
12-in., 28-in., 48-in. Transmission Line
Figure Point-to-Point Model With Only Driver Receiver Connected
Advantages Over CMOS/TTL
were developed solve bus-driving problem associated with enhance performance point-to-point backplane applications. also eliminate need extra time required signal settle reflection noise generated when switching. swing both signals versus swing CMOS signals helps reduce noise generated when outputs switching simultaneously. Table shows minimum high-level output voltage (VOH) maximum low-level output voltage (VOL) CMOS, TTL, BTL, signals. Table Levels Various Families
LOGIC LEVEL CMOS VOHmin VOLmax 0.44 0.55
buffers designed with minimal output capacitance maximum) compared output buffer typical). CMOS output capacitance, coupled with capacitance connectors, traces, vias reduces characteristic impedance backplane. high-frequency operation, this phenomenon makes difficult CMOS driver switch signal incident wave. CMOS device needs higher drive current than presently available able switch signal under these conditions. However, increasing output drive clearly increases output capacitance. This scenario again reduces characteristic impedance even more. That lower signal-swing family with reduced output capacitance, such GTL, recommended when designing high-speed backplanes.
Family Input Output Structure
input receiver differential comparator with side connected externally provided reference voltage, VREF (0.8 typical). threshold designed with precise window maximum noise immunity (VIH VREF VREF mV). output driver open-drain n-channel device which, when turned off, pulled output supply voltage (VTT typical). When turned device sink current (IOL) maximum output voltage (VOL) output designed transmission line terminated both ends (25- total load). inputs outputs designed work independently device's VCC. They communicate with devices designed 5-V, 3.3-V, even 2.5-V VCC. input tolerant 3.3-V CMOS inverter that interface with signals. hold also provided port eliminate need external resistors when inputs outputs unused floating. output bipolar output. similar output structure.1 this time, devices require power supplies function: supply [VCC(5)] 3.3-V supply [VCC(3.3)] LVTTL. supply used only GTL16612 GTL16616. maximum operating frequency family (GTL16612 GTL16616). future-generation family, which will available mid-1996, will operate both directions (GTL GTL) will have single 3.3-V power supply.1 Figure shows typical input output circuit.
Input Stage
Bias Voltage
Output Stage
Bias Voltage
VREF
VOUT
Figure Typical Input Output Cells
Family Input Output Structure
input receiver differential amplifier with side connected internal reference voltage. threshold designed with narrow window (VIH 1.62 1.47 Unlike GTL, requires separate supply voltage threshold circuit eliminate noise generated switching outputs. output driver open-collector output with termination resistor selected match impedance. When device turned off, output pulled output supply voltage (VTT typical). inputs outputs work independently device's VCC. They communicate with devices designed 3.3-V VCC. input CMOS inverter, output bipolar output similar output structure.1 requires three power supplies: main power supply (VCC), bias generator supply VCC), bias supply voltage (BIAS VCC) that establishes voltage between 1.62 outputs when connected. maximum operating frequency family MHz, depending application well board layout. Figure shows typical input output circuit.
Input Stage Output Stage
VOUT
VREF
Figure Typical Input Output Cells
Power Consumption
Several factors influence power consumption device: frequency operation, number outputs switching, load capacitance, number TTL-level inputs, junction temperature, ambient temperature, thermal resistance device. devices, output power supplied externally output voltage supply (VTT). maximum operating frequency limited thermal characteristics package. provides package power-dissipation information data sheets under "absolute maximum ratings". These values calculated using junction temperature 150°C board trace length mils airflow).3 Traces, power planes, connectors, cooling fans play important role improving heat dissipation. Figure shows power consumption devices driving backplane described above. frequency increases, GTL16612 power consumption does increase fast FB1650. This characteristic predominant CMOS technology, lower drive current, lower voltage swing (0.8-V swing versus swing BTL). Lower drive current lower voltage swing benefits that provides over drivers. power-consumption comparison (see Table illustrates advantage over when active inputs outputs switching.2 Another benefit offers that family uses common 56-pin SSOP TSSOP packages rather than 100-pin thin quad flat package (TQFP) with heat slug mounted above parts. count TQFP package almost twice count SSOP TSSOP packages.
25°C, outputs switching
ICC- Input Current GTL16612 FB1650
Frequency
Figure FB1650 GTL16612 Power Consumption With Outputs Switching Table Power Comparison (160 Active Inputs Outputs)
TECHNOLOGY POWER TERMINATION (BOTH ENDS)
Simultaneous Switching
given digital circuit, there large change current over very short time when multiple outputs switch simultaneously. this increased current flows through bond wires leadframe, develops voltage across wire's inductance. This feedback mechanism known simultaneous switching noise (SSN). This noise manifests itself voltage bounce package pin(s). From basic circuit analysis, induced voltage across inductor defined Where: Inductance di/dt Rate change current current through output dependent voltage level load output, which expressed mathematically
Analysis equations clearly shows that because lower voltage swing, offer better noise immunity compared CMOS outputs. speed today's circuits increases, current rate change (di/dt) increases does susceptibility SSN, i.e., voltage bounce (GND VCC). standard methodology devised industry measure voltage bounce keep output either logic high (VOH) logic (VOL) switch other outputs predefined frequency. Figures through compare both noise immunity outputs switching simultaneously.
25°C, BIAS
FB1650 VOHV VOHP
Outputs Switching
Channel mV/div, Timebase ns/div, VOHV 1.94 VOHP 2.26
Figure FB1650 High Output Voltage Peak Valley Noise Unswitched Output
25°C, VCC(5) VCC(3.3)
GTL16612 VOHP
Outputs Switching
VOHV
Channel mV/div, Timebase ns/div, VOHV 1.13 VOHP 1.58
Figure GTL16612 High Output Voltage Peak Valley Noise Unswitched Output
25°C, BIAS
FB1650 Outputs Switching VOLP Channel mV/div Timebase ns/div VOLV 0.97 VOLP
VOLV
Figure FB1650 Output Voltage Peak Valley Noise Unswitched Output
25°C, VCC(5) VCC(3.3)
GTL16612 Outputs Switching VOLP
VOLV Channel mV/div Timebase ns/div VOLV 0.02 VOLP 0.41
Figure GTL16612 Output Voltage Peak Valley Noise Unswitched Output
Output Capacitance
devices designed meet 5-pF capacitance their input output ports port). Figure shows variation output capacitance across both processes.
25°C, unused inputs biased
Capacitance
Port
Figure Capacitance Variation Across Process
Slew Rate
Slew rate plays important role backplane point-to-point application designs. slower output slew rate device, less susceptible signal reflections noise. Using backplane model (see Figures output slew rate driving device taken under following conditions: 10-in., transmission line single termination receiver end. Figures through show rise fall times both devices taken between specified voltages BTL. Both slew rates acceptable.
25°C, BIAS Frequency
FB1650
Channel mV/div, Timebase ns/div, 1.51 (distance between driver receiver in.)
Figure FB1650 Fall Time Measured Between
25°C, VCC(5) VCC(3.3) Frequency
GTL16612
Channel mV/div, Timebase ns/div, 2.05 (distance between driver receiver in.)
Figure GTL16612 Fall Time Measured Between
25°C, BIAS Frequency
FB1650 Channel mV/div, Timebase ns/div, 1.27 (distance between driver receiver in.)
Figure FB1650 Rise Time Measured Between
25°C, VCC(5) VCC(3.3) Frequency
GTL16612
Channel mV/div, Timebase ns/div, 2.05 (distance between driver receiver in.)
Figure GTL16612 Rise Time Measured Between
Signal Integrity
Figures show signal integrity data propagating across transmission line using three cable lengths in., in., in.). clock frequency MHz. measurement taken receiver cable. output waveform kept input square-wave shape better than waveform has. cable termination resistors used this laboratory precisely matched; that small reflection seen outputs when switching high. real systems, where both termination resistor traces matched, these reflections will reduced.
25°C, BIAS Frequency
FB1650
Channel mV/div, Timebase ns/div Distance between driver receiver: in., in.,
Figure FB1650 Signal Integrity Receiver Input Using Different-Length Cables
25°C, VCC(5) VCC(3.3) Frequency
GTL16612
Channel mV/div, Timebase ns/div Distance between driver receiver: in., in.,
Figure GTL16612 Signal Integrity Receiver Input Using Different-Length Cables
Design Considerations
successfully design with family, several rules techniques with regard voltage generation proper termination must followed. First, both 3.3-V needed present generation devices (only 3.3-V will needed next-generation GTL). Second, termination voltage (VTT should regulated from VCC, keeping mind current requirements outputs output). There several linear regulators that capable performing this function. Depending design, regulator could either backplane itself individual cards. Third, reference voltage (VREF must generated from VTT. VREF voltage generated using simple voltage-divider circuit with appropriate bypass capacitor (0.01 placed close possible VREF pin. VREF input circuitry consumes very little power maximum). This enables several devices have their VREF connected same voltage-divider circuit, thus eliminating need multiple voltage-divider circuits (see Figure 17).
VREF
Figure Proposed Circuit Generate VREF family, four power supplies grounds connected. live-insertion applications, power-up sequence should should make contact first, followed BIAS VCC. This sequence will precharge board device capacitance will establish voltage between 1.62 outputs. Next, makes contact and, ramps BIAS circuitry starts turn off. When reaches final value, BIAS circuitry completely isolated does interfere with device functionality. pins supply power bias generator input circuitry. must isolated from other power supplies ensure signal integrity input. 2.1-V should regulated from higher voltage should supply enough current switch outputs (100 output). variation should exceed recommended that proper bypass capacitors (0.01 used. termination resistor should exceed resistance value. Table gives designer estimate maximum number loads allowed when designing with families.4 Note that crosstalk poor board layout degrade overall quality backplane, thereby affecting number loads. Using formula:
assuming (for worst case condition), maximum number loads backplane calculated
follows: Where: Rise time device (ns) Fall time device (ns) Output impedance source GTL, 16.5 Characteristic capacitance unit length transmission line (pF/in.) (see Table Length backplane (in.) Maximum number loads backplane Capacitance each load (pF), device, connector Pulse width signal (ns) Frequency signal backplane (MHz)
Table Typical Strip-Line Characteristics
DIMENSIONS (mils) LINE IMPEDANCE MAXIMUM NUMBER LOADS CAPACITANCE (pF/in.) 6.67 5.83 5.58 4.75 4.67 3.25 2.92 (ns/in.) 0.18 0.186 0.189 0.176 0.187 0.172 0.176 0.179 0.179 0.178
characteristic impedance strip line based following: relative dielectric constant board material (G10 glass epoxy) thickness insulation dielectric cross-sectional length strip line cross-sectional width strip line Frequency signal backplane MHz.
Summary
Today's high-speed backplane point-to-point applications require devices that provide high performance, excellent signal integrity, cost effectiveness. transceivers designed meet these characteristics. Both transceiver families show similar skew, slew rate, performance. generally used heavily loaded backplanes (100-mA IOL) frequencies less than MHz. However, laboratory data presented this report show that more suitable designs that require high performance present family future generation) power consumption cost minimum board space.
References
1Texas Instruments Incorporated, Advanced BiCMOS Technology Data Book, 1994, literature number SCBD002B. 2Gunning, Bill; Yuan, Leo; Nguyen, Trung; Wong, Tony, GTL: Low-Voltage Swing Transmission Line Transceiver,
March 1991.
3Texas Instruments Incorporated, "Package Thermal Considerations", Advanced BiCMOS Technology Data Book, 1994,
literature number SCBD002B, 13-97.
4Texas Instruments Incorporated, Advanced Schottky Load Management, 1987, literature number SDAA006.

SCEA003 Application Report GTL/BTL: Low-Swing Solution High-

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