State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

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State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

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SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Protection Exceeds 2000 MIL-STD-883, Method 3015; Exceeds Using Machine Model Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C High-Drive Outputs (-32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic Ceramic DIPs, Ceramic Flat Packages
SN54ABT573 PACKAGE SN74ABT573A PACKAGE (TOP VIEW)
SN54ABT573 PACKAGE (TOP VIEW)
description
These 8-bit latches feature 3-state outputs designed specifically driving highly capacitive relatively low-impedance loads. They particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. eight latches SN54ABT573 SN74ABT573A transparent D-type latches. While latch-enable (LE) input high, outputs follow data inputs. When taken low, outputs latched logic levels inputs.
buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operations latches. data retained data entered while outputs high-impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. SN54ABT573 characterized operation over full military temperature range -55°C 125°C. SN74ABT573A characterized operation from -40°C 85°C.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC-B trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE 655303
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SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
FUNCTION TABLE (each latch) INPUTS OUTPUT
logic symbol
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
logic diagram (positive logic)
Seven Other Channels
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, SN54ABT573 SN74ABT573A Input clamp current, Output clamp current, Package thermal impedance, (see Note package 115°C/W package 97°C/W package 67°C/W package 128°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with EIA/JEDEC JESD51, except through-hole packages, which trace length zero.
recommended operating conditions (see Note
SN54ABT573 Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Outputs enabled SN74ABT573A UNIT ns/V
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER Vhys IOZH IOZL Ioff ICEX TEST CONDITIONS Outputs high Outputs high input Other inputs Outputs Outputs disabled -100 ±100 -180 -180 ±100 -180 0.55 0.55* 0.55 0.55 25°C -1.2 SN54ABT573 -1.2 SN74ABT573A -1.2 UNIT
products compliant MIL-PRF-38535, this parameter does apply. typical values This data sheet limit vary among suppliers. more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
SN54ABT573 25°C Pulse duration, high Setup time, data before time Hold time, data after High UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
SN74ABT573A 25°C Pulse duration, high High Setup time data before time, UNIT
Hold time, data after This data sheet limit vary among suppliers.
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN54ABT573 PARAMETER FROM (INPUT) (OUTPUT) 25°C tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN74ABT573A PARAMETER FROM (INPUT) (OUTPUT) 25°C tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT
This data sheet limit vary among suppliers.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
From Output Under Test (see Note
LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING tPLZ tPHZ
Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated

State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss

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