State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss
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SN54ABT377, SN74ABT377A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C High-Drive Outputs (-32-mA IOH, 64-mA IOL) Protection Exceeds 2000 MIL-STD-883, Method 3015; Exceeds Using Machine Model Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic Ceramic DIPs, Ceramic Flat Package
SN54ABT377 PACKAGE SN74ABT377A PACKAGE (TOP VIEW)
CLKEN
SN54ABT377 PACKAGE (TOP VIEW)
These 8-bit positive-edge-triggered D-type flip-flops with clock (CLK) input particularly suitable implementing buffer storage registers, shift registers, pattern generators. Data input information that meets setup time requirements transferred outputs positive-going edge clock pulse common clock-enable (CLKEN) input low. Clock triggering occurs particular voltage level directly related transition time positive-going pulse. When buffered clock (CLK) input either high level, D-input signal effect output. circuits designed prevent false clocking transitions CLKEN.
description
SN54ABT377 characterized operation over full military temperature range -55°C 125°C. SN74ABT377A characterized operation from -40°C 85°C.
FUNCTION TABLE (each flip-flop) INPUTS CLKEN OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC-B trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1997, Texas Instruments Incorporated
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CLKEN
SN54ABT377, SN74ABT377A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
logic symbol
CLKEN
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
logic diagram (positive logic)
CLKEN
Seven Other Channels
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SN54ABT377, SN74ABT377A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, SN54ABT377 SN74ABT377A Input clamp current, Output clamp current, Package thermal impedance, (see Note package 115°C/W package 97°C/W package 67°C/W package 128°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with EIA/JEDEC JESD51, except through-hole packages, which trace length zero.
recommended operating conditions (see Note
SN54ABT377 Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Outputs enabled SN74ABT377A UNIT ns/V
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
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SN54ABT377, SN74ABT377A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER Vhys Ioff ICEX TEST CONDITIONS Outputs high Outputs high Outputs -100 ±100 -180 -180 ±100 -180 0.55 0.55* 0.55 0.55 25°C -1.2 SN54ABT377 -1.2 SN74ABT377A -1.2 UNIT
input Other inputs
products compliant MIL-PRF-38535, this parameter does apply. typical values more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
SN54ABT377 25°C fclock Clock frequency Pulse duration Setup time before Hold time after high Data high CLKEN high Data high CLKEN high UNIT
This data sheet limit vary among suppliers.
POST OFFICE 655303
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SN54ABT377, SN74ABT377A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
SN74ABT377A 25°C fclock Clock frequency Pulse duration Setup time before Hold time after high Data high CLKEN high Data high CLKEN high UNIT
This data sheet limit vary among suppliers.
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN54ABT377 PARAMETER FROM (INPUT) (OUTPUT) 25°C fmax tPLH tPHL UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN74ABT377A PARAMETER FROM (INPUT) (OUTPUT) 25°C fmax tPLH tPHL UNIT
This data sheet limit vary among suppliers.
POST OFFICE 655303
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SN54ABT377, SN74ABT377A OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
From Output Under Test (see Note
LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING tPLZ tPHZ
Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
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Copyright 1996, Texas Instruments Incorporated
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