3-State Inverting Outputs Drive Lines Directly Full Parallel Access Lo

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3-State Inverting Outputs Drive Lines Directly Full Parallel Access Lo

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SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
3-State Inverting Outputs Drive Lines Directly Full Parallel Access Loading EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Chip Carriers (FK) Flatpacks (W), Standard Plastic Ceramic DIPs
SN54AC534 PACKAGE SN74AC534 PACKAGE (TOP VIEW)
description
These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically driving highly capacitive relatively low-impedance loads. devices particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. positive transition clock (CLK) input, outputs complements logic levels data inputs.
SN54AC534 PACKAGE (TOP VIEW)
buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components.
does affect internal operations flip-flops. data retained data entered while outputs high-impedance state. SN54AC534 characterized operation over full military temperature range -55°C 125°C. SN74AC534 characterized operation from -40°C 85°C.
FUNCTION TABLE (each flip-flop) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC trademark Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
Copyright 1996, Texas Instruments Incorporated
DALLAS, TEXAS 75265
SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
logic symbol
logic diagram (positive logic)
Seven Other Channels
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Note -0.5 Input clamp current, VCC) Output clamp current, VCC) Continuous output current, VCC) Continuous current through ±200 Maximum power dissipation 55°C still air) (see Note package package package package Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils, except package, which trace length zero.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54AC534 Supply voltage High-level input voltage High Low-level input voltage Input voltage Output voltage High-level output current High Low-level output current Input transition rise fall rate 3.15 3.85 1.35 1.65 SN74AC534 3.15 3.85 1.35 1.65 ns/V UNIT
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS GND, 2.56 3.86 4.86 0.36 0.36 0.36 ±0.5 ±0.1 25°C SN54AC534 SN74AC534 2.46 3.76 4.76 0.44 0.44 0.44 ±2.5 UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C Pulse duration, high Setup time, data before Hold time, data after SN54AC534 SN74AC534 UNIT
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C Pulse duration, high Setup time, data before Hold time, data after SN54AC534 SN74AC534 UNIT
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT)
free-air
temperature
SN74AC534 17.5 16.5 15.5 15.5 16.5 13.5
range,
UNIT
25°C
SN54AC534
12.5 12.5 13.5
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT)
free-air
temperature
SN74AC534 13.5 12.5 12.5 11.5 11.5 12.5
range,
UNIT
25°C
SN54AC534
10.5 11.5
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
LOAD CIRCUIT Timing Input Input VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input
Input tPLH In-Phase Output Out-of-Phase Output tPHL tPHL tPLH
Output Control (low-level enabling) Output Waveform (see Note Output Waveform Open (see Note
tPZL tPLZ tPHZ
tPZH
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated

3-State Inverting Outputs Drive Lines Directly Full Parallel Access Lo

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