3-State Noninverting Outputs Drive Lines Directly Full Parallel Access

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3-State Noninverting Outputs Drive Lines Directly Full Parallel Access

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SN54AC373, SN74AC373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
3-State Noninverting Outputs Drive Lines Directly Full Parallel Access Loading EPICt (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (DW) Shrink Small-Outline (DB) Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) Flatpacks (W), Standard Plastic Ceramic DIPs
SN54AC373 PACKAGE SN74AC373 PACKAGE (TOP VIEW)
description
These 8-bit latches feature 3-state outputs designed specifically driving highly capacitive relatively low-impedance loads. devices particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. eight latches D-type transparent latches. When latch-enable (LE) input high, outputs follow data inputs. When taken low, outputs latched logic levels inputs.
SN54AC373 PACKAGE (TOP VIEW)
buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) highimpedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines bus-organized systems without need interface pullup components. does affect internal operations latches. data retained data entered while outputs high-impedance state. SN54AC373 characterized operation over full military temperature range 55°C 125°C. SN74AC373 characterized operation from 40°C 85°C.
FUNCTION TABLE (each latch) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC373, SN74AC373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
logic symbol
logic diagram (positive logic)
Seven Other Channels
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Input voltage range, (see Note Output voltage range, (see Note Input clamp current, VCC) Output clamp current, VCC) Continuous output current, VCC) Continuous current through Maximum power dissipation 55°C still air) (see Note package package package package Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils, except package, which trace length zero.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC373, SN74AC373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54AC373 Supply voltage High-level voltage High input Low-level input voltage Input voltage Output voltage High-level output current High Low-level output current Input transition rise fall rate 4.5V 3.15 3.85 1.35 1.65 SN74AC373 3.15 3.85 1.35 1.65 UNIT
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS GND, 2.56 3.86 4.86 0.36 0.36 0.36 0.25 25°C SN54AC373 SN74AC373 2.46 3.76 4.76 0.44 0.44 0.44 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC373, SN74AC373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C Pulse duration, high Setup time, data before Hold time, data after SN54AC373 SN74AC373 UNIT
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C Pulse duration, high Setup time, data before Hold time, data after SN54AC373 SN74AC373 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ (INPUT) (OUTPUT) 25°C 13.5 13.0 13.5 12.5 11.5 11.5 12.5 11.5 SN54AC373 16.5 16.5 13.5 SN74AC373 14.5 14.5 12.5 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ (INPUT) (OUTPUT) 25°C SN54AC373 11.5 11.5 10.5 13.5 10.5 SN74AC373 10.5 10.5 10.5 10.5 12.5 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC373, SN74AC373 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH /tPHL tPLZ /tPZL tPHZ /tPZH Open Open
LOAD CIRCUIT Timing Input Input VOLTAGE WAVEFORMS Data Input VOLTAGE WAVEFORMS
Input tPLH In-Phase Output tPHL Out-of-Phase Output tPHL tPLH
Output Control (low-level enabling) Output Waveform (see Note Output Waveform Open (see Note
tPZL tPLZ tPHZ
tPZH
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated

3-State Noninverting Outputs Drive Lines Directly Full Parallel Access

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