Single-chip ZigBeeTM/802.15.4 solution Integrated 2.4GHz, IEEE 80
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SN250
Single-chip ZigBeeTM/802.15.4 solution
Integrated 2.4GHz, IEEE 802.15.4-compliant transceiver: Robust filtering allows co-existence with IEEE 802.11g Bluetooth devices 97dBm sensitivity PER, 20byte packet) 3dBm nominal output power Increased radio performance mode (boost mode) gives 98dBm sensitivity 5dBm transmit power Integrated loop filter Integrated IEEE 802.15.4 lower with Integrated hardware support Packet Trace Interface InSight Development Environment Provides integrated oscillator power operation Supports optional 32.768kHz crystal oscillator higher accuracy needs 16-bit XAP2b microprocessor
Integrated memory: 128kB Flash SRAM Configurable memory protection scheme sleep modes: Processor idle Deep sleep-1.0A (1.5A with optional 32.768kHz oscillator enabled) Seventeen GPIO pins with alternate functions Serial Controllers with SC1: master, master, UART SC2: master, master/slave 16-bit general-purpose timers; 16-bit sleep timer Watchdog timer power-on-reset circuitry Non-intrusive debug interface (SIF) Integrated encryption accelerator Integrated module first-order, sigma-delta converter with 12-bit resolution Integrated 1.8V voltage regulator
July 2006
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www.st.com
This preliminary information product development undergoing evaluation. Details subject change without notice.
Contents
SN250
Contents
General description Order codes assignment Top-level functional description Electrical characteristics
Absolute maximum ratings Recommended operating conditions Environmental characteristics electrical characteristics electrical characteristics
5.5.1 5.5.2 5.5.3 Receive Transmit Synthesizer
Functional description-system modules
Receive (RX) path
6.1.1 6.1.2 baseband RSSI
Transmit (TX) path
6.2.1 baseband
Integrated module Packet Trace Interface (PTI) XAP2b microprocessor Embedded memory
6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 Flash memory Simulated EEPROM Flash Information Area (FIA) Registers
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SN250 6.10
Contents Encryption accelerator Reset detection Power-on-Reset (POR) Clock sources
6.10.1 High-frequency crystal oscillator 6.10.2 Low-frequency oscillator 6.10.3 Internal oscillator
6.11 6.12 6.13 6.14
Random number generator Watchdog timer Sleep timer Power management
Functional description-application modules
GPIO
7.1.1 Registers
Serial controller
7.2.1 7.2.2 7.2.3 7.2.4 UART mode master mode master mode Registers
Serial controller
7.3.1 7.3.2 7.3.3 modes Master Mode Registers
General purpose timers
7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 Clock sources Timer functionality (counting) Timer functionality (output compare) Timer functionality (input capture) Timer interrupt sources Registers
module
7.5.1 Registers
Event manager .112
7.6.1 Registers
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Contents
SN250 Integrated voltage regulator .117
module programming debug interface Typical application Mechanical data Register address table Abbreviations acronyms References Revision history
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SN250
General description
General description
SN250 single-chip solution that integrates 2.4GHz, IEEE 802.15.4-compliant transceiver with 16-bit XAP2b microprocessor. contains integrated Flash memory peripherals designers ZigBee-based applications. transceiver utilizes efficient architecture that exceeds dynamic range requirements imposed IEEE 802.15.4-2003 standard over 15dB. integrated receive channel filtering allows co-existence with other communication standards 2.4GHz spectrum such IEEE 802.11g Bluetooth. integrated regulator, VCO, loop filter, power amplifier keep external component count low. optional high performance radio mode (boost mode) software selectable boost dynamic range further 3dB. XAP2b microprocessor power-optimized core integrated SN250. supports different modes operation-System Mode Application Mode. ZNet stack runs System Mode with full access areas chip. Application code runs Application Mode with limited access SN250 resources; this allows scheduling events application developer while preventing modification restricted areas memory registers. This architecture results increased stability reliability deployed solutions. SN250 128kB embedded Flash memory integrated data program storage. SN250 software stack employs effective wear-leveling algorithm order optimize lifetime embedded Flash. maintain strict timing requirements imposed ZigBee IEEE 802.15.4-2003 standard, SN250 integrates number functions into hardware. hardware handles automatic transmission reception, automatic backoff delay, clear channel assessment transmission, well automatic filtering received packets. addition, SN250 allows true level debugging integrating Packet Trace Interface. support user-defined applications, number peripherals such GPIO, UART, SPI, I2C, ADC, general-purpose timers integrated. Also, integrated voltage regulator, power-on-reset circuitry, sleep timer, low-power sleep modes available. deep sleep mode draws less than allowing products achieve long battery life. Finally, SN250 utilizes non-intrusive module powerful software debugging programming XAP2b microcontroller. Target applications SN250 include:
Building automation control Home automation control Home entertainment control Asset tracking
SN250 purchased with ZNet, ZigBee-compliant software stack codeveloped Ember Corporation STMicroelectronics, providing ZigBee profile-ready, platformcompliant solution.This technical datasheet details SN250 features available customers using with ZNet stack.
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Order codes
SN250
Order codes
Part Number SN250Q SN250QT Temperature Range +85°C +85°C Package QFN48 QFN48 Packing Tray Tape Reel Marking SN250 SN250
assignment
Figure SN250 assignment
Refer Table Table selecting alternate functions.
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SN250 Table
assignment descriptions
Signal VDD_24MHZ VDD_VCO RF_P RF_N VDD_RF RF_TX_ALT_P RF_TX_ALT_N VDD_IF BIAS_R VDD_PADSA TX_ACTIVE VDD_PADSA RSTB OSC32B OSC32A VREG_OUT VDD_PADS VDD_CORE GPIO11 Direction Power Power Power Power Power Power Power Power Power Description 1.8V high-frequency oscillator supply 1.8V supply Differential (with RF_N) receiver input/transmitter output Differential (with RF_P) receiver input/transmitter output 1.8V supply (LNA Differential (with RF_TX_ALT_N) transmitter output (optional) Differential (with RF_TX_ALT_P) transmitter output (optional) 1.8V supply (mixers filters) Bias setting resistor Analog supply (1.8V) Logic-level control external RX/TX switch Analog supply (1.8V) Active chip reset (internal pull-up) 32.768kHz crystal oscillator left open when using external clock OSC32A 32.768kHz crystal oscillator digital clock input Regulator output (1.8V) Pads supply (2.1-3.6V) 1.8V digital core supply Digital (enable GPIO11 with GPIO_CFG[7:4]) UART handshake Serial Controller (enable SC1-4A with GPIO_CFG[7:4], select UART with SC1_MODE) master clock Serial Controller (enable SC1-3M with GPIO_CFG[7:4], select with SC1_MODE, enable master with SC1_SPICFG[4]) Capture Input Timer (enable CAP2-0 with GPIO_CFG[7:4]) Digital (enable GPIO12 with GPIO_CFG[7:4]) UART handshake Serial Controller (enable SC1-4A with GPIO_CFG[7:4], select UART with SC1_MODE) Capture Input Timer (enable CAP2-0 with GPIO_CFG[7:4])
MCLK
TMR2IA.1 GPIO12 TMR2IB.1
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assignment Table
SN250
descriptions (continued)
Signal GPIO0 Direction Description Digital (enable GPIO0 with GPIO_CFG[7:4]) master data Serial Controller (enable SC2-3M with GPIO_CFG[7:4], select with SC2_MODE, enable master with SC2_SPICFG[4]) slave data Serial Controller (enable SC2-4S with GPIO_CFG[7:4], select with SC2_MODE, enable slave with SC2_SPICFG[4]) Capture Input Timer (enable CAP1-0 with GPIO_CFG[7:4]) Digital (enable GPIO1 with GPIO_CFG[7:4]) master data Serial Controller (enable SC2-3M with GPIO_CFG[7:4], select with SC2_MODE, enable master with SC2_SPICFG[4]) slave data Serial Controller (enable SC2-4S with GPIO_CFG[7:4], select with SC2_MODE, enable slave with SC2_SPICFG[4]) data Serial Controller (enable SC2-2 with GPIO_CFG[7:4], select with SC2_MODE) Capture Input Timer (enable CAP2-1 with GPIO_CFG[7:4]) Pads supply (2.1-3.6V) Digital (enable GPIO2 with GPIO_CFG[7:4]) master clock Serial Controller (enable SC2-3M with GPIO_CFG[7:4], select with SC2_MODE, enable master with SC2_SPICFG[4]) slave clock Serial Controller (enable SC2-4S with GPIO_CFG[7:4], select with SC2_MODE, enable slave with SC2_SPICFG[4]) clock Serial Controller (enable SC2-2 with GPIO_CFG[7:4], select with SC2_MODE) Capture Input Timer (enable CAP2-1 with GPIO_CFG[7:4])
MOSI MOSI
TMR1IA.1 GPIO1
MISO
MISO
TMR2IA.2 VDD_PADS GPIO2
Power
MSCLK
MSCLK
TMR2IB.2
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SN250 Table
assignment descriptions (continued)
Signal GPIO3 Direction Description Digital (enable GPIO3 with GPIO_CFG[7:4]) slave select Serial Controller (enable SC2-4S with GPIO_CFG[7:4], select with SC2_MODE, enable slave with SC2_SPICFG[4]) Capture Input Timer (enable CAP1-0 with GPIO_CFG[7:4]) Digital (enable GPIO4 with GPIO_CFG[12] GPIO_CFG[8]) Input (enable ADC0 with GPIO_CFG[12] GPIO_CFG[8]) Frame signal Packet Trace Interface (PTI) (enable with GPIO_CFG[12]) Digital (enable GPIO5 with GPIO_CFG[12] GPIO_CFG[9]) Input (enable ADC1 with GPIO_CFG[12] GPIO_CFG[9]) Data signal Packet Trace Interface (PTI) (enable with GPIO_CFG[12]) Pads supply (2.1-3.6V) Digital (enable GPIO6 with GPIO_CFG[10]) Input (enable ADC2 with GPIO_CFG[10]) External clock input Timer External enable mask Timer Digital (enable GPIO7 with GPIO_CFG[13] GPIO_CFG[11]) Input (enable ADC3 with GPIO_CFG[13] GPIO_CFG[11]) External regulator open collector output (enable REG_EN with GPIO_CFG[13]) Digital (enable GPIO8 with GPIO_CFG[14]) reference output (enable VREF_OUT with GPIO_CFG[14]) External clock input Timer External enable mask Timer External interrupt source
SSEL
TMR1IB.1 GPIO4 ADC0 PTI_EN GPIO5 ADC1 PTI_DATA VDD_PADS GPIO6 ADC2 TMR2CLK TMR1ENMSK GPIO7 ADC3 REG_EN GPIO8 VREF_OUT TMR1CLK TMR2ENMSK IRQA
Analog Analog Power Analog Analog Analog
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assignment Table
SN250
descriptions (continued)
Signal GPIO9 Direction Description Digital (enable GPIO9 with GPIO_CFG[7:4]) UART transmit data Serial Controller (enable SC1-4A SC1-2 with GPIO_CFG[7:4], select UART with SC1_MODE) master data Serial Controller (enable SC1-3M with GPIO_CFG[7:4], select with SC1_MODE, enable master with SC1_SPICFG[4]) data Serial Controller (enable SC1-2 with GPIO_CFG[7:4], select with SC1_MODE) Capture Input Timer (enable CAP1-1 CAP1-1h with GPIO_CFG[7:4]) Digital (enable GPIO10 with GPIO_CFG[7:4]) UART receive data Serial Controller (enable SC1-4A SC1-2 with GPIO_CFG[7:4], select UART with SC1_MODE) master data Serial Controller (enable SC1-3M with GPIO_CFG[7:4], select with SC1_MODE, enable master with SC1_SPICFG[4]) clock Serial Controller (enable SC1-2 with GPIO_CFG[7:4], select with SC1_MODE) Capture Input Timer (enable CAP1-1 with GPIO_CFG[7:4]) Serial interface, clock (internal pull-down) Serial interface, master in/slave Serial interface, master out/slave Serial interface, load strobe (open-collector with internal pull-up) Ground supply 1.8V Flash memory supply Digital (enable GPIO16 with GPIO_CFG[3]) Waveform Output Timer (enable TMR1OB with GPIO_CFG[3]) Capture Input Timer (enable CAP2-2 with GPIO_CFG[7:4]) External interrupt source
MSDA TMR1IA.2 GPIO10
MSCL TMR1IB.2 SIF_CLK SIF_MISO SIF_MOSI SIF_LOADB VDD_FLASH GPIO16 TMR1OB TMR2IB.3 IRQD
Power Power
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SN250 Table
assignment descriptions (continued)
Signal GPIO15 TMR1OA Direction Power Power Power Ground Description Digital (enable GPIO15 with GPIO_CFG[2]) Waveform Output Timer (enable TMR1OA with GPIO_CFG[2]) Capture Input Timer (enable CAP2-2 with GPIO_CFG[7:4]) External interrupt source Digital (enable GPIO14 with GPIO_CFG[1]) Waveform Output Timer (enable TMR2OB with GPIO_CFG[1]) Capture Input Timer (enable CAP1-2 with GPIO_CFG[7:4]) External interrupt source Digital (enable GPIO13 with GPIO_CFG[0]) Waveform Output Timer (enable TMR2OA with GPIO_CFG[0]) Capture Input Timer (enable CAP1-2 CAP1-2h with GPIO_CFG[7:4]) 1.8V digital core supply 1.8V prescaler supply 1.8V synthesizer supply 24MHz crystal oscillator left open when using external clock input OSCA 24MHz crystal oscillator external clock input Ground supply bottom center package forms (see SN250 Reference Design considerations)
TMR2IA.3 IRQC GPIO14 TMR2OB TMR1IB.3 IRQB GPIO13 TMR2OA TMR1IA.3 VDD_CORE VDD_PRE VDD_SYNTH OSCB OSCA
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Top-level functional description
SN250
Top-level functional description
Figure shows detailed block diagram SN250.
Figure
SN250 block diagram
radio receiver low-IF, super-heterodyne receiver. utilizes differential signal paths minimize noise interference, architecture been chosen optimize coexistence with other devices within 2.4GHz band (namely, IEEE 802.11g Bluetooth). After amplification mixing, signal filtered combined prior being sampled ADC. digital receiver implements coherent demodulator generate chip stream hardware-based MAC. addition, digital receiver contains analog radio calibration routines control gain within receiver path. radio transmitter utilizes efficient architecture which data stream directly modulates VCO. integrated boosts output power. calibration path well output power controlled digital logic. integrated loop filter minimize off-chip circuitry. Only 24MHz crystal with loading capacitors required properly establish reference signal. interfaces data memory baseband modules. provides hardware-based IEEE 802.15.4 packet-level filtering. supplies accurate symbol time base that minimizes synchronization effort software stack meets protocol timing requirements. addition, provides timer synchronization assistance IEEE 802.15.4 CSMA-CA algorithm.
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SN250
Top-level functional description SN250 integrates hardware support Packet Trace module, which allows robust packet-based debug. This element critical component InSight Desktop, software codeveloped Ember, providing advanced network debug capability when coupled with InSight Adapter. SN250 integrates 16-bit XAP2b microprocessor developed Cambridge Consultants Ltd. This power-efficient, industry-proven core provides appropriate level processing power meet needs ZigBee applications. addition, 128kB Flash SRAM comprise program data memory elements, respectively. SN250 employs configurable memory protection scheme usually found larger microcontrollers. addition, module provides non-intrusive programming debug interface allowing real-time application debugging. SN250 contains GPIO pins shared with other peripheral alternate) functions. Flexible routing within SN250 lets external devices utilize alternate functions variety different GPIOs. integrated Serial Controller configured (master-only), (master-only), UART functionality, Serial Controller configured (master slave) (master-only) operation. SN250 integrated which sample analog signals from four GPIO pins single-ended differentially. addition, unregulated voltage supply VDD_PADS, regulated supply VDD_PADSA, voltage reference VREF, sampled. integrated voltage reference VREF made available external circuitry. integrated voltage regulator generates regulated 1.8V reference voltage from unregulated supply voltage. This voltage decoupled routed externally supply 1.8V core logic. addition, integrated module allows proper cold start SN250. SN250 contains high-frequency (24MHz) crystal oscillator and, low-power operation, second low-frequency oscillator (either internal 10kHz oscillator external 32.768kHz crystal oscillator). SN250 contains power domains. always-powered High Voltage Supply used powering GPIO pads critical chip functions. rest chip powered regulated Voltage Supply which disabled during deep sleep reduce power consumption.
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Electrical characteristics
SN250
Electrical characteristics
Absolute maximum ratings
Table lists absolute maximum ratings SN250. Table
Parameter Regulator voltage (VDD_PADS) Core voltage (VDD_24MHz, VDD_VCO, VDD_RF, VDD_IF, VDD_PADSA, VDD_FLASH, VDD_PRE, VDD_SYNTH, VDD_CORE) Voltage RF_P,N; RF_TX_ALT_P,N Voltage GPIO[16:0], SIF_CLK, SIF_MISO, SIF_MOSI, SIF_LOADB, OSC32A, OSC32B, RSTB, VREG_OUT Voltage TX_ACTIVE, BIAS_R, OSCA, OSCB Storage temperature
Absolute maximum ratings
Test Conditions Min. Max. Unit
VDD_PADS VDD_CORE
Recommended operating conditions
Table lists rated operating conditions SN250. Table
Parameter Regulator input voltage (VDD_PADS) Core input voltage (VDD_24MHZ, VDD_VCO, VDD_RF, VDD_IF, VDD_PADSA, VDD_FLASH, VDD_PRE, VDD_SYNTH, VDD_CORE) Temperature range
Operating conditions
Test Conditions Min. Typ. Max. Unit
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SN250
Electrical characteristics
Environmental characteristics
Table lists environmental characteristics SN250. Table
Parameter (human body model) (charged device model) (charged device model) Moisture Sensitivity Level (MSL1)
Environmental characteristics
Test Conditions Non-RF Pins Pins Min. Typ. Max. Unit
electrical characteristics
Table lists electrical characteristics SN250. Table
Parameter Regulator input voltage (VDD_PADS) Power supply range (VDD_CORE) Deep Sleep Current Quiescent current, including internal oscillator Quiescent current, including 32.768kHz oscillator Current Radio receiver, MAC, baseband (boost mode) Radio receiver, MAC, baseband CPU, RAM, Flash memory Total current IRadio receiver, baseband, IRAM, Flash memory) Current Radio transmitter, MAC, baseband (boost mode) max. power 5dBm typical) 33.0 1.8V core VDD_PADS=3.0V 29.0 27.0 Regulator output external input
characteristics
Test Conditions Min. Typ. Max. Unit
35.5
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Electrical characteristics Table
Parameter
SN250
characteristics (continued)
Test Conditions max. power 3dBm typical) Min. Typ. 27.0 24.3 19.5 Max. Unit
Radio transmitter, MAC, baseband
typical min. power 32dBm typical)
CPU, RAM, Flash memory
VDD_PADS 3.0V
Total current IRadio transmitter, baseband, 1.8V core; max. power IRAM, Flash memory
35.5
Table contains digital specifications SN250. digital power (named VDD_PADS) comes from three dedicated pins (Pins 28). voltage applied these pins sets voltage. Table
Parameter Voltage supply Input voltage logic Input voltage logic Input current logic Input current logic Input pull-up resistor value Input pull-down resistor value Output voltage logic Output voltage logic Output source current (standard current pad) Output sink current (standard current pad)
Digital specifications
Name VDD_PAD RIPU RIPD IOHS IOLS 0.82 VDD_PADS 0.18 VDD_PADS VDD_PADS VDD_PADS Min. VDD_PADS Typ. Max. VDD_PADS VDD_PADS Unit
Output source current (high IOHH current pad: GPIO[16:13]) Output sink current (high current pad: GPIO[16:13]) IOLH
Total output current (for Pads) Input voltage threshold OSC32A
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SN250 Table
Parameter Input voltage threshold OSCA Output voltage level (TX_ACTIVE)
Electrical characteristics Digital specifications
Name Min. 0.18 VDD_COR Typ. Max. VDD_CORE 0.82 VDD_CORE Unit
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Electrical characteristics
SN250
5.5.1
electrical characteristics
Receive
Table lists parameters integrated IEEE 802.15.4 receiver SN250. Table
Parameter Frequency range Sensitivity (boost mode) Sensitivity High-side adjacent channel rejection Low-side adjacent channel rejection high-side adjacent channel rejection low-side adjacent channel rejection Channel rejection other channels 802.11g rejection centered 12MHz 13MHz Maximum input signal level correct operation (low gain) Image suppression Co-channel rejection Relative frequency error (2x40 required IEEE 802.15.4) Relative timing error (2x40 required IEEE 802.15.4) Linear RSSI range IEEE 802.15.4 signal 82dBm PER, 20byte packet defined IEEE 802.15.4 PER, 20byte packet defined IEEE 802.15.4 IEEE 802.15.4 signal 82dBm IEEE 802.15.4 signal 82dBm IEEE 802.15.4 signal 82dBm IEEE 802.15.4 signal 82dBm IEEE 802.15.4 signal 82dBm IEEE 802.15.4 signal 82dBm
Receive characteristics
Test Conditions Min. 2400 Typ. Max. 2500 Unit
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SN250
Electrical characteristics
5.5.2
Transmit
Table lists parameters integrated IEEE 802.15.4 transmitter SN250. Table
Parameter Maximum output power (boost mode) Maximum output power Minimum output power Error vector magnitude Carrier frequency error Load impedance mask relative mask absolute 3.5MHz away 3.5MHz away
Transmit characteristics
Test Conditions highest power setting highest power setting lowest power setting defined IEEE 802.15.4, which sets maximum Min. Typ. Max. Unit
5.5.3
Synthesizer
Table lists parameters integrated synthesizer SN250. Table
Parameter Frequency range Frequency resolution Lock time From off, with correct setting Channel change RX/TX turnaround (IEEE 802.15.4 defines 192s turnaround time)
Synthesizer characteristics
Test Conditions Min. 2400 11.7 Typ. Max. 2500 Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Relock time Phase noise 100kHz Phase noise 1MHz Phase noise 4MHz Phase noise 10MHz
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Functional description-system modules
SN250
Functional description-system modules
SN250 contains dual-thread mode operation-System Mode Application Mode-to guarantee microcontroller bandwidth application developer protect developer from errant software access. During System Mode, areas including Transceiver, MAC, Packet Trace Interface, Sleep Timer, Power Management Module, Watchdog Timer, Power Reset Module accessible. Since SN250 comes with license ZNet, ZigBee-compliant software stack codeveloped Ember Corporation STMicroelectronics, these areas available application developer Application Mode. following brief description these modules provides necessary background operation SN250. more information, please contact your nearest STMicroelectronics sales office.
Receive (RX) path
SN250 path spans analog digital domains. architecture based low-IF, super-heterodyne receiver. utilizes differential signal paths minimize noise interference. input signal mixed down frequency 4MHz mixers. output mixers filtered combined prior being sampled 12Msps ADC. filtering within path been designed optimize coexistence SN250 with other 2.4GHz transceivers, such IEEE 802.11g Bluetooth.
6.1.1
baseband
SN250 baseband (within digital domain) implements coherent demodulator optimal performance. baseband demodulates O-QPSK signal chip level synchronizes with IEEE 802.15.4-2003 preamble. Once packet preamble detected, de-spreads demodulated data into 4-bit symbols. These symbols buffered passed hardware-based module filtering. addition, baseband provides calibration control interface analog modules, including LNA, Baseband Filter, modulation modules. ZNet software includes calibration algorithms which this interface reduce effects process temperature variation.
6.1.2
RSSI
SN250 calculates RSSI over 8-symbol period well received packet. utilizes gain settings output level within algorithm. SN250 baseband provides support IEEE 802.15.4-2003 required methods summarized Table Modes defined 802.15.4-2003 standard; Mode proprietary mode.
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SN250 Table
Mode
Functional description-system modules Mode Behavior
Mode Behavior Clear channel reports busy medium either carrier sense RSSI exceeds their thresholds. Clear channel reports busy medium RSSI exceeds threshold. Clear channel reports busy medium carrier sense exceeds threshold. Clear channel reports busy medium both RSSI carrier sense exceed their thresholds.
Transmit (TX) path
SN250 transmitter utilizes both analog circuitry digital logic produce O-QPSK modulated signal. area-efficient architecture directly modulates spread symbols prior transmission. differential signal paths increase noise immunity provide common interface external balun.
6.2.1
baseband
SN250 baseband (within digital domain) performs spreading 4-bit symbol into IEEE 802.15.4-2003-defined 32-chip sequence. addition, provides interface software perform calibration module order reduce process, temperature, voltage variations.
Integrated module
SN250 integrates critical portions IEEE 802.15.4-2003 requirements hardware. This allows microcontroller provide greater bandwidth application network operations. addition, hardware acts first-line filter non-intended packets. SN250 utilizes interface memory further reduce overall microcontroller interaction when transmitting receiving packets. When packet ready transmission, software configures indicating packet buffer location. waits backoff period, then transitions baseband mode performs channel assessment. When channel clear, reads data from buffer, calculates CRC, provides 4-bit symbols baseband. When final byte been read sent baseband, remainder read transmitted. resides mode most time, different format address filters keep non-intended packets from using excessive buffers, well preventing from being interrupted. When reception packet begins, reads 4-bit symbols from baseband calculates CRC. assembles received data storage buffer. provides direct access memory. Once packet been received, additional data appended packet buffer space. appended data provides statistical information packet software stack.
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Functional description-system modules primary features are:
SN250
generation, appending, checking Hardware timers interrupts achieve symbol timing Automatic preamble, pre-pended packet Address recognition packet filtering received packets Automatic acknowledgement transmission Automatic transmission packets from memory Automatic transmission after backoff time channel clear (CCA) Automatic acknowledgement checking Time stamping received transmitted messages Attaching packet information received packets (LQI, RSSI, gain, time stamp, packet status) IEEE 802.15.4 timing slotted/unslotted timing
Packet Trace Interface (PTI)
SN250 integrates true PHY-level effective network-level debugging. This twosignal interface monitors packets non-intrusive manner) between baseband modules. asynchronous 500kbps interface cannot used inject packets into PHY/MAC interface. signals from SN250 frame signal (PTI_EN) data signal (PTI_DATA). supported InSight Desktop.
XAP2b microprocessor
SN250 integrates XAP2b microprocessor developed Cambridge Consultants Ltd., making true system-on-a-chip solution. XAP2b 16-bit Harvard architecture processor with separate program data address spaces. word width bits both program data sides. Data-side addresses always specified bytes, though they accessed either bytes words, while program-side addresses always specified accessed words. data-side address effectively bits wide, allowing address space 32kB; program-side address bits wide, addressing words. standard XAP2 microprocessor accompanying software tools have been enhanced create XAP2b microprocessor used SN250. XAP2b adds data-side byte addressing support XAP2 utilizing 15th data-side address indicate byte word accesses. This allows more productive usage RAM, optimized code, more familiar architecture customers when compared standard XAP2. XAP2b clock speed 12MHz. When used with ZNet stack, code loaded into Flash memory over serial link using built-in bootloader reserved area Flash. Alternatively, code loaded interface with assistance RAM-based utility routines also loaded SIF. XAP2b SN250 also been enhanced support separate protection levels. ZNet stack runs System Mode, which allows full, unrestricted access areas chip, while application code runs Application Mode. When running Application Mode, writing certain areas memory registers restricted prevent
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SN250
Functional description-system modules common software bugs from interfering with operation ZNet stack. These errant writes captured details reported developer assist tracking down fixing these issues.
Embedded memory
shown Figure program side address space contains mappings both integrated Flash blocks. Figure Program address space
data side address space contains mappings same Flash blocks, well registers separate Flash information area, shown Figure
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Functional description-system modules Figure Data address space
SN250
6.6.1
Flash memory
SN250 integrates 128kB Flash memory. Flash cell been qualified data retention time >100 years room temperature. Each Flash page size 1024 bytes rated have guaranteed 1,000 write/erase cycles. Flash memory mappings both program data side address spaces. program side, first 112kB Flash memory mapped corresponding first word addresses allow code storage, shown Figure program side, Flash always read whole words. data side, Flash memory divided into eight 16kB sections, which separately mapped into Flash window storage constant data Simulated EEPROM. shown Figure Flash window corresponds first 16kB data-side address space. data side, Flash read bytes, only written word time using utility routines ZNet stack HAL.
6.6.2
Simulated EEPROM
ZNet stack reserves section Flash memory provide Simulated EEPROM storage area stack customer tokens. Therefore, SN250 utilizes upper Flash storage. This section Flash only accessible when mapped Flash window data-side address space. Because Flash cells qualified 1,000 write cycles,
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SN250
Functional description-system modules Simulated EEPROM implements effective wear-leveling algorithm which effectively extends number write cycles individual tokens.
6.6.3
Flash Information Area (FIA)
SN250 also includes separate 1024-byte that used storage data during manufacturing, including serial numbers calibration values. This area mapped data side address space, starting address 0x5000. While this area read individual bytes, only written word time, only erased whole. Programming this special Flash page only enabled using interface prevent accidental corruption erasure. ZNet stack reserves small portion this space use, rest available application.
6.6.4
SN250 integrates SRAM. Like Flash memory, this also mapped both program data-side address spaces. program side, mapped 2.5k words program address space. program-side mapping used code when writing erasing Flash memory. data side, also mapped address space, occupying last 5kB, shown Figure Figure Additionally, SN250 supports protection mechanism prevent application code from overwriting system data stored RAM. enable this, segmented into 32byte sections, each with configurable that allows denies write access when SN250 running Application Mode. Read access always allowed entire RAM, full access always allowed when SN250 running System Mode. ZNet stack intelligently manages this protection mechanism assist tracking down many common application errors.
6.6.5
Registers
Table provides short description application-accessible registers within SN250. Complete descriptions provided each applicable Functional Description section. registers mapped data-side address space starting address 0x4000. These registers allow control configuration various peripherals modules. registers only accessed whole word quantities; attempts access them bytes result undefined behavior. There additional registers used ZNet stack when SN250 running System Mode, allowing control MAC, baseband, other internal modules. These system registers protected from being modified when SN250 running Application Mode.
Encryption accelerator
SN250 contains hardware encryption engine that attached using memory-mapped interface. NIST-based CCM, CCM*, CBC-MAC, modes implemented hardware. These modes described IEEE 802.15.4-2003 specification, with exception CCM*, which described ZigBee Security Services Specification 1.0. ZNet stack implements security applications that require security application level.
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Functional description-system modules
SN250
Reset detection
SN250 contains multiple reset sources. reset event logged into reset source register, which lets determine cause last reset. following reset causes detected:
Power-on-Reset Watchdog rollover Software reset Core Power
Power-on-Reset (POR)
Each voltage domain (1.8V Digital Core Supply VDD_CORE Pads Supply VDD_PADS) power-on-reset (POR) cell. VDD_PADS cell holds always-powered high-voltage domain reset until following conditions have been met:
high-voltage Pads Supply VDD_PADS voltage rises above threshold. internal clock starts generates three clock pulses. 1.8V cell holds main digital core reset until regulator output voltage rises above threshold.
Additionally, digital domain counts 1,024 clock edges 24MHz crystal before releasing reset main digital core. Table lists features SN250 circuitry. Table
Parameter VDD_PADS release VDD_PADS assert 1.8V release 1.8V hysteresis
specifications
Min. 1.35 0.08 Typ. Max. 1.65 0.12 Unit
6.10
Clock sources
SN250 integrates three oscillators: high-frequency 24MHz crystal oscillator, optional low-frequency 32.768kHz crystal oscillator, low-frequency internal 10kHz oscillator.
6.10.1
High-frequency crystal oscillator
integrated high-frequency crystal oscillator requires external 24MHz crystal with accuracy 40ppm. Based upon application Bill Materials current consumption requirements, external crystal cover range requirements. lower ESR, cost crystal increases overall current consumption decreases. Likewise,
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SN250
Functional description-system modules higher ESR, cost decreases current consumption increases. Therefore, designer choose crystal needs application. Table lists specifications high-frequency crystal. Table
Parameter Frequency Duty cycle Phase noise from 1kHz 100kHz Accuracy Crystal Crystal Start-up time stable clock (max. bias) Start-up time stable clock (optimum bias) Current consumption Current consumption Current consumption Good crystal: ESR, 10pF load Worst-case crystals (60, 18pF 100, 10pF) maximum bias Initial, temperature, aging Load capacitance 10pF Load capacitance 18pF
High-frequency crystal specifications
Test Conditions Min. Typ. Max. Unit dBc/Hz
6.10.2
Low-frequency oscillator
optional low-frequency crystal source SN250 32.768kHz crystal. Table lists requirements low-frequency crystal. low-frequency crystal used applications that require greater accuracy than provided internal oscillator. crystal oscillator been designed accept standard watch crystal with Table
Parameter Frequency Accuracy Load capacitance (double this each side ground) Crystal Start-up time Current consumption Initial, temperature, aging 12.5
Low-Frequency Crystal Specifications
Test Conditions Min. Typ. 32.768 Max. Unit
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Functional description-system modules
SN250
6.10.3
Internal oscillator
SN250 low-power, low-frequency oscillator that runs time. nominal frequency 10kHz. oscillator coarse analog trim control, which first adjusted frequency close 10kHz possible. This clock used chip management block. also divided down 1kHz using variable divider allow software accurately calibrate This calibrated clock available sleep timer. Timekeeping accuracy depends temperature fluctuations chip exposed power supply impedance, calibration interval, general will better than 150ppm (including crystal error 40ppm). Table lists specifications oscillator. Table
Parameter Frequency Analog trim steps Frequency variation with supply voltage drop from 3.6V 3.1V 2.6V 2.1V
Oscillator Specifications
Test Conditions Min. Typ. Max. Unit
6.11
Random number generator
SN250 allows generation random numbers exposing randomly generated from ADC. Analog noise current passed through path, sampled receive ADC, stored register. value contained this register could used seed software-generated random number. ZNet stack utilizes these random numbers seed Random Backoff Encryption Generators.
6.12
Watchdog timer
SN250 contains watchdog timer clocked from internal oscillator. watchdog disabled default, enabled disabled software. timer reaches time-out value approximately seconds, will generate reset signal chip. When software running properly, application periodically restart this timer prevent reset signal from being generated. watchdog will generate watermark interrupt advance actually resetting chip. This watermark interrupt occurs approximately 1.75 seconds after timer been restarted. This interrupt used assist during application debug.
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SN250
Functional description-system modules
6.13
Sleep timer
16-bit sleep timer contained always-powered digital block. following features:
output compare registers, with interrupts Only Compare Interrupt generates Wake signal Further clock divider
clock source sleep timer either 32.768 clock calibrated 1kHz clock (see Table 15). After choosing clock source, frequency slowed down with prescaler generate final timer clock (see Table 16). Legal values slowest rate sleep timer counter wraps 1kHz 67109 sec. about 1118.48 min. 18.6 hrs. Table
CLK_SEL
Sleep timer clock source selection
Clock Source Calibrated 1kHz clock 32.768kHz clock
Table
Sleep timer clock source prescaling
Clock Source Prescale Factor
CLK_DIV[3:0] 0.10 11.15
ZNet software allows application define clock source prescaler value. Therefore, programmable sleep/wake duty cycle configured according application requirements.
6.14
Power management
SN250 supports three different power modes: processor ACTIVE, processor IDLE, DEEP SLEEP. IDLE power mode stops code execution XAP2b until interrupt occurs external wakeup command seen. peripherals SN250 including radio continue operate normally. DEEP SLEEP power mode powers most SN250 leaves critical chip functions, such GPIO pads powered High Voltage Supply (VDD_PADS). SN250 woken configuring sleep timer generate interrupt after period time, using external interrupt, with interface. Activity serial interface also configured wake SN250, though actual reception data re-enabled until SN250 finished waking Depending speed serial data, possible finish waking middle byte. Care must taken reset serial interface between bytes discard garbage data before rest. Another condition wakeup general activity GPIO pins. GPIO activity monitoring described Section 7.1. When DEEP SLEEP, internal regulator disabled VREG_OUT turned off. GPIO output signals maintained frozen state. Additionally, state registers
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Functional description-system modules
SN250
powered-down low-voltage domain SN250 lost. Register settings application peripherals should preserved application desired. operation DEEP SLEEP controlled ZNet APIs which automatically preserve state necessary system peripherals. internal XAP2b registers automatically saved restored hardware when entering leaving DEEP SLEEP mode, allowing code execution continue from where left off. event that caused wakeup additional events that occurred while waking reported application ZNet APIs. Upon waking from DEEP SLEEP, internal regulator re-enabled.
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SN250
Functional description-application modules
Functional description-application modules
Application Mode, access privileged areas blocked while access applicationspecific modules such GPIO, Serial Controllers (SC1 SC2), General Purpose Timers, ADC, Event Manager enabled.
GPIO
SN250 multi-purpose GPIO pins that configured variety ways. pins have following programmable features:
Selectable input, output, bi-directional. Output totem pole, used open drain open source output wired-OR applications. have internal pull-up pull-down.
information flow between GPIO source controlled separate GPIO Data registers. GPIO_INH GPIO_INL registers report input level GPIO pins. GPIO_DIRH GPIO_DIRL registers enable output signals GPIO Pins. GPIO_PUH GPIO_PUL registers enable pull-up resistors while GPIO_PDH GPIO_PDL registers enable pull-down resistors GPIO Pins. GPIO_OUTH GPIO_OUTL control output level. Instead changing entire contents OUT/DIR registers with write access, limited change applied. Writing GPIO_SETH/L GPIO_DIRSETH/L register changes individual register bits from while data bits that already maintained. Writing GPIO_CLRH/L GPIO_DIRCLRH/L register changes individual register bits from while data bits that already maintained. Note that value read from GPIO_OUTH/L, GPIO_SETH/L, GPIO_CLRH/L registers reflect current state. observe state, GPIO_INH/L registers should read. registers controlling GPIO definitions unaffected power cycling main core voltage (VDD_CORE). Figure GPIO control logic
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Functional description-application modules
SN250
GPIO_DBG register must always remain zero. GPIO_CFG register controls GPIO signal routing alternate GPIO functions listed Table Refer Table individual alternate functions. Table defines alternate functions routed GPIO. allow more flexibility, timer signals come from alternative sources (e.g., TIM1IA.1, TIM1IA.2, TIM1IA.3), depending what serial controller functions used. When core powered down, peripherals stop driving correct output signals. maintain correct output signals, system software will ensure that GPIO output signals frozen before going into deep sleep. Monitoring circuitry place detect when logic state GPIO input pins change. lower GPIO pins that should monitored chosen software with GPIO_WAKEL register. resulting event used waking from deep sleep described Section 6.14.
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SN250 Table GPIO configurations
Mode
Functional description-application modules
GPIO_CFG[15:0]
0010 0000 0000 0000 DEFAULT Enable PTI_EN PTI_DATA Enable analog input ADC0 Enable analog input ADC1 Enable analog input ADC2 Enable REG_EN Enable analog input ADC3 Enable VREF_OUT 0000 Enable 0001 Enable SC1-2 SC2-2 Enable GPIO8 Enable GPIO7 Enable GPIO6 Enable GPIO5 EnableGPIO4
CAP2-0 CAP1-0 mode+ GPIO[12,11,10,9,3,2,1,0] CAP2-0 CAP1-0 mode+GPIO[12,11,
0010 Enable SC1-4A SC2-4S CAP2-2 CAP1-2h mode 0011 Enable SC1-3M SC2-3M CAP2-2 CAP1-2 0100 Enable 0101 Enable SC1-2 SC2-2 CAP2-0 CAP1-0 mode+GPIO[12,
mode+GPIO[12,11,10,9,3,
SC2-4S CAP2-0 CAP1-2h mode+GPIO[12,11 mode+GPIO[ mode+GPIO[12
0110 Enable SC1-4A SC2-3M CAP2-2 CAP1-2 0111 Enable SC1-3M 1000 Enable 1001 Enable SC1-2 1010 Enable SC1-4A 1011 Enable SC1-3M SC2-2 1100 Enable 1101 Enable SC1-2 1110 Enable SC1-4A SC2-2 CAP2-1 CAP1-0
3,2,1,0]
SC2-4S CAP2-0 CAP1-1h mode+GPIO[12,11,10,9 SC2-3M CAP2-0 CAP1-2 CAP2-1 CAP1-0 CAP2-2 CAP1-0 mode+GPIO[12,11, mode+GPIO[ mode+GPIO[12
3,2,1,0]
SC2-3M CAP2-0 CAP1-1 CAP2-0 CAP1-0 CAP2-2 CAP1-0
mode+GPIO[12,11,10,9,3 mode+GPIO[12,11, mode+GPIO[
3,2,1,0]
1111 Enable SC1-3M SC2-4S CAP2-2 CAP1-2h mode+GPIO[12 Enable TMR2OA Enable TMR2OB Enable TMR1OA Enable TMR1OB 0-EnableGPIO16 Enable GPIO15 Enable GPIO14 Enable GPIO13
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Functional description-application modules Table GPIO functions
Analog Function
SN250
Always GPIO Connected Input Functions IRQA
Timer Functions
Serial Digital Functions
Output Current Drive Standard Standard Standard Standard
TMR1IA.1 (when CAP1-0 mode) TMR2IA.2 (when CAP2-1 mode) TMR2IB.2 (when CAP2-1 mode) TMR1IB.1 (when CAP1-0 mode)
MOSI MISO MSCLK SSEL (input) PTI_EN PTI_DATA ADC0 input ADC1 input ADC2 input REG_EN (open collector enable external regulator) ADC3 input VREF_OUT
Standard Standard Standard Standard Standard Standard Standard Standard Standard High
TMR2CLK, TMR1ENMSK
TMR1CLK, TMR2ENMSK TMR1IA.2 MSDA (when CAP1-1 CAP1-1h mode) TMR1IB.2 (when CAP1-1 mode) MSCL TMR2IA.1 (when CAP2-0 mode) MCLK TMR2IB.1 (when CAP2-0 mode) TMR2OA TMR1IA.3 (when CAP1-2h CAP1-2 mode) TMR2OB TMR1IB.3 (when CAP1-2 mode) TMR1OA TMR2IA.3 (when CAP2-2 mode) TMR1OB TMR2IB.3 (when CAP2-2 mode)
IRQB IRQC IRQD
High High High
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SN250
Functional description-application modules
7.1.1
Registers
GPIO_CFG [0x4712]
0-RW 1-RW 0-RW 0-RW GPIO_CFG GPIO_CFG 0-RW GPIO_CFG 0-RW [14:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
GPIO configuration modes. Refer Table Table mode settings.
GPIO_INH [0x4700]
GPIO_INH GPIO_INH
Read input level GPIO[16] pin.
GPIO_INL [0x4702]
GPIO_INL GPIO_INL GPIO_INL [15:0]
Read input level GPIO[15:0] pins.
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Functional description-application modules
SN250
GPIO_OUTH [0x4704]
GPIO_OUTH GPIO_OUTH 0-RW
Write output level GPIO[16] pin. value read match actual value pin.
GPIO_OUTL [0x4706]
0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
GPIO_OUTL GPIO_OUTL 0-RW GPIO_OUTL 0-RW [15:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
Write output level GPIO[15:0] pins. value read match actual value pin.
GPIO_SETH [0x4708]
GPIO_SETH GPIO_SET
output level GPIO[16] pin. Only writing ones into this register will have effect. that written will cause corresponding GPIO_OUTH become
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SN250
Functional description-application modules
GPIO_SETL [0x470A]
GPIO_SETL GPIO_SETL GPIO_SETL [15:0]
output level GPIO[15:0] pins. Only writing ones into this register will have effect. that written will cause corresponding GPIO_OUTL become
GPIO_CLRH [0x470C]
GPIO_CLRH GPIO_CLRH
Clear output level GPIO[16] pin. Only writing ones into this register will have effect. that written will cause corresponding GPIO_OUTH become
GPIO_CLRL [0x470E]
GPIO_CLRL GPIO_CLRL GPIO_CLRL [15:0]
Clear output level GPIO[15:0] pins. Only writing ones into this register will have effect. that written will cause corresponding GPIO_OUTL become
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Functional description-application modules
SN250
GPIO_DIRH [0x4714]
GPIO_DIRH GPIO_DIRH 0-RW
Enable output GPIO[16] pin.
GPIO_DIRL [0x4716]
0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
GPIO_DIRL GPIO_DIRL 0-RW GPIO_DIRL 0-RW [15:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
Enable output GPIO[15:0] pins.
GPIO_DIRSETH [0x4718]
GPIO_DIRSETH GPIO_ DIRSETH
output enable GPIO[16] pin. Only writing ones into this register will have effect. that written will cause corresponding GPIO_DIRH become
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SN250
Functional description-application modules
GPIO_DIRSETL [0x471A]
GPIO_DIRSETL GPIO_DIRSETL GPIO_DIRSETL [15:0]
output enable GPIO[15:0] pins. Only writing ones into this register will have effect. that written will cause corresponding GPIO_DIRL become
GPIO_DIRCLRH [0x471C]
GPIO_DIRCLRH GPIO_ DIRCLRH
Clear output enable GPIO[16] pin. Only writing ones into this register will have effect. that written will cause corresponding GPIO_DIRH become
GPIO_DIRCLRL [0x471E]
GPIO_DIRCLRL GPIO_DIRCLRL GPIO_DIRCLRL [15:0]
Clear output enable GPIO[15:0] pins. Only writing ones into this register will have effect. that written will cause corresponding GPIO_DIRL become
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Functional description-application modules
SN250
GPIO_PDH [0x4720]
GPIO_PDH GPIO_PDH 0-RW
this enable pull-down resistors GPIO[16] pin.
GPIO_PDL [0x4722]
0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
GPIO_PDL GPIO_PDL 0-RW GPIO_PDL 0-RW [15:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
this enable pull-down resistors GPIO[15:0] pins.
GPIO_PUH [0x4724]
GPIO_PUH GPIO_PUH 0-RW
this enable pull-up resistors GPIO[16] pin.
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SN250
Functional description-application modules
GPIO_PUL [0x4726]
0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
GPIO_PUL GPIO_PUL 0-RW GPIO_PUL 0-RW [15:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
this enable pull-up resistors GPIO[15:0] pins.
GPIO_WAKEL [0x4728]
0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
GPIO_WAKEL GPIO_WAKEL 0-RW GPIO_WAKEL 0-RW [15:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
Setting bits will enable GPIO wakeup monitoring changing states GPIO[15:0] pins.
GPIO_INTCFGA [0x4630]
GPIO_INTMOD 0-RW GPIO_INTFILT GPIO_INTMOD 0-RW [7:5] 0-RW 0-RW GPIO_ INTFILT
this enable GPIO IRQA filter. GPIO IRQA input edge triggering selection: disabled; rising; falling; both edges; active high triggered; active trigger; reserved.
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Functional description-application modules
SN250
GPIO_INTCFGB [0x4632]
GPIO_INTMOD 0-RW GPIO_INTFILT GPIO_INTMOD 0-RW [7:5] 0-RW 0-RW GPIO_INTFILT
this enable GPIO IRQB filter GPIO IRQB input edge triggering selection: disabled; rising; falling; both edges; active high triggered; active trigger; reserved.
GPIO_INTCFGC [0x4634]
GPIO_INTMOD 0-RW GPIO_INTFILT GPIO_INTMOD 0-RW [7:5] 0-RW 0-RW GPIO_INTFILT
this enable GPIO IRQC filter. GPIO IRQC input edge triggering selection: disabled; rising; falling; both edges; active high triggered; active trigger; reserved.
GPIO_INTCFGD [0x4636]
GPIO_INTMOD 0-RW GPIO_INTFILT GPIO_INTMOD 0-RW [7:5] 0-RW 0-RW GPIO_INTFILT
this enable GPIO IRQD filter. GPIO IRQD input edge triggering selection: disabled; rising; falling; both edges; active high triggered; active trigger; reserved.
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SN250
Functional description-application modules
INT_GPIOCFG [0x4628]
INT_GPIOD INT_GPIOC INT_GPIOB INT_GPIOA INT_GPIOD 0-RW INT_GPIOC 0-RW INT_GPIOB 0-RW INT_GPIOA 0-RW
GPIO IRQD interrupt enable. GPIO IRQC interrupt enable. GPIO IRQB interrupt enable. GPIO IRQA interrupt enable.
INT_GPIOFLAG [0x4610]
INT_GPIOD INT_GPIOC INT_GPIOB INT_GPIOA INT_GPIOD 0-RW INT_GPIOC 0-RW INT_GPIOB 0-RW INT_GPIOA 0-RW
GPIO IRQD interrupt pending. GPIO IRQC interrupt pending. GPIO IRQB interrupt pending. GPIO IRQA interrupt pending.
GPIO_DBG [0x4710]
GPIO_DBG [1:0] GPIO_DBG 0-RW 0-RW
This register must remain zero.
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Functional description-application modules
SN250
Serial controller
SN250 module provides asynchronous (UART) synchronous (SPI I2C) serial communications. Figure block diagram module. Figure block diagram
full-duplex interface module configured into these three communication modes, cannot them simultaneously. reduce interrupt service requirements CPU, module contains buffered data management schemes three modes. dedicated, buffered controller available UART controllers while FIFO available three modes. addition, data register allows software application direct access data within three modes. Finally, routes interface signals GPIO pins. These shared with other functions controlled GPIO_CFG register. selecting alternate functions, please refer Table Table
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SN250
Functional description-application modules
7.2.1
UART mode
UART controller enabled with SC1_MODE UART mode contains following features:
Baud rate (300bps 921kbps) Data bits Parity bits (none, odd, even) Stop bits (optional) (optional)
following signals made available GPIO pins:
UART module obtains reference baud-rate clock from programmable baud generator. Baud rates clock division ratio from 24MHz clock: rate 24MHz (0.5 integer portion, written SC1_UARTPER register fractional remainder, SC1_UARTFRAC register. Table lists supported baud rates with associated baud rate error. minimum allowable setting SC1_UARTPER Table UART baud rates
SC1_UARTPER 40000 2500 1250 SC1_UARTFRAC Baud Rate Error 0.08 0.16 0.16 0.16
Baud Rate (bps) 4800 9600 19200 38400 57600 115200 460800 921600
UART module supports various frame formats depending upon number data bits (SC1_UART8BIT), number stop bits (SC1_UART2STP), parity (SC1_UARTPAR plus SC1_UARTODD). register bits SC1_UART8BIT, SC1_UART2STP, SC1_UARTPAR, SC1_UARTODD defined within SC1_UARTCFG register. addition, UART module supports flow control setting SC1_UARTFLOW, SC1_UARTAUTO, SC1_UARTRTS SC1_UARTCFG register (see Table 20).
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Functional description-application modules Table Configuration table UART module
SC1_UARTCFG SC1_MODE SC1_UARTFLOW SC1_UARTAUTO
SN250
SC1_UARTRTS GPIO_CFG[7:4] GPIO-Pin Function SC1-2 mode SC1-2 mode TXD/RXD output/input Illegal TXD/RXD/CTS output/input/input output ON/OFF TXD/RXD/CTS output/input/input output more bytes will receive buffer Reserved Illegal Illegal
SC1-4A mode
SC1-4A mode
SC1-4A mode SC1-4A mode SC1-3M mode
Characters transmitted received passed through transmit receive FIFOs. transmit receive FIFOs bytes deep. FIFOs accessed under software control accessing SC1_DATA data register under hardware control DMA. When transmit character written (empty) transmit FIFO, register SC1_UARTTXIDLE SC1_UARTSTAT register clears indicate that characters transmitted yet. Further transmit characters written transmit FIFO until full, which causes register SC1_UARTTXFREE SC1_UARTSTAT register clear. After shifting transmit character pin, space transmit character becomes available transmit FIFO. This causes register SC1_UARTTXFREE SC1_UARTSTAT register set. After characters shifted out, transmit FIFO empties, which causes register SC1_UARTTXIDLE SC1_UARTSTAT register set. received character stored with parity frame error status receive FIFO. register SC1_UARTRXVAL SC1_UARTSTAT register indicate that received characters read from receive FIFO. error status received byte available with register bits SC1_UARTPARERR SC1_UARTFRMERR SC1_UARTSTAT register. When controller transferring data from receive FIFO memory buffer, checks stored parity frame error status flags. When error flagged, SC1_RXERRA/B register updated, marking offset first received character with parity frame error. When 4-character receive FIFO contains characters, flow control needs used avoid overflow event. method software handshaking transmitting reserved XON/XOFF characters which interpreted transmitting terminal pause further transmissions receive FIFO). Another method hardware handshaking using XOFF assertion through signal.
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SN250
Functional description-application modules There schemes available assert signal. first scheme initiate assertion with software setting register SC1_UARTRTS SC1_UARTCFG register. second scheme assert automatically depending fill state receive FIFO. This enabled with register SC1_UARTAUTO SC1_UARTCFG register. UART also contains overrun protection both FIFO options. transmitting terminal continues transmit characters receive FIFO, only characters stored FIFO. Additional characters dropped, register SC1_UARTRXOVF SC1_UARTSTAT register set. Should this receive overrun occur during operation, SC1_RXERRA/B registers mark error-offset. FIFO hardware generates INT_SCRXOVF interrupt, register will indicate error condition until FIFO drained. Once marks error, there conditions that will clear error indication: setting appropriate SC_TX/RXDMARST SC1_DMACTRL register, loading appropriate buffer after unloaded. Interrupts generated following events:
Transmit FIFO empty last character shifted transition SC1_UARTTXIDLE) Transmit FIFO changed from full full transition SC1_UARTTXFREE) Receive FIFO changed from empty empty transition SC1_UARTRXVAL) Transmit buffer complete transition SC_TXACTA/B) Receive buffer complete transition SC_RXACTA/B) Character received with Parity error Character received with Frame error Received lost character while receive FIFO full (Receive overrun error)
generate interrupts CPU, interrupt masks INT_SC1CFG INT_CFG registers must enabled.
7.2.2
master mode
mode master mode only. fixed word length bits. controller enabled with SC1_MODE register SC_SPIMST SC1_SPICFG register. mode following features:
Full duplex operation Programmable clock frequency (12MHz max.) Programmable clock polarity clock phase Selectable data shift direction (either first) (master out) (master MCLK (serial clock)
following signals made available GPIO pins:
module obtains reference clock from programmable clock generator. Clock rates clock division ratio from 24MHz clock: rate 24MHz (LIN 2EXP
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Functional description-application modules
SN250
written SC1_RATEEXP register SC1_RATELIN register. Since range both values fastest data rate 12Mbps slowest rate 22.9bps. master supports various frame formats depending upon clock polarity (SC_SPIPOL), clock phase (SC_SPIPHA), direction data (SC_SPIORD) (see Table 21). register bits SC_SPIPOL, SC_SPIPHA, SC_SPIORD defined within SC1_SPICFG register. Note: Switching configuration from SC_SPIPOL=1 SC_SPIPOL=0 without subsequently setting SC1_MODE=0 reinitializing will cause extra byte (0xFE) transmitted immediately before first intended byte. master frame format
GPIO_CFG[7:4] SC1-3M mode SC1-3M mode SC1-3M mode SC1-3M mode SC1-3M Same above except first instead first mode SC1-2 mode SC1-4A mode Illegal Illegal
Table
SC1_SPICFG SC_SPIORD SC_SPIPHA SC_SPIMST SC_SPIPOL SC1_MODE
Frame Format
Serialized transmit data driven output master data received from input generate slave select signals slave devices, other GPIO pins have used their assertion must controlled software. Characters transmitted received passed through transmit receive FIFOs. transmit receive FIFOs bytes deep. These FIFOs accessed under software control accessing SC1_DATA data register under hardware control using controller.
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SN250
Functional description-application modules When transmit character written (empty) transmit FIFO, register SC_SPITXIDLE SC1_SPISTAT register clears indicates that characters transmitted yet. Further transmit characters written transmit FIFO until full, which causes register SC_SPITXFREE SC1_SPISTAT register clear. After shifting transmit character pin, space transmit character becomes available transmit FIFO. This causes register SC_SPITXFREE SC1_SPISTAT register set. After characters shifted out, transmit FIFO empties, which causes register SC_SPITXIDLE SC1_SPISTAT register also. character received stored (empty) receive FIFO. register SC_SPIRXVAL SC1_SPISTAT register indicate that received characters read from receive FIFO. software reading from receive FIFO, receive FIFO will store characters. further reception dropped register SC_SPIRXOVF SC1_SPISTAT register set. FIFO hardware generates INT_SCRXOVF interrupt, register will indicate error condition until FIFO drained. Once marks error, there conditions that will clear error indication: setting appropriate SC_TX/RXDMARST SC1_DMACTRL register, loading appropriate buffer after unloaded. Receiving character always requires transmitting character. case when long stream receive characters expected, long sequence (dummy) transmit characters must generated. avoid software transmit initiating these transfers (and consuming unnecessary bandwidth), serializer instructed retransmit last transmitted character, transmit busy token (0xFF), which determined register SC_SPIRPT SC1_SPICFG register. This functionality only enabled disabled) when transmit FIFO empty transmit serializer idle, indicated cleared SC_SPITXIDLE register SC1_SPISTAT register. Every time automatic character transmission started, transmit underrun detected there data transmit FIFO), register INT_SCTXUND INT_SC1FLAG register set. Note that after disabling automatic character transmission, reception characters stops receive FIFO holds characters just received.
Important: Receive complete event does automatically mean receive FIFO empty. Interrupts generated following events:
Transmit FIFO empty last character shifted transition SC_SPITXIDLE) Transmit FIFO changed from full full transition SC_SPITXFREE) Receive FIFO changed from empty empty transition SC_SPIRXVAL) Transmit buffer complete transition SC_TXACTA/B) Receive buffer complete transition SC_RXACTA/B) Received lost character while receive FIFO full (Receive overrun error) Transmitted character while transmit FIFO empty (Transmit underrun error)
generate interrupts CPU, interrupt masks INT_SC1CFG INT_CFG registers must enabled.
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Functional description-application modules
SN250
7.2.3
master mode
controller only available master mode. controller enabled with SC1_MODE Master controller supports Standard (100kbps) Fast (400kbps) modes. Address arbitration implemented, multiple master applications supported. signals pure open-collector signals, external pull-up resistors required. mode following features:
Programmable clock frequency (400kHz max.) Supports both 7-bit 10-bit addressing MSDA (serial data) MSCL (serial clock)
following signals made available GPIO pins:
Master controller obtains reference clock from programmable clock generator. Clock rates clock division ratio from 24MHz clock:
24MHz Nominal Rate -EXP
written SC1_RATEEXP register SC1_RATELIN register. Table shows rate settings Standard (100kbps) Fast (400kbps) operation. Table nominal rate programming
SC1_RATELIN SC1_RATEEXP
Nominal Rate 100kbps 375kpbs 400kbps
Note that 400kbps, specification requires minimum period 1.3µs. strictly compliant, rate needs lowered 375kbps. Master controller supports generation various frame segments controlled with register bits SC_I2CSTART, SC_I2CSTOP, SC_I2CSEND, SC_I2CRECV SC1_I2CCTRL1 registers. Table summarizes these frames.
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SN250 Table master frame segments
GPIO_CFG[7:4]
Functional description-application modules
SC1_I2CCTRL1 SC_I2CSTART SC_I2CSEND SC_I2CRECV SC_I2CSTOP SC1_MODE
Frame Segments
SC1-2 mode
SC1-2 mode
SC1-2 mode
SC1-2 mode
SC1-2 mode
pending frame segment
SC1-2 mode
Illegal
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Functional description-application modules Table master frame segments (continued)
GPIO_CFG[7:4]
SN250
SC1_I2CCTRL1 SC_I2CSTART SC_I2CSEND SC_I2CRECV SC_I2CSTOP SC1_MODE
Frame Segments
SC1-4M Illegal mode SC1-4A Illegal mode
Full frames have constructed under software control generating individual segments. necessary segment transitions shown Figure NACK generation receive frame segment determined with register SC_I2CACK SC1_I2CCTRL2 register. Figure segment transitions
Generation 7-bit address accomplished with transmit segment. upper bits transmitted character contain 7-bit address. remaining lower contains command type ("read" "write"). Generation 10-bit address accomplished with transmit segments. upper bits first transmit character must 0x1E. next bits most significant bits 10-bit address. remaining lower contains command type
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SN250
Functional description-application modules ("read" "write"). second transmit segment remaining bits 10-bit address. Characters received transmitted passed through receive transmit FIFOs. master transmit receive FIFOs 1-byte deep. These FIFOs accessed under software control. (Re)start stop segments initiated setting register bits SC_I2CSTART SC_I2CSTOP SC1_I2CCTRL1 register followed waiting until they have cleared. Alternatively, register SC_I2CCMDFIN SC1_I2CSTAT used waiting. initiate transmit segment, data have written SC1_DATA data register, followed setting register SC_I2CSEND SC1_I2CCTRL1 register, completed waiting until clears. Alternatively, register SC_I2CTXFIN SC1_I2CSTAT used waiting. receive segment initiated setting register SC_I2CRECV SC1_I2CCTRL1 register, waiting until clears, then reading from SC1_DATA data register. Alternatively, register SC_I2CRXFIN SC1_I2CSTAT used waiting. register SC_I2CRXNAK SC1_I2CSTAT register indicates NACK received from slave device. Interrupts generated following events:
command (SC_I2CSTART/SC_I2CSTOP) completed transition SC_I2CCMDFIN) Character transmitted slave device responded with NACK Character transmitted transition SC_I2CTXFIN) Character received transition SC_I2CRXFIN) Received lost character while receive FIFO full (Receive overrun error) Transmitted character while transmit FIFO empty (Transmit underrun error)
generate interrupts CPU, interrupt masks INT_SC1CFG INT_CFG registers must enabled.
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Functional description-application modules
SN250
7.2.4
Registers
SC1_MODE [0x44AA]
SC1_MODE [1:0] SC1_MODE 0-RW 0-RW
Mode: disabled; UART mode; mode; mode. Note change between modes, previous mode must disabled first.
SC1_DATA [0x449E]
SC1_DATA 0-RW SC1_DATA 0-RW [7:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
Transmit receive data register. Writing this register pushes byte onto transmit FIFO. Reading from this register pulls byte from receive FIFO.
SC1_UARTPER [0x44B4]
0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
SC1_UARTPER SC1_UARTPER 0-RW SC1_UARTPER 0-RW [15:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
baud rate period clock rate seen equation: 24MHz Rate
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SN250
Functional description-application modules
SC1_UARTFRAC [0x44B6]
SC1_ UARTFRAC 0-RW
SC1_UARTFRAC
baud rate fractional remainder clock rate derived from equation: 24MHz Rate
SC1_UARTCFG [0x44AE]
SC1_ UARTAUTO 0-RW SC1_ UARTFLOW 0-RW SC1_ UARTODD 0-RW SC1_ UARTPAR 0-RW SC1_ UART2STP 0-RW SC1_ UART8BIT 0-RW SC1_ UARTRTS 0-RW
SC1_UARTAUTO
this enable automatic assertion hardware. will deasserted when UART receive only more character before buffer full. will reasserted when UART receive more than character before buffer full. SC1_UARTRTS this register effect when this set. this enable RTS/CTS signals. Clear this disable signals. When this cleared, signal asserted hardware enable UART transmitter. GPIO_CFG register should configured mode SC1-4A hardware handshake with RTS/CTS SC1-2 handshaking. Clear this even parity. this parity. Clear this parity. this parity bit. Clear this stop bit. this stop bits Clear this seven data bits. this eight data bits. output signal. When this set, signal asserted logic GPIO low, 'XON', RS232 positive voltage), transmission will proceed. When this cleared, signal deasserted logic GPIO high, 'XOFF', RS232 negative voltage), transmission inhibited.
SC1_UARTFLOW
SC1_UARTODD SC1_UARTPAR SC1_UART2STP SC1_UART8BIT SC1_UARTRTS
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Functional description-application modules
SN250
SC1_UARTSTAT [0x44A4]
SC1_ UARTTXIDLE SC1_ UARTPARERR SC1_ UARTFRMERR SC1_ UARTRXOVF SC1_ UARTTXFREE SC1_ UARTRXVAL SC1_ UARTCTS
SC1_UARTTXIDLE SC1_UARTPARERR
This when transmit FIFO empty transmitter idle. This when receive FIFO seen parity error. This clears when data register (SC1_DATA) read. This when receive FIFO seen frame error. This clears when data register (SC1_DATA) read. This when receive FIFO been overrun. This clears when data register (SC1_DATA) read. This when transmit FIFO ready accept least byte. This when receive FIFO contains least byte. This shows current state input signal (pin GPIO11). When signal asserted logic GPIO low, 'XON', RS232 positive voltage), transmission will proceed. When signal deasserted logic GPIO high, 'XOFF', RS232 negative voltage), transmission inhibited current character. characters transmit buffer will remain there.
SC1_UARTFRMERR SC1_UARTRXOVF SC1_UARTTXFREE SC1_UARTRXVAL SC1_UARTCTS
SC1_RATELIN [0x44B0]
SC1_RATELIN [3:0] 0-RW
SC1_RATELIN 0-RW 0-RW 0-RW
linear component (LIN) clock rate seen equation: 24MHz Rate -EXP
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SN250
Functional description-application modules
SC1_RATEEXP [0x44B2]
SC1_RATEEXP [3:0] 0-RW
SC1_RATEEXP 0-RW 0-RW 0-RW
exponential component (EXP) clock rate seen equation: 24MHz Rate -EXP
SC1_SPICFG [0x44AC]
SPIRXDRV 0-RW SC_SPIMST 0-RW SC_SPIRPT 0-RW SC_SPIORD 0-RW SC_SPIPHA 0-RW SC_SPIPOL 0-RW
SC_SPIRXDRV
Receiver-driven mode selection (SPI master mode only). Clearing this will initiate transactions when transmit data available. Setting this will initiate transactions when receive buffer (FIFO DMA) space. This must always master mode (slave mode valid). This controls behavior transmit buffer underrun condition slave mode. Clearing this will send BUSY token (0xFF) setting this will repeat last byte. Changing this will only take effect when transmit FIFO empty transmit serializer idle. Clearing this will result Most Significant being transmitted first while setting this will result Least Significant being transmitted first. Clock phase configuration selected with clearing this sampling leading (first edge) setting this sampling second edge. Clock polarity configuration selected with clearing this rising leading edge setting this falling leading edge.
SC_SPIMST SC_SPIRPT
SC_SPIORD SC_SPIPHA SC_SPIPOL
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Functional description-application modules
SN250
SC1_SPISTAT [0x44A0]
SC_SPITXIDLE SC_SPITXFREE SC_SPIRXVAL SC_SPIRXOVF SPITXIDLE SPITXFREE SPIRXVAL SPIRXOVF
This when transmit FIFO empty transmitter idle. This when transmit FIFO ready accept least byte. This when receive FIFO contains least byte. This when receive FIFO been overrun. This clears when data register (SC1_DATA) read.
SC1_I2CCTRL1 [0x44A6]
SC_I2CSTOP SC_I2CSTART SC_I2CSEND SC_I2CRECV I2CSTOP 0-RW I2CSTART 0-RW I2CSEND 0-RW I2CRECV 0-RW
Setting this sends STOP command. auto clears when command completes. Setting this sends START repeated START command. autoclears when command completes. Setting this transmits byte. autoclears when command completes. Setting this receives byte. autoclears when command completes.
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SN250
Functional description-application modules
SC1_I2CCTRL2 [0x44A8]
SC_I2CACK SC_I2CAC 0-RW
Setting this will signal after received byte. Clearing this will signal NACK after received byte.
SC1_I2CSTAT [0x44A2]
SC_I2CCMDFIN SC_I2CRXFIN SC_I2CTXFIN SC_I2CRXNAK I2CCMDFIN I2CRXFIN I2CTXFIN I2CRXNAK
This when START STOP command completes. autoclears next activity. This when byte received. autoclears next activity. This when byte transmitted. autoclears next activity. This when NACK received from slave. autoclears next activity.
59/130
Functional description-application modules
SN250
SC1_DMACTRL [0x4498]
TXDMARST RXDMARST SC_TXLODB 0-RW SC_TXLODA 0-RW SC_RXLODB 0-RW SC_RXLODA 0-RW
SC_TXDMARST SC_RXDMARST SC_TXLODB
Setting this will reset transmit DMA. autocleared. Setting this will reset receive DMA. This autocleared. Setting this loads transmit buffer addresses starts controller processing transmit buffer This autocleared when completes. Writing zero this will have effect. Reading this indicates processing buffer active pending. Reading this zero indicates processing buffer complete idle. Setting this loads transmit buffer addresses starts controller processing transmit buffer This autocleared when completes. Writing zero this will have effect. Reading this indicates processing buffer active pending. Reading this zero indicates processing buffer complete idle. Setting this loads receive buffer addresses starts controller processing receive buffer This autocleared when completes. Writing zero this will have effect. Reading this indicates processing buffer active pending. Reading this zero indicates processing buffer complete idle. Setting this loads receive buffer addresses starts controller processing receive buffer This autocleared when completes. Writing zero this will have effect. Reading this indicates processing buffer active pending. Reading this zero indicates processing buffer complete idle.
SC_TXLODA
SC_RXLODB
SC_RXLODA
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SN250 SC1_DMASTAT [0x4496]
SC1_ RXPARB SC1_RXFRMB SC1_ RXPARA SC_RXOVF SC_RXOVF
Functional description-application modules
SC_TXACT
SC_TXACT
SC1_ RXFRMB SC_RXACT
SC1_ RXFRMA SC_RXACT
This when receive buffer passed frame error from lower hardware FIFO. This autocleared next time buffer loaded when receive reset. This when receive buffer passed frame error from lower hardware FIFO. This autocleared next time buffer loaded when receive reset. This when receive buffer passed parity error from lower hardware FIFO. This autocleared next time buffer loaded when receive reset. This when receive buffer passed parity error from lower hardware FIFO. This autocleared next time buffer loaded when receive reset. This when receive buffer passed overrun error from lower hardware FIFO. Neither receive buffers were capable accepting more bytes (unloaded), FIFO filled Buffer next buffer load, when drained FIFO, overrun error passed flagged with this bit. This autocleared next time buffer loaded when receive reset. This when receive buffer passed overrun error from lower hardware FIFO. Neither receive buffers were capable accepting more bytes (unloaded), FIFO filled Buffer next buffer load, when drained FIFO overrun error passed flagged with this bit. This autocleared next time buffer loaded when receive reset. This when transmit buffer currently active. This when transmit buffer currently active. This when receive buffer currently active. This when receive buffer currently active.
SC1_RXFRMA
SC1_RXPARB
SC1_RXPARA
SC_RXOVFB
SC_RXOVFA
SC_TXACTB SC_TXACTA SC_RXACTB SC_RXACTA
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Functional description-application modules
SN250
SC1_RXCNTA [0x4490]
SC1_RXCNTA SC1_RXCNTA [12:0] SC1_RXCNTA
byte offset (from which points location receive buffer where next byte will placed. When buffer fills subsequently unloads, this register wraps around holds value zero (pointing back first location buffer).
SC1_RXCNTB [0x4492]
SC1_RXCNTB SC1_RXCNTB [12:0] SC1_RXCNTB
byte offset (from which points location receive buffer where next byte will placed. When buffer fills subsequently unloads, this register wraps around holds value zero (pointing back first location buffer).
SC1_TXCNT [0x4494]
SC1_TXCNT SC1_TXCNT [12:0] SC1_TXCNT
byte offset (from which points location active (loaded) transmit buffer where next byte will placed. When buffer fills subsequently unloads, this register wraps around holds value zero (pointing back first location buffer).
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SN250
Functional description-application modules
SC1_RXBEGA [0x4480]
SC1_RXBEGA 0-RW SC1_RXBEGA 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC1_RXBEGA 0-RW 0-RW
Start address (byte aligned) receive buffer
SC1_RXENDA [0x4482]
SC1_RXENDA 0-RW SC1_RXENDA 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC1_RXENDA 0-RW 0-RW
address (byte aligned) receive buffer
SC1_RXBEGB [0x4484]
SC1_RXBEGB 0-RW SC1_RXBEGB 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC1_RXBEGB 0-RW 0-RW
Start address (byte aligned) receive buffer
63/130
Functional description-application modules
SN250
SC1_RXENDB [0x4486]
SC1_RXENDB 0-RW SC1_RXENDB 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC1_RXENDB 0-RW 0-RW
address (byte aligned) receive buffer
SC1_TXBEGA [0x4488]
SC1_TXBEGA 0-RW SC1_TXBEGA 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC1_TXBEGA 0-RW 0-RW
Start address (byte aligned) transmit buffer
SC1_TXENDA [0x448A]
SC1_TXENDA 0-RW SC1_TXENDA 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC1_TXENDA 0-RW 0-RW
address (byte aligned) transmit buffer
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SN250
Functional description-application modules
SC1_TXBEGB [0x448C]
SC1_TXBEGB 0-RW SC1_TXBEGB 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC1_TXBEGB 0-RW 0-RW
Start address (byte aligned) transmit buffer
SC1_TXENDB [0x448E]
SC1_TXENDB 0-RW SC1_TXENDB 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC1_TXENDB 0-RW 0-RW
address (byte aligned) transmit buffer
SC1_RXERRA [0x449A]
SC1_RXERRA SC1_RXERRA [12:0] SC1_RXERRA
byte offset (from which points location first error receive buffer there error, will hold value zero. This register will updated subsequent errors arriving DMA. next error will only recorded buffer unloads reloaded receive reset.
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Functional description-application modules
SN250
SC1_RXERRB [0x449C]
SC1_RXERRB SC1_RXERRB [12:0] SC1_RXERRB
byte offset (from which points location first error receive buffer there error, will hold value zero. This register will updated subsequent errors arriving DMA. next error will only recorded buffer unloads reloaded receive reset.
INT_SC1CFG [0x4624]
INT_ SCCMDFIN 0-RW 0-RW INT_ SC1PARERR INT_ SCTXFIN 0-RW 0-RW INT_ SC1FRMERR INT_ SCRXFIN 0-RW 0-RW INT_ SCTXULDB INT_ SCTXUND 0-RW 0-RW INT_ SCTXULDA INT_ SCRXOVF 0-RW 0-RW INT_ SCRXULDB INT_ SCTXIDLE 0-RW 0-RW INT_ SCRXULDA INT_ SCTXFREE 0-RW 0-RW INT_SCNAK INT_ SCRXVAL 0-RW
INT_SC1PARERR
[14]
Parity error received (UART) interrupt enable. Frame error received (UART) interrupt enable. buffer unloaded interrupt enable. buffer unloaded interrupt enable. buffer unloaded interrupt enable. buffer unloaded interrupt enable. Nack received (I2C) interrupt enable. START/STOP command complete (I2C) interrupt enable. Transmit operation complete (I2C) interrupt enable. Receive operation complete (I2C) interrupt enable. Transmit buffer underrun interrupt enable. Receive buffer overrun interrupt enable. Transmitter idle interrupt enable. Transmit buffer free interrupt enable. Receive buffer data interrupt enable.
INT_SC1FRMERR [13] INT_SCTXULDB INT_SCTXULDA INT_SCRXULDB INT_SCRXULDA INT_SCNAK INT_SCCMDFIN INT_SCTXFIN INT_SCRXFIN INT_SCTXUND INT_SCRXOVF INT_SCTXIDLE INT_SCTXFREE INT_SCRXVAL [12] [11] [10]
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SN250
Functional description-application modules
INT_SC1FLAG [0x460C]
INT_ SCCMDFIN 0-RW 0-RW INT_ SC1PARERR INT_ SCTXFIN 0-RW 0-RW INT_ SC1FRMERR INT_ SCRXFIN 0-RW 0-RW INT_ SCTXULDB INT_ SCTXUND 0-RW 0-RW INT_ SCTXULDA INT_ SCRXOVF 0-RW 0-RW INT_ SCRXULDB INT_ SCTXIDLE 0-RW 0-RW INT_ SCRXULDA INT_ SCTXFREE 0-RW 0-RW INT_SCNAK INT_ SCRXVAL 0-RW
INT_SC1PARERR
[14]
Parity error received (UART) interrupt pending. Frame error received (UART) interrupt pending. buffer unloaded interrupt pending. buffer unloaded interrupt pending. buffer unloaded interrupt pending. buffer unloaded interrupt pending. Nack received (I2C) interrupt pending. START/STOP command complete (I2C) interrupt pending. Transmit operation complete (I2C) interrupt pending. Receive operation complete (I2C) interrupt pending. Transmit buffer underrun interrupt pending. Receive buffer overrun interrupt pending. Transmitter idle interrupt pending. Transmit buffer free interrupt pending. Receive buffer data interrupt pending.
INT_SC1FRMERR [13] INT_SCTXULDB INT_SCTXULDA INT_SCRXULDB INT_SCRXULDA INT_SCNAK INT_SCCMDFIN INT_SCTXFIN INT_SCRXFIN INT_SCTXUND INT_SCRXOVF INT_SCTXIDLE INT_SCTXFREE INT_SCRXVAL [12] [11] [10]
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Functional description-application modules
SN250
Serial controller
SN250 module provides synchronous (SPI I2C) serial communications. Figure block diagram module. Figure block diagram
full-duplex interface module configured into these communication modes, cannot them simultaneously. reduce interrupt service requirements CPU, module contains buffered data management schemes. dedicated, buffered controller available while FIFO available both modes. addition, data register allows software application direct access data. Finally, routes interface signals GPIO pins. These shared with other functions controlled GPIO_CFG register. selecting alternate pin-functions, please refer Table Table
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SN250
Functional description-application modules
7.3.1
modes
mode supports both master slave modes. fixed word length bits. controller enabled with SC2_MODE mode following features:
Master slave modes Full duplex operation Programmable master mode clock frequency (12MHz max.) Slave mode 5MHz rate Programmable clock polarity clock phase Selectable data shift direction (either first) Optional slave select input MOSI (master out/slave MISO (master in/slave out) MSCLK (serial clock) SSEL (slave select-only slave mode)
following signals made available GPIO pins:
master mode
Master controller enabled with SC_SPIMST SC2_SPICFG register. module obtains reference clock from programmable clock generator. Clock rates clock division ratio from clock:
24MHz Rate -EXP
written SC2_RATEEXP register SC2_RATELIN register. Since range both values fastest data rate 12Mbps slowest 22.9bps. Master supports various frame formats depending upon clock polarity (SC_SPIPOL), clock phase (SC_SPIPHA), direction data (SC_SPIORD) (see Table 24). register bits SC_SPIPOL, SC_SPIPHA, SC_SPIORD defined within SC2_SPICFG register. Note: Switching configuration from SC_SPIPOL=1 SC_SPIPOL=0 without subsequently setting SC2_MODE=0 reinitializing will cause extra byte (0xFE) transmitted immediately before first intended byte.
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Functional description-application modules Table master mode formats
GPIO_CFG[7:4]
SN250
SC2_SPICFG SC_SPIORD SC_SPIPHA SC_SPIMST SC_SPIPOL SC2_MODE
Frame Format
SC2-3M mode
SC2-3M mode
SC2-3M mode
SC2-3M mode SC2-3M mode SC2-4S mode SC2-2 mode
Same above except first instead first Illegal Illegal
Serialized transmit data driven output MOSI. master data received from input MISO. generate slave select signals slave devices, other GPIO pins have used their assertion must controlled software. Characters transmitted received passed through transmit receive FIFOs. transmit receive FIFOs bytes deep. These FIFOs accessed under software control accessing SC2_DATA data register under hardware control using controller. When transmit character written (empty) transmit FIFO, register SC_SPITXIDLE SC2_SPISTAT register clears indicates that characters transmitted yet. Further transmit characters written transmit FIFO until full, which causes register SC_SPITXFREE SC2_SPISTAT register clear. After shifting transmit character MOSI pin, space transmit character becomes available transmit FIFO. This causes register SC_SPITXFREE SC2_SPISTAT register set. After characters shifted out, transmit FIFO empties, which causes register SC_SPITXIDLE SC2_SPISTAT register also. character received stored (empty) receive FIFO. register SC_SPIRXVAL SC2_SPISTAT register indicate that received characters read from receive FIFO. software reading from receive FIFO, receive FIFO will store characters. further reception
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SN250
Functional description-application modules dropped register SC_SPIRXOVF SC2_SPISTAT register set. FIFO hardware generates INT_SCRXOVF interrupt, register will indicate error condition until FIFO drained. Once marks error, there conditions that will clear error indication: setting appropriate SC_TX/RXDMARST SC2_DMACTRL register, loading appropriate buffer after unloaded. Receiving character always requires transmitting character. case when long stream receive characters expected, long sequence (dummy) transmit characters must generated. avoid software transmit initiating these transfers (and consuming unnecessary bandwidth), serializer instructed retransmit last transmitted character transmit busy token (0xFF), which determined register SC_SPIRPT SC2_SPICFG register. This functionality only enabled disabled) when transmit FIFO empty transmit serializer idle, indicated cleared SC_SPITXIDLE register SC2_SPISTAT register. Every time automatic character transmission started, transmit underrun detected there data transmit FIFO) register INT_SCTXUND INT_SC2FLAG register set. Note that after disabling automatic character transmission, reception characters stops receive FIFO holds characters just received.
Important: Receive complete event does automatically mean receive FIFO empty. Interrupts generated following events:
Transmit FIFO empty last character shifted transition SC_SPITXIDLE) Transmit FIFO changed from full full transition SC_SPITXFREE) Receive FIFO changed from empty empty transition SC_SPIRXVAL) Transmit buffer complete transition SC_TXACTA/B) Receive buffer complete transition SC_RXACTA/B) Received lost character while receive FIFO full (Receive overrun error) Transmitted character while transmit FIFO empty (Transmit underrun error)
generate interrupts CPU, interrupt masks INT_SC2CFG INT_CFG register must enabled.
slave mode
Slave controller enabled with SC_SPIMST cleared SC2_SPICFG register. Slave controller receives clock from external master device supports rates 5Mbps. Slave supports various frame formats depending upon clock polarity (SC_SPIPOL), clock phase (SC_SPIPHA), direction data (SC_SPIORD) (see Table 25). register bits SC_SPIPOL, SC_SPIPHA, SC_SPIORD defined within SC2_SPICFG registers. Note: Switching configuration from SC_SPIPOL=1 SC_SPIPOL=0 without subsequently setting SC2_MODE=0 reinitializing will cause extra byte (0xFE) transmitted immediately before first intended byte.
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Functional description-application modules Table slave formats
GPIO_CFG[7:4]
SN250
SC2_SPICFG SC_SPIORD SC_SPIPHA SC_SPIMST SC_SPIPOL SC2_MODE
Frame Format
SC2-4S mode
SC2-4S mode
SC2-4S mode
SC2-4S mode
SC2-4S Same above except first instead first mode SC23M mode SC2-2 mode Illegal
Illegal
When slave select (SSEL) signal asserted Master), transmit data driven output MISO data received from input MOSI. slave select signal SSEL used enable driving serialized data output signal MISO. also used reset slave shift register. Characters received transmitted passed through receive transmit FIFOs. transmit receive FIFOs bytes deep. These FIFOs accessed under software control accessing SC2_DATA data register under hardware control using controller. character received stored (empty) receive FIFO. register SC_SPIRXVAL SC2_SPISTAT register indicate that received characters read from receive FIFO. software reading from receive FIFO, receive FIFO will store characters. further reception dropped, register SC_SPIRXOVF SC2_SPISTAT register set.
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SN250
Functional description-application modules FIFO hardware generates INT_SCRXOVF interrupt, register will indicate error condition until FIFO drained. Once marks error, there conditions that will clear error indication: setting appropriate SC_TX/RXDMARST SC2_DMACTRL register, loading appropriate buffer after unloaded. Receiving character always causes serialization transmit character pulled from transmit FIFO. When transmit FIFO empty, transmit underrun detected data transmit FIFO) register INT_SCTXUND INT_SC2FLAG register set. Because there character available serialization, serializer retransmits last transmitted character busy token (0xFF), which determined register SC_SPIRPT SC2_SPICFG register. When transmit character written (empty) transmit FIFO, register SC_SPITXIDLE SC2_SPISTAT register clears indicates that characters transmitted yet. Further transmit characters written transmit FIFO until full, which causes register SC_SPITXFREE SC2_SPISTAT register clear. After shifting transmit character MISO pin, space transmit character becomes available transmit FIFO. This causes register SC_SPITXFREE SC2_SPISTAT register set. After characters shifted out, transmit FIFO empty, which causes register SC_SPITXIDLE SC2_SPISTAT register also. Interrupts generated following events:
Transmit FIFO empty last character shifted transition SC_SPITXIDLE) Transmit FIFO changed from full full transition SC_SPITXFREE) Receive FIFO changed from empty empty transition SC_SPIRXVAL) Transmit buffer complete transition SC_TXACTA/B) Receive buffer complete transition SC_RXACTA/B) Received lost character while receive FIFO full (Receive overrun error) Transmitted character while transmit FIFO empty (Transmit underrun error)
generate interrupts CPU, interrupt masks INT_SC2CFG INT_CFG register must enabled.
7.3.2
Master Mode
controller only available master mode. controller enabled with SC2_MODE Master controller supports Standard (100kbps) Fast (400kbps) modes. Address arbitration implemented, multiple master applications supported. signals pure open-collector signals, external pull-up resistors required. mode following features:
Programmable clock frequency (400kHz max.) 10-bit addressing (serial data) (serial clock)
following signals made available GPIO pins:
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Functional description-application modules
SN250
Master controller obtains reference clock from programmable clock generator. Clock rates clock division ratio from 24MHz clock:
24MHz Nominal Rate -EXP
written SC2_RATEEXP register SC2_RATELIN register. Table shows rate settings Standard (100kbps) Fast (400kbps) operation. Table nominal rate programming
SPPR
Nominal Rate 100kbps 375kpbs 400kbps
Note that, 400kbps, specification requires minimum period 1.3µs. strictly compliant, rate needs lowered 375kbps. Master controller supports generation various frame segments defined register bits SC_I2CSTART, SC_I2CSTOP, SC_I2CSEND, SC_I2CRECV within SC2_I2CCTRL1 register. Table summarizes these frames. Full frames have constructed under software control generating individual segments. necessary segment transitions shown Figure NACK generation receive frame segment determined with register SC_I2CACK SC2_I2CCTRL2 register. Generation 7-bit address accomplished with transmit segment. upper bits transmitted character contain 7-bit address. remaining lower contains command type ("read" "write"). Generation 10-bit address accomplished with transmit segments. upper bits first transmit character must 0x1E. next bits most significant bits 10-bit address. remaining lower contains command type ("read" "write"). second transmit segment remaining bits 10-bit address.
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SN250 Table master segment formats
Functional description-application modules
SC2_I2CCTR GPIO_CFG[7:4] SC_I2CSTART SC_I2CSEND SC_I2CRECV SC_I2CSTOP SC2_MODE
Frame Segments
SC2-2 mode
SC2-2 mode
SC2-2 mode
SC2-2 mode
SC2-2 mode SC2-2 mode
pending frame segment Illegal
SC2-4M mode Illegal SC2-4A mode Illegal
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Functional description-application modules
SN250
Characters received transmitted passed through receive transmit FIFOs. master transmit receive FIFOs byte deep. These FIFOs accessed under software control. (Re)start stop segments initiated setting register bits SC_I2CSTART SC_I2CSTOP SC2_I2CCTRL1 register, followed waiting until they have cleared. Alternatively, register SC_I2CCMDFIN SC2_I2CSTAT used waiting. initiating transmit segment, data written SC2_DATA data register, followed setting register SC_I2CSEND SC2_I2CCTRL1 register, completed waiting until clears. Alternatively, register SC_I2CTXFIN SC2_I2CSTAT used waiting. receive segment initiated setting register SC_I2CRECV SC2_I2CCTRL1 register, waiting until clears, then reading from SC2_DATA data register. Alternatively, register SC_I2CRXFIN SC2_I2CSTAT used waiting. register SC_I2CRXNAK SC2_I2CSTAT register indicates NACK received from slave device. Interrupts generated following events:
command (SC_I2CSTART/SC_I2CSTOP) completed transition SC_I2CCMDFIN) Character transmitted slave device responded with NACK Character transmitted transition SC_I2CTXFIN) Character received transition SC_I2CRXFIN) Received lost character while receive FIFO full (Receive overrun error) Transmitted character while transmit FIFO empty (Transmit underrun error)
generate interrupts CPU, interrupt masks INT_SC2CFG INT_CFG register must enabled.
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SN250
Functional description-application modules
7.3.3
Registers
SC2_MODE [0x442A]
SC2_MODE [1:0] SC2_MODE 0-RW 0-RW
Mode: disabled; disabled; mode; mode. Note: change between modes, previous mode must disabled first.
SC2_DATA [0x441E]
SC2_DATA 0-RW SC2_DATA 0-RW [7:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW
Transmit receive data register. Writing this register pushes byte onto transmit FIFO. Reading from this register pulls byte from receive FIFO.
SC2_RATELIN [0x4430]
SC2_RATELIN [3:0] 0-RW
SC2_RATELIN 0-RW 0-RW 0-RW
linear component (LIN) clock rate seen equation: 24MHz Rate -EXP
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Functional description-application modules
SN250
SC2_RATEEXP [0x4432]
SC2_RATEEXP [3:0] 0-RW
SC2_RATEEXP 0-RW 0-RW 0-RW
exponential component (EXP) clock rate seen equation: 24MHz Rate -EXP
SC2_SPICFG [0x442C]
SC_SPIRXDRV SPIRXDRV 0-RW SC_SPIMS 0-RW SC_SPIRP 0-RW SC_SPIOR 0-RW SC_SPIPH 0-RW SC_SPIPO 0-RW
Receiver-driven mode selection (SPI master mode only). Clearing this will initiate transactions when transmit data available. Setting this will initiate transactions when receive buffer (FIFO DMA) space. Setting this will master mode while clearing this will slave mode. This controls behavior transmit buffer underrun condition slave mode. Clearing this will send BUSY token (0xFF) setting this will repeat last byte. Changing this will only take effect when transmit FIFO empty transmit serializer idle. Clearing this will result Most Significant being transmitted first while setting this will result Least Significant being transmitted first. Clock phase configuration selected with clearing this sampling leading (first edge) setting this sampling second edge. Clock polarity configuration selected with clearing this rising leading edge setting this falling leading edge.
SC_SPIMST SC_SPIRPT
SC_SPIORD SC_SPIPHA SC_SPIPOL
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SN250
Functional description-application modules
SC2_SPISTAT [0x4420]
SPITXIDLE SPITXFREE SPIRXVAL SPIRXOVF
SC_SPITXIDLE SC_SPITXFREE SC_SPIRXVAL SC_SPIRXOVF
This when transmit FIFO empty transmitter idle. This when transmit FIFO ready accept least byte. This when receive FIFO contains least byte. This when receive FIFO been overrun. This clears when data register (SC2_DATA) read.
SC2_I2CCTRL1 [0x4426]
SC_I2CSTOP SC_I2CSTART SC_I2CSEND SC_I2CRECV I2CSTOP 0-RW I2CSTART 0-RW I2CSEND 0-RW I2CRECV 0-RW
Setting this sends STOP command. autoclears when command completes. Setting this sends START repeated START command. autoclears when command completes. Setting this transmits byte. autoclears when command completes. Setting this receives byte. autoclears when command completes.
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Functional description-application modules
SN250
SC2_I2CCTRL2 [0x4428]
SC_I2CACK SC_I2CAC 0-RW
Setting this will signal after received byte. Clearing this will signal NACK after received byte.
SC2_I2CSTAT [0x4422]
SC_I2CCMDFIN SC_I2CRXFIN SC_I2CTXFIN SC_I2CRXNAK I2CCMDFIN I2CRXFIN I2CTXFIN I2CRXNAK
This when START STOP command completes. autoclears next activity. This when byte received. autoclears next activity. This when byte transmitted. autoclears next activity. This when NACK received from slave. autoclears next activity.
80/130
SN250
Functional description-application modules
SC2_DMACTRL [0x4418]
SC_TXDMARST TXDMARST RXDMARS SC_TXLOD 0-RW SC_TXLOD 0-RW SC_RXLOD 0-RW SC_RXLOD 0-RW
Setting this will reset transmit DMA. autocleared. Setting this will reset receive DMA. This autocleared. Setting this loads transmit buffer addresses starts controller processing transmit buffer This autocleared when completes. Writing zero this will have effect. Reading this indicates processing buffer active pending. Reading this zero indicates processing buffer complete idle. Setting this loads transmit buffer addresses starts controller processing transmit buffer This autocleared when completes. Writing zero this will have effect. Reading this indicates processing buffer active pending. Reading this zero indicates processing buffer complete idle. Setting this loads receive buffer addresses starts controller processing receive buffer This autocleared when completes. Writing zero this will have effect. Reading this indicates processing buffer active pending. Reading this zero indicates processing buffer complete idle. Setting this loads receive buffer addresses starts controller processing receive buffer This autocleared when completes. Writing zero this will have effect. Reading this indicates processing buffer active pending. Reading this zero indicates processing buffer complete idle.
SC_RXDMARST SC_TXLODB
SC_TXLODA
SC_RXLODB
SC_RXLODA
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Functional description-application modules
SN250
SC2_DMASTAT [0x4416]
SC_RXOVFB SC_RXOVFA SC_TXACTB SC_TXACTA SC_RXACTB SC_RXACTA
SC_RXOVFB
This when receive buffer passed overrun error from lower hardware FIFO. Neither receive buffers were capable accepting more bytes (unloaded), FIFO filled Buffer next buffer load, when drained FIFO overrun error passed flagged with this bit. This autocleared next time buffer loaded when receive reset. This when receive buffer passed overrun error from lower hardware FIFO. Neither receive buffers were capable accepting more bytes (unloaded), FIFO filled Buffer next buffer load, when drained FIFO overrun error passed flagged with this bit. This autocleared next time buffer loaded when receive reset. This when transmit buffer currently active. This when transmit buffer currently active. This when receive buffer currently active. This when receive buffer currently active.
SC_RXOVFA
SC_TXACTB SC_TXACTA SC_RXACTB SC_RXACTA
SC2_RXCNTA [0x4410]
SC2_RXCNTA SC2_RXCNTA [12:0] SC2_RXCNTA
byte offset (from which points location receive buffer where next byte will placed. When buffer fills subsequently unloads, this register wraps around holds value zero (pointing back first location buffer).
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SN250
Functional description-application modules
SC2_RXCNTB [0x4412]
SC2_RXCNTB SC2_RXCNTB [12:0] SC2_RXCNTB
byte offset (from which points location receive buffer where next byte will placed. When buffer fills subsequently unloads, this register wraps around holds value zero (pointing back first location buffer).
SC2_TXCNT [0x4414]
SC2_TXCNT SC2_TXCNT [12:0] SC2_TXCNT
byte offset (from which points location active (loaded) transmit buffer where next byte will placed. When buffer fills subsequently unloads, this register wraps around holds value zero (pointing back first location buffer).
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Functional description-application modules
SN250
SC2_RXBEGA [0x4400]
SC2_RXBEGA 0-RW SC2_RXBEGA 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC2_RXBEGA 0-RW 0-RW
Start address (byte aligned) receive buffer
SC2_RXENDA [0x4402]
SC2_RXENDA 0-RW SC2_RXENDA 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC2_RXENDA 0-RW 0-RW
address (byte aligned) receive buffer
84/130
SN250
Functional description-application modules
SC2_RXBEGB [0x4404]
SC2_RXBEGB 0-RW SC2_RXBEGB 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC2_RXBEGB 0-RW 0-RW
Start address (byte aligned) receive buffer
SC2_RXENDB [0x4406]
SC2_RXENDB 0-RW SC2_RXENDB 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC2_RXENDB 0-RW 0-RW
address (byte aligned) receive buffer
SC2_TXBEGA [0x4408]
SC2_TXBEGA 0-RW SC2_TXBEGA 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC2_TXBEGA 0-RW 0-RW
Start address (byte aligned) transmit buffer
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Functional description-application modules
SN250
SC2_TXENDA [0x440A]
SC2_TXENDA 0-RW SC2_TXENDA 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC2_TXENDA 0-RW 0-RW
address (byte aligned) transmit buffer
SC2_TXBEGB [0x440C]
SC2_TXBEGB 0-RW SC2_TXBEGB 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC2_TXBEGB 0-RW 0-RW
Start address (byte aligned) transmit buffer
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SN250
Functional description-application modules
SC2_TXENDB [0x440E]
SC2_TXENDB 0-RW SC2_TXENDB 0-RW [12:0] 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW 0-RW SC2_TXENDB 0-RW 0-RW
address (byte aligned) transmit buffer
SC2_RXERRA [0x441A]
SC2_RXERRA
[12:0]
6&B5;(55$
6&B5;(55$
byte offset (from which points location first error receive buffer there error, will hold value zero. This register will updated subsequent errors arriving DMA. next error will only recorded buffer unloads reloaded receive reset.
SC2_RXERRB [0x441C]
SC2_RXERRB SC2_RXERRB [12:0] SC2_RXERRB
byte offset (from which points location first error receive buffer there error, will hold value zero. This register will updated subsequent errors arriving DMA. next error will only recorded buffer unloads reloaded receive reset.
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Functional description-application modules
SN250
INT_SC2CFG [0x4626]
INT_ SCCMDFIN 0-RW INT_SCTXULDB INT_SCTXULDA INT_SCRXULDB INT_SCRXULDA INT_SCNAK INT_SCCMDFIN INT_SCTXFIN INT_SCRXFIN INT_SCTXUND INT_SCRXOVF INT_SCTXIDLE INT_SCTXFREE INT_SCRXVAL INT_ SCTXFIN 0-RW [12] [11] [10] INT_ SCRXFIN 0-RW 0-RW INT_ SCTXULDB INT_ SCTXUND 0-RW 0-RW INT_ SCTXULDA INT_ SCRXOVF 0-RW 0-RW 0-RW 0-RW INT_SCNA INT_ SCRXVAL 0-RW
INT_ INT_ SCRXULDB SCRXULDA INT_ SCTXIDLE 0-RW INT_ SCTXFREE 0-RW
buffer unloaded interrupt enable. buffer unloaded interrupt enable. buffer unloaded interrupt enable. buffer unloaded interrupt enable. Nack received (I2C) interrupt enable. START/STOP command complete (I2C) interrupt enable. Transmit operation complete (I2C) interrupt enable. Receive operation complete (I2C) interrupt enable. Transmit buffer underrun interrupt enable. Receive buffer overrun interrupt enable. Transmitter idle interrupt enable. Transmit buffer free interrupt enable. Receive buffer data interrupt enable.
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SN250
Functional description-application modules
INT_SC2FLAG [0x460E]
INT_ SCCMDFIN 0-RW INT_ SCTXFIN 0-RW INT_ SCRXFIN 0-RW 0-RW INT_ SCTXULDB INT_ SCTXUND 0-RW 0-RW INT_ SCTXULDA INT_ SCRXOVF 0-RW 0-RW INT_ SCRXULDB INT_ SCTXIDLE 0-RW 0-RW INT_ SCRXULDA INT_ SCTXFREE 0-RW 0-RW INT_SCNAK INT_ SCRXVAL 0-RW
INT_SCTXULDB INT_SCTXULDA INT_SCRXULDB INT_SCRXULDA INT_SCNAK INT_SCCMDFIN INT_SCTXFIN INT_SCRXFIN INT_SCTXUND INT_SCRXOVF INT_SCTXIDLE INT_SCTXFREE INT_SCRXVAL
[12] [11] [10]
buffer unloaded interrupt pending. buffer unloaded interrupt pending. buffer unloaded interrupt pending. buffer unloaded interrupt pending. Nack received (I2C) interrupt pending. START/STOP command complete (I2C) interrupt pending. Transmit operation complete (I2C) interrupt pending. Receive operation complete (I2C) interrupt pending. Transmit buffer underrun interrupt pending. Receive buffer overrun interrupt pending. Transmitter idle interrupt pending. Transmit buffer free interrupt pending. Receive buffer data interrupt pending.
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Functional description-application modules
SN250
General purpose timers
SN250 integrates general-purpose, 16-bit timers-TMR1 TMR2. Each timers contains following features:
Configurable clock source Counter load output compare registers input capture registers configured Up/down counting (for motor drive phase correction) Single shot operation mode (timer stops zero threshold)
Figure block diagram Timer TMR1 module. Timer TMR2 identical. Figure Timer TMR1 block diagram
7.4.1
Clock sources
clock source each timer chosen from main 12MHz clock, 32.768kHz clock, 1kHz RC-Clock, from external source 100kHz) through TMR1CLK TMR2CLK. After choosing clock source (see Table 28), frequency further divided generate final timer cycle provided timer controller (see Table 29). addition, clock edge (either rising falling) this timer clock selected (see Table 30).
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SN250 Table
Functional description-application modules TMR1 TMR2 clock source settings
Clock Source clock 32.768kHz clock clock GPIO clock input
TMR_CLK[1:0]
Table
Clock source divider settings
Clock Source Prescale Factor
TMR_PSCL[3:0] 0.10 11.15
Table
TMR_EDGE
Clock edge setting
Clock Source Rising Falling
Note:
configuration changes take effect until next edge timer's clock source. These functions separately controlled TMR1 TMR2 setting bits TMR_CLK, TMR_FILT, TMR_EDGE, TMR_PSCL timer registers TMR1_CFG TMR2_CFG, respectively.
7.4.2
Timer functionality (counting)
Each timer supports three counting modes: increasing, decreasing, alternating (where counting will increase, then decrease, then increase). These modes controlled setting TMR_DOWN TMR_BIDIR bits within TMR1_CFG TMR2_CFG registers. Upward counting continues until counter value reaches threshold value stored TMR1_TOP TMR2_TOP register. Downward counting continues until counter value reaches value zero. When alternating counting mode enabled, triangular-shaped waveform count-value created. Figure through Figure illustrate different counting modes available from timers. Counting enabled disabled with register TMR_EN TMR1_CFG TMR2_CFG registers. When timer disabled, counter stops counting maintains count value. Enabling masked with TMR1ENMSK TMR2ENMSK, depending register TMR_EXTEN TMR1_CFG TMR2_CFG registers. default, counting operation repetitive. restricted single counting enabled with register TMR_1SHOT located TMR1_CFG TMR2_CFG registers.
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Functional description-application modules Figure Timer counting mode-saw tooth,
SN250
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SN250 Figure
Functional description-application modules Timer counting mode-saw tooth, down
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Functional description-application modules Figure Timer counting mode-alternating, initially
SN250
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SN250
Functional description-application modules Figure Timer counting mode-alternating, initially down
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Functional description-application modules
SN250
7.4.3
Timer functionality (output compare)
There output signals from each timer generate application-specific waveforms. These waveforms generated altered comparison results with timer count value. There four comparison results:
Counter value reaches zero. Counter value reaches threshold value TMR1_TOP TMR2_TOP register. Counter value reaches comparison value TMR1_CMPA TMR2_CMPA register. Counter value reaches comparison value TMR1_CMPB TMR2_CMPB register.
output waveform generation from each timer controlled with register bits (TMR_CMPMOD inverted with TMR_CMPINV) TMR1_CMPCFGA, TMR1_CMPCFGB, TMR2_CMPCFGA, TMR2_CMPCFGB registers. Table summarizes output waveform generation modes. Table Output waveform settings
Output waveform generation mode Disable alteration Toggle count count TOP, clear count CMPA count TOP, clear count CMPB count CMPA, clear count Toggle count CMPA count CMPA, clear count CMPB Clear count CMPB, clear count count CMPB, clear count CMPA Toggle count CMPB Toggle count ZERO count ZERO, clear count count ZERO, clear count CMPA count ZERO, clear count CMPB
TMR_CMPMOD[3:0]
output signals TMR1OA TMR1OB from Timer TMR2OA TMR2OB from Timer available GPIO. selecting alternate functions, refer Table Table Figure Figure show examples timer output generation modes.
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SN250
Functional description-application modules Figure Timer output generation mode example-saw tooth, non-inverting
Figure Timer output generation mode example-alternating, non-inverting
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Functional description-application modules
SN250
7.4.4
Timer functionality (input capture)
There capture registers that store timer count value trigger condition from GPIO signals. timer trigger signals TMR1IA TMR1IB Timer TMR2IA TMR2IB Timer provided external signals routed GPIO pins. These timer trigger signals synchronized main 12MHz clock, passed optional glitch filter, followed edge detection circuitry. These functions controlled software with register bits TMR_CAPMOD[1:0], TMR_CAPFILT TMR1_CAPCFGA, TMR1_CAPCFGB, TMR2_CAPCFGA, TMR2_CAPCFGB registers. Table GPIO/Timer trigger conditioning
Detection Mode Disabled Rising Edge Falling Edge Either Edge
TMR_CAPMOD[1:0]
glitch filters consist flip-flop-driven, 4-bit shift register clocked with main 12MHz clock.
7.4.5
Timer interrupt sources
Each timer supports number interrupts sources:
overflow during up-count from zero. counter reaching output compare values stored TMR1_CMPA, TMR1_CMPB TMR2_CMPA, TMR2_CMPB registers. counter reaching zero, TMR1_TOP, TMR2_TOP. capturing events from GPIO.
generate interrupts CPU, interrupt masks INT_TMRCFG INT_CFG registers must enabled.
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SN250
Functional description-application modules
7.4.6
Registers
TMR1_CFG [0x450C]
TMR_PSCL 0-RW 0-RW 0-RW 0-RW 0-RW TMR_EXTEN 0-RW TMR_EN TMR_FILT 0-RW 0-RW TMR_BIDIR TMR_EDGE 0-RW 0-RW TMR_DOWN 0-RW TMR_1SHOT
TMR_CLK 0-RW 0-RW
TMR_EXTEN
[12]
Control external enable mask pin. When this clear, check status TMR1ENMSK pin. When thi
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