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Rhine Datasheet Revision January 2002 AMCC Dear custome


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S4804CBI41
Rhine Datasheet
Revision January 2002
AMCC
Dear customer,
Thank choosing AMCC device. appreciate your confidence products.
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AMCC
Part Number S4804CBI41 Product Brief Version January 2002 Datasheet Revision
RHINE
Features
PRODUCT BRIEF
OC-48 4xOC-12 16xOC-3 SONET/SDH FRAMER POS/AMAPPER
S4804 highly-integrated VLSI device that provides full-duplex mapping packets Acells SONET/SDH payloads. provides support both uni-directional bi-directional rings. S4804 provides full section, line, path overhead processing, supports framing, scrambling/descrambling, alarm signal insertion/detection, bit-interleaved parity (B1/B2/B3) processing. S4804 SONET/SDH standards compliant with Bellcore GR-253, G.707, ITU-T 432.1, ANSI T1.105 -1995, IETF RFCs 1619/1661/1662/2615. general purpose 8-bit 16-bit microprocessor interface provided control monitoring. interface supports both Inteland Motorolatype microprocessors, capable operating either interrupt-driven polled-mode configuration. addition, standard signal IEEE 1149.1 JTAG Test Port provided Boundary Scan test purposes.
Provides SONET/SDH STS-48/STM-16, STS-12/STM4, STS-3/STM-1 line interfaces. STS-48/STM-16 data stream supports single STS-48c/ AU-4-16c, valid combination STS-12c/AU-4-4c and/or STS-3c/AU-4 SONET/SDH payloads. Each STS-12/STM-4 data stream supports single STS12c/AU-4-4c STS-3c/AU-4 SONET/SDH payloads. Each STS-3/STM-1 data stream supports single STS-3c/AU-4 SONET/SDH payload. Supports mixed STS-3 STS-12 line rates Provides full-duplex mapping Acells packets each payload tributary. Supports termination mixed Aand tributaries. Terminates/generates SONET/SDH section, line, path layers with transport/section overhead interfaces both transmit receive directions. port support protection-switching configurations between RHINE devices. 16-bit, interface STS-48/STM-16 mode, serial interfaces operating 622/155 STS-12/3 (STM-4/1) modes line side. 32-bit, parallel interface (FlexBus-3TM) operating system side. micron, 2.5V core, 3.3V tolerant I/O. Packaged CBGA.
Applications
Aswitches Packet over SONET Routers Switches SONET/SDH Drop Multiplexers, Terminal Multiplexers, Digital Cross Connects Test equipment
S4804CBI Block Diagram
APS_DAT_IN[0:31] APS_CLK_IN[3:0] TX_TOH_FRAME TX_RING_DATA SYNCMODE RSTB INTB D[15:0] ADDR[13:0] WRB(RWB) RDB(DSB) RDYB(DTACKB) BUSMODE APS_INTB TX_TOH_DAT TX_TOH_CLK
UPCLK
TX_ERR[1:4] TX_EOP[1:4] TX_LBYTE[1:0] TX_SYS_DAT[31:0] TX_ADR[4:0] TX_CLK[1:4] TX_PRTY[1:4] TX_ENB[1:4] TX_SOC/P[1:4] TX_CLAV_PDA[1:4] TX_CLK_OUT[1:4] RX_SYS_DAT[31:0] RX_ADR[4:0] RX_CLK[1:4] RX_PRTY[1:4] RX_ENB[1:4] RX_SOC/P[1:4] RX_CLAV_PDA[1:4] RX_DV[1:4] RX_LBYTE[1:0] RX_EOP[1:4] RX_ERR[1:4] RX_CLK_OUT[1:4} Production Release Information information contained this document about product fully tested characterized phase. features described herein supported. Contact AMCC updates this document latest product status.
TX_SONETCLK_OUT_155_622
INSERT SPE/VC GEN.
MICROPROCESSOR ATM/HDLC PROC (X43 SCRMBL MON.
LINE SIDE INTERFACE
TX_SONETCLK_OUT_155 TX_DATA[15:0] TX_SONETCLK_IN TX_FRAME_IN RX_DATA[15:0] RX_SONETCLK[1:16] RX_LOSEXT[1:16] RX_REF_CLK_OUT
FRAMER
FRAMER
MON. Proc
ATM/HDLC PROC (X43 DeSCRMBL ATM/ HDLC CNTRS
Intrp
EXTRACT
GPIO/LED
JTAG PORT
FIFO TRTSB TS_EN
APS_DAT_OUT[0:31]
RX_TOH_DAT
RX_TOH_CLK
APS_CLK_OUT
RX_RING_DATA
RX_TOH_FRAME
RX_ALARM_OUT[1:16]
AMCC
GPIO[7:0]
UTOPIA-3 FlexBusINTERFACE
FIFO
Datasheet Revision
S4804CBI41: RHINE
Product Brief Version January 2002
STS-48 POS/ASONET MAPPER
Overview Applications
Sonet/SDH Processing
S4804 implements SONET/SDH processing fullduplex ATM/packet-mapping functions STS-48/STM-16, STS-12/STM-4, STS-3/STM-1 data streams. support either single STS-48c/AU-4-16c valid combination STS-12c/AU-4-4c STS-3c/AU-4 signals within STS-48/ STM-16. S4804 also supports STS-12/STM-4 signals (each containing single STS-12c/AU-4-4c STS-3c/AU4), STS-3c/STM-1 signals each containing STS-3c/ AU-4. TOH/SOH interface provides direct add/drop capability both Section Line channels. S4804 also includes clear channel mode that enables direct transmission system payload from system interface line-side interface. transmit side, S4804 generates section, line, path overhead. performs framing pattern insertion (A1, A2), scrambling, alarm-signal insertion, generates section, line, path Interleaved Parity (B1/B2/B3) far-end performance monitoring. receive side, S4804 processes section, line, path overhead. performs framing (A1, A2), descrambling, alarm detection, pointer processing, Interleaved Parity monitoring (B1/B2/B3), error-count accumulation performance monitoring.
PRODUCT BRIEF
HDLC Processing
When configured mode, S4804's HDLC processor(s) provides HDLC packet processing defined IETF RFCs 1619, 1662 2615. addition, S4804 optionally performs scrambling (X43+1).
Direct Mode
Direct Mode allows protocol directly into Sonet/SDH Synchronous Payload Envelope, by-passing Aand HDLC processing circuitry.
Automatic Protection Switching
S4804 provides input output interfaces convey signals between S4804 devices configured operation. This configuration supports both configurations.
Line-side Interface
line side, S4804 supports 16-bit parallel interface, operating 155MHz single OC-48 optical interface. provides serial interfaces either OC-12 and/or OC-3 optical interfaces. Mixed OC-3 OC-12 line rates supported.
System Interface
S4804 supports 32-bit, 100-MHz system interface. Acell transfers, S4804 supports Utopia Level interface. packet transfers, S4804 supports FlexBusinterface. S4804 also provides support quad, 8-bit extension Utopia
AProcessing
When configured Acell processing, S4804's transmit Aprocessor(s) will perform necessary cell processing defined AUNI3.1, ITU-T I.432.1, I.432.2.
TYPICAL APPLICATIONS: S4804CBI RHINE System
Microprocessor Control Reference Clock Control Addr Data
Single STS-48 Quad STS-12/ 16xSTS-3 Aover SONET Application
Router ASwitch TX_SONETCLK_IN TX_DATA[15:0] SONET XCVR RX_LOSEXT[1] with Recovery RX_SONETCLK[2] RX_DATA[15:0]
SONET Line Side Interface
SerTxD± Fiber Optic Transceiver SerRxD± Lucent Either Single OC-48 Four OC-12 Sixteen OC-3
AMCC
RHINE S4804CBI
TX_CLK TX_SYS_DAT[31:0] RX_SYS_DAT[31:0] RX_CLK
Multi Channel Link Layer Device
Switching/ Routing Logic
OC-48 Mode: AMCC 3055 Insertion Extraction
AMCC Minuteman Road, Andover, 01810 (978) 623-0009 Fax: (978) 623-0024
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Specification History
Rev.
Date
5/24/99 6/15/99 6/15/99 8/25/99 9/30/99 12/2/99 7/14/00
Description Change
Incorporated Engineering Requirements document (Rev document. Incorporated review updates (Rev document changes. Incorporated review updates (Rev document changes. Updated document. Included Table Incorporated final spec; added appendix with corrections memory maps; fixed typos based customer feedback reviews. This major revision RHINE. Change bars appear outside edge; they reflect information that changed. Note: Capabilities Rhine shown blue with double underline. Change bars outside edge designate corrections editorial changes. Updated timing diagrams specifications. Inserted Power figures Described GPIO when SYS_SYNC_OUT_EN=1. Removed J1_3_MATCH functionality. Deleted SF/SD monitoring blocks since adequate mixed payloads. Added TX_CLK_OUT_INH_[1:4] Renamed TX_SEL_ENB RX_SYS_B2B_ALLOW. Updated default reset values register map. Removed cross-connect functionality (HPIN_SEL_x[3:0]). Corrected Framing description (search order). Modified Flexbus-3 Utopia-3 compliant. Removed built-in support UPSR: RDI/REI Ring channel, dual-feed auto path switching, RX_LAIS_SW_INH_x Removed references TX_FIFO_ERR_E Removed framer bypass functionality. Added provisionable send EOP, LBYTE Amode; Made interpretation LBYTE programmable. Corrected mislabeled Use" table. Corrected TX_SING_CLAV reset value (=1). Removed restriction single flags between packets. Corrected Group Clear value. Added SYS_SYNC_OUT_EN functionality Added APS_DELAY_EN accommodate 156ns delay. Deleted RX_LOS_INH inhibit PAIS based LOS. Documented current RX_LOSEXT_INH_x inhibit PAIS LOS. Corrected location RX_PG_FIFO_i_j_E bits map. Removed support. Corrected K1K2 Insert text Corrected TX_, RX_TRIB_INH functional descriptions. Deleted TX_FOUT_BYTE[2:0], TX_FRAME_IN_INH_[x] since they're used control frame alignment. Specified frame sync alignment after resync. Corrected capture MSBs K2[7:3]; LSBs separately. Corrected Table section only APS_CLK_OUT. Removed Sonet Loopback support STS-3 STS-12
12/13/00
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Description Change
Corrected errors Description section Register section
Rev.
Date
1/5/01
7/2/01
Added Tables that were missing from 1.6. Corrected Tables updated STS-3C table values. Corrected interpretation fifofull, fifoempty POS. Deferred RX_LAIS_DATA_DIS_INH_x; implemented essential. (Editorial) Changed "Read Only, cleared "Read cleared input expects, checks only single byte (section 8.2.3) Changed signal names interface remove _RING_ (for consistency w/sumd/s) Corrected PATH_J1_SUMD equation eliminate PATH_J1_SUMD_MASK used next higher level. trace order reverted TX_J1_COMMON_[47:0]_[7:0]. Corrected resolution FIFOFULL, FIFOEMPTY regs bytes STS-3c. Removed refs TX_POH_SCR_INH RX_POH_DSCR_INH. Rhine timing, updated tPRXI min/max from 2.5/8ns 2/6ns; Changed THTX15 THTX15 from .75ns .5ns. Combined STS48C TSTX15 THTX15 common spec TX_DATA[0:15] references FILL_CHECK tagged with NotInRhine4.0. Tagged remaining refs LINE_RING PATH_RING NotInRhine4.0. Updated Power numbers spec section provide measured values each mode Removed section (since redundant section outdated information. Changed type desc section 3.3V tolerant Conditionalized references TX_POS_FIFOUNDER_E Corrected rating units from ATM_IDLE_CAP_E longer supported; Text tagged NotInRhine4.0. RX_PI_PAIS_x, RX_PI_LOP_x undefined concatenated tribs. BIT_BLKCNT does apply Rhine comply with SONET/SDH specs (B1, B3/G1 count block errs; B2/M1 always count errs). UDF2-UDF4 undefined direction.
Changed TXFRAMEIN timing diagram spec from setup hold time pulse width requirement since TXFRAMEIN asynchronous TXSONETCLKIN.
11/27/01
P-RDI removed within frame removal received P-AIS. Document exact behaviour. Increase FlexBus3 clock spec 104Mhz minor typographical errors Corrected error first line RX_REF_CLK_OUT selection table text description TX/RX_APS_SEL description RX_ENB toggle initialization requirement Added user notes Rhine appendix datasheet.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Description Change
Changed document Production Released document longer document status. Added final User Notes, section called Appendix "User Notes".
Rev.
Date
1/8/02
Note: Features changes applicable Rhine later indicated blue double-underscored text.
viii
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Contents
Applicable Documents Assignments Descriptions
Table SONET Interface Table FlexBus Interface Table Auto Protection Switching Interface Table Drop/Insert Interface Table Microprocessor Interface Table GPIO/LOS/ALARM Interface Table Test Interface Table Power, Ground, Connect Pins
Assignments
Mechanical Packaging Information
Table Mechanical Package Specifications Table Thermal Performance
Functional Description
Common Conventions, Controls, Configuration Monitors Control Interface Configuration Conventions Table TX_LINE_CONFIG_[4:0] Provisioning Table TX_CONFIG_[20:0] Values. Power Minimization
Transmit Direction
Transmit FIFO Interface 5.1.1 Transmit Data Parity Check 5.1.2 Transmit FIFO 5.1.3 Errored Packet Handling 5.1.4 System Side Cell/Packet Loopback Transmit HDLC Processing (POS) 5.2.1 Transmit Valid Packet Count. 5.2.2 Pre-HDLC Scrambling. 5.2.3 Encapsulation Packets HDLC Frame. 5.2.4 Address Control Fields. 5.2.5 Frame Check Sequence (FCS) Field 5.2.6 Transparency Table Octet Values Handled Transparency Processing 5.2.7 Creation Transmit AProcessing 5.3.1 Transmit Data Check. 5.3.2 Transmit Valid Cell Count 5.3.3 Payload Creation 5.3.4 Header Error Control (HEC) Sequence Generation.
AMCC
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STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Contents (continued)
Table Pattern Default Idle Cell Table ACell Header Format
Scrambling 5.4.1 AScrambler Operation 5.4.2 HDLC Direct Scrambler Operation. Insert SPE/VC Generation 5.5.1 SPE/VC Structure 5.5.2 Table Path Provisioning Table Path Values. 5.5.3 Unequipped Generation 5.5.4 PAIS Generation 5.5.5 Pointer Bytes (H1, Pointer Action Byte (H3). Transmit Multiplexer Transmit Port Selector 5.7.1 Dual-Feed Output Port. 5.7.2 Transmit Selector 5.7.3 Internal Hairpin Selector. Transmit Demultiplexer SONET/SDH Frame Generation 5.9.1 Frame Alignment. 5.9.2 Payload Generation 5.9.3 TOH/SOH Generation Table STS-48/STM-16 TOH/SOH. Table STS-12/STM-4 TOH/SOH. Table STS-3/STM-1 TOH/SOH. 5.9.4 Scrambling 5.10 SONET R-to-T Loopback 5.11 Transmit Output Disable
Receive Direction
Configuration Receive Input Disable T-to-R Loopback Clock Reference Output Table RX_REF_CLK_SEL_[4:0] Register Values 6.4.1 LOC. 6.4.2 SONET/SDH Framers Table RX_REF_CLK_FREQ_[1:0] Register Value. 6.5.1 Descrambling 6.5.2 Monitor. Transport Overhead Monitoring 6.6.1 Monitoring. 6.6.2 BIP-384 (B2) Checking Table Recommended Provisioning STS-48/STM-16 Signal Fail Signal Degrade
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Contents (continued)
Table Recommended Provisioning STS-12/STM-4 Signal Fail Signal Degrade
Table Recommended Provisioning STS-3/STM-1 Signal Fail Signal Degrade
6.6.3 K1K2 Monitoring. 6.6.4 AIS-L Data Disable. 6.6.5 Monitoring 6.6.6 Monitoring 6.6.7 External Alarm Signal. Pointer Processors 6.7.1 Concatenation Provisioning Table RX_PP_CONFIG_[20:0] Provisioning. 6.7.2 Pointer State Determination 6.7.3 Pointer Interpretation. 6.7.4 Pointer Generation Receive Port Selector 6.8.1 Dual-Feed Output Port. 6.8.2 Receive Selector. Pointer Interpreter Configuration Table RX_PI_CONFIG_[4:0] Values 6.9.1 Pointer State Determination 6.9.2 State Transition Rules. 6.9.3 Concatenated Pointer Determination 6.9.4 PAIS Indicators 6.10 Pointer Interpretation 6.11 Path Overhead Monitoring 6.11.1 Path Trace (J1) Capture/Monitor. Table J1_CAP_TRIB Usage 6.11.2 BIP-8 (B3) Checking 6.11.3 Signal Label (C2) Monitoring. 6.11.4 Path Status (G1) Monitoring. 6.11.5 Other Bytes 6.12 Receive Payload Descrambling 6.12.1 ADescrambler Operation 6.12.2 Direct Mapping Descrambler Operation 6.13 Receive HDLC Processing 6.13.1 Direct Mapping Data from 6.13.2 HDLC Framer. 6.13.3 Removal Transparency Byte Stuffing. 6.13.4 Errored Frames 6.13.5 Frame Check Sequence (FCS) Field 6.13.6 HDLC Frame Termination 6.13.7 Post-HDLC Descrambling 6.13.8 Receive Valid Packet Count. 6.14 Receive AProcessing 6.14.1 Payload Deconstruction 6.14.2 ACell Delineation
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Contents (continued)
6.14.3 Header Error Control Functions 6.14.4 AIdle Cell Removal 6.14.5 Receive Valid Cell Count 6.15 Receive FIFO Interface 6.15.1 System Side Cell/Packet Loopback 6.15.2 FIFO Processing 6.15.3 Errored Cell/Packet Handling. 6.15.4 Receive Data Parity
Output Processing
Output Selection Frame Generation 7.2.1 TOH/SOH Generation 7.2.2 K1K2 Insert 7.2.3 Scrambling .110 Output Format .110
Input Processing .111
Input Format .111 SONET/SDH Framers .111 8.2.1 Input Deskew Start Frame Alignment .111 8.2.2 Descrambling .112 8.2.3 Monitor.112 8.2.4 Monitor .112 Input Data .112 Disable
RHINE System Interface Requirements
Conventions RHINE System Interface Basic Concepts 9.2.1 FlexBus-3 Modes Operation Table Operational Modes. Table FlexBus-3Operational Modes Supported RHINE. 9.2.2 RHINE System Interface Mode Selection 9.2.3 RHINE Utopia Operation. 9.2.4 RHINE Packet Mode Common System Interface Specifications 9.3.1 Widths 9.3.2 Clock Rates. Utopia Level System Interface Requirements 9.4.1 Interface Data Structures Table System Interface Clock Rates. Table 8-Bit Data Structure Configuration TX/RX_ATM_UDF TX/RX_ATM_UDF53 Table 52-Byte Data Structure 8-Bit AMode. Table 53-Byte Data Structure 8-Bit AMode.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Contents (continued)
Table 56-Byte Data Structure 8-Bit AMode.
9.4.2 AUtopia Transmit Operation
Table 52-Byte Data Structure 32-Bit AMode. Table 56-Byte Data Structure 32-Bit AMode, TX/RX_ATM_UDF Table TX/RX_FIFOFULL_T/RPA_y_[3:0] TX/RX_FIFOEMPTY_T/RPA_y_[3:0] Values
Amode.
Table FIFOFULL/FIFOEMPTY Register Tributary Assignment
9.4.3 AUtopia Receive Operation RHINE Packet Interface Requirements 9.5.1 Packet Format 9.5.2 RHINE Packet Transmit Operation Table RX_LBYTE_[1:0] Values Table Data Structure 32-Bit Mode Table TX/RX_FIFOFULL_T/RPA_y_[3:0] TX/RX_FIFOEMPTY_T/RPA_y_[3:0] Values Direct mode 9.5.3 RHINE Packet Receive Operation 9.5.4 Direct Mode Operation RHINE FlexBus-3 Operation with Mixed Payloads
10.0 Management Interface
10.1 Interrupt Polled Operation 10.1.1 Interrupt Sources. 10.1.2 Interrupt Driven 10.1.3 Polled mode
11.0 Register Descriptions
11.1 Transmit Side Registers 11.1.1 Transmit Configuration Summary Status Addresses 0x0000 through 0x01FF (Table Table Transmit Side Configuration Summary Status 11.1.2 Transmit Side Addresses 0x0200 through 0x03FF (Table Table Transmit Side Register Address SONET/SDH TOH/SOH Provisioning Scrambler Inhibit. 11.1.3 Transmit Side Addresses 0x0400 through 0x05FF Table Path Overhead Provisioning Register 11.1.4 Transmit Side Addresses 0x0600 through 0x08FF (Table Table Transmit Provisioning Register 11.1.5 Transmit Side Address 0x0900 through 0x0AFF (Table Table ATransmit Provisioning Register 11.1.6 Transmit Side Address 0x0B00 through 0x0CFF (Table Table Transmit System Interface Provisioning. 11.1.7 Transmit Side Address 0x0D00 through 0x0EFF (Table Table Transmit Provisioning Register Map. 11.2 Receive Side Registers 11.2.1 Receive Side Addresses 0x2000 through 0x21FF (Table Table Receive Side Base Register
AMCC xiii
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Contents (continued)
11.2.2 Receive Side Addresses 0x2200 through 0x25FF (Table
Table Receive Monitoring Provisioning Register Map.
11.2.3 Receive Side Addresses 0x2600 through 0x27FF (Table Table Pointer Processor Provisioning 11.2.4 Receive Side Addresses 0x2800 through 0x29FF (Table Table Pointer Generator Provisioning Register 11.2.5 Receive Side Addresses 0x2A00 through 0x2BFF (Table Table Pointer Interpreter Provisioning Monitoring Register 11.2.6 Receive Side Addresses 0x2C00 through 0x2DFF (Table Table Receive Monitoring Provisioning Register 11.2.7 Receive Side Addresses 0x2E00-0x2FFF (Table 61). Table Receive AMonitoring Provisioning Register 11.2.8 Receive Side Addresses 0x3000 through 0x31FF (Table Table Receive System Interface Monitoring Provisioning Register 11.2.9 Receive Side Addresses 0x3200 through 0x33FF (Table Table Receive Monitoring Provisioning Register Map. 11.2.10 Interface Addresses 0x3600 through 0x3FFE (Table Table Interface Provisioning 11.2.11 Address 0x3FFF. Table Device Register
12.0 Electrical Characteristics
12.1 FlexBus3System Interface Transmit Timing
Table FlexBus-3 System Interface Transmit Timing
12.2 FlexBus3System Interface Receive Timing Table FlexBus-3 System Interface Receive Timing 12.3 UTOPIA-3 System Interface Transmit Timing Table Utopia-3 System Inteface Transmit Timing 12.4 UTOPIA-3 System Interface Receive Timing Table UTOPIA-3 System Interface Receive Timing 12.5 SONET Line Interface Transmit Timing Table SONET Line Interface Transmit Timing 12.6 SONET Line Interface Receive Timing Table SONET Line Interface Receive Timing 12.7 Receive Drop Timing 12.8 Transmit Insert Timing Table Receive Drop Timing Table Transmit Insert Timing 12.9 Automatic Protection Switching Output Interface Timing Table Automatic Protection Switching Output Interface Timing 12.10 Automatic Protection Switching Input InterfaceTiming Table Automatic Protection Switching Input InterfaceTiming. 12.11 Microprocessor Interface Write Timing (Asynchronous Mode) Table Microprocessor Interface Write Timing (Asynchronous Mode) 12.12 Microprocessor Interface Read Timing (Asynchronous Mode) Table Microprocessor Interface Read Timing (Asynchronous Mode) 12.13 Microprocessor Interface Write Timing (Synchronous Mode)
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Contents (continued)
Table Microprocessor Interface Write Timing (Synchronous Mode
12.14 Microprocessor Interface Read Timing (Synchronous Mode) 12.15 JTAG Interface Timing Table Microprocessor Interface Read Timing (Synchronous Mode). Table JTAG Interface Timing
13.0 Electrical Characteristics
13.1 Absolute Maximum Ratings
Table
13.2 Power Supply
Table
13.3 3.3V LVTTL Specifications 13.4 2.5V CMOS Specifications Table Table 13.5 LVPECL Specifications Table
Appendix User Notes
Chapter 1.0: User Notes Introduction Chapter 2.0: SONET/SDH 2.1: RX_LOS_RDI_INH must when operating SONET Loopback mode 2.2: RX_LAIS error reported during condition mode 2.3: does contribute LRDI mode. 2.4: change RX_PI_PAIS causes pulse RX_PI_LOP 2.5: Channel STS-12c mode) Channel STS-3c mode) properly respond NDF. 2.6: RX_SDH_PP[x] RX_PP_SS_EN[x] bits miswired 2.7: Channels 16xSTS-3c mode) received error counters SECE bits report errors when BIT_BLKCNT 2.8: P-RDI removed immediately following clearing received P_AIS condition Chapter 3.0: 3.1: RX_ATM_IDLE_CAP_E reliable 3.2: STS48C mode, Acell counter incremented FIFO almost full 3.3: TX_ATM_CELL_CNT counter channel only bits wide Chapter 4.0: 4.1: condition Rhine result infinitely large packet transmission over Flexbusinterface direct modes 4.2: TX_POS_FIFOUNDER_E reliable 4.3: RX_EOP asserted RX_CLK cycles. 4.4: Rhine maps corrupted data after FIFO underflow STS-48c mode 4.5: RX_POS_PABORT_ERRCNT does increment short packets. 4.6: Packets aborted inverting counted packet count. 4.7: PMAX abort operate incorrectly STS3C/STS12C modes
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Contents (continued)
4.8: Packets failing PMIN counted error 4.9: When addr/cntrl drop active, packets matching addr/cntrl field dropped mismatch 4.10: RX_POS_ADRCTL_DROP_INH_x then RX_POS_ADRCTL_INVALID_x will always 4.11: RX_POS_PMAX feature fully functional RX_POS_PMAX_ERRCNT counting completely accurate STS-48c mode 4.12: Extra Flags inserted transmit Address/Control bytes bytes inserted OC-48c mode Chapter 5.0: 5.1: APS_MISALIGN_ERR_E always Chapter 6.0: Miscellaneous 6.1: *_SECE register bits values count registers values reliable mode when CNT_SEC_EN 6.2: TX_CLK_OUT_INH[1:4] register writable readable.
14.0 Index Registers 15.0 Ordering Packaging Information
Table Part Number decoding S4804CBI41.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Applicable Documents
AForum, "Utopia Specification Level Version 2.01, af-phy-0017.001, March 1994. AForum, "Utopia Specification Level Version 1.0, af-phy-0039.000, June 1995. AForum, "Utopia Specification Level af-phy-136.000, November 1999. AForum "AUser-Network Interface Specification," 1af-uni-0010.002, 1994. "PPP Over SONET/SDH," IETF 2615, June 1999. "PPP HDLC-Like Framing," IETF 1662, July 1994. "The Point-to-Point Protocol," IETF 1661, July 1994. ISO/IEC 3309:1991(E), "Information Technology Telecommunications information exchange between systems High Level Data Link Control (HDLC) procedures Frame structure," International Organization Standardization, Fourth Edition 1991-06-01. ISO/IEC 3309:1991/Amd.2:1992(E), "Information Technology Telecommunications information exchange between systems High Level Data Link Control (HDLC) procedures Frame structure Amendment Extended transparency options start/stop transmission," International Organization Standardization, 1992-01-15. Bellcore Specification "SONET Transport Systems: Common Generic Criteria," GR-253-CORE, Issue Rev. December 1997. ITU-T Recommendation G.707, "Network Node Interface Synchronous Digital Hierarchy," March 1996. ITU-T I.432.1, "Series Integrated Services Digital Network: B-ISDN user-network interface Physical layer specification: General characteristics," August 1996. ITU-T I.432.2, "Series 1:Integrated Services Digital Network: B-ISDN user-network interface Physical layer specification: kbit/s kbit/s operation," August 1996. Bellcore Specification "SONET Dual-Fed Unidirectional Path Switched Ring (UPSR) Equipment Generic Criteria," GR-1400-CORE, Revision October 1995.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Assignments Descriptions
RHINE (S4804)
CBGA (VIEWED FROM TOP)
Unuse
Signal
(2.5V)
(3.3V)
Figure RHINE Assignments
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Assignments
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table SONET Interfacea Signal Name
155/622 Mb/s Serial I/O's (OC-3/12) TX_DATA[1]TX_DATA[1]+ RX_DATA[1]RX_DATA[1]+ RX_SONETCLK[1]RX_SONETCLK[1]+ TX_DATA[5]TX_DATA[5]+ RX_DATA[5]RX_DATA[5]+ RX_SONETCLK[5]RX_SONETCLK[5]+ TX_DATA[9]TX_DATA[9]+ RX_DATA[9]RX_DATA[9]+ RX_SONETCLK[9]RX_SONETCLK[9]+ TX_DATA[13]TX_DATA[13]+ RX_DATA[13]RX_DATA[13]+ RX_SONETCLK[13]RX_SONETCLK[13]+ Mb/s Serial I/O's TX_DATA[2]TX_DATA[2]+ RX_DATA[2]RX_DATA[2]+ RX_SONETCLK[2]RX_SONETCLK[2]+ TX_DATA[3]TX_DATA[3]+ RX_DATA[3]RX_DATA[3]+ RX_SONETCLK[3]RX_SONETCLK[3]+ TX_DATA[4]TX_DATA[4]+ RX_DATA[4]RX_DATA[4]+ RX_SONETCLK[4]RX_SONETCLK[4]+
Revision January 2002 DATASHEET
(I/O)
Signal Type
Signal Description
TX_DATA_[n]:
LVPECL
Line side transmit output data signals used when Rhine's Line side interface configured either STS-12/STM-4 STS-3/STM-1 (serial) modes. With line side interface configured STS-12/STM-4 mode, TX_DATA[1,5,9,13] outputs updated rising edge TX_SONETCLK_OUT_155_622. With line side interface configured STS-3/STM-1 mode, TX_DATA[1,5,9,13] updated rising edge TX_SONETCLK_OUT_155_622 while other TX_DATA_[n] outputs updated rising edge TX_SONETCLK_OUT_155. RX_DATA_IN[n]: Line side receive input data signals used when Rhine's Line side interface configured STS-12/STM-4 STS-3/STM-1 (serial) modes. Data updated rising edge RX_SONETCLK[n]. RX_SONETCLK[n]: clock STS-12/STM-4 modes; clock STS-48/STM-16 STS-3/STM-1 mode. Unused RX_DATA RX_SONETCLK differential input pairs should tied low. This accomplished connecting terminal VDD_2.5 pull resistor terminal pull down resistor. resistor values should chosen ensure that differential voltage between terminals greater than When calculating 200mV differential, internal termination resistor between terminals must considered. Unused TX_DATA differential output pairs should left floating.
LVPECL
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table SONET Interfacea Signal Name
Mb/s Serial I/O's (OC-3) TX_DATA[6]TX_DATA[6]+ RX_DATA[6]RX_DATA[6]+ RX_SONETCLK[6]RX_SONETCLK[6]+ TX_DATA[7]TX_DATA[7]+ RX_DATA[7]RX_DATA[7]+ RX_SONETCLK[7]RX_SONETCLK[7]+ TX_DATA[8]TX_DATA[8]+ RX_DATA[8]RX_DATA[8]+ RX_SONETCLK[8]RX_SONETCLK[8]+ TX_DATA[10]TX_DATA[10]+ RX_DATA[10]RX_DATA[10]+ RX_SONETCLK[10]RX_SONETCLK[10]+ TX_DATA[11]TX_DATA[11]+ RX_DATA[11]RX_DATA[11]+ RX_SONETCLK[11]RX_SONETCLK[11]+ TX_DATA[12]TX_DATA[12]+ RX_DATA[12]RX_DATA[12]+ RX_SONETCLK[12]RX_SONETCLK[12]+ TX_DATA[14]TX_DATA[14]+ RX_DATA[14]RX_DATA[14]+ RX_SONETCLK[14]RX_SONETCLK[14]+
Revision January 2002 DATASHEET
(I/O)
Signal Type
Signal Description
LVPECL
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table SONET Interfacea Signal Name
Mb/s Serial I/O's (OC-3) TX_DATA[15]TX_DATA[15]+ RX_DATA[15]RX_DATA[15]+ RX_SONETCLK[15]RX_SONETCLK[15]+ TX_DATA[16]TX_DATA[16]+ RX_DATA[16]RX_DATA[16]+ RX_SONETCLK[16]RX_SONETCLK[16]+ Mb/s Parallel Outputs (OC-48) TX_DATA[15]TX_DATA[15]+ TX_DATA[14]TX_DATA[14]+ TX_DATA[13]TX_DATA[13]+ TX_DATA[12]TX_DATA[12]+ TX_DATA[11]TX_DATA[11]+ TX_DATA[10]TX_DATA[10]+ TX_DATA[9]TX_DATA[9]+ TX_DATA[8]TX_DATA[8]+ TX_DATA[7]TX_DATA[7]+ TX_DATA[6]TX_DATA[6]+ TX_DATA[5]TX_DATA[5]+ TX_DATA[4]TX_DATA[4]+ TX_DATA[3]TX_DATA[3]+ TX_DATA[2]TX_DATA[2]+ TX_DATA[1]TX_DATA[1]+ TX_DATA[0]TX_DATA[0]+
Revision January 2002 DATASHEET
(I/O)
Signal Type
Signal Description
LVPECL
TX_DATA_[n]: LVPECL Line side transmit output data signals used when Rhine's Line side interface configured STS-48/STM-16 (parallel) mode. TX_DATA[15] MSB; TX_DATA[0] LSB.
**Important** Application Note "System Design Consideration When Using Rhine OC-48 Line Interface Mode" When using Rhine OC-48 Line Side Interface Mode. This applications note required when designing with Rhine later.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table SONET Interfacea Signal Name
Mb/s Parallel Inputs RX_DATA[15]RX_DATA[15]+ RX_DATA[14]RX_DATA[14]+ RX_DATA[13]RX_DATA[13]+ RX_DATA[12]RX_DATA[12]+ RX_DATA[11]RX_DATA[11]+ RX_DATA[10]RX_DATA[10]+ RX_DATA[9]RX_DATA[9]+ RX_DATA[8]RX_DATA[8]+ RX_DATA[7]RX_DATA[7]+ RX_DATA[6]RX_DATA[6]+ RX_DATA[5]RX_DATA[5]+ RX_DATA[4]RX_DATA[4]+ RX_DATA[3]RX_DATA[3]+ RX_DATA[2]RX_DATA[2]+ RX_DATA[1]RX_DATA[1]+ RX_DATA[0]RX_DATA[0]+
Revision January 2002 DATASHEET
(I/O)
Signal Type
Signal Description
RX_DATA_IN[n]:
Line side receive input data signals used when Rhine's Line side interface configured STS-48/STM-16 (parallel) mode. RX_DATA[15] MSB; RX_DATA[0] LSB. Data sampled rising edge RX_SONETCLK[2].
LVPECL
TRANSMIT SONET REFERENCE CLOCK INPUT: TX_SONETCLK_INTX_SONETCLK_IN+ LVPECL Must STS-12/STM-4 mixed STS12/STM-4 STS-3/STM1 mode operation; Must STS-48/STM-16 STS-3/STM-1 line modes. TRANSMIT SONET CLOCK OUT: TX_SONETCLK_OUT_155 line side transmit clock output provides timing source which synchronous TX_DATA[2:4,6:8,10:12,14:16] outputs STS-3 mode TX_DATA[15:0] STS-48 mode. TX_SONETCLK_155 operates 155.52 MHz.
LVPECL
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table SONET Interfacea Signal Name (I/O) Signal Type
Revision January 2002 DATASHEET
Signal Description
TRANSMIT SONET CLOCK OUT: TX_SONETCLK_OUT_155_622 line side transmit clock output provides timing source which synchronous TX_DATA[1,5,9,13] outputs STS-3/STS-12 line interface modes. TX_SONETCLK_155_ operates 155.52 none line interfaces STS-12 mode; operates 622.08 line interfaces STS-12/STM-4. TRANSMIT FRAMER START-OF-FRAME INDICATION: This signal nominally used aligning frames multiple RHINE devices (including Rhines connected port). Should terminated, used, using pull-up TX_FRAME_IN- VDD_2.5 pull-down TX_FRAME_IN+ Ground. REFERENCE CLOCK OUTPUT: RX_REF_CLK_OUT provides reference clock signal output that generated various input clock sources RHINE (see section 6.4).
LVPECL
TX_FRAME_INTX_FRAME_IN+
AB23
LVPECL
RX_REF_CLK_OUT
LVTTL
unused differential input pairs should tied low. This accomplished connecting terminal VDD_2.5 pull resistor terminal pull down resistor. resistor values should chosen ensure that differential voltage between terminals greater than differential LVPECL inputs RHINE include internal termination resistor between terminals. This resistor must included calculation external resistor values necessary ensure >200mV voltage between terminals. Unused differential output pairs should left floating. single ended LVTTL CMOS inputs should passively tied unused (unless designated with internal pull-up/down no-connect pin). 10Kohm pull up/down resistor value sufficient unless specific value specified. Unused signals should tied inactive logic level. Certain SONET interface data clock pins support different signal types/numbers when configuring SONET interface serial (STS-3/STM-1 STS-12/STM-4) mode parallel (STS-48/STM-16) mode. example used RX_SONETCLK[12]+ input STS-3/STM-1mode RX_DATA[1]+ STS-48/STM-16 mode. assigning single signal label (which includes both signals names) common Rhine schematic symbol, common symbol used Rhine designs supporting both serial parallel SONET side configurations.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table FlexBus Interfacea Signal Name
Single 32-bit Mode RX_ADR[4] RX_ADR[3] RX_ADR[2] RX_ADR[1] RX_ADR[0] Quad 8-bit Mode RX_ADR[4][2] RX_ADR[4][1] RX_ADR[4][0] RX_ADR[3][2] RX_ADR[3][1] RX_ADR[3][0] RX_ADR[2][2] RX_ADR[2][1] RX_ADR[2][0] RX_ADR[1][2] RX_ADR[1][1] RX_ADR[1][0] Single 32-bit Mode RX_CLAV_PDA Quad 8-bit Mode RX_CLAV_PDA[4] RX_CLAV_PDA[3] RX_CLAV_PDA[2] RX_CLAV_PDA[1] Single 32-bit Mode RX_CLK Quad 8-bit Mode RX_CLK[4] RX_CLK[3] RX_CLK[2] RX_CLK[1]
(I/O)
Signal Type
Signal Description
Receive Port Address. Driven Link Layer device RHINE select specific port. both direct status multiplexed status addressing modes, port address driven RX_ADR_y, when falling edge occurs RX_ENB, port that will selected transfer data over Flexbus interface. multiplexed status polling mode, RX_ADR_y also used poll ports RX_CLAV_PDA_y signal (independent state RX_ENB_y). Single, mode, port selected using RX_ENB_[1] RX_ADR_[4] MSB. Quad, 8-bit mode, port selcted using RX_ENB_y RX_ADR_y_[2] MSB.
AA08 AC08 AE08
AC06 AB07 AE06 AD07 AA08 AC08 AE08
LVTTL
LVTTL
AA09 AB09
Receive Cell/Packet available: Provides indication whether specified number cells Amode) bytes POS/direct mapped modes) available FIFO addressed port.
AE10 LVTTL
AC10 AA10 AE10
Data transfer/synchronization input clock: Provided Link Layer RHINE synchronizing transfers RX_SYS_DAT. RX_CLK_[1] used single, 32-bit, operation; RX_CLK_[1:4] used quad, 8-bit, operation (RX_CLK_[1] RX_SYS_DAT_[31:24]. .RX_CLK_[4] RX_SYS_DAT_[7:0]
Single 32-bit Mode RX_CLK_OUT Quad 8-bit Mode RX_CLK_OUT[4] RX_CLK_OUT[3] RX_CLK_OUT[2] RX_CLK_OUT[1]
AE12 LVTTL
Data transfer/synchronization output clock: gate version RX_CLK[N] input signal. Provides timing source that synchronous with FlexBus data control output signals. required Utopia. RX_CLK_OUT_INH_[N] register enables/inhibits each RX_CLK_OUT_[N] output signal reduce power output used.
AC12 AA12 AE12
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name (I/O) Signal Type
Revision January 2002 DATASHEET
Signal Description
FlexBus-3TM: Receive data valid signal. When high, RX_DV_y indicates that receive data output signals current driven system interface (RX_SYS_DAT, RX_SOC/P_y, RX_EOP_y, RX_LBYTE, RX_PRTY_y RX_ERR_y) valid. Since RX_DV_y changes state same edge other system interface outputs, sampled Link layer device each time output signals latched. This allows link layer device qualify output signals each cycle. RX_DV_[1] provides receive data valid signal single, 32-bit, mode; RX_DV_[1:4] used quad, 8-bit, operation (RX_DV_[1] RX_SYS_DAT_[31:24].and RX_DV_[4] RX_SYS_DAT_[7:0]).
Single 32-bit Mode RX_DV Quad 8-bit Mode RX_DV[4] RX_DV[3] RX_DV[2] RX_DV[1]
LVTTL
Single 32-bit Mode RX_ENB Quad 8-bit Mode RX_ENB[4] RX_ENB[3] RX_ENB[2] RX_ENB[1]
UTOPIA: Receive Enable. Provides Alayer with flow control. Active signal asserted ALayer device indicate that RX_SYS_DAT RX_SOC will sampled next cycle. When deasserted, data transfer halted. address, presented RX_ADR, clock cycle immediately preceding transition RX_ENB from becomes selected address data transfer that initiated assertion RX_ENB. This data transfer commences clock cycles after assertion RX_ENB. LVTTL FlexBUS-3TM: Receive enable. Active-low signal asserted Link Layer device start packet-data transfer from Receive FIFO. When deasserted, data transfer halted. address, presented RX_ADR, clock cycle immediately preceding transition RX_ENB from becomes selected address data transfer that initiated assertion RX_ENB. This data transfer commences clock cycles after assertion RX_ENB. RX_ENB_[1] provides transfer enable signal single, 32-bit, operation; RX_ENB_[1:4] used quad, 8-bit operation (RX_ENB_[1] RX_SYS_DAT_[31:24].RX_ENB_[4] RX_SYS_DAT_[7:0]).
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name (I/O) Signal Type
Revision January 2002 DATASHEET
Signal Description
UTOPIA: Used. FlexBUS-3
Receive end-of-packet. Active-high
Single 32-bit Mode RX_EOP Quad 8-bit Mode RX_EOP[4] RX_EOP[3] RX_EOP[2] RX_EOP[1]
AE11 LVTTL
AD11 AC11 AB11 AE11
When RX_EOP high, last byte mode) word mode) packet being transferred RX_SYS_DAT bus. support number bytes packet, RX_LBYTE indicates many bytes this last word valid. RX_SOC/P high same time RX_EOP high packets less than bytes size 32-bit mode) byte size (for mode). RX_EOP_[1] provides receive end-of-packet signal 32-bit operation; RX_EOP_[1:4] used quad, 8-bit operation (RX_EOP_[1] RX_SYS_DAT_[31:24].RX_EOP_[4] RX_SYS_DAT_[7:0]).
UTOPIA: Used. Single 32-bit Mode RX_ERR Quad 8-bit Mode RX_ERR[4] RX_ERR[3] RX_ERR[2] RX_ERR[1] FlexBUS-3TM: Receive error. RX_ERR asserted simultaneously with RX_EOP indicate link layer device that packet currently being transferred should aborted link layer device. RX_ERR_[1] provides receive error signal 32-bit operation; RX_ERR_[1:4] used quad, 8-bit operation (RX_ERR_[1] RX_SYS_DAT_[31:24].RX_ERR_[4] RX_SYS_DAT_[7:0]).
AA11 LVTTL
AA11
Single 32-bit Mode RX_LBYTE[1] RX_LBYTE[0]
LVTTL
FlexBus-3TM: RX_LBYTE_[1:0] available single, 32-bit, mode only, provide support transfer packets size. only valid during last word packet transfer (RX_EOP_[1] high). provides number valid bytes within final word packet transfer. (See Table 40.)
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name (I/O) Signal Type
Revision January 2002 DATASHEET
Signal Description
UTOPIA: Parity. RX_PRTY parity over RX_SYS_DAT data bus, which driven RHINE. RX_PRTY_MODE indicates parity; RX_PRTY_MODE indicates even parity.
Single 32-bit Mode RX_PRTY Quad 8-bit Mode RX_PRTY[4] RX_PRTY[3] RX_PRTY[2] RX_PRTY[1]
LVTTL
FlexBUS-3TM: RX_PRTY parity over entire RX_SYS_DAT data bus, which driven RHINE. RX_PRTY_MODE[N] indicates parity; RX_PRTY_MODE[N] indicates even parity. RX_PRTY_[1] provides parity signal 32-bit operation; RX_PRTY_[1:4] used quad, 8-bit operation (RX_PRTY_[1] RX_SYS_DAT_[31:24].RX_PRTY_[4] RX_SYS_DAT_[7:0]).
UTOPIA: Start cell. Active-high signal asserted RHINE when RX_SYS_DAT contains first valid bytes cell. Single 32-bit Mode RX_SOC/P Quad 8-bit Mode RX_SOC/P[4] RX_SOC/P[3] RX_SOC/P[2] RX_SOC/P[1] LVTTL FlexBUS-3TM: Start packet. Active-high signal asserted RHINE when RX_SYS_DAT contains first valid bytes packet. RX_SOC/P_[1] provides start cell/packet signal 32-bit operation; RX_SOC/P_[1:4] used quad, 8-bit operation (RX_SOC/P_[1] RX_SYS_DAT_[31:24].RX_SOC/P_[4] RX_SYS_DAT_[7:0]).
AE09
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name
RX_SYS_DAT[31] RX_SYS_DAT[30] RX_SYS_DAT[29] RX_SYS_DAT[28] RX_SYS_DAT[27] RX_SYS_DAT[26] RX_SYS_DAT[25] RX_SYS_DAT[24] RX_SYS_DAT[23] RX_SYS_DAT[22] RX_SYS_DAT[21] RX_SYS_DAT[20] RX_SYS_DAT[19] RX_SYS_DAT[18] RX_SYS_DAT[17] RX_SYS_DAT[16] RX_SYS_DAT[15] RX_SYS_DAT[14] RX_SYS_DAT[13] RX_SYS_DAT[12] RX_SYS_DAT[11] RX_SYS_DAT[10] RX_SYS_DAT[9] RX_SYS_DAT[8] RX_SYS_DAT[7] RX_SYS_DAT[6] RX_SYS_DAT[5] RX_SYS_DAT[4] RX_SYS_DAT[3] RX_SYS_DAT[2] RX_SYS_DAT[1] RX_SYS_DAT[0]
Revision January 2002 DATASHEET
AA01 AB01 AC01 AD01 AE01 AA02 AC02 AE02 AA03 AB03 AC03 AD03 AE03 AA04 AC04 AE04 AA05 AB05 AD05 AA06
(I/O)
Signal Type
Signal Description
UTOPIA/FlexBus-3TM: Receive System Data. Four byte-wide, true data driven from RHINE Link Layer. RX_SYS_DAT_[31] MSB. Four, 8-bit wide, data buses driven from RHINE Link Layer. RX_SYS_DAT_[31] [23] [15] MSBs.
LVTTL
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name
Single 32-bit Mode TX_ADR[4] TX_ADR[3] TX_ADR[2] TX_ADR[1] TX_ADR[0] Quad 8-bit Mode TX_ADR[4][2] TX_ADR[4][1] TX_ADR[4][0] TX_ADR[3][2] TX_ADR[3][1] TX_ADR[3][0] TX_ADR[2][2] TX_ADR[2][1] TX_ADR[2][0] TX_ADR[1][2] TX_ADR[1][1] TX_ADR[1][0] Single 32-bit Mode TX_CLAV_PDA Quad 8-bit Mode TX_CLAV_PDA[4] TX_CLAV_PDA[3] TX_CLAV_PDA[2] TX_CLAV_PDA[1] Single 32-bit Mode TX_CLK Quad 8-bit Mode TX_CLK[4] TX_CLK[3] TX_CLK[2] TX_CLK[1]
Revision January 2002 DATASHEET
(I/O)
Signal Type
Signal Description
Receive Port Address. Driven Link Layer device RHINE select specific port. both direct status multiplexed status addressing modes, port address driven TX_ADR_y when falling edge occurs TX_ENB port that will selected transfer data over Flexbus interface. multiplexed status polling mode, TX_ADR_y also used poll ports TX_CLAV_PDA_y signal (independent state TX_ENB_y). SIngle, mode, port selcted using TX_ENB_[1] TX_ADR_[4] MSB. Quad, 8-bit mode, port selcted using TX_ENB_y TX_ADR_y_[2]
LVTTL
AB19 LVTTL
AC18 AC19 AC20 AB19 AD19
Transmit Cell/Packet available: Provides indication whether space available FIFO accept specified number cells Amode) bytes POS/direct mapped modes) addressed port.
AE18 AE19 AE20 AD19
LVTTL
Data transfer/synchronization input clock: Provided Link Layer RHINE synchronizing transfers TX_SYS_DAT. TX_CLK_[1] used single, 32-bit, operation; TX_CLK_[1:4] used quad, 8-bit, operation (TX_CLK_[1] TX_SYS_DAT_[31:24]. .TX_CLK_[4] TX_SYS_DAT_[7:0]
Data transfer/synchronization output clock: Single 32-bit Mode TX_CLK_OUT Quad 8-bit Mode TX_CLK_OUT[4] TX_CLK_OUT[3] TX_CLK_OUT[2] TX_CLK_OUT[1] AE24 LVTTL gate version TX_CLK[N] input signal. Provides timing source that synchronous with FlexBus data control output signals. required Utopia. TX_CLK_OUT_INH_[N] register enables/inhibits each TX_CLK_OUT_[N] output signal reduce power output used.
AA21 AE23 AB21 AE24
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name (I/O) Signal Type
Revision January 2002 DATASHEET
Signal Description
UTOPIA Transmit Enable: Provides ALayer with flow control. Active signal asserted ALayer device during cycles when TX_SYS_DAT contains valid data. When deasserted, data transfer halted. multi-port operation, address presented TX_ADR_y clock cycle immediately preceding transition TX_ENB_y from becomes selected address data transfer that initiated this assertion TX_ENB both single-port multi-port modes, when TX_ENB_y asserted, data transferred selected PHY-layer port. When TX_ENB_y deasserted, TX_SYS_DAT ignored.
Single 32-bit Mode TX_ENB Quad 8-bit Mode TX_ENB[4] TX_ENB[3] TX_ENB[2] TX_ENB[1]
LVTTL FlexBUS-3Transmit Enable: Active-low signal asserted Link Layer device start packet-data transfer addressed FIFO. When deasserted, data transfer halted. address, presented TX_ADR, clock cycle immediately preceding transition TX_ENB from becomes selected address data transfer that initiated assertion TX_ENB. When TX_ENB asserted, data transferred selected RHINE port. When TX_ENB deasserted, TX_SYS_DAT ignored. TX_ENB_[1] provides transfer enable indications single, 32-bit, operation; TX_ENB_[1:4] used quad, 8-bit, operation (TX_ENB_[1] TX_SYS_DAT_[31:24] TX_ENB_[4] TX_SYS_DAT_[7:0]).
AA18 AA19 AA20
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name (I/O) Signal Type
Revision January 2002 DATASHEET
Signal Description
UTOPIA: Used. FlexBUS-3TM: Transmit end-of-packet. Active-high When TX_EOP high, last byte mode) word mode) packet being transferred TX_SYS_DAT bus. support number bytes packet, TX_LBYTE indicate provided indicate which bytes last word packet transferred valid. TX_SOC/P high same time TX_EOP high packets less than bytes size 32-bit mode) byte size (for mode). TX_EOP_[1] provides transmit packet indication single, 32-bit, operation; TX_EOP_[1:4] used quad, 8-bit, operation (TX_EOP_[1] TX_SYS_DAT_[31:24] TX_EOP_[4] TX_SYS_DAT_[7:0]).
Single 32-bit Mode TX_EOP Quad 8-bit Mode TX_EOP[4] TX_EOP[3] TX_EOP[2] TX_EOP[1]
LVTTL
UTOPIA: Used. FlexBUS-3TM: Transmit error. TX_ERR asserted link layer device indicate Rhine that packet currently being transferred over system interface should aborted Rhine. packet being transferred over system interface completely contained within FIFO, then packet will deleted Rhine. packet started mapping process into SONET SPE, then packet will aborted. TX_EOP must asserted simultaneously with TX_ERR Rhine correctly recognize TX_ERR signal.
Single 32-bit Mode TX_ERR Quad 8-bit Mode TX_ERR[4] TX_ERR[3] TX_ERR[2] TX_ERR[1]
LVTTL
Single 32-bit Mode TX_LBYTE[1] TX_LBYTE[0]
AD21 AC22
LVTTL
FlexBus-3TM: TX_LBYTE_[1:0] available single, 32-bit, mode only, provide support transfer packets size. only valid during last word packet transfer (TX_EOP_[1] high). provides number valid bytes within final word packet transfer. (See Table 40.)
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name (I/O) Signal Type
Revision January 2002 DATASHEET
Signal Description
UTOPIA: Parity over TX_SYS_DAT, driven ALayer. TX_PRTY_MODE indicates parity; TX_PRTY_MODE indicates even parity.
Single 32-bit Mode TX_PRTY Quad 8-bit Mode TX_PRTY[4] TX_PRTY[3] TX_PRTY[2] TX_PRTY[1]
LVTTL
FlexBUS-3TM: TX_PRTY parity over entire TX_SYS_DAT data bus, which driven Link Layer. TX_PRTY_MODE[N] indicates parity; TX_PRTY_MODE[N] indicates even parity. TX_PRTY considered valid only when TX_ENB asserted. TX_PRTY_[1] provides parity signal 32-bit operation; TX_PRTY_[1:4] used quad, 8-bit operation (TX_PRTY_[1] TX_SYS_DAT_[31:24].TX_PRTY_[4] TX_SYS_DAT_[7:0]).
UTOPIA: Start cell. Active-high signal asserted ALayer device when TX_SYS_DAT contains first valid byte cell. Single 32-bit Mode TX_SOC/P Quad 8-bit Mode TX_SOC/P[4] TX_SOC/P[3] TX_SOC/P[2] TX_SOC/P[1] AB25 LVTTL FlexBUS-3TM: Start-of-packet. Active-high signal asserted Link Layer device when TX_SYS_DAT contains first valid byte packet. Considered valid only when TX_ENB asserted. TX_SOC/P_[1] provides start cell/packet signal 32-bit operation; TX_SOC/P_[1:4] used quad, 8-bit operation (TX_SOC/P_[1] TX_SYS_DAT_[31:24].TX_SOC/P_[4] TX_SYS_DAT_[7:0]).
AC25 AA22 AB25
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table FlexBus Interfacea Signal Name
Single 32-bit Mode TX_SYS_DAT[31] TX_SYS_DAT[30] TX_SYS_DAT[29] TX_SYS_DAT[28] TX_SYS_DAT[27] TX_SYS_DAT[26] TX_SYS_DAT[25] TX_SYS_DAT[24] TX_SYS_DAT[23] TX_SYS_DAT[22] TX_SYS_DAT[21] TX_SYS_DAT[20] TX_SYS_DAT[19] TX_SYS_DAT[18] TX_SYS_DAT[17] TX_SYS_DAT[16] TX_SYS_DAT[15] TX_SYS_DAT[14] TX_SYS_DAT[13] TX_SYS_DAT[12] TX_SYS_DAT[11] TX_SYS_DAT[10] TX_SYS_DAT[9] TX_SYS_DAT[8] TX_SYS_DAT[7] TX_SYS_DAT[6] TX_SYS_DAT[5] TX_SYS_DAT[4] TX_SYS_DAT[3] TX_SYS_DAT[2] TX_SYS_DAT[1] TX_SYS_DAT[0]
Revision January 2002 DATASHEET
(I/O)
Signal Type
Signal Description
UTOPIA/FlexBus-3TM: Transmit System Data. Four byte-wide, true data driven from Link Layer RHINE. TX_SYS_DAT_[31] MSB. Four, 8-bit wide, data buses driven from Link Layer RHINE. TX_SYS_DAT_[31] [23] [15] MSBs.
AA13 AB13 AC13 AD13 AE13 AA14 AC14 AE14 AA15 AB15 AC15 AD15 AE15 AA16 AC16 AE16 AA17 AB17 AC17 AD17 AE17
LVTTL
RHINE's single ended LVTTL CMOS inputs should passively tied unused (unless designated with internal pull-up/down no-connect pin). 10Kohm pull up/down resistor value sufficient unless specific value specified. Unused signals should tied inactive logic level. unused LVTTL/CMOS outputs should left floating
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Auto Protection Switching Interface Signal Name
APS_DATA_OUT[31] APS_DATA_OUT[30] APS_DATA_OUT[29] APS_DATA_OUT[28] APS_DATA_OUT[27] APS_DATA_OUT[26] APS_DATA_OUT[25] APS_DATA_OUT[24] APS_DATA_OUT[23] APS_DATA_OUT[22] APS_DATA_OUT[21] APS_DATA_OUT[20] APS_DATA_OUT[19] APS_DATA_OUT[18] APS_DATA_OUT[17] APS_DATA_OUT[16] APS_DATA_OUT[15] APS_DATA_OUT[14] APS_DATA_OUT[13] APS_DATA_OUT[12] APS_DATA_OUT[11] APS_DATA_OUT[10] APS_DATA_OUT[9] APS_DATA_OUT[8] APS_DATA_OUT[7] APS_DATA_OUT[6] APS_DATA_OUT[5] APS_DATA_OUT[4] APS_DATA_OUT[3] APS_DATA_OUT[2] APS_DATA_OUT[1] APS_DATA_OUT[0]
(I/O)
Signal Type
Signal Description
Parallel DATA interface. Updated rising edge APS_CLK_OUT. APS_OUT_INH turn APS_DATA_OUT APS_CLK_OUT logic reduce power/EMI) interface used.
2.5V CMOS
APS_CLK_OUT
2.5V CMOS
Reference clock APS_DATA_OUT operates 77.76 MHz.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Auto Protection Switching Interface Signal Name
APS_DATA_IN[31] APS_DATA_IN[30] APS_DATA_IN[29] APS_DATA_IN[28] APS_DATA_IN[27] APS_DATA_IN[26] APS_DATA_IN[25] APS_DATA_IN[24] APS_DATA_IN[23] APS_DATA_IN[22] APS_DATA_IN[21] APS_DATA_IN[20] APS_DATA_IN[19] APS_DATA_IN[18] APS_DATA_IN[17] APS_DATA_IN[16] APS_DATA_IN[15] APS_DATA_IN[14] APS_DATA_IN[13] APS_DATA_IN[12] APS_DATA_IN[11] APS_DATA_IN[10] APS_DATA_IN[9] APS_DATA_IN[8] APS_DATA_IN[7] APS_DATA_IN[6] APS_DATA_IN[5] APS_DATA_IN[4] APS_DATA_IN[3] APS_DATA_IN[2] APS_DATA_IN[1] APS_DATA_IN[0] APS_CLK_IN[1] APS_CLK_IN[2] APS_CLK_IN[3] APS_CLK_IN[4]
(I/O)
Signal Type
Signal Description
Four byte-wide data input stream transmit side DATA interface. Updated rising edge APS_CLK_IN[N]. APS_DA TA_IN{31:24] clocked using APS_CLK_IN[1]. APS_DA TA_IN{23:16] clocked using APS_CLK_IN[2]. APS_DA TA_IN{15:8] clocked using APS_CLK_IN[3]. APS_DA TA_IN[7:0] clocked using APS_CLK_IN[4]. APS_IN_INH register inhibits APS_DATA_IN[N] provide means reducing power consumption input used. single ended, CMOS inputs, APS_DATA_IN APS_CLK_IN inputs should passively tied (high low) unused.
2.5V CMOS 3.3V Tolerant
2.5V CMOS 3.3V Tolerant
Reference clocks driven APS_CLK_OUT chip sending APS_DATA operating 77.76 MHz.
Table Drop/Insert Interface Signal Name
RX_TOH_DATA
(I/O)
Signal Type
2.5V CMOS 2.5V CMOS 3.3V Tolerant 2.5V CMOS 3.3V Tolerant
Signal Description
Serial-outputs received TOH/SOH bytes (E1, D1-D12, F1). Clocked falling edge RX_TOH_CLK. 19.44-MHz clock reference serial channels. Byte alignment indication received channels.
RX_TOH_CLK
RX_TOH_FRAME
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table Drop/Insert Interface Signal Name
TX_TOH_DATA
Revision January 2002 DATASHEET
(I/O)
Signal Type
2.5V CMOS 3.3V Tolerant 2.5V CMOS 2.5V CMOS
Signal Description
Serial input transmitted TOH/SOH bytes (E1, D1-D12, F1). Clocked rising edge TX_TOH_CLK. 19.44-MHz clock reference TOHchannels.
TX_TOH_CLK
TX_TOH_FRAME
Byte alignment indication transmitted TOHchannels.
Table Microprocessor Interface Signal Name
ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
(I/O)
Signal Type
Signal Description
ADDRESS BUS: Allows host microprocessor perform register selection within S4804. Since each register address stores value, addressing scheme differs depending microprocessor configured 8-bit, asynchronous mode 16-bit, synchronous mode. 8-bit, asynchronous mode, each byte wide register register addressed uniquely. 16-bit, synchronous mode, only even addresses valid with D[7:0] data transferred even address (n)and D[15:8] transferred address (n+1).
LVTTL
APS_INTB
LVTTL
INTERRUPT: Active-low output from S4804 triggered event. APS_INTB open-drain output that tri-stated when RX_APS_INT interrupt register set, masked been cleared back INTERFACE MODE: This signal allows data-transfer operations compatible with most microprocessor interfaces. When Busmode=1, data transfer occurs "Intel mode" (RDB,WRB,RDYB); when Busmode=0, data transfer occurs "Motorola mode" (DSB, RWB, DTACKB). CHIP SELECT: Active-low chip select S4804 used validate address read-and-write transfers.
BUSMODE
LVTTL
LVTTL
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table Microprocessor Interface Signal Name
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Revision January 2002 DATASHEET
(I/O)
Signal Type
Signal Description
DATA BUS: Allows transfer data between host microprocessor S4804. Only lower bits (D[7:0]) used asynchronous mode. synchronous mode, D[7:0] written even addresses D[15:8] written addresses.
LVTTL
INTB
LVTTL
INTERRUPT: Active-low output from S4804 triggered event that caused internal interrupts become activated. INTB open-drain output that tri-stated when RX/TXSUM_INT interrupt register bits set, masked been cleared back Read data strobe. Busmode=1, active input enable read data from addressed location data bus. Busmode=0 active input enable read data from RHINE, strobe write data into RHINE This signal only valid 8-bit asynchronous operation. Ready/Data Acknowledge: RDYB/DTACKB goes acknowledge data transfers over data bus. RDYB/DTACKB signal tri-stated output operates same both BUSMODE settings. RESET: Active-low input reset S4804. Sync Mode: Selects mode operation Microprocessor interface. SYNCMODE=1 16-bit synchronous operation; SYNCMODE=0 8-bit asynchronous operation. Microprocessor Clock: Microprocessor system clock. Maximum rate MHz. This signal must driven with valid clock signal both synchronous asynchronous processor modes. (See12.13 (page 218) 12.14 (page 219).
RDB/DSB
LVTTL
RDYB/DTACKB
LVTTL
RSTB
AC23
LVTTL
SYNCMODE
LVTTL
uPCLK
LVTTL
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table Microprocessor Interface Signal Name (I/O) Signal Type
Revision January 2002 DATASHEET
Signal Description
Write/Read Read/Write. Busmode=1, input write high read. Busmode=0, input defines access read write "0."
WRB/RWB
LVTTL
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table GPIO/LOS/ALARM Interface Signal Name (I/O) Signal Type Signal Description
GENERAL PURPOSE I/O: GPIO register allows user define each grouping (GPIO[0,1], GPIO[2,3], GPIO[4,5], GPIO[6,7]) either input output bits. These bits used user-defined input control. GPIOCTL1 controls GPIO[1:0] LVTTL GPIOCTL2 controls GPIO[3:2] GPIOCTL3 controls GPIO[5:4] GPIOCTL4 controls GPIO[7:6] Specific restrictions apply when configuring certain GPIO signals input outputs (see section 11.1.1.6 details)
GPIO[7] GPIO[6] GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0]
RX_ALARM_OUT[1] RX_ALARM_OUT[2] RX_ALARM_OUT[3] RX_ALARM_OUT[4] RX_ALARM_OUT[5] RX_ALARM_OUT[6] RX_ALARM_OUT[7] RX_ALARM_OUT[8] RX_ALARM_OUT[9] RX_ALARM_OUT[10] RX_ALARM_OUT[11] RX_ALARM_OUT[12] RX_ALARM_OUT[13] RX_ALARM_OUT[14] RX_ALARM_OUT[15] RX_ALARM_OUT[16] RX_LOSEXT[1] RX_LOSEXT[2] RX_LOSEXT[3] RX_LOSEXT[4] RX_LOSEXT[5] RX_LOSEXT[6] RX_LOSEXT[7] RX_LOSEXT[8] RX_LOSEXT[9] RX_LOSEXT[10] RX_LOSEXT[11] RX_LOSEXT[12] RX_LOSEXT[13] RX_LOSEXT[14] RX_LOSEXT[15] RX_LOSEXT[16]
RECEIVE ALARM SIGNAL: Reports SONET receive alarms, OOF, LOF, LOC, LAIS, each line interface. Contribution each alarm inhibited using bits within register map. (addr 220Bh, 224Bh, 228Bh, 25CB) LVTTL
External Loss Signal indication RHINE. interpretation sense signal dependant RX_LOSEXT_LEVEL_x register bit. these inputs optional since RHINE itself supports internal monitoring.
LVTTL
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S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Test Interface Signal Name
(I/O)
Signal Type
LVTTL
Signal Description
TEST CLOCK: JTAG input clock used sample data pins. Internal pull-up. TEST DATA Input serial-data stream sent S4804. sampled rising edge TCK. Internal pull-up. TEST DATA OUT: Output serial-data stream sent from S4804. updated falling edge TCK. TEST MODE SELECT: Controls operating mode JTAG interface. sampled rising edge TCK. Should pulled high when JTAG interface use. Internal pull-up. TEST PORT RESET: Active-low input used reset JTAG interface. Must pulsed >30ns after power tied 220ohm resistor unused) device operate correctly. Includes weak internal pull-up. TRI-STATE ENABLE: When TRISTATE_EN brought high, output input/output pins tri-stated. Internal pull-down.
LVTTL
LVTTL
LVTTL
TRSTB
LVTTL
TRISTATE_EN
LVTTL
Table Power, Ground, Connect Pins Chip Signal Name
VDD_2.5
H02, M02, V02, B04, F04, Y04, AD04, M06, P06, F08, Y08, D10, M10, P10, AB10, L11, R11, K12, N12, T12, M13, P13, B14, K14, N14, T14, AD14, L15, R15, D16, M16, P16, AB16, F18, Y18, M20, P20, B22, F22, Y22, AD22, H24, M24, V24, D02, P02, AB02, K04, T04, D06, H06, V06, AB06, B08, K08, T08, AD08, H10, V10, B12, F12, Y12, AD12, F14, Y14, H16, V16, B18, K18, T18, AD18, D20, H20, V20, AB20, K22, T22, D24, P24, AB24, AC21
Signal Type
2.5V power supply
VDD_3.3
3.3V power supply
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Power, Ground, Connect Pins Chip Signal Name
Ground
B02, F02, K02, T02, Y02, AD02, D04, H04, M04, P04, V04, AB04, B06, F06, K06, T06, Y06, AD06, D08, H08, M08, P08, V08, AB08, B10, F10, K10, T10, Y10, AD10, N11, D12, H12, M12, P12, V12, AB12, L13, N13, R13, D14, H14, M14, P14, V14, AB14, N15, B16, F16, K16, T16, Y16, AD16, D18, H18, M18, P18, V18, AB18, B20, F20, K20, T20, Y20, AD20, D22, H22, M22, P22, V22, AB22, B24, F24, K24, T24, Y24, AD24, P23, AA25, AC24, AD09 L12, AC09, AA24, AA07, G19, D21, C02, AE22, AD23 A23, AE05, AC05, C05, C21, A19, E03, AE21, C19, M25, AA23, M15, M19, M21, A21, AC07, AE07, E02, D01, AE25, AD25, A05,
Signal Type
Ground
CONNECT
Leave disconnected
EXTERNAL PULL-DOWN RESERVED
Provide pull-down ground Provide pull-up VDD_2.5 Provide pull-down ground
RESERVED
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Mechanical Packaging Information
Bottom
S4804CBI
AMCC
(Lid)
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table Mechanical Package Specifications Dimension
0.80 2.638 32.3 30.18 31.3 30.28
0.90 2.83 1.27 32.5 30.48 32.5 30.48 1.65 5.38 30.5 30.5 10.37
1.00 3.022 32.7 30.68 32.7 30.68 5.672
Weight (grams) dimensions millimeters. Total module height, summation location. Outline conforms JEDEC MO-156.
Table Thermal Performance
Theta C/W)
11.8 10.6
Thermal Performance Theta JA(oC/W) Airflow
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Functional Description
Common Conventions, Controls, Configuration
Note: Bytes within SONET signal transmitted first. convention, MSBs SONET/SDH bytes referred LSBs however, register words that provision monitor SONET/SDH bytes defined with LSB. S4804 supports SONET modes. brevity, SONET terminology will used main protocol discussion unless otherwise indicated. interface where data flows from Link Layer device S4804 device labeled Transmit System Interface. interface where data flows from S4804 Link Layer device labeled Receive System Interface.
Monitors Control Interface
performance-monitoring purposes, RHINE contains number "delta" bits, "event" bits, "second event" bits, error counters. Delta bits logic "1") RHINE when monitored-parameter changes state. delta then stays high until controller clears logic "0") writing bit. write-to-1 occurs simultaneously with parameter state change, delta set. Delta bits indicated suffix. Event bits similar delta bits, they have corresponding status bit. Event bits logic "1") RHINE when associated event occurs (such FIFO overflow). event then stays high, regardless whether event reoccurs, until controller clears logic "0") writing bit. write occurs simultaneously with event occurrence, event set. Event bits indicated suffix. There several "events" that monitored occurrence each second. This allows controller accumulate number seconds that contain particular event, example, number seconds that least error detected received signal monitoring bytes. this purpose, RHINE creates signal, SEC_EVENT. Alternatively, timing "second events" controlled LATCH_CNT register. When RHINE detects rising edge SEC_EVENT (and CNT_SEC_EN when LATCH_CNT, register 0x2000, written from (and CNT_SEC_EN produces pulse internal signal, LATCH_EVENT. When pulse occurs LATCH_EVENT, *_SECE register bits their corresponding internal-current, second-event, monitoring-bits active. Like delta event bits, *_SECE bits cleared until they written controller. microprocessor notified LATCH_E when pulse occurs LATCH_EVENT. internal performance-monitoring counter blocks comprised running error counter holding register that presents stable results controller. counts running counters latched into hold registers running counters cleared when pulse occurs LATCH_EVENT. prevent missing count that occurs when latching occurs, counter rather than clear signal simultaneous with increment. After being latched, results held read microprocessor. internal counters have ability store more than maximum possible count 1-second interval error rate 10-3. long count values latched (and results read) every second, counts will lost. case this doesn't happen, running counters will hold their maximum value rather than roll over (zero). Summary delta/event/second event-bits provide consolidated view various individual delta/event/second event-bits, grouped either function tributary. Summary delta/event/second events AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
therefore function other delta/event/second event-bits register maps. These summary bits behave their individual counterparts that summary bits cleared when written summary bits read-only, should only clear when delta/event/second event-bits that contribute them cleared. summary bits, well some delta, event second event-bits, "NORed" form RHINE interrupt outputs: INTB APS_INTB. contribution these bits summary interrupts deleted setting corresponding "mask" bit.
Configuration Conventions
RHINE many configuration monitoring registers that accessible through microprocessor interface. There different tributaries with STS-48 SONET interface signal. terminology used here based "STS-3#/STS-1#" tributary indexing convention defined GR-253. Pointer processor pointer interpreter registers provided STS-1 basis; therefore, required. These referred using Bellcore double indexing, ranging from [1]_[1] [16]_[3]. Most parameters RHINE tied STS-3 tributary; they require only 16-separate provisioning monitoring registers. following descriptions, used names these registers indicate register particular SONET/SDH, ATM, HDLC signal, where value ranges from [16] (the first index Bellcore terminology) second index, ranges values from [3]. possible data-streams that input/output system interface will referred throughout document `tributaries.' There `tributaries' that supported RHINE. When configured STS-12 tributaries, values that correspond `active' tributaries [1], [5], [9], [13]. RHINE supports 8-bit, Utopia Level bus, there other registers pins that must replicated times. following descriptions, used names these registers pins, where ranges from [4]. When RHINE configured interface STS-48c/STM-16 tributary, only provisioning and/or monitoring register each parameter used. other configurations, other provisioning monitoring registers also unused. modes, unused provisioning registers "don't care" should left their default values; unused monitoring registers should ignored. TX_LINE_CONFIG_[4:0] register determines format rate SONET/SDH output signal. coding TX_LINE_CONFIG_[4:0] given Table Table TX_LINE_CONFIG_[4:0] Provisioning TX/RX_LINE_CONFIG_[4:0]
XXXX 1XXX 0XXX X1XX X0XX XX1X XX0X XXX1
Line-Side Interface Configuration
STS-48/STM-16 signal. Quadrant configured 1STS-12/STM-4 signal. Quadrant configured STS-3c/STM-1 signals. Quadrant configured STS-12/STM-4 signal. Quadrant configured STS-3c/STM-1 signals. Quadrant configured STS-12/STM-4 signal. Quadrant configured STS-3c/STM-1 signals. Quadrant configured STS-12/STM-4 signal.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Table TX_LINE_CONFIG_[4:0] Provisioning TX/RX_LINE_CONFIG_[4:0]
XXX0
Line-Side Interface Configuration
Quadrant configured STS-3c/STM-1 signals.
TX_LINE_CONFIG_[4] (the default) instructs RHINE output STS-48/STM-16 signal byte-wide format 155.52 MHz. Setting TX_LINE_CONFIG_[3:0] places RHINE STS-12/STM-4 mode that quadrant, where device outputs serial signal 622.08 MHz. Setting TX_LINE_CONFIG_[3:0] places corresponding quadrant RHINE quad STS-3c/STM-1 mode, where device outputs serial signals 155.52 MHz. Setting TX_LINE_CONFIG_[3:0] 1111 places RHINE STS-12/STM-4 mode four quadrants, where device outputs serial signals 622.08 MHz. Setting TX_LINE_CONFIG_[3:0] 0000 places RHINE STS-3c/STM-1 mode, where device outputs serial signals from each quadrant) 155.52 MHz. comparable register exists Receive side, named RX_LINE_CONFIG_[4:0]. interpretation identical TX_LINE_CONFIG register defined Table configuration tributaries within line interface signals defined TX_CONFIG_[20:0] register. contents TX_CONFIG_[20:0] have following definition: Table TX_CONFIG_[20:0] Values TX_CONFIG_[20:0]
1_xxxx_xxxx_xxxx_xxxx_xx 0_1xxx_xxxx_xxxx_xxxx_xx 0_x1xx_xxxx_xxxx_xxxx_xx 0_xx1x_xxxx_xxxx_xxxx_xx 0_xxx1_xxxx_xxxx_xxxx_xx 0_0xxx_1xxx_xxxx_xxxx_xx 0_0xxx_0xxx_xxxx_xxxx_xx 0_0xxx_x1xx_xxxx_xxxx_xx 0_0xxx_x0xx_xxxx_xxxx_xx
Contents Tributary
STS-48c/AU-4-16c payload (Tributary index 1,1) STS-12c/AU-4-4c payload first quadrant (Tributary index 1,1) STS-12c/AU-4-4c payload second quadrant (Tributary index 5,1) STS-12c/AU-4-4c payload third quadrant (Tributary index 9,1) STS-12c/AU-4-4c payload fourth quadrant (Tributary index 13,1) STS-3c/AU-4 payload first STS-3 tributary group first quadrant (Tributary index 1,1) STS-3/3xAU-3 payloads first STS-3 tributary group first quadrant (Tributary indexes (1,1), (1,2), (1,3)) STS-3c/AU-4 payload second STS-3 tributary group first quadrant (Tributary index 2,1) STS-3/3xAU-3 payloads second STS-3 tributary group first quadrant (Tributary indexes (2,1), (2,2), (2,3))
0_xxx0_xxxx_xxxx_xxxx_xx
STS-3c/AU-4 payload fourth STS-3 tributary group fourth quadrant (Tributary index 16,1)
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper Table TX_CONFIG_[20:0] Values TX_CONFIG_[20:0]
0_xxx0_xxxx_xxxx_xxxx_xx
Revision January 2002 DATASHEET
Contents Tributary
STS-3/3xAU-3 payloads fourth STS-3 tributary group fourth quadrant (Tributary indexes (16,1), (16,2), (16,3))
comparable register exists Receive side, named RX_PP_CONFIG_[20:0]. interpretation identical TX_CONFIG register defined Table RHINE cannot terminate STS-3 tributaries; that RHINE cannot process STS-3/STM-1 containing STS-1/AU-3 paths extract payloads from them. received STS-3 tributaries will discarded unless they hairpinned back SONET Transmit interface. STS-12/STM-4 STS-3c/STM-1 line-side configurations, RHINE provisioned additional functionality. Each STS-12/STM-4 STS-3/STM-1 line enabled/disabled management interface. Disabled lines have their circuitry shut down order minimize power dissipation. STS-12/STM-4 STS-3/STM-1 lines disabled setting TX_TRIB_INH_x default enabled (TX_TRIB_INH_x Identical controls provided receive direction, RX_TRIB_INH_x.
Power Minimization1
general, power dissipation concern customers. order minimize power consumption each mode operation, RHINE disables unused circuitry. guidelines used this disabling follows:
each mode operation, RHINE disables unused circuitry: (that STS-48c/STM-16 mode, RHINE disables unused framers, TOH/POH monitors, HDLC/Aprocessors, on). modes, RHINE powers down unused tributary logic I/O. This shut-down controlled user TX/RX_TRIB_INH_x. Rhine disables interface inputs outputs APS_IN_INH APS_OUT_INH bits respectively. configurations which path/line switching functionality enabled, unused HDLC/Aprocessing blocks disabled. RHINE disables clock data outputs that unused current configuration. user should clock unused clock-inputs, order minimize power requirements. After MASTER_RESET RX/TX_PROV_RESET been set, RHINE activates circuitry consistent with default configuration. When RHINE reconfigured another operating mode, RHINE activates/deactivates circuitry accordingly. After RX/TX_STATE_RESET been set, RHINE will again return `configured' state, which maintained through STATE_RESET (see section 11.1.1.1) deactivate circuitry accordingly.
Even with RHINE's ability disable unused logic I/O, unused inputs (both differential single ended) must tied externally prevent unstable input conditions (see description section)
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S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Transmit Direction
transmit direction, RHINE provides insertion packets, Acells, direct data into STS/SSPE paths. operating mode these tributaries provisionable through management interface. register value TX_POS_x instructs device perform processing tributary register value TX_POS_x selects Amode these path(s). Optionally, RHINE accept data from system interface directly SONET/SDH local paths. This mode operation selected setting TX_DIRECT_MAP_x value TX_POS_x ignored when TX_DIRECT_MAP_x default value TX_DIRECT_MAP_x TX_POS_x which places RHINE Amode. provisioning TX_LINE_CONFIG, TX_POS_x, TX_DIRECT_MAP_x registers (and their Receive side counterparts RX_LINE_CONFIG, RX_POS_x, RX_DIRECT_MAP_x) must same values ensure that loopback modes will operate correctly. While expected that most applications will configure both side configurations same settings, non-loopback mode, possible configured each side independently. example, side quadrant tributaries could configured traffic into STS12 while side configured de-map STS3Cs containing direct mapped data.
Transmit FIFO Interface
Amode operation, Transmit system interface operates Utopia Level compliant interface. mode, Transmit system interface operates Utopia-like interface (FlexBus packet applications. direct mapping mode-of-operation, Transmit system interface operates variant packet interface, with TX_SOC/P_y, TX_EOP_y, TX_LBYTE, TX_ERR_y signals disabled. addition 32-bit wide, Utopia Level interface, RHINE supports derivative this interface, which provides parallel, 8-bit wide, buses STS-12 STS-3 line configurations. support this mode, there sets following signals: TX_SOC/P_y, TX_EOP_y, TX_ERR_y, TX_ENB_y, TX_CLK_y, TX_PRTY_y. Individual instantiations these signals would apply data bus: TX_SYS_DAT_[31:24], [23:16], [15:8], [7:0]. These modes selectable management interface. detailed description system interface presented section
5.1.1 Transmit Data Parity Check
modes (packet, ATM, direct data), RHINE calculates parity each word received over appropriate Transmit system interface data bits (TX_SYS_DAT), compares received parity (TX_PRTY_y). Parity errors reported management interface setting TX_PRTY_ERR_y_E register TX_PRTY_MODE_y (the default) indicates that parity used this calculation. TX_PRTY_MODE_y indicates that even parity used. RHINE does treat cell/packet received with parity errors errored cell/packet. does alter cell/packet simply notifies management interface parity error.
5.1.2 Transmit FIFO
Link Layer device provides interface clock RHINE synchronizing interface transfers. This convention requires RHINE incorporate rate-matching buffers (namely, FIFOs). FIFOs [1], [5], [9], [13] handle tributaries, which depending configuration, carry STS-48c/AU-4-16c STS-12c/AU-4-4c tributaries. these configurations, these FIFOs 1024 octets deep. FIFOs that handle STS-3c/AU-4 tributaries octets deep. RHINE also maintains packet/cell status through FIFOs. AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
5.1.2.1 Transmit FIFO Error
Amodes, state FIFOs monitored RHINE. FIFO error-condition declared whenever following occur: TX_SOC/P_y received prior cell packet (TX_EOP_y indication) TX_ENB_y active while FIFO full (i.e. FIFO overflow). each tributary, RHINE contains 8-bit, FIFO, error-counter that counts every cell/packet affected FIFO error-event. When performance-monitoring counters latched, value these counters latched TX_FIFOERR_CNT_x_[7:0] registers FIFO error-counters cleared. (See section 4.2.) there been least FIFO error-event since last rising edge LATCH_EVENT, then FIFO error event-bit, TX_FIFOERR_x_SECE, set. mode (TX_POS_x RHINE deletes aborts errored packets, depending size. (See section 5.1.3.) Amode (TX_POS_x TX_DIRECT_MAP_x Acells corrupted FIFO error-events deleted.
5.1.3 Errored Packet Handling
mode-of-operation, (TX_POS_x following errored, packet-handling procedures provided:
5.1.3.1 TX_ERR_y Link Layer Indication
Transmit system interface provides method which Link Layer device indicate RHINE when particular packet contains errors, should aborted discarded. (See definition TX_ERR_y section 9.0.) each tributary, RHINE contains 8-bit, link layer, error-counter that counts every packet received from Link Layer that marked errored. (See TX_ERR_y, section 9.0) When performance-monitoring counters latched (LATCH_EVENT transitions high), value these counters latched TX_POS_LLPKT_ERRCNT_x_[7:0] registers, link layer, packet, error-counters cleared. (See section 4.2.) there been least link-layer packet-error since last rising edge LATCH_EVENT, then link layer, packet, error-event bit, TX_POS_LLPKT_ERR_x_SECE, set.
5.1.3.2 Minimum/Maximum Packet Sizes
RHINE also, option, views packet being errored does transmit aborts violates minimum maximum packet sizes. packet sizes refer size packet only, does include bytes inserted RHINE (such flag sequence, address, control, FIFO underflow, transparency, bytes). These minimum maximum sizes programmable management interface. Register TX_POS_PMIN_[3:0] contains minimum packet size. default value this register Register TX_POS_PMAX_[15:0] contains maximum packet size. default value this register 0x05DE (RFC 1661, page minimum valid size TX_POS_PMAX_[15:0] bytes. packet length checking unreliable TX_POS_PMAX_[15:0] smaller than RHINE disables/enables minimum maximum packet-size checking per-tributary basis when instructed through management interface. TX_POS_PMIN_ENB_x TX_POS_PMAX_ENB_x packet-abort that violation packet-size restriction enabled. (the default), packet size violations ignored. each tributary, RHINE contains two, 8-bit, error-counters that count every violation maximum AMCC
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minimum packet-size limits. When performance-monitoring counters latched, value these counters latched TX_POS_PMIN_ERRCNT_x_[7:0] TX_POS_PMAX_ERRCNT_x_[7:0] registers, packet-size violation-counters cleared. (See section 4.2.) there been least packet-size violation-error since last rising edge LATCH_EVENT, then appropriate, packet-size violation, second event-bit, TX_POS_PMIN_ERR_x_SECE TX_POS_PMAX_ERR_x_SECE, set.
5.1.3.3 Errored Packet Abort
RHINE cannot delete packets error condition received detected after packet begun transmission. These packets therefore aborted. RHINE supports options aborting errored packet. default option abort packet inserting abort sequence, 0x7d7e. Reception this code should cause receiver discard this packet. alternative, RHINE also abort errored packet simply inverting bytes. Abort mode controlled management interface. TX_POS_FCSABRT_ENB_x enables inversion method; TX_POS_FCSABRT_ENB_x (the default) disables
5.1.4 System Side Cell/Packet Loopback
debug purposes, RHINE provides test mode called system loopback. When enabled (SYS_R_TO_T_LOOP_x=1), Acells packets within given tributary extracted from incoming SONET/SDH frames processed normally into FIFO. However, instead data being transferred from FIFO system interface, tributary data FIFO rerouted directly HDLC/Aprocessor (where replaces tributary data received from System Interface). From this point, loopback data mapped normally into outgoing SONET/SDH frames. When SYS_R_TO_T_LOOP loopback inhibited independent operation performed. NOTE: Since SYS_R_TO_T_LOOP test mode passes data directly from FIFO HDLC processor, there flow control provided prevent FIFO from underflowing when data bytes extracted from SONET encompasses multiple rows SONET frame. Therefore, system test loopback limited specific packet size range 20-60 bytes with inter-packet bytes. This system loopback limitation only applicable mode since Amode, ACell processor will cells until complete cell been taken from FIFO. alternative loopback scheme, without above packet size packet liminations, performed using RHINE's hairpin feature described section 5.7.3
Transmit HDLC Processing (POS)
Following Transmit system interface, RHINE performs following processing when mode (TX_POS_x RHINE performs subset this processing when direct mapping mode (TX_DIRECT_MAP_x Specifically, direct mapping mode RHINE optionally performs transparency processing order support insertion FIFO, underflow, stuff-byte into data stream.
5.2.1 Transmit Valid Packet Count
mode (TX_POS_x RHINE contains packet-counters that count every valid packet that transmitted line interface. When performance-monitoring counters latched (LATCH_EVENT transitions high), value these counters latched TX_POS_PKT_CNT_x_[22:0] registers, AMCC
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5.2.2 Pre-HDLC Scrambling
both direct mapping modes, prior HDLC processing, data scrambled using self-synchronizing scrambler. Registers TX_PREHDLC_SCR_INH_x control operation pre-HDLC scramblers. When TX_PREHDLC_SCR_INH_x scrambler tributary enabled. When TX_PREHDLC_SCR_INH_x (the default), operation scrambler inhibited. scrambling operates data big-endian bit-order. payload scrambler (section 5.4) priority over pre-HDLC scrambler must disabled pre-HDLC scrambler enabled.
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RHINE provides pre-HDLC, self-synchronizing scramblers based following generator polynomial:
This scrambler illustrated following figure: Figure Scrambler
Data
Scrambled Data
mode (TX_POS_x this scrambler scrambles entire, incoming, packet stream. Direct Data mode (TX_DIRECT_MAP_x this scrambler randomizes entire, incoming, direct, data stream.
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5.2.3 Encapsulation Packets HDLC Frame
HDLC frame defined Packet-Over-Sonet (POS) applications illustrated Figure packet mode (TX_POS_x each packet received from Link Layer delineated using Flag Sequence defined 1662, which used indicate both beginning HDLC frame. value this Flag Sequence 01111110 (hexadecimal 0x7e).
Flag Sequence byte) 0111 1110 Address byte) (provisionable) Control byte) (provisionable) Protocol bytes)
Optional
HDLC Frame
Received Packet (e.g., PPP)
Information (variable)
Padding (variable)
(16/32bits) Flag Sequence (fill, start next frame) 0111 1110
Optional
Figure HDLC Encapsulation Packet over SONET
option, RHINE insert single flag indicate both frame start following frame. This controlled management interface; TX_POS_EOP_FLAG_x RHINE inserts separate flags tributary indicate start-of-frame end-of-frame. TX_POS_EOP_FLAG_x (the default), only Flag Sequence inserted. STS-48c payloads, both address/control removal inhibited, reception continuous stream either 2-byte packets with only single flag between these bytes (resulting average more than packet clock cycle) will result packets being periodically dropped.
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5.2.4 Address Control Fields
HDLC standards specify fields immediately following start-of-frame Flag Sequence: Address byte Control byte. values both these bytes provisionable per-tributary basis registers TX_POS_ADDRESS_x_[7:0] TX_POS_CONTROL_x_[7:0]. mode (TX_POS_x RHINE will optionally insert these fields tributary TX_POS_ADRCTL_INS_x will insert these fields TX_POS_ADRCTL_INS_x (the default).
5.2.5 Frame Check Sequence (FCS) Field
mode (TX_POS_x option, field then calculated inserted each frame. This option controlled register TX_POS_FCS_INH. value TX_POS_FCS_INH (the default) enables tributaries. value TX_POS_FCS_INH disables types fields have been defined 1662, 16-bit check sequence (FCS-16) 32-bit check sequence (FCS-32). device supports both types. TX_POS_FCS_MODE_x places device FCS-32 mode default. TX_POS_FCS_MODE_x places device FCS-16 mode. RHINE provides FCS-16 functionality, using following generator polynomial:
X12+
RHINE provides FCS-32 functionality, using following generator polynomial:
X10+
field calculated over bits original packet, well Address Control fields. does include Flag Sequence, field itself. also does include added FIFO underflow bytes. (See section 5.2.7.3.) TX_POS_FCS_BIT_ORDR packet data read into shift register big-endian order (MSB first). TX_POS_FCS_BIT_ORDR (the default), packet data read into shift register little-endian order (LSB first). either case, packet data restored big-endian order processing after calculation. inverted then transmitted (most significant octet first), which contains coefficient highest term. TX_POS_FCS_BIT_ORDR transmitted big-endian order. TX_POS_FCS_BIT_ORDR transmitted little-endian order. Figure illustrates calculation FCS-16 functionality:
Input
Figure Calculation FCS-16 Computation preceding figure, feedback contributions shown: shift register inputs that shown come directly from preceding shift register. location addition operators between shift AMCC
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registers feedback determined coefficients polynomial. coefficient indicates that there feedback contribution input corresponding flip-flop shift register. shift register implementation FCS-32 functionality similar, with location feedback contribution shift register input determined FCS-32 generator polynomial. FCS-32, addition operators located above registers calculation begins initializing shift register with data over which calculation performed loaded into shift register from bottom right. After last data entered shift register, contents shift register contain 16/32-bit FCS, with register
5.2.6 Transparency
5.2.6.1 mode
mode (TX_POS_x TX_DIRECT_MAP_x octet stuffing procedure performed this point, which referred Transparency Processing. specific octet, Control Escape (01111101 hexadecimal 0x7d) used marker indicate bytes that will require specific processing Receive side. Control Escape used mark occurrence specific codes (see following table) frame data. After computation, RHINE examines entire frame between Flag Sequences. Each occurrence code identified Table replaced 2-octet sequence consisting Control Escape octet followed original octet exclusive-or'd with hexadecimal 0x20. RHINE performs transparency processing following byte sequences. Occurrences 0x7e payload (between Flag Sequences) processed described. Table Octet Values Handled Transparency Processing Octet Value (Hex) Register
0x7e 0x7d TX_POS_FIFOUNDER_BYTE_ [7:0]
Name
Flag Sequence Control Escape FIFO Underflow
example: 0x7e encoded 0x7d, 0x5e 0x7d encoded 0x7d, 0x5d transparency byte stuffing FIFO, underflow, byte code controlled per-tributary basis TX_POS_FIFOUNDER_MODE_x register. (See section 5.2.7.3.) TX_POS_FIFOUNDER_MODE_x FIFO byte code TX_POS_FIFOUNDER_BYTE_[7:0] inserted during periods FIFO underflow, transparency byte stuffing FIFO byte code enabled. TX_POS_FIFOUNDER_MODE_x FIFO byte code inserted byte stuffing FIFO byte code performed.
5.2.6.2 Direct Mode
direct mapping mode (TX_DIRECT_MAP_x transparency byte stuffing Flag Sequence (0x7e) performed. TX_POS_FIFOUNDER_MODE_x transparency byte stuffing performed tributary Control Escape (0x7d) FIFO underflow code (TX_POS_FIFOUNDER_BYTE_[7:0]). TX_POS_FIFOUNDER_MODE_x transparency process56 AMCC
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5.2.7 Creation
5.2.7.1 Packet Operation (TX_POS_x
packet stream then mapped payload SONET/SDH Synchronous Payload Envelope (SPE). packet octet boundaries aligned with octet boundaries. packet frames variable length, they allowed cross boundaries. When, during operation, there HDLC frames available immediate insertion into SPE, Flag Sequence transmitted fill time between HDLC frames. This done only between complete frames. (See section 5.2.7.3 case where FIFO underflow occurs prior packet.) available information rate Packet over SONET/SDH STS-3c/STM-1 149.760 Mbps, which rate with section, line, path overhead removed. available information rate Packet over SONET/SDH STS-12c/STM-4 (622.080 Mb/s) applications 599.040 Mbps; STS-48c/STM-16 applications, available information rate 2396.16 Mbps.
5.2.7.2 Direct Data Mapping (TX_DIRECT_MAP_x
direct data mapped into payload SONET/SDH Synchronous Payload Envelope (SPE). data octet boundaries aligned with octet boundaries. direct data mapping applications, Link Layer device responsible insuring there enough data RHINE fill SONET/SDH SPE. (See section 5.2.7.3 case where FIFO underflow occurs direct mapping mode.)
5.2.7.3 FIFO Underflow
mode (TX_POS_x transmit FIFO will become empty matter course between packets, should become empty during packet transmission: that after TX_SOC/P_y indication been received before TX_EOP_y indication been received. does, RHINE provides options handling FIFO underflow: packet aborted, using abort methods described section 5.1.3.3; special code transmitted, TX_POS_FIFOUNDER_BYTE_[7:0], filling until valid data once again FIFO. Register TX_POS_FIFOUNDER_MODE_x controls response per-tributary basis; TX_POS_FIFOUNDER_MODE_x indicates that packet will aborted. This default value. TX_POS_FIFOUNDER_MODE_x indicates that special FIFO underflow code, TX_POS_FIFOUNDER_BYTE_[7:0] will transmitted while underflow condition exists. TX_POS_FIFOUNDER_BYTE_[7:0] defaults 0x50. direct mapping mode, (TX_DIRECT_MAP_x TX_POS_FIFOUNDER_MODE_x TX_POS_FIFOUNDER_BYTE_[7:0] enabled well. TX_POS_FIFOUNDER_MODE_x RHINE does nothing except report FIFO underflow events; responsibility user ensure that correct amount data delivered RHINE timely manner. TX_POS_FIFOUNDER_MODE_x RHINE will insert TX_POS_FIFOUNDER_BYTE_[7:0] into SONET/SDH until valid data once again present FIFO. RHINE contains 8-bit FIFO underflow counter each tributary that counts every packet affected FIFO underflow event direct mapping case, each FIFO underflow event counted). When performance-monitoring counters latched, value these counters latched TX_POS_FIFOUNDER_ERRCNT_x_[7:0] registers, FIFO, underflow, error counters cleared. (See section 4.2.) there been least FIFO underflow event since last rising edge LATCH_EVENT, then FIFO, underflow, error event bit, TX_POS_FIFOUNDER_ERR_x_SECE, set.
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Transmit AProcessing
5.3.1 Transmit Data Check
Amode (TX_POS_x RHINE calculates value across Acell header (the first octets) transmit data. calculation follows procedure used section 5.3.4, including TX_ATM_HEC_ENH register. errors reported management interface per-tributary basis setting TX_ATM_HEC_ERR_x_E event This check inhibited setting TX_ATM_UTP_HEC_INH Register TX_ATM_HEC_UDF_[1:0] defines location AHEC within User Defined bytes Utopia Adata structures. (See section 9.4.1.)
5.3.2 Transmit Valid Cell Count
Amode (TX_POS_x RHINE contains, every tributary, Acell counter that counts every Acell (including idle cells) received from ALayer that appears Utopia interface. When performance-monitoring counters latched (LATCH_EVENT transitions high), value these counters latched TX_ATM_CELL_CNT_x_[22:0] registers, Acell counters cleared. (See section 4.2.)
5.3.3 Payload Creation
5.3.3.1 ACells into STS-3c/AU-4
rate available Acells (user information cells, signalling cells, cells, unassigned cells, cells used cell rate decoupling, excluding SONET overhead packets) 149.760 Mb/s. STS-3c/AU-4 signals, RHINE maps Acell stream container (VC-4 without column i.e.,. minus stuff columns). Acell boundaries aligned with STS-3c/STM-1 octet boundaries. Since capacity (2340 octets) integer multiple cell length octets), cell cross boundary.
5.3.3.2 ACells into STS-12c/AU-4-4c
rate available Acells (user information cells, signalling cells, cells, unassigned cells, cells used cell rate decoupling, excluding SONET overhead) 599.040 Mb/s. STS-12c/AU-4-4c signals, RHINE maps local Acell streams C-4-4c containers (VC-4-4c without fixed stuff columns i.e.,. minus stuff columns). Acell boundaries aligned with STS-12c/STM-4 octet boundaries. Since C-4-4c capacity (9360 octets) integer multiple cell length octets), cell cross C-4-4c boundary.
5.3.3.3 ACells into STS-48c/AU-4-16c
rate available Acells (user information cells, signalling cells, cells, unassigned cells, cells used cell rate decoupling, excluding SONET overhead) 2396.16 Mb/s. STS-48c/AU-4-16c signals, RHINE maps local Acell stream C-4-16c container (VC-4-16c without fixed stuff columns i.e.,. minus stuff columns). Acell boundaries aligned with STS-48c/STM-16 octet boundaries. Since C-4-16c capacity (37440 octets) integer multiple cell length octets), cell cross C-4-16c boundary.
5.3.3.4 Idle Cell Stuffing
ATM, idle, cell stuffing used when necessary match rate Acell stream with C-4, C-4-4c, C-4-16c.
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Header pattern 00000000
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Octet
00000000
Octet
00000000
Octet
00000001
Octet
valid code 01010010
Note default content information field "01101010" repeated times. Note There significance these individual header fields from point view Alayer, idle cells passed Alayer.
RHINE provides user programmable fields within idle cell. format Acell header across illustrated following table: Table ACell Header Format ACell Header
(Generic Flow Control)
(Virtual Path Identifier) VCI(Virtual Channel Identifier)
(Payload Type Indicator) (Header Error Control)
(Cell Loss Priority)
RHINE allows user provision GFC, PTI, fields idle cells registers TX_ATM_IDLE_GFC_[3:0], TX_ATM_IDLE_PTI_[2:0], TX_ATM_IDLE_CLP. default values these fields PTI, CLP. (See Table 14.) other fields within first bytes header valid field calculated idle cell, according section 5.3.4 including final stage with 0x55. RHINE also allows user provision contents information octets idle cell register TX_ATM_IDLE_DATA_[7:0]. default value this register 01101010.
5.3.4 Header Error Control (HEC) Sequence Generation
RHINE optionally calculates value across entire Acell header (the first octets) inserts result appropriate header field. This option controlled register TX_ATM_HEC_INH. value TX_ATM_HEC_INH enables tributaries. value TX_ATM_HEC_INH disables When disabled, RHINE passes through byte received from ALayer.
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CRC-8 calculation used produce octet, using following generator polynomial:
Figure illustrates calculation.
Figure Calculation
Input
calculation begins initializing shift register with location addition operators between shift registers feedback determined coefficients CRC-8 polynomial. addition operators illustrated figure. shift registers that shown feed directly into following register, with feedback contribution. data over which calculation performed loaded into shift register from bottom right. After last data entered shift register, contents shift register contain 8-bit HEC, with register another configurable option improve cell delineation process, RHINE supports addition (modulo pattern 01010101 8-bit before being inserted into last octet header. This option controlled register TX_ATM_HEC_ENH. value TX_ATM_HEC_ENH enables modulo addition alternating pattern (0x55) HEC. value disables default
Scrambling
After HDLC Aprocessing, data scrambled using self-synchronizing scrambler. modes, register TX_SCR_INH_x controls operation scrambler per-tributary basis. When TX_SCR_INH_x (the default), scrambler enabled. When TX_SCR_INH_x operation scrambler inhibited. This payload scrambler cannot enabled simultaneously with pre-HDLC scrambler. payload scrambler enabled, pre-HDLC scrambler disabled, regardless setting TX_PREHDLC_SCR_INH_x bit. RHINE provides self-synchronizing scrambler based following generator polynomial:
This scrambler illustrated Figure AMCC
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5.4.1 AScrambler Operation
Amode (TX_POS_x operation scrambler adheres following requirements: scrambler randomizes bits information fields, only. During 5-octet header, scrambler operation suspended scrambler state retained.
5.4.2 HDLC Direct Scrambler Operation
mode (TX_POS_x scrambler scrambles whole payload, including flags. Direct modes (TX_POS_x TX_DIRECT_MAP_x scrambler operates C-4-Xc, therefore does scramble fixed stuff bytes. result scrambling entire payload after HDLC processing, including interframe fill flags.
Insert SPE/VC Generation
this point transmission flow, packets, Acells, direct data have been encapsulated into more SONET/SDH SPE/VCs. From this point modes operate identically. Synchronous Payload Envelope/Virtual Container (SPE/VC) Generation block multiplexes bytes from system interface with Path Overhead (POH) bytes that generates create SONET SDH.
5.5.1 SPE/VC Structure
first column SPE/VC POH. ordering these bytes shown below SONET SDH.
SONET POH: structure STS-3c VC-4 shown Figure POH:
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Figure STS-3c VC-4 Structure Bytes)
Rows
Payload Capacity (2340 Bytes)
Columns
There SPE/VCs this type, each bytes. bytes, which defined section 5.5.2, provisioned using provisioning bytes indexed through [16]. indexes ascending order: first STS-3c/STM-1 provisioned with bytes indexed [1]. structure STS-12c VC-4-4c shown Figure Col. Bytes)
Fixed Stuff Bytes)
Rows
Payload Capacity (9360 Bytes)
1044 Columns
Figure STS-12c VC-4-4c Structure There SPE/VCs this type, each bytes. bytes provisioned using provisioning bytes indexed [1], [5], [9], [13]. indexes ascending order: first STS-12c/STM-4 provisioned with bytes indexed [1].
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Col. Bytes) Fixed Stuff (135 Bytes)
Rows
Payload Capacity (37440 Bytes)
4176 Columns
Figure STS-48c VC-4-16c Structure single required STS-48c/VC-4-16c operation provisioned using index [1].
5.5.2
There bytes path overhead. first byte path overhead path-trace byte, location with respect SONET/SDH TOH/SOH indicated associated STS/AU pointer. (See section 5.5.5.) following sections define transmitted values bytes. Where byte names differ between SONET SDH, SONET name will listed first.
5.5.2.1 Path Trace (J1)
RHINE provides registers through which user program either 16-byte 64-byte, path-trace message byte each tributary. path-trace message provisioned slightly differently, depending mode (SONET SDH) tributary type. 5.5.2.1.1 Mode TX_J1SEL_x (SDH mode), byte transmitted repetitively 16-byte sequence TX_J1_x_[15]_[7:0] down TX_J1_x_[0]_[7:0]. This true tributary types (AU-4-16c AU-4). 5.5.2.1.2 SONET Mode STS-48c Operation TX_J1SEL_[1] TX_CONFIG_[20] RHINE concatenates path-trace messages obtain 64-byte path-trace. 64-byte message stored registers TX_J1_[1:4]_[15:0]_[7:0]. transmission order TX_J1_[1]_[15]_[7:0] first TX_J1_[4]_[0]_[7:0] last. 5.5.2.1.3 SONET Mode STS-12c Operation TX_J1SEL_x (for corresponding TX_CONFIG_[19:16] RHINE concatenates four, 16-byte, path-trace messages obtain 64-byte path trace designated tributary. STS-12c/AU-4-4c tributary (according SONET convention, [1], [5], [9], [13]), 64-byte message stored registers TX_J1_[x:x+3]_[15:0]_[7:0]. transmission order TX_J1_[x+3]_[15]_[7:0] first TX_J1_[x]_[0]_[7:0] last. 5.5.2.1.4 SONET Mode STS-3c Operation TX_J1SEL_x TX_CONFIG_[15:0] RHINE provides slightly different mechanism storing path-trace message. This method allows user provision path-trace message each STS-3c tributaries, which majority path-trace message consistent value, common across tributaries, only portion full 64-byte message variable tributary-by-tribuAMCC
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tary basis. RHINE provides registers hold common portion message, TX_J1_COMMON_[47:0]_[7:0]. variable portion 64-byte trace message each tributary stored TX_J1_x_[15:0]_[7:0]. sequence bytes transmitted specific STS-3c (here, represents concatenation): TX_J1_x_[15:0]_[7:0] TX_J1_COMMON_[47:0]_[7:0]
5.5.2.2 Path BIP-8 (B3)
Interleaved Parity (BIP-8) transmitted even parity (normal) B3_INV_x Otherwise, parity (incorrect) generated. BIP-8 calculated over bits previous SPE/VC (including POH) before scrambling then placed byte from current SPE/VC before scrambling. definition BIP-8, first provides parity over first from bytes previous SPE/VC; second provides parity over second bytes previous SPE/VC,
5.5.2.3 Signal Label (C2)
signal label byte indicates composition SPE/VC. provisioned value, TX_C2_x_[7:0], inserted into generated bytes.
5.5.2.4 Path Status (G1)
Path REI. Receive side monitors errors received SPE/VC. (See section 6.11.2.) number errors detected each frame transferred from Receive side Transmit side insertion into transmit path status byte, Remote Error Indication. FORCE_G1ERR_x MSBs will continuously transmitted 1000 (for testing purposes). Else PREI_INH_x they binary value (0000 through 1000, indicating between equal number errors most recently detected Receive side monitoring block. Else PREI_INH they
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Path RDI. used Path/AU Remote Defect Indication (RDI-P), bits used enhanced RDI-P indicator. values transmitted bits taken from variety sources, according following tableIn certain modes, Trace Identifier Mismatch (TIM) indication contributes enhanced PRDI indication. condition detected externally RHINE user software. RHINE provides RX_TIM_x register each tributary allow user notify RHINE when condition occurred. RHINE then include this term automatic PRDI calculation. contribution desired, user should RX_TIM_x register Table Path Provisioning PRDI_AUTO_x
PRDI_ENH_x
Source/Format Bits
TX_G1_x_[2:0]. One-bit RDI, generated from internal parameters. Three-bit PRDI, generated from internal parameters.
values transmitted bits shown Table source side parameters used drive Path values side this RHINE Table Path Values PRDI_ ENH_
PRDI_ AUTO_x
RX_PI_PAIS_ RX_PI_LOP_x
(RX_UNEQ_x TX_UNEQ_PRDI_x) RX_TIM_x
(RX_PLM_x TX_PLM_PRDI_x) RX_ATM_LCD_x TX_ATM_LCD_PRDI_x
Bits (for Tributary
TX_G1_x_[2:0]
Table VII. 1/G.707, PLM-P trigger condition PRDI; however, T1X1.5/99-036, contribution T1X1 that attempting align definition PRDI SONET SDH, trigger condition PRDI. Therefore, TX_PLM_PRDI_x registers have been defined support both options. TX_PLM_PRDI_x (the default), does contribute PRDI tributary TX_PLM_PRDI_x considered Remote Payload Defect contributes PRDI. analogous manner, TX_UNEQ_PRDI_x TX_ATM_LCD_PRDI_x registers have been defined support both options UNEQ contributions PRDI tributary TX_UNEQ_PRDI_x UNEQ considered Remote Payload Defect, equivalent condition contributes PRDI. PRDI_AUTO_x values shown above transmitted minimum frames. Once frames have been transmitted with same value, value corresponding current state defect indication values listed Table will transmitted. defect persists less than frames AMCC
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transmitted minimum frames. persists beyond frames, transmitted increments frames. That defect received less than frames would transmitted 20+21 frames, received less than frames would transmitted 20+21+21 frames. This frame timer located Transmit side RHINE. Table PRD1_AUTO_x=0. (the LSB) unused
5.5.2.5 Other Bytes
remaining bytes supported RHINE transmitted fixed bytes. These include path user channel (F2), position indicator (H4), path growth/user channel (Z3/F3), path growth/path channel (Z4/K3), tandem connection monitoring (Z5/N1) bytes.
5.5.3 Unequipped Generation
Unless active, unequipped SPE/VC tributary (all SPE/VC bytes filled with generated TX_UNEQ_x
5.5.4 PAIS Generation
Normal generation SONET/SDH payload suspended during transmission Path Administrative Unit (AU) signals: PAIS. PAIS generation controlled TX_PAIS_x register. TX_PAIS_x entire payload applicable tributary (determined TX_LINE_CONFIG_[4:0] TX_CONFIG_[20:0]) filled with all-1s bytes.
5.5.5 Pointer Bytes (H1, Pointer Action Byte (H3)
bytes contain fields, shown Figure Data Flag (NDF) Bit: Bits 10-Bit Pointer Value
Byte disabled: 0110 enabled: 1001
Byte Positive stuff: Invert I-bits Negative stuff: Invert D-bits
Figure Pointer Byte Fields
Because SPE/VC generated synchronously with TOH, variable pointer generation required. Instead, active bytes generated with fixed pointer value (decimal) 10_0000_1010 (binary), bytes fixed Thus, byte SPE/VC tributary placed column SONET/SDH frame STS-48/STM-16 signals. placed column SONET/SDH frame quad STS-12/STM-4 operation; placed column SONET/SDH frame STS-3c/STM-1 operation.
5.5.5.1 AIS-P Generation
TX_PAIS_x active, corresponding bytes transmitted When TX_PAIS_x transitions RHINE transmits first byte next frame corresponding tributary with enabled Data Flag (NDF). Succeeding frames generated with field disabled first byte. AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
5.5.5.2 Non-AIS Generation
first H1-H2 byte pair AU-4, AU-4-4c AU-4-16c transmitted normal pointer, with 0110 TX_SDH_PG_x, Pointer Value 10_0000_1010
remaining H1-H2 byte pairs transmitted concatenation indication bytes, with =1001 TX_SDH_PG_x, Pointer Value 11_1111_1111
Transmit Multiplexer
this point, RHINE multiplexes transmit signals into single STS-48 format (see Figure 10), facilitate switching.
Transmit Port Selector
5.7.1 Dual-Feed Output Port
RHINE supports configurations through interface. transmit processing path, entire transmit SPE(s) dual from this point Output Selector block (7.1), well Transmit Selector block.
5.7.2 Transmit Selector
support switching between RHINE devices, selector provided this point transmit processing. This selector select data input TOH/SOH Generation block from possible sources; Payload Generation block this RHINE Input interface. selection controlled per-tributary basis register TX_APS_SEL_x. TX_APS_SEL_x data coming from Payload Generation block this RHINE selected (the default). TX_APS_SEL_x data coming from Input interface selected. Note that order operate properly between RHINE devices, they must have their frames aligned. This achieved supplying each with common TX_FRAME_IN. STS-48/STM-16 operation (TX/RX_LINE_CONFIG[4] TX_APS_SEL_x registers must written switch entire signal. STS-12/STM-4 configurations (TX/RX_LINE_CONFIG[3:0] 1111), TX_APS_SEL_x registers corresponding each STS-12/STM-4 tributary must written.
5.7.3 Internal Hairpin Selector
support hairpin turn from direction within single RHINE device, second selector provided just after Transmit Selector transmit processing. This selector select data input TOH/SOH Generation block from possible sources: output Transmit Selector this RHINE output Receive Pointer Processor block. selection controlled per-tributary basis register TX_APS_DXC_SEL_x. TX_APS_DXC_SEL_x data coming from Transmit Selector block this RHINE selected (the default). TX_APS_DXC_SEL_x data coming from Receive Pointer Processor block selected.
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Transmit Demultiplexer
this point, RHINE demultiplexes transmit signals into formats defined TX_LINE_CONFIG_[4:0] registers.
SONET/SDH Frame Generation
TX_LINE_CONFIG_[4] SONET/SDH Frame Generation block creates STS-48/STM-16 signal, multiplexing designated tributaries from SPE/VC Generation blocks. TX_LINE_CONFIG_[4:0] 01111, SONET/SDH Frame Generation block creates STS-12/STM-4 signal each quadrant. TX_LINE_CONFIG_[4:0] 00000, SONET/SDH Frame Generation block creates STS-3c/STM-1 signals each quadrant. Frame Generation block then generates Transport (Section) Overhead (TOH/SOH) bytes scrambles bytes SONET/SDH signal(s) except first TOH/SOH bytes. structure STS-48/STM-16 shown Figure
4320 Columns TOH/SOH (1296 Bytes)
Rows
SPE/VC (37584 Bytes)
Figure STS-48/STM-16 Structure
Figure first columns each shown SOH. This strictly true SDH, because first columns fourth frames considered part SOH. Instead, Administrative Unit (AU) pointer bytes fourth TOH/SOH grouped with form AU-4, AU-4-4c, AU-4-16c. structure STS-12/STM-4 shown Figure
1080 Columns
TOH/SOH (324 Bytes)
Rows
SPE/VC (9396 Bytes)
Figure STS-12/STM-4 Structure
AMCC
S4804CBI41: RHINE
STS-48 SONET/SDH Framer POS/AMapper
Revision January 2002 DATASHEET
Figure first columns each shown SOH.
AMCC
S4804CBI41: RHINE<br

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