S3091 SONET/SDH/AOC-192 16:1 Transmitter Silicon Germanium B

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

S3091 SONET/SDH/AOC-192 16:1 Transmitter Silicon Germanium B

Datasheet Thumbnail

Top Searches for this datasheet

Part Number S3091 Revision February 2002
S3091
SONET/SDH/AOC-192 16:1 Transmitter
Silicon Germanium BiCMOS technology Complies with Telcordia, ITU-T, G.709 specifications On-chip high-frequency clock generation OC-192 with Digital Wrapper (DW) (9.953 10.709 Gbps) Reference frequency 155.52 622.08 equivalent rate) 16-bit parallel, 622.08 Mbps LVDS data path Lock detect/Phase error indicator jitter differential single-ended serial interface Dual +3.3 -5.2 power supply Supports line timing Internal FIFO decouple transmit clocks 311.04 622.08 parallel input clock Programmable skew 311.04 parallel clock mode 148-pin CBGA package Typical power dissipation
DEVICE SPECIFICATION
APPLICATIONS
SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment Aover SONET/SDH Section repeaters Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
GENERAL DESCRIPTION
S3091 SONET/SDH chip fully integrated serializer with SONET OC-192 with Digital Wrapper (9.953 10.709 Gbps) rate capability. chip performs necessary parallel-to-serial functions conformance with SONET/SDH/Digital Wrapper transmission standards. device suitable SONET-based Aapplications. Figure shows typical network application. On-chip clock synthesis components contained S3091 chip, allowing slower external transmit clock reference. chip used with 155.52 622.08 reference clock equivalent rate), support existing system clocking schemes.
Figure System Block Diagram
INDUS (19201), GANGES (19202) HUDSON (19203)
S3091
S3092
S3092 S3091
INDUS (19201), GANGES (19202) HUDSON (19203)
S3091 SONET/SDH/AOC-192 16:1 Transmitter Contents
Revision February 2002
DEVICE SPECIFICATION
FEATURES APPLICATIONS GENERAL DESCRIPTION CONTENTS LIST FIGURES LIST TABLES SONET OVERVIEW Data Rates Signal Hierarchy Frame Byte Boundary Detection S3091 OVERVIEW S3091 ARCHITECTURE/FUNCTIONAL DESIGN OPERATION Clock Divider Phase Detector Timing Generator Parallel-to-Serial Converter FIFO FIFO Initialization Power Sequencing ORDERING INFORMATION
S3091 SONET/SDH/AOC-192 16:1 Transmitter List Figures
Revision February 2002
DEVICE SPECIFICATION
Figure System Block Diagram Figure SONET Structure Figure STS-192 Frame Format Figure Functional Block Diagram Figure S3091 Pinout Figure S3091 148-Pin CBGA Package Figure Input Timing (PICLKP/N 622.08 MHz) Figure Input Timing (PICLKP/N 311.04 MHz) Figure Phase Adjust Timing Figure Differential Voltage Measurement Figure Output -5.2 Input Coupled Termination, Reference Only Figure S3091 LVDS Driver LVDS Input, Reference Only Figure LVDS Driver S3091 LVDS Input Direct Coupled Termination, Reference Only Figure LVDS Driver S3091 LVDS Input Coupled Termination, Reference Only Figure External Loop Filter Figure S3091 622.08 REFCLK Phase Noise Limit Figure S3091 155.52 REFCLK Phase Noise Limit
List Tables
Table SONET Signal Hierarchy Table Modes Table Reference Frequency Table Clock Select Table Skew Select Table Input Assignment Descriptions Table Output Assignment Descriptions Table Common Assignment Descriptions Table Thermal Management Table Performance Specifications Table Absolute Maximum Ratings Table Recommended Operating Conditions Table LVTTL Input Characteristics Table LVTTL Output Characteristics Table Differential Output Characteristics Table Internally Biased Differential Input Characteristics Table Internally Biased LVDS Input Characteristics Table LVDS Output Characteristics (See Figure Table Transmitter Timing Characteristics (PICLKP/N 622.08 MHz) Table Transmitter Timing Characteristics (PICLKP/N 311.04 MHz) Table External Loop Filter Components
S3091 SONET/SDH/AOC-192 16:1 Transmitter SONET OVERVIEW
Synchronous Optical Network (SONET) standard connecting fiber system another optical level. SONET, together with Synchronous Digital Hierarchy (SDH) administered ITU-T, forms single international standard fiber interconnect betwe ephone works diff erent countries. SONET capable accommodating variety transmission rates applications. SONET standard layered protocol with four separate layers defined. These are: Photonic Section Line Path
Revision February 2002
DEVICE SPECIFICATION
Frame Byte Boundary Detection SONET/SDH fundamental frame format STS-192 consists transport overhead bytes followed Synchronous Payload Envelope (SPE) bytes. This pattern overhead 16,704 bytes repeated nine times each frame. Frame byte boundaries detected using bytes found transport overhead. (See Figure more details SONET operations, refer Bellcore SONET standard document. Figure SONET Structure
Functions
Payload mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Figure shows layers their functions. Each layers overhead bandwidth dedicated administration maintenance. photonic layer simply handles conversion from electrical optical back with overhead. responsible transmitting electrical signals optical form over physical media. section layer handles transport framed electrical signals across optical cable from next. functions this layer framing, scrambling, error monitoring. line layer responsible reliable transmission path layer information stream carrying voice, data, video signals. main functions synchronization, multiplexing, reliable transport. path layer responsible actual transport services appropriate signaling rates. Data Rates Signal Hierarchy Table contains data rates signal designations SONET hierarchy. lowest level basic SONET signal, referred synchronous transport signal level-1 (STS-1). STS-N signal made byte-interleaved STS-1 signals. optical counterpart each STS-N signal optical carrier level-N signal (OC-N). chip supports OC-192 with Digital Wrapper (9.95328 10.709 Gbps) rates.
Path layer Line layer Section layer
Path layer Line layer Section layer
Photonic layer
Photonic layer
Equipment
Fiber Cable Equipment
Table SONET Signal Hierarchy
Elec. STS-1 STS-3 STS-12 STS-24 STS-48 STS-192 STM-1 STM-4 STM-8 STM-16 STM-64 ITU-T Optical OC-1 OC-3 OC-12 OC-24 OC-48 OC-192 Data Rate (Mbps) 51.84 155.52 622.08 1244.16 2488.32 9953.28
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Figure STS-192 Frame Format
Revision February 2002
DEVICE SPECIFICATION
Rows
Bytes
Bytes
Transport Overhead Columns 5,184 bytes µsec
Synchronous Payload Envelope 16,704 Columns 16,704 150,336 bytes
S3091 SONET/SDH/AOC-192 16:1 Transmitter S3091 OVERVIEW
S3091 transmitter implements SONET/SDH serialization transmission functions. This chip used implement front SONET equipment, which consists primarily serial transmit interface serial receive interface. chip includes parallel-to-serial conversion system timing. system timing circuitry consists high-speed phase detector, clock dividers, clock distribution throughout front end.
Revision February 2002
DEVICE SPECIFICATION
sequence transmitter operations follows: 16-bit parallel input Parallel-to-serial conversion Serial output Internal clocking control functions transparent user. Details data timing seen Figures Suggested Interface Devices
AMCC AMCC AMCC AMCC S3092 19201 19202 19203 OC-192 CDR+DeMUX OC-192 OC-48 MUX/DeMUX OC-192 SONET/SDH Mapper OC-192 Digital Wrapper
Figure Functional Block Diagram
16:1 PARALLEL SERIAL TSDP/N
PINP/N[15:0] PICLKP/N PHINITP/N CLKSEL SKEWSEL[1:0]
TIMING RSTB PCLKP/N PHERRP/N TESTB REFSEL REFCLKP/N CLOCK DIVIDER PHASE DETECTOR
LOCKERRB
155MCKP/N 77MCKP/N
CAP1 CAP2
S3091 SONET/SDH/AOC-192 16:1 Transmitter S3091 ARCHITECTURE/FUNCTIONAL DESIGN
OPERATION S3091 performs serialization processing transmit SONET STS-192 serial data stream. converts 16-bit parallel 622.08 Mbps data stream serial format 9.953 Gbps. high-frequency clock generated from 155.52 622.08 equivalent rates) frequency reference using frequency synthesizer that consist on-chip phase-lock loop circuit with divider, loop filter. Clock Divider Phase Detector clock divider phase detector, shown block diagram Figure contains monolithic components that generate signals required drive loop filter. Table REFCLK required. order clock frequency meet accuracy required operation SONET system, REFCLK input must generated from differential crystal oscillator which frequency accuracy equals value stated Table Oscillator phase noise allowable defined best looking plots oscillators that allow part meet SONET jitter generation specifications mUIpp. seen from Figures different vendors' oscillators yield similar results. REFCLK, mUIpp graph noise floor part.
Revision February 2002
DEVICE SPECIFICATION
best jitter generation, 622.08 oscillator with phase noise that meets exceeds phase noise plots shown Figure 155.52 oscillator with phase noise that meets exceeds phase noise plots Figure Timing Generator timing generator function, shown Figure provides separate functions. provides 16-bit parallel rate clock mechanism aligning phase between incoming clock clock that loads parallel-to-serial shift register. PCLK output 16-bit parallel rate clock. STS-192, PCLK frequency 622.08 MHz. PCLK intended 16-bit parallel speed clock upstream multiplexing overhead processing circuits. Using PCLK upstream circuits will ensure stable frequency phase relationship between data coming into leaving S3091 device. parallel-to-serial conversion process, incoming data passed from PICLK clock timing domain internally generated byte clock timing domain using internal FIFO. timing generator also produces feedback reference clock clock synthesizer. counter divides synthesized clock down same frequency reference clock (REFCLK). clock synthesizer maintains stability synthesized clock comparing phase feedback clock that reference clock (REFCLK). modulus counter function reference clock frequency operating frequency.
Table Modes
Error Correcting Capability bytes 255-byte block bytes 255-byte block bytes 255-byte block bytes 255-byte block bytes 255-byte block bytes 255-byte block bytes 255-byte block Digital Wrapper (OTU2) Code Rate showing Bandwidth Expansion code words Increase 2.82% Increase 3.66% Increase 4.51% Increase 5.37% Increase 6.25% Increase 7.14% Increase 7.59% Increase Increased Input Clock (REFCLK) Frequency 622.08 639.62 644.84 650.13 655.48 660.96 666.51 669.33
Increased Frequency 9.953 Gbps 10.234 Gbps 10.317 Gbps 10.402 Gbps 10.488 Gbps 10.575 Gbps 10.664 Gbps 10.709 Gbps
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Parallel-to-Serial Converter parallel-to-serial converter shown Figure comprised byte-wide registers. PICLK (622.08 311.04 dual edge clock) clocks data from PINP/N[15:0] first register parallel-to-serial register. second register parallel loadable shift register, which takes parallel input from first register. internally generated byte clock activates parallel data transfer between registers. serial data shifted second register. 311.04 dual edge PICLK mode selected, PICLK skew relative PINP/N[15:0] introduced optimize data clock setup hold times. SKEWSEL[1:0] used control skew which nominally Table skew selections. FIFO FIFO added decouple internal external parallel clocks. internally generated divide-by-16 clock used clock data from FIFO. PHINIT LOCKERRB used center reset FIFO. PHINIT LOCKERRB signals will center FIFO after third PICLK pulse. (See Figure This ensures that PICLK stable. This scheme allows user have infinite PCLK PICLK delay through ASIC. Once FIFO centered, PCLK PICLK delay have maximum drift specified Table FIFO Initialization FIFO initialized following three ways: During power once locked reference clock provided REFCLK pins, LOCKERRB will active initialize FIFO. When RSTB goes active, entire chip reset. This causes lock, thus LOCKERRB goes inactive. When reacquires lock, LOCKERRB goes active initializes FIFO. Note that PCLK does toggle when RSTB active. user also initialize FIFO raising PHINIT. During normal running operation, incoming data passed from PICLK timing domain internally generated divide-by-16 clock timing domain. Although frequency PICLK internally generated clock same, their phase relationship arbitrary.
Revision February 2002
DEVICE SPECIFICATION
Table Reference Frequency
REFSEL REFCLK 155.52 equivalent rate) 622.08 equivalent rate)
prevent errors caused short setup hold times between timing domains, timing generator circuitry monitors phase relationship between PICLK internally generated clock. When potential setup hold time violation detected, Phase Error (PHERR) goes High. condition persi sts, PHERR will PHERR conditions occur, PHINIT should activated recenter FIFO least ns). This done connecting PHERR PHINIT. When realignment occurs, four bytes data will lost. user also take PHERR signal, process send output PHINIT such that idle bytes lost during realignment process. PHERR will inactive when realignment complete. (See Figure Phase Adjust Timing.) Power Sequencing order avoid latchup, required that -5.2 power applied S3091 minimum before power applied. Table Clock Select
CLKSEL PICLK Frequency 622.08 equivalent rate) 311.04 equivalent rate)
Table Skew Select
SKEWSEL[1] SKEWSEL[0] PICLK Target Skew 1015
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table Input Assignment Descriptions
Name Level
Revision February 2002
DEVICE SPECIFICATION
Description
PINP0 PINN0 PINP1 PINN1 PINP2 PINN2 PINP3 PINN3 PINP4 PINN4 PINP5 PINN5 PINP6 PINN6 PINP7 PINN7 PINP8 PINN8 PINP9 PINN9 PINP10 PINN10 PINP11 PINN11 PINP12 PINN12 PINP13 PINN13 PINP14 PINN14 PINP15 PINN15 PICLKP PICLKN
LVDS
Parallel Data Input. 16-bit parallel, 622.08 Mbps, aligned PICLK parallel input clock. PINP/N[15] most significant (corresponding each word, first transmitted). PINP/N[0] least significant (corresponding each word, last transmitted). PINP/N[15:0] sampled rising edge PICLK (when CLKSEL rising falling edge PICLK (when CLKSEL Internally biased terminated.
LVDS
Parallel Input Clock. 622.08 dual edge 311.04 nominally duty cycle input clock, which PINP/N[15:0] aligned. PICLK used transfer data inputs into holding register parallel-to-serial converter. Internally biased terminated. Test Clock Enable. Active Low. provide access during production tests. (Pull High normal operation.) Reference Clock. Input used reference internal clock frequency synthesizer. Internally terminated biased. Master Reset. Active Low. Reset input device. correct reset, this input must asserted During reset, PCLK does toggle. Loop Filter Capacitors. Connections external loop filter capacitor resistors. (See Figure 15.)
TESTB REFCLKP REFCLKN RSTB
LVTTL Diff. LVTTL
CAP1 CAP2
Analog
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table Input Assignment Descriptions (Continued)
Name Level
Revision February 2002
DEVICE SPECIFICATION
Description
REFSEL PHINITP PHINITN CLKSEL SKEWSEL1 SKEWSEL0
LVTTL LVDS LVTTL LVTTL
Reference Select. Used select reference clock frequency. Table Phase Initialization. Asynchronous input that initializes phase adjust circuit. (See Figure Clock Select. Used select between 622.08 311.04 dual edge clock PICLKP/N. Table Allows magnitude error delaying PICLK compensate variations data valid window Inter-Symbol Interference (ISI) static skew. Table
Table Output Assignment Descriptions
Name Level Description
TSDP TSDN
Diff.
Transmit Serial Data. Serial data stream signals, normally connected optical transmitter module. Coplanar Waveguide Structure best results. Layout Recommendation application note. Characterization Report plot. Parallel Clock. 622.08 clock. normally used coordinate transfers between upstream logic S3091 device. 155.52 Clock Output. 155.52 clock output from clock synthesizer. output should connected reference clock input external clock recovery function (such S3092). Pull-down resistors removed minimize power. 77.76 Clock Output. 77.76 clock output from clock synthesizer. test purposes only. Pull-down resistors removed minimize power. Lock Error/Phase Error. Active Low. Goes inactive after internal delay locked clock provided REFCLK pins. LOCKERRB goes active least when PHERR goes active. LOCKERRB stays active long PHERR active. LOCKERRB asynchronous output. Phase Error. Pulses High during each PCLK cycle which there potential set-up/hold timing violation between internal byte clock PICLK timing domains.
PCLKP PCLKN 155MCKP 155MCKN
LVDS LVDS
77MCKP 77MCKN LOCKERRB
LVDS
LVTTL
PHERRP PHERRN
LVDS
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table Common Assignment Descriptions
Name Level
Revision February 2002
DEVICE SPECIFICATION
Description
AVEE VEE_FILTER VEE_VCO DGND AGND THERMALGND
-5.2 -5.2 -5.2
A13, A14, B14, C10, E13, L14, M10, N10, P11, P12, P13, E10, F10, G10, H10, J10, H13,
Analog Analog Filter Analog Digital Ground Analog Thermal Ground
VCCLVDS VCCLVTTL
+3.3 +3.3
LVDS LVTTL
Note: digital, analog, thermal grounds connected together package.
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Figure S3091 Pinout
Revision February 2002
DEVICE SPECIFICATION
AGND
AGND
FILTER
AGND
CLKSEL
RSTB
DGND
77MCKN
77MCKP
PCLKN
PHERRN
DGND
DGND
REFCLKP
AGND
AGND
CAP1
AGND
AGND
DGND
AVEE
155MCKN
155MCKP
PCLKP
PHERRP
PHINITN
DGND
REFCLKN
AGND
AGND
CAP2
AGND
TESTB
VCCLVTTL
AVEE
VCCLVDS
DGND
LOCKERRB
PHINITP
PICLKN
REFCLK
AGND
SKEWSEL0
PICLKP
AGND
AVEE
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
DGND
PIN15N
AGND
AGND
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
PIN14N
PIN15P
TSDP
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
PIN14P
PIN13N
AGND
AGND
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
VCCLVDS
PIN13P
TSDN
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
SKEWSEL1
PIN12N
AGND
AGND
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
PIN11N
PIN12P
AGND
AVEE
PIN11P
DGND
AGND
REFSEL
VCCLVDS
DGND
AVEE
VCCLVDS
DGND
AVEE
VCCLVDS
DGND
PIN8P
PIN8N
VCCLVDS
PIN10N
DGND
PIN0P
PIN0N
PIN2P
PIN2N
PIN4P
PIN4N
PIN6P
PIN6N
DGND
AVEE
PIN9P
PIN9N
PIN10P
DGND
DGND
PIN1P
PIN1N
PIN3P
PIN3N
PIN5P
PIN5N
PIN7P
PIN7N
DGND
DGND
DGND
DGND
S3091 (Package View) (Die BOTTOM View)
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Figure S3091 148-Pin CBGA Package
Revision February 2002
DEVICE SPECIFICATION
Table Thermal Management
Device S3091 Package Power (70°C Ambient) 2.68 20.5°C/W 3.0°C/W
Note: application note simulation results, thermal management suggestions thermal profile attachment.
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table Performance Specifications
Parameter Units
Revision February 2002
DEVICE SPECIFICATION
Conditions
Nominal VCOCLK Center Frequency Data Output Jitter STS-192 with 622.08 REFCLK. Data Output Jitter STS-192 with155.52 REFCLK. TSDP/N Output Return Loss (S22) Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle (622.08 MHz) equivalent rate) Reference Clock Input Duty Cycle (155.52 MHz) equivalent rate) Reference Clock Rise Fall Times 155.52 Clk. equivalent rate) Reference Clock Rise Fall Times 622.08 Clk. equivalent rate) Acquisition Lock Time (phase lock)
9.953
10.709
mUIpp mUIpp Limited B.W., MHz, 1E-12. Limited B.W., MHz, 49/51 duty cycle REFCLK. required meet SONET output frequency specification.
-100 +100
Required best jitter performance.
amplitude.
amplitude.
After release RSTB, with device already powered with valid REFCLK. Guaranteed, tested.
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table Absolute Maximum Ratings
Parameter -0.5 -0.5 -0.25 -0.25 AGND -0.5
Revision February 2002
DEVICE SPECIFICATION
-7.0 +0.5 AGND AGND +0.5
Units
Storage Temperature Supply -5.2 Supply LVTTL Input Voltage LVDS Input Voltage LVDS Output Voltage Input Voltage Output Voltage LVTTL Output Voltage Output Current LVDS Input Current LVTTL Input Current LVTTL Output Current LVDS Output Current Input Current
-450
1000
Electrostatic Discharge (ESD) Ratings S3091 rated following voltages based human body model: pins rated Volts. Standards protection should adhered when handling devices ensure that they damaged. standards used defined ANSI standard ANSI/ESD S20.20-1999, "Protection Electrical Electronic Parts, Assemblies Equipment." Contact your local sales representative application notes.
Table Recommended Operating Conditions
Parameter 3.135 -4.94 -5.2 3.465 -5.46 Units
Ambient Temperature Under Bias (Commercial) Junction Temperature Under Bias Voltage with Respect Voltage with Respect Supply Current Supply Current
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table LVTTL Input Characteristics
Parameters Description 3.465 -500
Revision February 2002
DEVICE SPECIFICATION
Units
Condition
Input High Voltage Input Voltage Input High Current Input Current
Table LVTTL Output Characteristics
Parameters Description Units Condition
Output High Voltage
Output Voltage
Table Differential Output Characteristics
Parameters Description AGND 1.25 AGND 0.55 1000 AGND 0.80 AGND 0.25 1500 Units Condition
VOUTDIFF
Output Voltage Output High Voltage Serial Output Differential Voltage Swing Serial Output Singleended Voltage Swing Single-ended Resistance
line-to-line. line-to-line. line-to-line. Figure line-to-line. Figure Over process, voltage temperature range.
Data
VOUTSINGLE
Data RSINGLE
Table Internally Biased Differential Input Characteristics
Parameters VINDIFF VINSINGLE Description 1600 Units Comments
Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Input High Voltage Input Voltage
Figure Figure
RDIFF
AGND
AGND
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table Internally Biased LVDS Input Characteristics
Symbol Description 1.16 Unit
Revision February 2002
DEVICE SPECIFICATION
Conditions
VINDIFF VINSINGLE RDIFF
Input High Voltage Input Voltage Input Voltage Differential Input Single-ended Voltage Differential Input Resistance
Over process, voltage temperature range Over process, voltage temperature range Over process, voltage temperature range Over process, voltage temperature range Over process, voltage temperature range
2600
1300
Table LVDS Output Characteristics1,2 (See Figure
Symbol Description 1.25 Unit Conditions
VOUTDIFF VOUTSINGLE
Output High Voltage Output Voltage Output Differential Voltage Output Singleended Voltage
Over process, voltage temperature range Over process, voltage temperature range Over process, voltage temperature range Over process, voltage temperature range
0.85
1.45
1100
Output loading line-to-line. pull-down resistor line ground.
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table Transmitter Timing Characteristics (PICLKP/N 622.08 MHz)
Symbol Description PICLKP/N Duty Cycle tDPICLK/T0 tSPIN tHPIN
Revision February 2002
DEVICE SPECIFICATION
Units
PINP/N[15:0] Set-up Time w.r.t. rising edge PICLKP (622.08 PICLK) PINP/N[15:0] Hold Time w.r.t. rising edge PICLKP (622.08 PICLK) PCLKP/N Duty Cycle Output Rise Fall Time (20% 80%), Pattern LVDS Output Rise Fall Time (20% 80%)
PHINIT Minimum Pulse Width (See Figure RSTB Minimum Pulse Width1 155MCKP/N Duty Cycle PCLK PICLK drift after FIFO centered
Guaranteed design.
Figure Input Timing (PICLKP/N 622.08 MHz)
tDPICLK (622.08 MHz) PICLKP tSPIN PINP/N[15:0] tHPIN
When set-up time specified LVDS signals between input clock, set-up time picoseconds, from point input point clock. When hold time specified LVDS signals between input clock, hold time picoseconds, from point clock point input.
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Table Transmitter Timing Characteristics (PICLKP/N 311.04 MHz)
Symbol Description PICLKP/N Duty Cycle tDPICLK/T0 TR,TF tSPIN tHPIN LVDS output rise fall times (20% 80%) PINP/N[15:0] setup time w.r.t. next edge PICLKP (311.04 PICLK) PINP/N[15:0] hold time w.r.t. next edge PICLKP (311.04 PICLK) PCLK PICLK drift after FIFO centered
Revision February 2002
DEVICE SPECIFICATION
1000
Units
Figure Input Timing (PICLKP/N 311.04 MHz)
tDPICLK
(311.04 MHz) PICLKP
Vcross tSPIN
Vcross tSPIN
Vcross
PINP/N[15:0]
tHPIN
tHPIN
Table External Loop Filter Components
Symbol Description Value Unit
Resistor, Surface Mount, 0402 Capacitor, Surface Mount, 0603 larger
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Figure Phase Adjust Timing
Revision February 2002
DEVICE SPECIFICATION
4-10 BYTE CLOCKS PHERR PHINIT
PCLK
PICLK
TRANSFER (Internal)
Note: byte clock 622.08 669.33 MHz.
Figure Differential Voltage Measurement
V(+)
VISINGLE V(-)
V(+) V(-) VIDIFF VISINGLE
Note: with respect
Note: V(+) V(-) algebraic difference input signals.
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Revision February 2002
DEVICE SPECIFICATION
Figure Output -5.2 Input Coupled Termination, Reference Only
Zo=50 Zo=50
-5.2 S3091 TSDP/N
-5.2 LASER DRIVER
Figure S3091 LVDS Driver LVDS Input, Reference Only
+3.3
Bias Zo=50 Zo=50
+3.3
S3091 LVDS Output
Bias
LVDS Input
Figure LVDS Driver S3091 LVDS Input Direct Coupled Termination, Reference Only
+3.3 Zo=50
Bias
+3.3
Zo=50 Bias
LVDS Output
S3091 LVDS Input
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Revision February 2002
DEVICE SPECIFICATION
Figure LVDS Driver S3091 LVDS Input Coupled Termination, Reference Only
+3.3 Zo=50 0.1µF
Bias
+3.3
Zo=50 0.1µF Bias
LVDS Output
S3091 LVDS Input
Figure External Loop Filter
CAP1 CAP2
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Figure S3091 622.08 REFCLK Phase Noise Limit
Revision February 2002
DEVICE SPECIFICATION
Phase Noise (dBc)
622.08 Limit (100mUI jitter) 622.08 Limit (100mUI jitter) 82mUI Jitter 82mUI Jitter
-105 -115 -125 -135 -145
1,000 10,000 100,000 1,000,000 10,000,000 100,000,000
Freq (Hz)
Note: Using oscillator with phase noise spectrums shown above, will yield respective jitter generation numbers associated with each phase noise plot.
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Figure S3091 155.52 REFCLK Phase Noise Limit
Revision February 2002
DEVICE SPECIFICATION
Phase Noise (dBc)
155.52 Limit (100mUI jitter)
-100
155.52 Limit (100mUI jitter)
-120
-140
-160
1,000 10,000 100,000 1,000,000 10,000,000 100,000,000
Freq (Hz)
Note: Using oscillator with either phase noise spectrum shown above, will yield similar jitter generation integrated phase noise under each mask similar.
S3091 SONET/SDH/AOC-192 16:1 Transmitter
Ordering Information
Prefix Integrated Circuit Device 3091 Package CBGA
Revision February 2002
DEVICE SPECIFICATION
Revision
Prefix
XXXX
Device
Package
Revision
Applied Micro Circuits Corporation 6290 Sequence Dr., Diego, 92121 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITAB -SUPPO ICATIONS, DEVICES SYSTEMS THER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. Copyright 2002 Applied Micro Circuits Corporation. D526/R971

S3091 SONET/SDH/AOC-192 16:1 Transmitter Silicon Germanium B

Top Searches for this datasheet

Other recent searches