High Performance Audio Processor Data Sheet v0.5 2005/12/13

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High Performance Audio Processor Data Sheet v0.5 2005/12/13

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OxygenTMHD CMI8787
High Performance Audio Processor
Data Sheet v0.5
2005/12/13
C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
NOTICES
THIS DOCUMENT PROVIDED WITH WARRANTIES WHATSOEVER, INCLUDING WARRANTY MERCHANTABILITY, NONINFRINGEMENT, FITNESS PARTICULAR PURPOSE, WARRANTY OTHERWISE ARISING PROPOSAL, DOCUMENT SAMPLE. RIGHTS RESERVED. PART THIS DOCUMENT REPRODUCED TRANSMITTED FORM MEANS, ELECTRONIC MECHANICAL, INCLUDING INFORMATION STORAGE RETRIEVAL SYSTEMS, WITHOUT PERMISSION WRITING FROM C-MEDIA ELECTRONICS, INC.
Third-party brands names property their respective owners.
Copyright 2004-2005 C-Media Electronics Inc.
C-Media Electronics, Inc.
100, Sec. Civil Boulevard, Taipei, Taiwan 106, R.O.C. TEL: 886-2-8773-1100 http://www.cmedia.com.tw detailed product information, please contact sales@cmedia.com.tw FAX: 886-2-8773-2211
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Contents
Revision History. Features software description
Hardware Features General Description Application.
Block Diagram. Assignment
Pinout Diagram Description. Maximum Ratings. Recommended Operation Conditions Power consumption. Characteristics EEPROM Timing Characteristics. 4.5.1 SIGNAL TIMING. 4.5.2 CONTROL INTERFACE TIMING WIRE MODE. 4.5.3 CONTROL INTERFACE TIMING WIRE MODE. 4.5.4 EEPROM INTERFACE TIMING 4.5.5 EEPROM Timing Characteristics 4.5.6 AC-LINK TIMING CHARACTERISTICS Package Dimension.
Electrical Characteristics
Mechanical Specifications
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
List Figures
Figure Block Diagram OxygenT CMI8787 Figure Pinout Diagram OxygenT CMI8787
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Revision History
Date
2005/03/15 2005/12/13
Rev.
Preliminary vision
Release Note
Edit readability
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Features General Description
Hardware Features
interface with mastering burst modes Only 24.576MHz oscillator needed synchronous output data stream pairs within flexible output Programmable channel routing mechanism among output pairs synchronous input data stream pairs spread input DMA' (for Dolby pro-audio applications) Optionally, multi-channel link support AC97 codecs Programmable monitoring routing from inputs outputs pairs support 32-bit data transfer adjustable sample rate 192KHz) Integrated 192k/24-bit S/PDIF transmitter with dedicated S/PDIF Integrated 192k/24-bit S/PDIF receiver recording S/PDIF supports digital loopback path switching between optical connections 48k/16-bit front panel AC97 codec 2-wire master serial 4-wire (Serial Peripheral Interface) control codecs 2-wire slave serial communicate with microcontroller unit (MCU) Interrupt inform external retrieve data from system driver MPU-401 MIDI UART port EEPROM control interface phone jack detection pins Advanced device-sensing technology indicates whether speaker headphone plugged jack direct-access GPIO pins bonding-option bits identification possibilites 128-pin LQFP thin high-quality package
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
General Description
CMI8787 high quality 32-bit multi-channel audio processor that built into home audio electronics personal computers provide high fidelity sound playback processing. supports output channels input channels. output channels composed playback DMA' which multi-channel bits, channels, 192k), S/PDIF bits, channels, 192k), front panel bits, channels, 48k). input channels spread across recording DMA' bits, 192k) recording DMA' architecture recording unique point CMI8787 that enables very flexible recording options user. details recording mode selection will explained later sections. CMI8787 compatible with popular codecs, from codecs with over 120dB quality usual AC97 codecs. This ability gives customers flexibility design their products exactly they want them. AC-Link, 2-wire master bus, interfaces used transfer audio data control data between CMI8787 codecs. facilitate connection with existing home audio electronics, CMI8787 incorporated S/PDIF transmitter receiver with 192k sampling rate. EEPROM interface built CMI8787 connection with EEPROM store retrieve non-evaporable data customer applications, such board configuration, sub- vendor sub-system configuration, dynamic data that customers want restore next power-on. CMI8787 independent 2-wire slave communicate with micro control unit (MCU). This interface used medium system driver exchange data. applications 2-wire slave transmit control data from remote controller system driver. MPU-401 MIDI UART also integrated CMI8787. There phone jack detect pins CMI8787, which used distinguish cable plugged phone jack. GPIO pins chip, however some them shared with other functions. C-Media's unique device sensing technology implemented CMI8787, which indicate whether speaker headphone plugged jack. Then according this information, system driver decide turn C-Media' X-ear audio technology appropriate.
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Applications
Pro-sumer high-quality sound card retailer market Consume sound card powered Dolby® technologies PC-based media center Professional musician application High-end motherboard requiring audio quality Audio up-sell systems Bundle selling with high-profile cards General purpose multi- channel
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Block Diagram
Figure Block Diagram OxygenTMHD CMI8787
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Assignment
Pinout Diagram
Figure Pinout Diagram OxygenTMHD CMI8787
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Descriptions
following table gives descriptions OxygenT CMI8787. Some pins perform multiple functions, sake consistency, listed more than once table. abbreviations used description table explained below. digital input signal digital output signal DIO: digital bidirectional signal analog input pull- with resistor pull-down with resistor active signal Table description table OxygenTMHD CMI8787
Symbol
XRST XCLK33 XIDSEL XGNT#
Type Interface
Reset. clock, 33MHz.
Description
Initialization Device Select. This chip select during configuration access. Grant. When active, master granted CMI8787.
XREQ# XAD[31:0]
1-3, 7-11, 13-15, 28-31, 35-38, 40-44, 123-126,
Master Request. When active, CMI8787 requesting become master. Address Data
XCB#[3:0] XFRAME# XDEVSEL# XIRDY# XTRDY#
Command Byte Enable Cycle Frame. driven current master indicate beginning duration access Device Select. When active, indicates that driving device decoded address target current access. Initiator Ready. When active, indicates that initiator complete current data phase transaction. Target Ready. When active, indicates target device complete current data phase transaction.
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5 XSTOP# XPAR XINTA# Stop. When active, indicates that target requesting that master stop current transaction. Parity. even parity across XAD[31:0] XCB#[3:0]. Interrupt Request
MPU-401 MIDI UART Interface
XTXD DIO, MP-401 MIDI transmitter (output). also used XGPIO5~8 configuration (input, GPIO5~8, rising edge XRST. MPU401 MIDI receiver.
XRXD
Interface
XDAC_MCLK XDAC_LRCK XDAC_BCLK XDAC_SDOUT0 XDAC_SDOUT1 XDAC_SDOUT2 XDAC_SDOUT3 XADC1_MCLK XADC1_LRCK XADC1_BCLK XADC1_SDIN XAC97_SDI1/ XADC1_SDIN1 XADC2_MCLK XADC2_LRCK XADC2_BCLK XADC2_SDIN XGPIO5/ XADC3_MCLK XGPIO6/ XADC3_BCLK XGPIO7/ XADC3_LRCK XGPIO8/ XADC3_SDIN master clock output. Left/Right sample clock. clock. channel 0,channel serial data output. channel 2,channel serial data output. channel 4,channel serial data output. channel 6,channel serial data output. master clock output. Left/Right sample clock. clock.
serial data input. serial data input This shared with AC97 serial data input determined XSPI_DOUT/XA1 input configuration rising edge XRST. master clock output. Left/Right sample clock. clock.
serial data input. DIO, master clock output. This shared with XGPIO5, which determined XTXD input configuration rising edge XRST. DIO, clock. This shared with XGPIO6, which determined XTXD input configuration rising edge XRST. DIO, Left/Right sample clock. This shared with XGPIO7, which determined XTXD input configuration rising edge XRST. DIO, GPIO8, default input. This shared with XADC3_SDIN, which determined XTXD input configuration rising edge XRST.
AC-Link Interface
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5 XAC97_BCLK XAC97_SDI0 XAC97_SDI1/ XADC1_SDIN1 XAC97_SYNC XAC97_SDO0 XAC97_SDO1 XAC97_RST0 XAC97_RST1 XAC97_MCLK AC97 serial clock input8 AC97 serial data input AC97 serial data input This shared with XADC1_SDIN1, determined XSPI_DOUT/XA1 input configuration rising edge XRST. AC97 frame synchronization. AC97 serial data output AC97 serial data output AC97 codec reset AC97 codec reset AC97 master clock 24.5760M AC97 codec.
Serial Port Interface
XSPI_DIN/ XMSDA XSPI_CLK/ XMSCL XSPI_DOUT/ DIO, data input. This shared with 2-wire master serial data. DIO, clock output. This shared with 2-wire master serial clock. DIO, data output. This shared with 2-wire Codec address also used XAC97_SDI1 XADC1_SDIN1 configuration rising edge XRST (input, XAC97_SDI1, XADC1_SDIN1). DIO, chip enable, which select codec controlled. shared with Codec address also used XGPIO3~4 SSCL/SSDA configuration (input, GPIO3~4, SSCL/SSDA) rising edge XRST. DIO, chip enable, which select codec controlled (output). shared with codec configuration (input) rising edge XRST. DIO, chip enable, which select codec controlled (output). shared with codec configuration (input) rising edge XRST. DIO, chip enable, which select codec controlled (output). shared with codec configuration (input) rising edge XRST. chip enable, which select codec controlled. shared with EEPROM serial clock. chip enable, which select codec controlled. shared with EEPROM serial data out.
XSPI_CEN0/
XSPI_CEN1/ XCID0 XSPI_CEN2/ XCID1 XSPI_CEN3/ XCID2 XSPI_CEN4/ XEESK XSPI_CEN5/ XEEDO XMSDA/ XSPI_DIN XMSCL/ XSPI_CLK XA1/ XSPI_DOUT
2-Wire Master Serial
DIO, 2-wire serial data. This shared with data input. DIO, 2-wire serial clock. This shared with clock output. DIO, 2-wire serial codec address This shared with data output. also used XAC97_SDI1 XADC1_SDIN1 configuration rising edge XRST (input, XAC97_SDI1,
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5 XADC1_SDIN1). DIO, 2-wire serial codec address This shared with chip enable, which select codec controlled. also used XGPIO3~4 SSCL/SSDA configuration (input, GPIO3~4, SSCL/SSDA) rising edge XRST.
XA0/ XSPI_CEN0
2-Wire Slave Serial
XSSCL/ XGPIO3 XSSDA/ XGPIO4 XMCU_INT XSLAVE_RDY/ XGPIO1 DIO, 2-wire serial clock. This shared with XGPIO3. DIO, 2-wire serial data. This shared with XGPIO4. Interrupt output external Micro Control Unit (MCU).
DIO, 2-wire serial data ready. This shared with XGPIO1.
S/PDIF Interface
XSPDIFI XSPDIFO S/PDIF receiver. S/PDIF transmitter.
EEPROM Interface
XEECS DIO, EEPROM chip enable (output). also used power EEPROM delay configuration (input, delay, delay clock) rising edge XRST EEPROM serial clock. This shared with chip enable, which select codec controlled EEPROM serial data EEPROM serial data out. This shared with chip enable, which select codec controlled
XEESK/ XSPI_CEN4 XEEDI XEEDO/ XSPI_CEN5
Jack Detect Interface
XGPI0 XGPI1 XGPI2 XGPI3 XGPI4 XGPI5 JACK detection input JACK detection input JACK detection input JACK detection input JACK detection input JACK detection input
GPIO Interface
XGPIO0 XGPIO1/ XSLAVE_RDY XGPIO2 XGPIO3/XSSCL XGPIO4/XSSDA XGPIO5/ XADC3_MCLK DIO, GPIO0, default output Low. DIO, GPIO1, default output Low. This shared with Slave data ready. DIO, GPIO2, default input. DIO, GPIO3, default output Low. This shared with Slave serial clock. DIO, GPIO4, default input. This shared with Slave serial data DIO, GPIO5, default output Low. This shared with XADC3_MCLK, which determined XTXD input configuration
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5 rising edge XRST. DIO, GPIO6, default input. This shared with XADC3_BCLK, which determined XTXD input configuration rising edge XRST. DIO, GPIO7, default output Low. This shared with XADC3_LRCK, which determined XTXD input configuration rising edge XRST. DIO, GPIO8, default input. This shared with XADC3_SDIN, which determined XTXD input configuration rising edge XRST.
XGPIO6/ XADC3_BCLK XGPIO7/ XADC3_LRCK XGPIO8/ XADC3_SDIN
Headphone Sensing Interface
XHPD_E/ XTEST XHPD_IN XHPD_R1 XHPD_R2 DIO, Head phone detect enable. This shared with test mode selection rising edge XRST Head phone voltage input Head phone reference resistor Head phone reference resistor
Miscellaneous
XTAL1 XTAL2 XRSTO XPWDN DVDD 102, 24.576Mhz input output External Codec reset, programmed Active High with Register 0x50-bit Power Down output pin, Active Low, default High 3.3V power input
DGND
Ground
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Electrical Characteristics
Maximum Ratings
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o
Parameter Storge temperature Operating ambient temperature supply voltage voltage Power dissipation Symbol 0.15 Units
Recommended Operation Conditions
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o
Parameter Input voltage range Output voltage range Symbol VDD-0.3 VDD+0.3 Units
Power consumption
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o
Parameter Supply current power Supply current power down Symbol Units
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Characteristics
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o
Parameter Input voltage range Output voltage range High level input voltage level input voltage High level output voitage level output voltage Input leakage current Output leakage current Output buffer driver current SPDIF transmit output driver current
Symbol Vout
VDD-0.3 0.7VDD
VDD+0.3 0.3VDD
Units
Timing Characteristics
4.5.1 SIGNAL TIMING
SYSTEM CLOCK TIMING
System Clock Timing Diagram
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o C,fs=96KHz,MCLK=512fs,24 data,unless otherwise stated
System Clock Timing Parameters
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Parameter MCLK clock cycle time MCLK pulse width high MCLK pulse width high MCLK duty cycle Symbol tmclk tmclkh tmclkl Units
AUDIO INTERFACE TIMING
Audio Interface Timing Diagram
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o C,fs=96KHz,MCLK=512fs,24 data,unless otherwise stated
Audio Interface Timing Parameters Parameter LRCK propagation delay from BCLK falling edge SDOUT propagation delay from BCLK falling edge Symbol Units
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4.5.2 CONTROL INTERFACE TIMING WIRE MODE
Control Interface Timing Wire Diagram
Note: latch data XSPI_CEN clock mode XSPI_CEN clock high mode
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o C,SPI clock ns,unless otherwise stated
Control Interface Timing Wire Parameters Parameter XSPI_CLK rising edge XSPI_CEN rising edge XSPI_CLK pulse cycle time XSPI_CLK pulse width XSPI_CLK pulse width high XSPI_DOUT XSPI_CLK set-up time XSPI_DOUT XSPI_CLK hold time XSPI_CEN rising SCLK rising Tscy Tscl Tsch Tdsu Tdho Tcss Symbol Tscs Units
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4.5.3 CONTROL INTERFACE TIMING WIRE MODE
Control Interface Timing Wire Diagram
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o wire,Fast speed mode,unless otherwise stated
Control Interface Timing Wire Parameters Parameter XMSCL frequency XMSCL pulse width XMSCL pulse width high Hold time (start condition) Set-up time (start condition) Data set-up time XMSDI,XMSCL rise time XMSDI,XMSCL fall time Set-up time (stop condition) Data hold time Symbol Units
Note: test parameters wire,Fast speed mode
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4.5.4 EEPROM INTERFACE TIMING
EEPROM Interface Timing Diagram
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o C,unless otherwise stated
EEPROM Interface Timing Parameters Parameter XEESK clock frequency XEESK high time XEESK time XEECS setup time XEEDI setup time XEECS hold time XEEDI hold time Output delay Output delay XEECS status valid XEECS XEEDO high impedance Symbol tskh tskl tcss tdis tcsh tdih tpd1 tpd0 Units
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4.5.5 EEPROM Timing Characteristics
Symbol tskh tskl tcss tcsh tdis tdih tpd0 tpd1 Description Clock Frequency High Time Time Setup Time Hold Time Setup Time Hold Time Output Delay Output Delay Status Valid High Impedance Units
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4.5.6 AC-LINK TIMING CHARACTERISTICS
Test Conditions DVDD 3.3V, DGND =0V,TA=+25o ,unless otherwise stated
COLD RESET
Cold Reset Timing Diagram
Cold Reset Timing Parameters
Parameter XAC97_RST active pulse width XAC97_RST inactive XAC97_BCLK startup delay Symbol Trst_low Trst2clk Units
denotes active low.
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WARM RESET
Warm Reset Diagram
Warm Reset Parameters Parameter XAC97_SYNC active high pulse width XAC97_SYNC inactive XAC97_BCLK startup delay Symbol Tsync_high Tsync2clk Units
AC-LINK CLOCKS
BIT_CLK SYNC Timing Diagram
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
BIT_CLK SYNC Timing Parameters Parameter XAC97_BCLK frequency XAC97_BCLK period XAC97_BCLK output jitter XAC97_BCLK high pulsewidth (note XAC97_BCLK pulse width (note XAC97_SYNC frequency XAC97_SYNC period XAC97_SYNC high pulse width XAC97_SYNC low_pulse width Tsync_period Tsync_high Tsync_low Tclk_high Tclk_low Tclk_period Symbol 12.288 81.4 40.7 40.7 48.0 20.8 19.5 Units
Note: Worst case duty cycle restricted 45/55.
DATA SETUP HOLD
Data Setup Hold diagram
Data Setup Hold Parameters Parameter Setup falling edge Hold from falling edge XAC97_BCLK XAC97_BCLK Symbol Tsetup Thold Units
Note: Setup hold time parameters SDATA_IN with respect Controller.
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SIGNAL RISING FALLING TIMES
Signal Rising Falling Times Diagram
Signal Rising Falling time Parameters Parameter XAC97_BCLK rising time XAC97_BCLK falling time XAC97_SYNC rising time XAC97_SYNC falling time XAC97_SDI rising time XAC97_SDI falling time XAC97_SDO rising time XAC97_SDO falling time Symbol Triseclk Tfallclk Trisesync Tfallsync Trisedin Tfalldin Trisedout Tfalldout Units
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Mechanical Specification
Package Dimension
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C-Media High Performance Audi Processor OxygenHD CMI8787 Datasheet v0.5
Datasheet
C-Media Electronics, Inc.
100, Sec. Civil Boulevard, Taipei, Taiwan 106, R.O.C. TEL: 886-2-8773-1100 http://www.cmedia.com.tw detailed product information, please contact sales@cmedia.com.tw FAX: 886-2-8773-2211
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High Performance Audio Processor Data Sheet v0.5 2005/12/13

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