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SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST3


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Kbit Mbit Mbit Mbit (x8) Multi-Purpose Flash
SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
SST39LF/VF512 0403.0 2.7V 512Kb (x8) memories
FEATURES:
Organized 128K 256K 512K Single Voltage Read Write Operations 3.0-3.6V SST39LF512/010/020/040 2.7-3.6V SST39VF512/010/020/040 Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Sector-Erase Capability Uniform KByte sectors Fast Read Access Time: SST39LF512/010/020/040 SST39LF020/040 SST39VF512/010/020/040 Latched Address Data Fast Erase Byte-Program: Sector-Erase Time: (typical) Chip-Erase Time: (typical) Byte-Program Time: (typical) Chip Rewrite Time: second (typical) SST39LF/VF512 seconds (typical) SST39LF/VF010 seconds (typical) SST39LF/VF020 seconds (typical) SST39LF/VF040 Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 32-lead PLCC 32-lead TSOP (8mm 14mm) 48-ball TFBGA (6mm 8mm) Mbit
PRODUCT DESCRIPTION
SST39LF512/010/020/040 SST39VF512/010/ 020/040 128K 256K 5124K CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39LF512/ 010/020/040 devices write (Program Erase) with 3.03.6V power supply. SST39VF512/010/020/040 devices write with 2.7-3.6V power supply. devices conform JEDEC standard pinouts memories. Featuring high performance Byte-Program, SST39LF512/010/020/040 SST39VF512/010/020/ devices provide maximum Byte-Program time µsec. These devices Toggle Data# Polling indicate completion Program operation. protect against inadvertent write, they have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, they offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST39LF512/010/020/040 SST39VF512/010/ 020/040 devices suited applications that require convenient economical updating program, configuration, data memory. system applications, they
©2002 Silicon Storage Technology, Inc. S71150-03-000 2/02
significantly improves performance reliability, while lowering power consumption. They inherently less energy during Erase Program than alternative flash technologies. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. These devices also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet surface mount requirements, SST39LF512/ 010/020/040 SST39VF512/010/020/040 devices offered 32-lead PLCC 32-lead TSOP packages. 39LF/VF010 also offered 48-ball TFBGA package. Figures pinouts.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Multi-Purpose Flash trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Device Operation
Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
edge sixth pulse. internal Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during Sector-Erase operation will ignored.
Chip-Erase Operation
SST39LF512/010/020/040 SST39VF512/010/ 020/040 devices provide Chip-Erase operation, which allows user erase entire memory array `1's state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth CE#, whichever occurs first. During internal Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during ChipErase operation will ignored.
Read
Read operation SST39LF512/010/020/040 SST39VF512/010/020/040 device controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
Byte-Program Operation
SST39LF512/010/020/040 SST39VF512/010/ 020/040 programmed byte-by-byte basis. Before programming, sector where byte exists must fully erased. Program operation accomplished three steps. first step three-byte load sequence Software Data Protection. second step load byte address byte data. During Byte-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed, within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored.
Write Operation Status Detection
SST39LF512/010/020/040 SST39VF512/010/ 020/040 devices provide software means detect completion Write (Program Erase) cycle, order optimize system write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Sector-Erase Operation
Sector-Erase operation allows system erase device sector-by-sector basis. sector architecture based uniform sector size KByte. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. sector address latched falling edge sixth pulse, while command (30H) latched rising
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data# Polling (DQ7)
When SST39LF512/010/020/040 SST39VF512/ 010/020/040 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce "0". Once internal Erase operation completed, will produce "1". Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector- Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
Software Data Protection (SDP)
SST39LF512/010/020/040 SST39VF512/010/ 020/040 provide JEDEC approved Software Data Protection scheme data alteration operation, i.e., Program Erase. Program operation requires inclusion series three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. These devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device read mode, within TRC.
Product Identification
Product Identification mode identifies devices SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040 manufacturer SST. This mode accessed software operations. Users Software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Table software operation, Figure Software Entry Read timing diagram, Figure Software entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 0001H 0001H 0001H 0001H
T1.1
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector- ChipErase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart.
Data
Data Protection
SST39LF512/010/020/040 SST39VF512/010/ 020/040 provide both hardware software features protect nonvolatile data from inadvertent writes.
0000H
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Product Identification Mode Exit/Reset
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read operation. Please note that Software Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform, Figure flowchart.
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffers Latches Y-Decoder
B1.1
Control Logic
Buffers Data Latches
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
32-lead PLCC View
F02b.3
FIGURE ASSIGNMENTS 32-LEAD PLCC
©2002 Silicon Storage Technology, Inc. S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
Standard Pinout View
F01.0
FIGURE ASSIGNMENTS 32-LEAD TSOP (8MM
14MM)
VIEW (balls facing down) SST39LF/VF010 F01a.0.eps
FIGURE ASSIGNMENT 48-BALL TFBGA (6MM
8MM) MBIT
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet TABLE DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Name Address Inputs Data Input/output Functions provide memory addresses. During Sector-Erase AMS-A12 address lines will select sector. During Block-Erase AMS-A16 address lines will select block. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide power supply voltage: 3.0-3.6V SST39LF512/010/020/040 2.7-3.6V SST39VF512/010/020/040
Chip Enable Output Enable Write Enable Power Supply Ground Connection
Unconnected pins.
T2.1
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020, SST39LF/VF040
TABLE OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode Table
T3.4
DOUT High High DOUT High DOUT
Address Sector address, Chip-Erase
VIH, other value.
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Chip-Erase Software Entry4,5 Software Exit6 Software Exit6 Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data 2AAAH 5555H
T4.2
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH Data
Write Cycle Addr1 5555H 5555H 5555H 5555H Data
Write Cycle Addr1 5555H 5555H Data Data
Write Cycle Addr1 2AAAH 2AAAH Data
Write Cycle Addr1 SAX3 5555H Data
Address format A14-A0 (Hex), Address VIH, other value, Command sequence SST39LF/VF512. Addresses AMS-A15 VIH, other value, Command sequence. Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020, SST39LF/VF040 Program Byte address Sector-Erase; uses AMS-A12 address lines device does remain Software Product mode powered down. With AMS-A1 Manufacturer's BFH, read with SST39LF/VF512 Device D4H, read with SST39LF/VF010 Device D5H, read with SST39LF/VF020 Device D6H, read with SST39LF/VF040 Device D7H, read with Both Software Exit operations equivalent
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial
SST39LF512/010/020/040
3.0-3.6V
CONDITIONS
TEST
Ambient Temp +70°C
Input Rise/Fall Time Output Load SST39LF512/010/020/040 SST39VF512/010/020/040 Figures
OPERATING RANGE
Range Commercial Industrial
SST39VF512/010/020/040
2.7-3.6V 2.7-3.6V
Ambient Temp +70°C -40°C +85°C
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet TABLE OPERATING CHARACTERISTICS 3.0-3.6V SST39LF512/010/020/040
Limits Symbol Parameter Power Supply Current Read Write VIHC Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 Units Test Conditions Address input=VIL/VIH, f=1/TRC VDD=VDD CE#=OE#=VIL, WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T5.2
2.7-3.6V SST39VF512/010/020/040
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
Parameter Power-up Read Operation Power-up Program/Erase Operation
Minimum
Units
T6.1
TPU-WRITE1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O1
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T7.0
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T8.2
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 3.0-3.6V SST39LF512/010/020/040
SST39LF512-45 SST39LF010-45 SST39LF020-45 SST39LF040-45 Symbol Parameter TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output
Output Hold from Address Change
2.7-3.6V SST39VF512/010/020/040
SST39VF512-70 SST39VF010-70 SST39VF020-70 SST39VF040-70 SST39VF512-90 SST39VF010-90 SST39VF020-90 SST39VF040-90 Units
T9.2
SST39LF020-55 SST39LF040-55
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH TSCE
Parameter Byte-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Chip-Erase
Units
TIDA1
T10.1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
ADDRESS AMS-0
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
F03.0
DQ7-0
HIGH-Z
TCLZ
DATA VALID
Note:
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 Note: DATA BYTE (ADDR/DATA)
F04.0
2AAA
5555
ADDR
TWPH
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 Note: DATA BYTE (ADDR/DATA) TCPH 2AAA 5555 ADDR
F05.0
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TOEH TOES
Note:
F06.0
Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
ADDRESS AMS-0 TOEH TOES
READ CYCLES
Note:
WITH SAME OUTPUTS Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
F07.0
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
DQ7-0
F08.0
Note: This device also supports controlled Sector-Erase operation. signals interchageable long minmum timings met. (See Table Sector Address Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
SIX-BYTE CODE CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
DQ7-0
F17.0
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minmum timings met. (See Table Most significant address SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 SST39LF/VF040
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
TWPH DQ7-0 Device
F09.2
TIDA
Note: Device SST39LF/VF512, SST39LF/VF010, SST39LF/VF020, SST39LF/VF040.
FIGURE SOFTWARE ENTRY
READ
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
TIDA
F10.0
FIGURE SOFTWARE EXIT RESET
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F12.1
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
F11.1
FIGURE TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Start
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 5555H
Load Byte Address/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
F13.1
FIGURE BYTE-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Internal Timer Byte-Program/ Erase Initiated
Toggle Byte-Program/ Erase Initiated
Data# Polling Byte-Program/ Erase Initiated
Wait TBP, TSCE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match?
Program/Erase Completed
Program/Erase Completed
F14.0
FIGURE WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Software Entry Command Sequence
Software Exit Reset Command Sequence
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address:
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Wait TIDA
Load data: Address: 5555H
Load data: Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Read Software
Return normal operation
F15.2
FIGURE SOFTWARE COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Chip-Erase Command Sequence Load data: Address: 5555H
Sector-Erase Command Sequence Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address:
Wait TSCE
Wait
Chip erased
Sector erased
F16.1
FIGURE ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
PRODUCT ORDERING INFORMATION
Device SST39xFxxx Speed Suffix1 Suffix2 Package Modifier leads balls Package Type TFBGA (0.8mm pitch, 8mm) PLCC TSOP (type 14mm) Temperature Range Commercial +70°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Mbit Mbit Mbit Kbit Voltage 3.0-3.6V 2.7-3.6V
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Data Sheet Valid combinations SST39LF512 SST39LF512-45-4C-NH SST39LF512-45-4C-WH
Valid combinations SST39VF512 SST39VF512-70-4C-NH SST39VF512-90-4C-NH SST39VF512-70-4I-NH SST39VF512-90-4I-NH SST39VF512-70-4C-WH SST39VF512-90-4C-WH SST39VF512-70-4I-WH SST39VF512-90-4I-WH
Valid combinations SST39LF010 SST39LF010-45-4C-NH SST39LF010-45-4C-WH SST39LF010-45-4C-B3K
Valid combinations SST39VF010 SST39VF010-70-4C-NH SST39VF010-90-4C-NH SST39VF010-70-4I-NH SST39VF010-90-4I-NH SST39VF010-70-4C-WH SST39VF010-90-4C-WH SST39VF010-70-4I-WH SST39VF010-90-4I-WH SST39VF010-70-4C-B3K SST39VF010-90-4C-B3K SST39VF010-70-4I-B3K SST39VF010-90-4I-B3K
Valid combinations SST39LF020 SST39LF020-45-4C-NH SST39LF020-55-4C-NH SST39LF020-45-4C-WH SST39LF020-55-4C-WH
Valid combinations SST39VF020 SST39VF020-70-4C-NH SST39VF020-90-4C-NH SST39VF020-70-4I-NH SST39VF020-90-4I-NH SST39VF020-70-4C-WH SST39VF020-90-4C-WH SST39VF020-70-4I-WH SST39VF020-90-4I-WH
Valid combinations SST39LF040 SST39LF040-45-4C-NH SST39LF040-55-4C-NH SST39LF040-45-4C-WH SST39LF040-55-4C-WH
Valid combinations SST39VF040 SST39VF040-70-4C-NH SST39VF040-90-4C-NH SST39VF040-70-4I-NH SST39VF040-90-4I-NH
Note:
SST39VF040-70-4C-WH SST39VF040-90-4C-WH SST39VF040-70-4I-WH SST39VF040-90-4I-WH
Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
PACKAGING DIAGRAMS
VIEW
Optional Identifier .048 .042 .495 .485 .453 .447
SIDE VIEW
.112 .106 .020 MAX. .029 .023 .040 .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 .490
.050 .015 Min. .050 .095 .075 .140 .125 .032 .026
Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .008 inches. Coplanarity: mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
Identifier
1.05 0.95 0.50
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0.70 0.50 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads.
32-tsop-WH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
14MM
©2002 Silicon Storage Technology, Inc.
S71150-03-000 2/02
Kbit Mbit Mbit Mbit Multi-Purpose Flash SST39LF512 SST39LF010 SST39LF020 SST39LF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040
BOTTOM VIEW
8.00 0.20
VIEW
5.60 0.80 0.45 0.05 (48X)
0.80 CORNER 4.00 6.00 0.20
CORNER 1.10 0.10
SIDE VIEW
SEATING PLANE 0.35 0.05
0.12
48-tfbga-B3K-6x8-450mic-2
Note:
Complies with JEDEC Publication MO-210, variant 'AB-1', although some dimensions more stringent. linear dimensions millimeters. Coplanarity: 0.12 actual shape corners slightly different than portrayed drawing.
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71150-03-000 2/02

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