SST39VF320 SST39VF3202.7V 32Mb (x16) memory FEATURES: O
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Mbit (x16) Multi-Purpose Flash
SST39VF320
SST39VF3202.7V 32Mb (x16) memory
FEATURES:
Organized Single 2.7-3.6V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption (typical values MHz) Active Current: (typical) Standby Current: (typical) Auto Power Mode: (typical) Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Fast Read Access Time Latched Address Data Fast Erase Word-Program Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Word-Program Time: (typical) Chip Rewrite Time: seconds (typical) Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 48-lead TSOP (12mm 20mm) 48-ball TFBGA (6mm 8mm)
PRODUCT DESCRIPTION
SST39VF320 devices CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39VF320 write (Program Erase) with 2.7-3.6V power supply. Featuring high performance Word-Program, SST39VF320 devices provide typical Word-Program time µsec. devices Toggle Data# Polling indicate completion Program operation. protect against inadvertent write, these devices have on-chip hardware software data protection schemes. Designed, manufactured, tested wide spectrum applications, SST39VF320 offered with guaranteed typical endurance 100,000 cycles. Data retention rated greater than years. SST39VF320 devices suited applications that require convenient economical updating program, configuration, data memory. system applications, SST39VF320 significantly improve performance reliability, while lowering power consumption. SST39VF320 inherently less energy during Erase Program than alternative flash technologies. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current pro©2003 Silicon Storage Technology, Inc. S71143-02-000 11/03
gram shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. devices also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet high density, surface mount requirements, SST39VF320 offered 48-lead TSOP 48-ball TFBGA packages. Figures pinouts.
Device Operation
Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications SST39VF320 also have Auto Power mode which puts device near standby mode after data been accessed with valid Read operation. This reduces active read current from typically typically Auto Power mode reduces typical active read current range mA/MHz read cycle time. device exits Auto Power mode with address transition control signal transition used initiate another Read cycle, with access time penalty. Note that device does enter Auto Power mode after power-up with held steadily until first address transition driven high. based uniform block size KWord. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-ofErase operation determined using either Data# Polling Toggle methods. Figures timing waveforms. commands issued during Sectoror Block-Erase operation ignored.
Read
Read operation SST39VF320 controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
Chip-Erase Operation
SST39VF320 provide Chip-Erase operation, which allows user erase entire memory array state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored.
Word-Program Operation
SST39VF320 programmed word-by-word basis. Before programming, sector where word exists must fully erased. Program operation accomplished three steps. first step three-byte load sequence Software Data Protection. second step load word address word data. During Word-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Write Operation Status Detection
SST39VF320 provide software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Sector/Block-Erase Operation
Sector- Block-) Erase operation allows system erase device sector-by-sector block-byblock) basis. SST39VF320 offer both Sector-Erase Block-Erase modes. sector architecture based uniform sector size KWord. Block-Erase mode
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
Data# Polling (DQ7)
When SST39VF320 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector-, Block- Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. This group devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15-DQ8 VIH, other value, during command sequence.
Common Flash Memory Interface (CFI)
SST39VF320 also contain information describe characteristics device. order enter Query mode, system must load three-byte sequence, similar Software Entry command. last byte cycle this command loads (CFI Query command) address 5555H. Once device enters Query mode, system read data addresses given Tables through system must write Exit command return Read mode from Query mode.
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between When internal Program Erase operation completed, will stop toggling. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector-, Block- Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart.
Product Identification
Product Identification mode identifies devices SST39VF320 manufacturer SST. This mode accessed software operations. Users Software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Table software operation, Figure Software Entry Read timing diagram, Figure Software Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST39VF320 0001H 2783H
T1.1 1143
Data Protection
SST39VF320 provide both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Data 00BFH
0000H
Product Identification Mode Exit/ Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/
S71143-02-000 11/03
Software Data Protection (SDP)
SST39VF320 provide JEDEC approved Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent
©2003 Silicon Storage Technology, Inc.
Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform, Figure flowchart.
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer Latches Y-Decoder
DQ15
1143 B1.1
Control Logic
Buffers Data Latches
SST39VF320
SST39VF320 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
Standard Pinout View
SST39VF320
1143 48-tsop P01.10
FIGURE ASSIGNMENTS 48-LEAD TSOP
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
VIEW (balls facing down)
SST39VF320
DQ15
DQ14 DQ13 DQ12 DQ10 DQ11 1143 48-tfbga P02a.3
FIGURE ASSIGNMENTS 48-BALL TFBGA TABLE DESCRIPTION
Symbol A20-A0 DQ15-DQ0 Name Address Inputs Data Input/output Functions provide memory addresses. During Sector-Erase A20-A11 address lines will select sector. During Block-Erase A20-A15 address lines will select block. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide power supply voltage: Unconnected pins.
T2.2 1143
Chip Enable Output Enable Write Enable Power Supply Ground Connection
2.7-3.6V SST39VF320
TABLE OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode Table
T3.1 1143
DOUT High High DOUT High DOUT
Address Sector Block address, Chip-Erase
VIH, other value
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Software Software /CFI Exit Entry5,6 Exit7 Query Entry5 Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2 2AAAH 5555H
T4.4 1143
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data2
Write Cycle Addr1 5555H 5555H 5555H Data2 Data
Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 SAX4 BAX4 5555H Data2
Software Exit7 /CFI Exit
Address format A14-A0 (Hex), Addresses AMS-A15 VIH, other value, Command sequence Most significant address SST39VF320 DQ15 VIH, other value, Command sequence Program word address Sector-Erase; uses AMS-A11 address lines BAX, Block-Erase; uses AMS-A15 address lines device does remain Software Product Mode powered down. With AMS-A1 Manufacturer's 00BFH, read with SST39VF320 Device 2783H, read with Both Software Exit operations equivalent
TABLE QUERY IDENTIFICATION STRING1 SST39VF320
Address Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
T5.1 1143
Refer publication more details.
©2003 Silicon Storage Technology, Inc.
S71143-02-000
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Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications TABLE SYSTEM INTERFACE INFORMATION
Address Data 0027H 0036H 0000H 0000H 0003H 0000H 0004H 0005H 0001H 0000H 0001H 0001H Data (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Word-Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Word-Program times typical Maximum time buffer program times typical Maximum time individual Sector/Block-Erase times typical Maximum time Chip-Erase times typical
T6.3 1143
SST39VF320
TABLE DEVICE GEOMETRY INFORMATION
Address Data 0016H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0010H 0000H 003FH 0000H 0000H 0001H
SST39VF320
Data Device size Bytes (16H 4MByte) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number bytes multi-byte write (00H supported) Number Erase Sector/Block sizes supported device Sector Information Number sectors; 256B sector size) 1023 1024 sectors (03FFH 1023) Bytes KByte/sector (0010H Block Information Number blocks; 256B block size) blocks (0007H Bytes KByte/block (0100H 256)
T7.2 1143
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V 0.5V Transient Voltage (<20 Ground Potential -1.0V 1.0V Voltage Ground Potential -0.5V 12.6V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Industrial Ambient Temp +70°C -40°C +85°C
2.7-3.6V 2.7-3.6V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
Preliminary Specifications TABLE OPERATING CHARACTERISTICS 2.7-3.6V1
Limits Symbol Parameter Power Supply Current Read2 Program Erase IALP VIHC Standby Current Auto Power Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 Units Test Conditions Address input=VILT/VIHT, MHz, VDD=VDD CE#=VIL, OE#=WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD CE#=VILC, VDD=VDD Max, inputs=VSS VDD, WE#=VIHC VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T8.11 1143
Typical conditions Active Current shown front page data sheet average values 25°C (room temperature), 3.0V. 100% tested. current listed typically less than 2mA/MHz, with VIH. Typical 3.0V.
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
Parameter Power-up Read Operation Power-up Program/Erase Operation
Minimum
Units
T9.0 1143
TPU-WRITE1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O1
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T10.0 1143
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND1,2 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 10,000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T11.3 1143
This parameter measured only initial qualification after design process change that could affect this parameter. NEND endurance rating qualified 10,000 cycle minimum whole device. sector- block-level rating would result higher minimum specification.
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 2.7-3.6V
SST39VF320-70 Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change SST39VF320-90 Units
T12.1 1143
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH TSCE
Parameter Word-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Block-Erase Chip-Erase
Units
TIDA1
T13.2 1143
This parameter measured only initial qualification after design process change that could affect this parameter.
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
ADDRESS A20-0
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
DQ15-0
HIGH-Z
TCLZ
DATA VALID
1143 F03.1
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS A20-0 5555 DQ15-0 XXAA XX55 XXA0 DATA TWPH 2AAA 5555 ADDR
Note:
WORD (ADDR/DATA) VIH, other value
1143 F04.2
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
INTERNAL PROGRAM OPERATION STARTS ADDRESS A20-0 5555 DQ15-0 XXAA Note: XX55 XXA0 DATA WORD (ADDR/DATA) TCPH 2AAA 5555 ADDR
1143 F05.2
VIH, other value
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A20-0 TOEH TOES
DATA
DATA#
DATA#
DATA
1143 F06.1
FIGURE DATA# POLLING TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
ADDRESS A20-0 TOEH TOES
READ CYCLES WITH SAME OUTPUTS
1143 F07.1
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE CHIP-ERASE ADDRESS A20-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
1143 F08.2
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minimum timings met. (See Table VIH, other value
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
SIX-BYTE CODE BLOCK-ERASE ADDRESS A20-0 5555 2AAA 5555 5555 2AAA
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
1143 F17.2
Note: This device also supports controlled Block-Erase operation. signals interchageable long minimum timings met. (See Table Block Address VIH, other value
FIGURE CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS A20-0 5555 2AAA 5555 5555 2AAA
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
1143 F18.2
Note: This device also supports controlled Sector-Erase operation. signals interchageable long minimum timings met. (See Table Sector Address VIH, other value
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
TWPH DQ15-0 XXAA XX55 XX90 00BF Device
1143 F09.2
TIDA
Device 2783H SST39VF320 Note: VIH, other value
FIGURE SOFTWARE ENTRY
READ
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
TWPH DQ15-0 XXAA XX55 XX98
1143 F20.1
TIDA
Note: VIH, other value
FIGURE QUERY ENTRY
READ
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
XXAA
XX55
XXF0 TIDA
1143 F10.1
Note: VIH, other value
FIGURE SOFTWARE EXIT/CFI EXIT
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
1143 F11.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
1143 F12.0
FIGURE TEST LOAD EXAMPLE
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1143 F13.2
VIH, other value
FIGURE WORD-PROGRAM ALGORITHM
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1143 F14.0
FIGURE WAIT OPTIONS
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
Query Entry Command Sequence
Software Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXF0H Address:
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Wait TIDA
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
1143 F15.1
VIH, other value
FIGURE SOFTWARE ID/CFI COMMAND FLOWCHARTS
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
1143 F16.1
VIH, other value
FIGURE ERASE COMMAND SEQUENCE
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
PRODUCT ORDERING INFORMATION
Environmental Attribute non-Pb Package Modifier balls leads Package Type TFBGA (0.8mm pitch, 8mm) TSOP (type 12mm 20mm) Temperature Range Commercial +70°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Mbit Voltage 2.7-3.6V Product Series Multi-Purpose Flash
Valid combinations SST39VF320 SST39VF320-70-4C-EK SST39VF320-70-4C-EKE SST39VF320-90-4C-EK SST39VF320-90-4C-EKE SST39VF320-70-4I-EK SST39VF320-70-4I-EKE SST39VF320-90-4I-EK SST39VF320-90-4I-EKE SST39VF320-70-4C-B3K SST39VF320-70-4C-B3KE SST39VF320-90-4C-B3K SST39VF320-90-4C-B3KE SST39VF320-70-4I-B3K SST39VF320-70-4I-B3KE SST39VF320-90-4I-B3K SST39VF320-90-4I-B3KE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
PACKAGING DIAGRAMS
1.05 0.95 Identifier 0.50
12.20 11.80
0.27 0.17
18.50 18.30
0.15 0.05
DETAIL 1.20 max. 0.70 0.50 20.20 19.80 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads. 0.70 0.50
48-tsop-EK-8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM PACKAGE CODE:
20MM
©2003 Silicon Storage Technology, Inc.
S71143-02-000
11/03
Mbit Multi-Purpose Flash SST39VF320
VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
0.80 CORNER 4.00 6.00 0.20
SIDE VIEW
1.10 0.10
CORNER
SEATING PLANE 0.35 0.05
0.12
Note:
Complies with JEDEC Publication MO-210, variant 'AB-1', although some dimensions more stringent. linear dimensions millimeters. Coplanarity: 0.12 Ball opening size 0.38 0.05 48-tfbga-B3K-6x8-450mic-4
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) PACKAGE CODE:
TABLE REVISION HISTORY
Number Description Date 2003 2003 2003
Initial release Clarified Test Conditions Power Supply Current parameter Table page 2004 Data Book Updated package diagram Added non-Pb MPNs removed footnote. (See page
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2003 Silicon Storage Technology, Inc. S71143-02-000 11/03
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