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µPD98442 CELL/PACKET SERIAL TRANSCEIVER (8-LINE) DESCRIPTION


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INTEGRATED CIRCUIT
µPD98442
CELL/PACKET SERIAL TRANSCEIVER (8-LINE)
DESCRIPTION
µPD98442 backplane transceiver that serially transmits parallel data stream UTOPIA Level3/Level2 POS-PHY
Level3/Level2 interface full-duplex mode eight channels LVDS line. This device ideal
backboard connection cable connection between link device device network system. reliable backplane with star topology configured combining product with µPD98441 having channels LVDS line. µPD98442 consists eight channels LVDS drivers/receivers, PLL/clock data recovery (CDR) block, 8B/10B endec block, parallel interface block, realizing high-performance, power-saving single-chip solution. UTOPIA mode)/128 POS-PHY mode) logical ports connected parallel interface, that number components system board space reduced. These LVDS drivers/receivers have mode which some channels operates redundant auxiliary channel, that various connection configuration made.
device LVDS Line0 device device
µPD98441
(Master) UTOPIA-L2/POS-PHYL2
µPD98441
(Master)
Link device (Master)
µPD98442
(Slave)
µPD98441
UTOPIA-L2/POS-PHY-L2 UTOPIA-L3/POS-PHY-L3 LVDS Line7 (Master) UTOPIA-L2/POS-PHYL2
µPD98441
(Master) device device device
functions explained detail following User's Manual. sure read this User's Manual when designing your system.
µPD98442 User's Manual: S17098E
FEATURES
Parallel interface supporting packet Acell with optimum mode selectable UTOPIA/POS-PHY Level2 MAX.) UTOPIA/POS-PHY Level3 MAX.) 16-bit 32-bit ports connected UTOPIA mode combination extension signal port identifier. ports connected POS-PHY mode.
information this document subject change without notice. Before using this document, please confirm that this latest version.
products and/or types available every country. Please check with Electronics sales representative availability additional information.
Document S17097EJ2V0DS00 (2nd edition) Date Published September 2004 CP(N) Printed Japan
mark
shows major revised points.
2004
PD98442
Supported Interface Mode
Interface UTOPIA mode Level Level2 Level3 Width bits bits bits POS-PHY mode Level2 Level3 bits bits bits Frequency
Number Identifiable Logical Ports
Interface Access Mode Number Identifiable Logical Ports UTOPIA Level2 Standard access mode Extended access mode UTOPIA Level3 Standard access mode Extended access mode POS-PHY Level2 Standard access mode Extended access mode POS-PHY Level3 Standard access mode
Cell length selectable range bytes Eight channels standard LVDS driver/receiver interfaces Line rate channel: Mbps. Throughput data OC12 transferred. Redundant connection allowing four LVDS channels operate auxiliary channel supported On-chip 10-time multiplication PLL, clock data recovery circuit (CDR) Reference clock input LVTTL PECL level MHz) Back pressure transmission function prevent cell/packet loss. Flow control port units preventing influence throughput other ports Mode setting status check register access 8-bit interface types interfaces selectable RD-WR-RDY type DS-R/W-ACK type Support extended function interface Messages transmission enabled register µPD98442 between MPUs connected µPD98441s remote side Registers µPD98441 remote side read written. Employment encoder/decoder transmission mode 8B/10B Generation verification FCS16 cell/packet units Generation cell (option mode) Monitoring status receive data. Detection error reported register signal Error report LOS: Input signal loss detection FCS16 error detection 10B8B decode error detection
Data Sheet S17097EJ2V0DS
PD98442
Running disparity error detection Input/output FIFO overflow detection SOC, SOP, input error detection Logical port selection error detection Various event counters provided (such transmit/receive data error counters) Support types loop-back modes serial/parallel sides Loop-back settable port address Self-test function Transmission: Generation transmission test pattern (PRBS23) Reception: Test pattern verification circuit that reports error detection Power-down control enabled each LVDS channel IEEE 1149.1 JTAG test function Operating temperature range: power consumption Main power supply core logic/serial interface: +1.8 Power supply LVTTL I/O: +3.3 0.18-µm CMOS process 304-pin fine-pitch package pitch)
ORDERING INFORMATION
Part Number Package 304-pin plastic FBGA
PD98442F1-HN2-A
Data Sheet S17097EJ2V0DS
PD98442
SYSTEM
Router Aswitch Access concentration equipment (radio base station, DSLAM, etc.) Add/drop multiplexer, digital cross connector, etc.
µPD98441
Serial transmission UTOPIA/POS interface Inter-shelf transmission Inter-card transmission
µPD98442
Line card Control card Uplink card
Cell buffer Header memory
µPD98441
µPD98441
µPD98441
Aswitch
µPD98442
µPD98441
Controller
P30: µPD98404 (OC3 APHY) S20: µPD98405 (OC3 ASAR) X15: µPD98412 (1.5G ASwitch) Remark µPD98441 functionally compatible with µPD98442, which lines serial interfaces.
Data Sheet S17097EJ2V0DS
PD98442
BLOCK DIAGRAM
LVDS Line0_Rx Line1_Rx Line2_Rx Line3_Rx Line4_Rx Line5_Rx Line6_Rx Line2_Tx Line3_Tx Line4_Tx Line5_Tx Line6_Tx Line7_Tx REFCLK Line7_Rx Line0_Tx Line1_Tx
10:1 Selector
10:1 Selector
1:10 demux
1:10 demux
PRBS generator
generator
generator
Selector framer framer
framer
framer
Flow Data cont.
Flow Data cont.
Counter
Input FIFO
Receiver control FIFO
Output FIFO
parallel interface
parallel interface
bits UTOPIA Level2/Level3 POS-PHY Level2/Level3
bits
Register
generator
bits
Loop back pass
Data Sheet S17097EJ2V0DS
interface
Alarm
check
check
Error monitor
8B10B encoder
8B10B encoder
8B10B decoder
8B10B decoder
JTAG
PRBS check
PD98442
CONFIGURATION
IDATA[31:0] ISOC ICLAV IENB IPRTY IADDR[7:0] ISPA IEOP IERR IMOD[1:0] IPCK
TXLP0, TXLN0
RXLP0, RXLN0
TXLP1, TXLN1 RXLP1, RXLN1 TXLP2, TXLN2 RXLP2, RXLN2 TXLP3, TXLN3 RXLP3, RXLN3 TXLP4, TXLN4 RXLP4, RXLN4 TXLP5, TXLN5 RXLP5, RXLN5 TXLP6, TXLN6 RXLP6, RXLN6 TXLP7, TXLN7 RXLP7, RXLN7
Data
Serial line interface (40)
ODATA[31:0]
Data
Parallel interface (104)
OSOC OCLAV OENB OPRTY OADDR[7:0] OVAL OEOP OERR OMOD[1:0] OPCK
RFTCKTTL IREFVT IREFVR
µPD98442
RFCKPLT RFCKPLC TBFEN RFTCKTTL(Connect GND) RFRCKTTL(Connect GND)
Mode
IFM[1:0]
ALM[15:0] EXIN[7:0]
BUSM INTB DATA[7:0] ADDR[10:0]
Alarm& general ports (24)
interface (26)
DSB/RDB RWB/WRB ACKB/RDYB RESETB
JRSTB
VDD_33 VDD_18 VDT[2:0] VDR[6:0] VAT[1:0] VQT[3:0] VAR[1:0]
JTAG
PCKO (Pull-up VDD_33)
Supply (95)
(Connect GND)
Others (10)
TMC0(Connect GND) TMC1(Connect GND)
TST[3:0] (Connect GND)
TAFCLK (Connect GND)
GND_33 GND_18 GDT[2:0] GDR[6:0] GAT[1:0] GQT[3:0] GAR[1:0]
Remark Active-low pins expressed XXXB this document.
Data Sheet S17097EJ2V0DS
PD98442
CONNECTION (BOTTOM VIEW)
304-pin fine-pitch FBGA
µPD98442F1-HN2-A
Index mark
Data Sheet S17097EJ2V0DS
PD98442
ALLOCATION
(1/2)
Serial Address
IDATA14 IDATA13 IDATA8 IDATA4 GND_33 IDATA0 IADDR6 IADDR4 IADDR0 GND_18 IPRTY IFM0 GND_18 VDD_18 DATA2 DATA0 INTB ADDR10 ADDR6 ADDR2 RWB/WRB DSB/RDB VDD_18 TST1 GND_33 OADDR1 OADDR3
Serial
Address
RXLM3 GAR0 RXLP4 RXLP5 RXLM6 RXLM7 ALM15 ALM13 ALM11 ALM8 ALM5 ALM1 EXIN6 EXIN5 EXIN0 RFCKTTL TXLP0 TXLM0 TXLM1 TXLM2 TXLM3 GAT0 TXLP4 TXLP5 TXLM6 TXLM7 VDD_33 IDATA30 IDATA28 IDATA25 IDATA21 IDATA17 GND_33 GND_18 IDATA15 IDATA10 IDATA6 IDATA3 VDD_33 ISPA IADDR2 VDD_18 ISOC IMOD0 VDD_33 DATA6 DATA1 ACKB/RDYB
Serial
Address
VDD_33 ADDR8 ADDR4 GND_18 GND_33 TAFCLK JRSTB TST3 TST0 OENB
Serial
Address
TXLP2 TXLP3 RFTCKTTL TXLM4 TXLM5 TXLP6 TXLP7 IDATA31 IDATA29 IDATA27 IDATA23 IDATA19 GND_18 IDATA12 IDATA11 IDATA5 IDATA1 IADDR5 IENB IEOP IFM1 GND_18 DATA4 GND_33 ADDR5 ADDR1 ADDR0 VDD_18 TMC0 OADDR2 VDD_18 OPRTY OMOD1 ODATA3 VDD_33 ODATA13 ODATA16 ODATA20 VDD_18 GND_18 VDD_33 ODATA24 ODATA30 GDR0 VDR1
AA10 OADDR5 AA11 VDD_18 AA12 AA13 OMOD0 AA14 ODATA2 AA15 ODATA6 AA16 ODATA8 AA17 ODATA10 AA18 ODATA12 AA19 GND_18 AA20 ODATA17 AA21 GND_33 GND_18 ODATA21 ODATA25 ODATA29 VDD_33 RXLP1 RXLP2 RXLP3 RFRCKTTL RXLM4 RXLM5 RXLP6 RXLP7 ALM14 ALM12 ALM10 ALM7 ALM3 GND_18 VDD_18 EXIN7 EXIN2 RFCKPLT RESETB TXLP1
AB10 OADDR7 AB11 OVAL AB12 OEOP AB13 VDD_33 AB14 ODATA0 AB15 ODATA4 AB16 VDD_18 AB17 ODATA9 AB18 ODATA11 AB19 ODATA14 AB20 VDD_33 AB21 ODATA19 AA22 ODATA22 ODATA23 ODATA27 ODATA31 RXLP0 RXLM0 RXLM1 RXLM2
Data Sheet S17097EJ2V0DS
PD98442
(2/2)
Serial Address
VDR3 IREFVR GDR4 VDR5 VDD_18 ALM9 ALM4 ALM0 GND_33 VDD_18 EXIN4 EXIN3 RFCKPLC GQT0 VQT1 VDT1 IREFVT GQT2 VQT2 VDD_18 IDATA26 IDATA20 IDATA16 IPCK VDD_18 IDATA9 IDATA7 VDD_18 IADDR7
Serial
Address
IADDR1 GND_33 IMOD1 PCKO DATA5 ADDR9 ADDR3 GND_18 TST2 OADDR0 OADDR6 GND_18 OSOC OERR ODATA1 ODATA7 ODATA15 ODATA18 VDD_18 ODATA26 ODATA28 VDD_18 GDR1 VDR2 GDR3 GAR1
Serial
Address
VAR1 GDR5 VDR6 VDD_33 ALM2 VDD_33 EXIN1 TBFEN GND_18 GDT0 VDT0 GDT1 GAT1 VAT1 GDT2 VQT3 IDATA24 IDATA18 GND_33 IDATA2 ICLAV IADDR3 IERR BUSM DATA7 DATA3 ADDR7 VDD_18 TMC1
Serial
Address
VDD_33 OADDR4 OCLAV GND_33 ODATA5 GND_18 OPCK GND_33 GND_18 VDR0 GDR2 VAR0 VDR4 GDR6 GND_18 ALM6 GND_18 VDD_18 VQT0 GQT1 VAT0 VDT2 GQT3 GND_18 IDATA22
Data Sheet S17097EJ2V0DS
PD98442
NAME
ACKB/RDYB: ADDR[10:0] ALM[15:0] BUSM: CSB: DATA[7:0] DSB/RDB: EXIN[2:0] GAR[1:0] GAT[1:0] GDR[4:0] GDT[2:0] GND_18: GND_33: GQT[3:0] IADDR[7:0] ICLAV IDATA[31:0] IENB IEOP: IERR: IFM[1:0] IMOD: INTB: IPCK: IPRTY: IREFVR: IREFVT: ISOC: ISPA: ISX: JCK: JDI: JDO: JMS: JRSTB: TBFEN: Acknowledge Ready Address Alarm Mode Select Connect Ground Chip Select Data Data Strobe Read External Input Analog Ground Analog Ground Ground LVDS Block Ground LVDS Block Ground 1.8-V Supply Ground 3.3-V Supply Ground LVDS Buffer Input Parallel Address Input Parallel Cell Available Input Parallel Data Input Parallel Enable Input Parallel POS-PHY Packet Input Parallel POS-PHY Packet Error Interface Mode Input Parallel POS-PHY Word Modulo Interrupt Output Input Parallel Clock Input Parallel Parity Input Reference Voltage LVDS Input Reference Voltage LVDS Input Parallel Start Cell Input Parallel POS-PHY Data Valid Input Parallel POS-PHY Address Valid JTAG Clock JTAG Data Input JTAG Data Output JTAG Mode Select JTAG Reset Transmit LVDS Line Buffer Enable OADDR[7:0] OCLAV: ODATA[31:0] OENB OEOP: OERR: OMOD: OPCK: OPRTY: OSOC: OSX: OVAL: PCKO: RCVRLCK[1:0] RESETB: RFCKPLC: RFCKPLT: RFCKTTL: RFRCKTTL: RFTCKTTL: RWB/WRB: RXLM[7:0] RXLP[7:0] SMC: TAFCLK: TEN: TMC[1:0] TST[3:0] TXLM[7:0] TXLP[7:0] VAR[1:0] VAT[1:0] VDR[6:0] VDT[2:0] VDD_18: VDD_33: VQT[3:0] Output Parallel Address Output Parallel Cell Available Output Parallel Data Output Parallel Enable Output Parallel POS-PHY Packet Output Parallel POS-PHY Packet Error Output Parallel POS-PHY Word Modulo Output Parallel Clock Output Parallel Parity Output Parallel Start Cell Output Parallel POS-PHY Address Valid Output Parallel Data Valid Parallel Clock Recover Clock Line1/0 Reset Reference Clock Complement Reference Clock True LVTTL Reference Clock Input PECL True Reference Clock Input PECL Comp. Reference Clock Input Read Write Write Serial Line (Inverted) Line1/0 Serial Line (True) Line1/0 Test Mode Select Test Async Clock Test Enable Test Mode Test Select Serial Line (Inverted) Line1/0 Serial Line (True) Line1/0 1.8-V Analog Power Supply 1.8-V Analog Power Supply 1.8-V Power Supply LVDS Block 1.8-V Power Supply LVDS Block 1.8-V Power Supply 3.3-V Power Supply 1.8-V Power Supply LVDS Driver
Data Sheet S17097EJ2V0DS
PD98442
CONTENTS
FUNCTIONS.12
1.10 1.11 1.12 1.13 Parallel Interface Serial Interface Interface Alarm Output General-Purpose Input Port JTAG Boundary Scan.19 Power Supply Ground Others Connection Unused Pins.21 Default Status Parallel Interface Mode Function.23 Function Names Parallel Interface Pins Each Mode.24
ELECTRICAL SPECIFICATIONS.25
Absolute Maximum Ratings.25 Recommended Operating Conditions Characteristics (IVDD ±0.15 EVDD ±0.3 °C).26 Capacitance Characteristics (IVDD ±0.15 EVDD ±0.3 °C).27 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.5.8 2.5.9 test condition Reset.27 Reference clock Parallel interface interface Alarm output.43 General-purpose input port Others JTAG interface
CONNECTION POWER SUPPLY GROUND PINS SERIAL INTERFACE RESTRICTION
Illegal Data Driving After Register Write.48
PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS
Data Sheet S17097EJ2V0DS
PD98442
FUNCTIONS
Remarks Active-low pins expressed XXXB this document. Pins same name different numbers, such IFM1 IFM0 pins, collectively expressed IFM[1:0]. Expression IFM[1:0] means that IFM1 IFM0
Parallel Interface
(1/5)
Serial 165, Address Level LVTTL Function Parallel interface mode select signals These signals select mode parallel interface. input levels these pins changed after power turned sure execute reset (RESETB level). IFM[1:0] UTOPIA-Level2 mode POS-PHY-Level2 mode UTOPIA-Level3 mode POS-PHY-Level3 mode Mode
This interface transfers Acells/POS packets with link device device.
IFM[1:0]
IDATA[31:0]
152, 153, 154, 213, 267, 155, 304, 214, 156, 268, 215, 158, 159, 218, 219, 160, 270, 161,
LVTTL
Input interface data UTOPIA mode: TxData POS-PHY mode: TDAT This 32-bit data that accepts cell packet data from external devices. When UTOPIA/POS-PHY Level2 mode selected 16-bit operation, IDATA[15:0] used IDATA [31:16] disabled. IDATA31 most significant bit. Caution unused input pins level.
ISOC
LVTTL
Input interface cell/packet start position signal UTOPIA mode: TxSOC POS-PHY mode: TSOP This inputs signal that indicates start position cell/packet IDATA[31:0]. link device inputs high level synchronization with start byte cell/packet. Input interface packet transfer start signal POS-PHY mode: This inputs signal indicating that in-band address being transferred IDATA[31:0]. link device inputs logical port address IDATA[7:0] when asserted IENB deasserted. This signal used only POS-PHY Level3 mode. this used, level low.
LVTTL
Data Sheet S17097EJ2V0DS
PD98442
(2/5)
ICLAV Serial Address Level LVTTL Tri-state Function Input interface cell/packet available signal UTOPIA mode: TxClav POS-PHY mode: PTPA µPD98442 outputs vacant status input FIFO when polled from link device. When there free space, high level output. When there free space, level output. This functions tri-state UTOPIA/POS-PHY Level2 mode two-state Level3 mode. Input interface selection FIFO available signal POS-PHY mode: STPA µPD98442 outputs vacant state input FIFO selected logical port. When there specified number bytes free space, high level output. Otherwise, level output. This used only POS-PHY mode, functions tristate Level2 mode two-state Level3 mode. this used, level low. Input interface port address signals UTOPIA mode: TxAddr POS-PHY mode: TADDR These pins input selection address polling address port. POS-PHY-Level3 mode, these pins used only polling address. IADDR[4:0] used UTOPIA/POS-PHYLevel2 mode IADDR[7:0] used UTOPIA/POS-PHYLevel3 mode. IADDR[7:5] used, their levels low. Input interface enable signal UTOPIA mode: TxEnb POS-PHY mode: TENB This signal asserted when link device inputs valid data IDATA[31:0]. port address signals selected clock cycle before this signal asserted. IPRTY LVTTL Input interface parity signal UTOPIA mode: TxPrty POS-PHY mode: TPRTY This inputs parity signal IDATA[31:0] signals both UTOPIA POS-PHY modes. parity mode switched even parity mode making register settings. IEOP LVTTL Input interface packet position signal POS-PHY mode: TEOP This signal asserted when link device inputs last byte packet data. When IEOP asserted, IMOD indicates number valid bytes last word packet. This used only POS-PHY mode. this used, level low. Input interface packet error signal POS-PHY mode: TERR This inputs signal that indicates that packet currently being transferred error packet. This valid only when IEOP asserted. This used only POS-PHY mode. this used, level low.
ISPA
LVTTL Tri-state
IADDR[7:0]
221, 162, 272, 222,
LVTTL
IENB
LVTTL
IERR
LVTTL
Data Sheet S17097EJ2V0DS
PD98442
(3/5)
IMOD[1:0] Serial 225, Address Level LVTTL Function Input interface last word valid byte signals POS-PHY mode: TMOD These pins indicate number valid bytes transferred data. POS-PHY-Level2 mode, only IMOD[0] used. level unused IMOD[1] low. IMOD must always except when last word packet transferred. number valid packet bytes IDATA[31:0] follows when IEOP asserted. POS-PHY-Level2 IMOD Valid Bytes bytes IDATA[15:0] byte IDATA[15:8]
POS-PHY-Level3 IMOD[1:0] Valid Bytes bytes IDATA[31:0] bytes IDATA[31:8] bytes IDATA[31:15] byte IDATA[31:24]
These pins used only POS-PHY mode. these pins used, their levels low. IPCK LVTTL Input interface clock UTOPIA mode: TxClk POS-PHY mode: TFCLK This clock input input interfaces. This inputs clock UTOPIA/POS-PHY Level2 mode clock Level3 mode. operations input interface executed synchronization with this clock. ODATA[31:0] 190, 123, 245, 244, 122, 189, 121, 185, 242, 118, 184, 241, 183, 116, 115, 114, 240, 113, 284, 181, 112, 239, OSOC V22, T19, U21, T18, W22, U18, V21, U19, Y22, AA22, W21, W17, AB21, V17, AA20, W16, V16, AB19, W15, AA18, AB18, AA17, AB17, AA16, V15, AA15, U14, AB15, W13, AA14, V14, AB14 LVTTL Tri-state LVTTL Tri-state Output interface cell/packet data UTOPIA mode: RxData POS-PHY mode: RDAT This 32-bit data which µPD98442 outputs cell packet data. When UTOPIA/POS-PHY Level2 mode selected 16-bit operation, ODATA[15:0] used ODATA [31:16] disabled. ODATA31 most significant bit. This functions tri-state UTOPIA/POS-PHY Level2 mode two-state Level3 mode. Output interface cell/packet start position signal UTOPIA mode: RxSOC POS-PHY mode: RSOP µPD98442 outputs signal indicating start position cell packet data ODATA[31:0]. µPD98442 output high level sync with start byte cell packet data. This functions tri-state UTOPIA/POS-PHY Level2 mode two-state Level3 mode.
Data Sheet S17097EJ2V0DS
PD98442
(4/5)
Serial Address AA12 Level LVTTL Function Output interface packet transfer start signal POS-PHY mode: µPD98442 outputs signal indicating that in-band address being transferred ODATA[31:0]. This signal used only POS-PHY Level3 mode. OCLAV LVTTL Tri-state Output interface cell/packet available signal This tri-state signal their direction (input/output) changes depending mode setting. UTOPIA mode: RxClav POS-PHY mode: PRPA µPD98442 outputs available status cell packet data output FIFO when polled from link device. When there data transferred FIFO, high level output. When there data, level output. This functions tri-state UTOPIA/POS-PHY Level2 mode two-state Level3 mode. OADDR[7:0] 235, 108, 281, 177, AB10, V10, AA10, AB9, AB8, LVTTL Output interface port address signals UTOPIA mode: RxAddr POS-PHY mode: RADR These pins input polling address selection address port. OADDR[4:0] used UTOPIA/POS-PHY-Level2 mode OADDR[7:0] used UTOPIA Level3 mode. These address signals used POS-PHY-Level3 mode. pins used, their levels low. OENB LVTTL Output data enable signal UTOPIA mode: RxEnb POS-PHY mode: RENB link device inputs this signal µPD98442 enable signal data output. port address signals selected clock cycle before this signal asserted. OPRTY LVTTL Tri-state Output interface parity signal UTOPIA mode: RxPrty POS-PHY mode: RPRTY This outputs parity signal sync with data output
µPD98442 ODATA[31:0] both UTOPIA POS-PHY
modes. parity mode switched even parity mode making register settings. This functions tri-state UTOPIA/POS-PHY Level2 mode two-state Level3 mode. OVAL AB11 LVTTL Tri-state Output interface available/data valid signal POS-PHY mode: RVAL µPD98442 asserts this signal high level when outputs valid signals ODATA[31:0], OMOD[1:0], OSOC, OEOP, OERR. used only POS-PHY mode. functions tri-state POS-PHY Level2 mode twostate Level3 mode.
Data Sheet S17097EJ2V0DS
PD98442
(5/5)
OEOP Serial Address AB12 Level LVTTL Tri-state Function Output interface packet position signal POS-PHY mode: REOP µPD98442 asserts this signal when outputs last byte packet data. This signal that asserted while data being transferred. When OEOP asserted, OMOD indicates number valid bytes last word packet. used only POS-PHY mode. functions tri-state POS-PHY Level2 mode two-state Level3 mode. OERR LVTTL Tri-state Output interface packet position signal POS-PHY mode: RERR µPD98442 outputs signal indicate that packet currently being transferred error packet. assertion OERR valid only when OEOP asserted. used only POS-PHY mode. functions tri-state POS-PHY Level2 mode two-state Level3 mode. OPCK LVTTL Output interface clock UTOPIA mode: RxClk POS-PHY mode: RFCLK This clock input output interfaces. This inputs clock UTOPIA/POS-PHY Level2 mode clock Level3 mode. operations output interface executed synchronization with this clock. OMOD[1:0] 180, W12, AA13 LVTTL Tri-state Output interface last word valid byte signals POS-PHY mode: RMOD µPD98442 outputs number valid bytes transferring data. POS-PHY-Level2 mode, only OMOD[0] used. OMOD always outputs except when last word packet transferred. number valid packet bytes ODATA[31:0] follows when OEOP asserted. POS-PHY-Level2 OMOD Valid Bytes bytes ODATA[15:0] byte ODATA[15:8]
POS-PHY-Level3 OMOD[1:0] Valid Bytes bytes ODATA[31:0] bytes ODATA[31:8] bytes ODATA[31:15] byte ODATA[31:24]
These pins used only POS-PHY mode. These pins function tri-state pins UTOPIA/POS-PHY Level2 mode two-state pins Level3 mode.
Data Sheet S17097EJ2V0DS
PD98442
Serial Interface
serial interface LVDS interface that connected another µPD98441.
TXLP[7:0] Serial 151, 150, 146, 145, 144, 149, 148, 132, 131, 127, 126, 125, 130, 129, Address A10, A11, B13, B14, B15, B10, B11, A13, A14, A15, H21, J21, K22, L22, N21, P21, R21, H22, J22, K21, L21, N22, P22, R22, Level LVDS (True) LVDS (Inverted) LVDS (True) LVDS (Inverted) PECL reference clock input These pins input reference clock PECL level that generates transmission clock serial line. Input clock range these pins. Serial data output frequency that times frequency this clock (640 PECL MHz). input reference clock RFCKTTL pin, (Inverted) RFCKPLT high level, RFCKPLC level. This clock also used system clock internal logic. PECL (True) LVTTL LVTTL reference clock input serial line This inputs reference clock LVTTL level that generates transmission clock serial line. Input clock range this pin. Serial data output frequency that times frequency this clock (640 MHz). input reference clock RFCKPLT/RFCKPLC pin, this high level. This clock also used system clock internal logic. Transmission LVDS test input This used only test LSI. During normal operation, this high level. Reception LVDS test input This used only test LSI. During normal operation, this high level. LVDS transceiver reference potential Connect this analog power supply VAT[1:0] resistor. LVDS receiver reference potential Connect this analog power supply VAR[1:0] resistor. External enable signals LVDS transmission driver These pins forcibly disable 8-line transmission drivers. These signals ANDed with driver enable setting FTXEN register. Transmission driver enabled (normal operation). 8-line transmission LVDS drivers forcibly disabled (Hi-Z) regardless setting FTXEN register. Data input reception serial lines These pins input serial data. When these pins used, leave open. Function Data output transmission serial lines These pins output serial data. When these pins used, leave open.
TXLM[7:0]
RXLP[7:0]
RXLM[7:0]
RFCKPLT
RFCKPLC
RFCKTTL
RFTCKTTL
LVTTL LVTTL LVTTL
RFRCKTTL
IREFVT IREFVR TBFEN
Data Sheet S17097EJ2V0DS
PD98442
Interface
interface connects microprocessor that accesses registers µPD98442.
BUSM Serial Address Level LVTTL Function interface mode select signal input mode interface changed depending input level this pin. BUSM Selects <RDB, WRB, RDYB> mode. BUSM Selects <DSB, RWB, ACKB> mode. ADDR[10:0] 228, 277, 169, 229, 170, DATA[7:0] 275, 227, 167, 276, AA1, LVTTL Tri-state LVTTL LVTTL LVTTL Address input This address that inputs addresses internal registers µPD98442. 8-bit data This data that reads/writes data from/to internal registers µPD98442. Chip select signal input This enables access internal registers when level. Data strobe signal input read signal input This functions, RDB, which selected depending mode selected BUSM pin. BUSM Functions data strobe signal DSB. BUSM Functions that selects read access. RWB/WRB LVTTL Read/write signal input write signal input This functions, WRB, which selected depending mode selected BUSM pin. BUSM Functions read/write control signal RWB. High level: Read cycle level: Write cycle BUSM Functions that selects write access. ACKB/RDYB LVTTL Tri-state Data acknowledge signal output ready signal output This functions, ACKB RDYB, which selected depending mode selected BUSM pin. BUSM Functions ACKB. BUSM Functions RDYB. INTB LVTTL Open drain RESETB LVTTL Interrupt signal output This goes (active), internal interrupt source generated, report host. Externally pull this because open-drain pin. System reset signal input This system reset µPD98442. Input pulse duration periods more with longer period parallel clocks IPCK OPCK input µPD98442.
DSB/RDB
Caution Write access registers interface restricted. details, RESTRICTION.
Data Sheet S17097EJ2V0DS
PD98442
Alarm Output
ALM[15:0] Serial 133, 134, 135, 198, 136, 295, 199, 137, 255, Address G22, G21, F22, F21, E22, E21, H19, D22, D21, G17, C22, G19, C21, F18, B22, Level LVTTL Alarm output These pins output error (signal loss (LOS), 10B8B decode error, error) detection statuses reception serial lines setting internal registers. type information output changed using RALM0 RALM7 registers. output level controlled GOCG0 GOCG1 registers, that these pins also used general-purpose output ports. Function
General-Purpose Input Port
Serial 140, Address B19, A21, A20, Level LVTTL General-purpose input port This port inputs state signals external peripheral devices. levels signals input these pins reflected corresponding field internal EXINS register, changes that field used interrupt source. Function
EXIN[7:0]
203, 204, 141, D18, D17, B18, 257, E17,
JTAG Boundary Scan
Serial Address Level LVTTL LVTTL (Internal pull-up) Boundary scan clock input Ground this when used. Boundary scan data input Ground this when used. Function
Tri-state LVTTL
Boundary scan data output Open this when used. Boundary scan mode select signal input Ground this when used.
LVTTL (Internal pull-up)
JRSTB
LVTTL (Internal pull-up)
Boundary scan reset signal input Ground this when used.
Remark Processing JTAG boundary scan pins normal operation JTAG logic reset pulse input RESETB pin. µPD98442 perform normal operation when JTAG reset. perform normal operation, reset JTAG logic either following methods after power turned Ground JRSTB pin. Input low-level pulse (pulse width: clock cycle input more) JRSTB after power application (open pins ground pin).
Data Sheet S17097EJ2V0DS
PD98442
Power Supply
Serial Address Level Function
VDD_33 VDD_18
124, 182, 188, 254, 256, 109, 139, 172, 178, 186, 197, 202, 212, 217, 220, 243, 246, 278,
AB13, AB20, T21, W14, V19, G18, E18, AB5, AB16, AA11, B20, W10, W18, J19, D19, V18, R18, F10, D13, H18, K19, K17, N19, N18, P19, E10, K18, D10, D14,
3.3-V LVTTL power supply (+3.3 ±5%) 1.8-V logic block power supply (+1.8 ±5%)
VDT[2:0] VDR[6:0] VAT[1:0] VAR[1:0] VQT[3:0]
301, 208, 253, 196, 292, 193, 248, 192, 264, 251, 266, 211, 207,
1.8-V transmission LVDS block power supply (+1.8 ±5%) 1.8-V reception LVDS block power supply (+1.8 ±5%) 1.8-V transmission analog power supply (+1.8 ±5%) 1.8-V reception analog power supply (+1.8 ±5%) 1.8-V transmission LVDS driver power supply pins (+1.8 ±5%)
Ground
Serial Address Level Function
GND_33 GND_18
101, 119, 168, 201, 223, 269, 283, 100, 117, 120, 138, 157, 166, 187, 230, 236, 259, 285, 288, 294, 296,
AB7, AA3, AA21, E19, U13, AA2, AA19, Y21, B21, W19, V11, E15, U15, T17, H17, F17, E12, J17, J18, L19, M18, P17, P18, E11, L18, D11, F14,
3.3-V LVTTL ground 1.8-V logic block ground
GDT[2:0] GDR[6:0] GAT[1:0] GAR[1:0] GQT[3:0]
265, 262, 293, 252, 195, 249, 290, 247, 263, 250, 302, 210, 299,
Transmission LVDS block ground Reception LVDS receiver ground Transmission analog ground Reception analog ground Transmission LVDS driver ground
Remark connections power supply ground pins, CONNECTION POWER SUPPLY GROUND PINS SERIAL INTERFACE.
Data Sheet S17097EJ2V0DS
PD98442
Others
PCKO Serial Address Level LVTTL Function Clock monitoring pin. This outputs reference clock divided MHz). clock switched TxPLL clock (640 MHz) setting CKSEL CKOE register. addition, PCKOE register used stop output. These test pins. Ground these pins.
TAFCLK TST[3:0] TMC[1:0]
105, 233, 279,
AA7, AB6,
Pull
1.10 Connection Unused Pins
Some pins used depending mode. Connect unused pins shown below.
Input pins parallel interface Output pins parallel interface PCKO TXLP[7:0] TXLM[7:0] RXLP[7:0] RXLM[7:0] RFCKPLT RFCKPLC RFCKTTL RFRCKTTL RFTCKTTL TBFEN RESETB INTB ALM[15:0] EXIN[7:0] JRSTB Pull Pull Leave open Leave open Pull ground Remark JTAG Boundary Scan. Pull Ground Pull Pull ground Leave open Connection Unused Pins Pull ground Leave open Leave open Leave open
Remark pins parallel interface that used differ depending mode parallel interface. pins used each mode, 1.13 Function Names Parallel Interface Pins Each Mode.
Data Sheet S17097EJ2V0DS
PD98442
1.11 Default Status
Default status dependent upon mode parallel interface
ICLAV ISPA ODATA[15:0] ODATA[31:16] OPRTY OMOD[1:0] OSOC OEOP OERR OVAL OCLAV Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z UTOPIA Level2 During RESET After RESET Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z UTOPIA Level3 During RESET After RESET
ICLAV ISPA ODATA[15:0] ODATA[31:16] OPRTY OMOD[0] OMOD[1] OSOC OEOP OERR OVAL OCLAV Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
POS-PHY Level2 During RESET After RESET Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
POS-PHY Level3 During RESET After RESET
Default status other pins
TXLP[7:0] TXLM[7:0] DATA[7:0] ACKB/RDYB INTB(Pull ALM[15:0] PCKO During RESET Hi-Z Hi-Z Hi-Z Hi-Z After RESET Hi-Z Hi-Z Hi-Z Hi-Z
Outputs reference clock divided two.
Remark pins parallel interface that used vary with mode setting [1:0] pins. above default statuses indicate statuses output pins. pins used, 1.13 Function Names Parallel Interface Pins Each Mode.
Data Sheet S17097EJ2V0DS
PD98442
1.12 Parallel Interface Mode Function
UTOPIA mode Level2 mode
TxClk TxAddr[4:0] TxClav TxEnb TxData[15:0] TxSOC TxPrty
Level3 mode
TxClk TxAddr[7:0] TxClav TxEnb TxData[31:0] TxSOC TxPrty
IPCK IADDR[4:0] ICLAV[3:0] IENB[0] IDATA[15:0] ISOC IPRTY
IPCK IADDR[4:0] ICLAV[3:0] IENB[0] IDATA[15:0] ISOC IPRTY
Alink device (master)
RxClk RxAddr[4:0] RxClav RxEnb RxData[15:0] RxSOC RxPrty
µPD98442
(slave)
OPCK OADDR[4:0] OCLAV[3:0] OENB[0] ODATA[15:0] OSOC OPRTY
Alink device (master)
RxClk RxAddr[7:0] RxClav RxEnb RxData[31:0] RxSOC RxPrty
µPD98442
(slave)
OPCK OADDR[4:0] OCLAV[3:0] OENB[0] ODATA[15:0] OSOC OPRTY
POS-PHY Level2 mode Level2 mode
TFCLK TENB TADR[4:0] TDAT[15:0] TMOD TPRTY TSOP TEOP TERR STPA PTPA IPCK IENB IADDR[4:0] IDAT[15:0] IMOD[0] IPRTY ISOC IEOP IERR ISPA ICLAV
Level3 mode
TFCLK TENB TADR[7:0] TDAT[31:0] TMOD[1:0] TPRTY TSOP TEOP TERR STPA PTPA IPCK IENB IADDR[4:0] IDAT[31:0] IMOD[1:0] IPRTY ISOC IEOP IERR ISPA ICLAV
Link device (master)
RFCLK RENB RADR[4:0] RXDAT[15:0] RMOD RPRTY RVAL RSOP REOP RERR PRPA
µPD98442
(slave)
OPCK OENB OADDR[4:0] ODAT[15:0] OMOD[0] OPRTY OVAL OSOC OEOP OERR OCLAV
Link device (master)
RFCLK RENB RXDAT[31:0] RMOD[1:0] RPRTY RVAL RSOP REOP RERR
µPD98442
(slave)
OPCK OENB ODAT[15:0] OMOD[1:0] OPRTY OVAL OSOC OEOP OERR
Data Sheet S17097EJ2V0DS
PD98442
1.13 Function Names Parallel Interface Pins Each Mode
µPD98442
Number Pins IDATA[15:0] IDATA[31:16] IPRTY IMOD[0] IMOD[1] ISOC IEOP IERR IENB IADDR[4:0] IADDR[7:5] ICLAV ISPA IPCK ODATA[15:0] ODATA[31:16] OPRTY OMOD[0] OMOD[1] OSOC OENB OADDR[4:0] OADDR[7:5] OEOP OERR OVAL OCLAV OPCK TxData[15:0] used TxPrty used used TxSOC used used TxEnb TxAddr[4:0] used TxClav used used TxClk RxData[15:0] used RxPrty used used RxSOC RxEnb RxAddr[4:0] used used used used RxClav used RxClk TxData[7:0] TxData[31:16] TxPrty used used TxSOC used used TxEnb TxAddr[4:0] TxAddr[7:5] TxClav used used TxClk RxData[15:0] RxData[31:16] RxPrty used used RxSOC RxEnb RxAddr[4:0] RxAddr[7:5] used used used RxClav used RxClk TDAT[15:0] used TPRTY TMOD[0] used TSOP TEOP TERR TENB TADR[4:0] used PTPA used SPTA TFCLK RDAT[15:0] used RPRTY RMOD[0] used RSOP RENB RADR[4:0] used REOP RERR RVAL PRPA used RFCLK TDAT[15:0] TDAT[31:16] TPRTY TMOD[0] TMOD[1] TSOP TEOP TERR TENB TADR[4:0] TADR[7:5] PTPA SPTA TFCLK RDAT[15:0] RDAT[31:16] RPRTY RMOD[0] RMOD[1] RSOP RENB used used REOP RERR RVAL used RFCLK UTOPIA-Level2 Standard UTOPIA-Level3 POS-PHY-Level2 POS-PHY-Level3
Data Sheet S17097EJ2V0DS
PD98442
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Parameter Supply voltage Symbol IVDD EVDD Input/output voltage Output current Operating ambient temperature Storage temperature VI/VO Tstg Conditions Internal logic core buffer Rating -0.5 +2.5 -0.5 +4.6 -0.5 +4.6 +150 Unit
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damages, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Remark Apply input/output pins after supply voltage stabilized.
Recommended Operating Conditions
Parameter Symbol IVDD EVDD Conditions MIN. 1.65 LVTTL level LVDS level PECL level pin. requirements must same time. -0.5 TYP. MAX. 1.95 0.3EVDD 1700 2.15 Unit
Supply voltage
Low-level input voltage
VIL1 VIL2 VIL3
High-level input voltage
VIH1 VIH2 VIH3
LVTTL level LVDS level PECL level pin. requirements must same time.
0.5EVDD 1.85
EVDD 1800
LVDS differential input voltage LVDS differential input threshold PECL differential input voltage PECL input cross point Operating ambient temperature
VID1 VIDTH VID2
|VGPD| |VGPD|
-100 1.65
+100 2.35
Remark |VGPD|: Difference potential between driver receiver
Data Sheet S17097EJ2V0DS
PD98442
Characteristics (IVDD ±0.15 EVDD ±0.3
Parameter Supply current Symbol Conditions IVDD (1.8 type), During normal operation IVDD (3.3 type), During normal operation Input leakage current Off-state output current Low-level output voltage VOL1 VOL2 High-level output voltage VOH1 VOH2 Differential input impedance Differential output voltage Offset output voltage Output impedance (single) Output current |VOD| ISA, ISAB EVDD EVDD LVTTL level LVDS level LVTTL level LVDS level LVDS level LVDS level LVDS level LVDS level LVDS level Short-circuit driver GND. LVDS level Connect between differential outputs. 1025 1350 1535 EVDD MIN. TYP. MAX. 1200 Unit
Remarks current values this table indicate direction current. current that flows into device indicated current that flows indicated Each level shown under heading Conditions indicates following pins.
Level LVDS level PECL level LVTTL level TXLP[7:0], TXLM[7:0], RXLP[7:0], RXLM[7:0] RFCKPLT, RFCKPLC Signal pins other than above
Capacitance
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output capacitance Input capacitance Input/output capacitance
Data Sheet S17097EJ2V0DS
PD98442
Characteristics (IVDD ±0.15 EVDD ±0.3
2.5.1 test condition Definition delay time propagation delay time defined follows.
0.7IVDD Input 0.3IVDD 0.5IVDD
Output
0.5IVDD
test load circuit
D.U.T. (Device under test)
includes capacitance jig.
2.5.2 Reset
Parameter lock time
Note
Symbol tCLK tWLRST
Conditions
MIN.
TYP.
MAX.
Unit
RESETB assert time
Note
Notes
stabilize output, input reference clock more after power turned clocks input IPCK OPCK, input low-pulse width duration periods clock with longer period.
Power
tCLK
RFCKTTL
RESETB
tWLRST
Data Sheet S17097EJ2V0DS
PD98442
2.5.3 Reference clock
Parameter Reference clock frequency Frequency difference (referred input data) Reference clock jitter tHADRDB Symbol tREFCLK fDREFCLK Conditions RFCKTTL, RFCKPLT, RFCKPLC Difference between reference clock input serial data RFCKTTL, RFCKPLC, RFCKPLC -500 +500 MIN. TYP. MAX. Unit
tREFCLK tHREFCLK RFCKTTL (LVTTL input) tREFCLK tREFCLK/2 RFCKPLT/ RFCKPLC (PECL input) tREFCLK/2 tLREFCLK
Data Sheet S17097EJ2V0DS
PD98442
2.5.4 Parallel interface Summary UTOPIA Level2 (IFM[1:0] POS-PHY Level2 (IFM[1:0]
Parameter Hold time from IPCK/OPCK Setup time IPCK/OPCK Output delay time from IPCK/OPCK Active delay time from IPCK/OPCK Float delay time from IPCK/OPCK IPCK/OPCK period IPCK/OPCK high-level width Symbol tHPCK2 tSPCK2 tDPCK2 tAPCK2 tFPCK2 tIOPCK2 tHIOPCK2 IPCK/OPCK period: IPCK/OPCK period: IPCK/OPCK low-level width tLIOPCK2 IPCK/OPCK period: IPCK/OPCK period: Load capacitance: Load capacitance: Load capacitance: Conditions MIN. TYP. MAX. Unit
Summary UTOPIA Level3 (IFM[1:0] 10), POS-PHY Level3 (IFM[1:0]
Parameter Hold time from IPCK/OPCK Setup time IPCK/OPCK Output delay time from IPCK/OPCK IPCK/OPCK period IPCK/OPCK high-level width Symbol tHPCK3 tSPCK3 tDPCK2 tIOPCK3 tHIOPCK3 IPCK/OPCK period: 12.5 IPCK/OPCK period: IPCK/OPCK low-level width tLIOPCK3 IPCK/OPCK period: IPCK/OPCK period: Load capacitance: Conditions MIN. 12.5 TYP. MAX. Unit
tIOPCK2/3 tHIOPCK2/3 IPCK/OPCK tSPCK2/3 Input tDPCK2/3 Output tHPCK2/3 tLIOPCK2/3
tri-state tAPCK2 tDPCK2 tFPCK2
Data Sheet S17097EJ2V0DS
PD98442
UTOPIA Level2 mode (IFM[1:0] 00), input interface
Parameter IPCK ICLAV delay time IPCK ICLAV active time IPCK ICLAV float delay time IDATA[15:0] setup time IPCK IDATA[15:0] hold time from IPCK ISOC setup time IPCK ISOC hold time from IPCK IPRTY setup time IPCK IPRTY hold time from IPCK IADDR[4:0] setup time IPCK IADDR[4:0] hold time from IPCK IENB setup time IPCK IENB hold time from IPCK Symbol tDICAIPK2 tAICAIPK2 tFICAIPK2 tSIDAIPK2 tHIDAIPK2 tSISOIPK2 tHISOIPK2 tSIPRIPK2 tHIPRIPK2 tSIADIPK2 tHIADIPK2 tSIENIPK2 tHIENIPK2 Conditions Load capacitance: Load capacitance: Load capacitance: MIN. TYP. MAX. Unit
UTOPIA Level3 mode (IFM[1:0] 10), input interface
Parameter IPCK ICLAV delay time IDATA[31:0] setup time IPCK IDATA[31:0] hold time from IPCK ISOC setup time IPCK ISOC hold time from IPCK IPRTY setup time IPCK IPRTY hold time from IPCK IADDR[7:0] setup time IPCK IADDR[7:0] hold time from IPCK IENB setup time IPCK IENB hold time from IPCK Symbol tDICAIPK3 tSIDAIPK3 tHIDAIPK3 tSISOIPK3 tHISOIPK3 tSIPRIPK3 tHIPRIPK3 tSIADIPK3 tHIADIPK3 tSIENIPK3 tHIENIPK3 Conditions Load capacitance: MIN. TYP. MAX. Unit
Data Sheet S17097EJ2V0DS
PD98442
IPCK (Input) TxClk tSIADIPK2/3 IADDR (Input) TADD1[4:0] ICLAV (Output) IENB (Input) TxAddr tDICAIPK2/3 TxClav tAICAIPK2 TxEnb tSISOIPK2/3 ISOC (Input) TxSOC tSIDAIPK2/3 IDATA (Input) TxData tSIPREIPK2/3 IPRTY (Input) TxPrty tHIPRIPK2/3 tHIDAIPK2/3 tHISOIPK2/3 tSIENIPK2/3 tHIENIPK2/3 tDICAIPK2/3 tFICAIPK2 tHIADIPK2/3
Remark ICLAV functions tri-state signal Level2 mode, two-state signal Level3 mode. UTOPIA Level2 mode (IFM[1:0] 00), output interface
Parameter OPCK OCLAV active time OPCK OCLAV float delay time OPCK ODATA[15:0] delay time OPCK ODATA[15:0] active time OPCK ODATA[15:0] float delay time OPCK OSOC delay time OPCK OSOC active time OPCK OSOC float delay time OPCK OPRTY delay time OPCK OPRTY active time OPCK OPRTY float delay time OADDR[4:0] setup time OPCK OADDR[4:0] hold time from OPCK OENB setup time OPCK OENB hold time from OPCK Symbol tAOCAOPK2 tFOCAOPK2 tDODAOPK2 tAODAOPK2 tFODAOPK2 tDOSOOPK2 tAOSOOPK2 tFOSOOPK2 tDOPROPK2 tAOPROPK2 tFOPROPK2 tSOADOPK2 tHOADOPK2 tSOENOPK2 tHOENOPK2 Conditions Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: MIN. TYP. MAX. Unit
Data Sheet S17097EJ2V0DS
PD98442
UTOPIA Level3 mode (IFM[1:0] 10), output interface
Parameter OPCK OCLAV delay time OPCK ODATA[31:0] delay time OPCK OSOC delay time OPCK OPRTY delay time OADDR[7:0] setup time OPCK OADDR[7:0] hold time from OPCK OENB setup time OPCK OENB hold time from OPCK Symbol tDOCAOPK3 tDODAOPK3 tDOSOOPK3 tDOPROPK3 tSOADOPK3 tHOADOPK3 tSOENOPK3 tHOENOPK3 Conditions Load capacitance: Load capacitance: Load capacitance: Load capacitance: MIN. TYP. MAX. Unit
OPCK (Input)
RxClk tSOADOPK2/3 tHOADOPK2/3
OADDR (Input) TADD1[4:0] OCLAV (Output)
RxAddr
RxClav tDOCAOPK3 tDOCAOPK3 tFOCAOPK2 tSOENOPK2/3 tHOENOPK2/3 tAOCAOPK2
OENB (Input)
RxEnb
OSOC (Output)
RxSOC tFOSOOPK2 tAOSOOPK2 tAODAOPK2 tDOSOOPK2/3 tDODAOPK2/3
ODATA (Output)
RxData tFODAOPK2
OPRTY (Output)
RxPrty tFOPROPK2 tAOPROPK2 tDOPROPK2/3
Remark OCLAV, OSOC, ODATA, OPRTY function tri-state signals Level2 mode, two-state signals Level3 mode.
Data Sheet S17097EJ2V0DS
PD98442
POS-PHY Level2 mode (IFM[1:0] 01), input interface
Parameter IADDR[4:0] setup time IPCK IADDR[4:0] hold time from IPCK IENB setup time IPCK IENB hold time from IPCK ISOC setup time IPCK ISOC hold time from IPCK IEOP setup time IPCK IEOP hold time from IPCK IMOD[0] setup time IPCK IMOD[0] hold time from IPCK IERR setup time IPCK IERR hold time from IPCK IDATA[15:0] setup time IPCK IDATA[15:0] hold time from IPCK IPRTY setup time IPCK IPRTY hold time from IPCK IPCK ICLAV active time IPCK ICLAV float delay time IPCK ISPA active time IPCK ISPA float delay time Symbol tSIADIPK2 tHIADIPK2 tSIENIPK2 tHIENIPK2 tSISOIPK2 tHISOIPK2 tSIEOIPK2 tHIEOIPK2 tSIMOIPK2 tHIMOIPK2 tSIERIPK2 tHIERIPK2 tSIDAIPK2 tHIDAIPK2 tSIPRIPK2 tHIPRIPK2 tAICAIPK2 tFICAIPK2 tAISPIPK2 tFISPIPK2 Load capacitance: Load capacitance: Load capacitance: Load capacitance: Conditions MIN. TYP. MAX. Unit
Data Sheet S17097EJ2V0DS
PD98442
POS-PHY Level3 mode (IFM[1:0] 11), input interface
Parameter IADDR[7:0] setup time IPCK IADDR[7:0] hold time from IPCK IENB setup time IPCK IENB hold time from IPCK ISOC setup time IPCK ISOC hold time from IPCK IEOP setup time IPCK IEOP hold time from IPCK IMOD[1:0] setup time IPCK IMOD[1:0] hold time from IPCK IERR setup time IPCK IERR hold time from IPCK IDATA[31:0] setup time IPCK IDATA[31:0] hold time from IPCK IPRTY setup time IPCK IPRTY hold time from IPCK IPCK ICLAV delay time IPCK ISPA delay time setup time IPCK hold time from IPCK Symbol tSIADIPK3 tHIADIPK3 tSIENIPK3 tHIENIPK3 tSISOIPK3 tHISOIPK3 tSIEOIPK3 tHIEOIPK3 tSIMOIPK3 tHIMOIPK3 tSIERIPK3 tHIERIPK3 tSIDAIPK3 tHIDAIPK3 tSIPRIPK3 tHIPRIPK3 tDICAIPK3 tDISPIPK3 tSISXIPK3 tHISXIPK3 Load capacitance: Load capacitance: Conditions MIN. TYP. MAX. Unit
Data Sheet S17097EJ2V0DS
PD98442
IPCK (Input) TFCLK tSIADIPK2/3 IADDR (Input) TADR tHIADIPK2/3 tAISPIPK2 ISPA (Output) STPA tDICAIPK3 ICLAV (Output) PTPA tSIENIPK2/3 IENB[0] (Input) TENB tSISOIPK2/3 ISOC (Input) TSOP IEOP (Input) TEOP tHISOIPK2/3 tHIENIPK2/3 tAICAIPK2 tFICAIPK2 tFISPIPK2
tDISPIPK3
tSIEOIPK2/3
tHIEOIPK2/3
tSIMOIPK2/3
tHIMOIPK2/3
IMOD (Input) TMOD
tSIERIPK2/3
tHIERIPK2/3
IERR (Input) TERR tSISXIPK2/3 (Input) tSIDAIPK2/3 IDATA (Input) TDAT] tSIPRIPK2/3 IPRTY (Input) TPRTY tHIPRIPK2/3 tHIDAIPK2/3 tHISXIPK2/3
Remark ISPA ICLAV function tri-state signals Level2 mode, two-state signals Level3 mode.
Data Sheet S17097EJ2V0DS
PD98442
POS-PHY Level2 mode (IFM[1:0] 01), output interface
Parameter OENB setup time OPCK OENB hold time from OPCK OADDR[4:0] setup time OPCK OADDR[4:0] hold time from OPCK OPCK ODATA[15:0] delay time OPCK ODATA[15:0] active time OPCK ODATA[15:0] float delay time OPCK OPRTY delay time OPCK OPRTY active time OPCK OPRTY float delay time OPCK OSOC delay time OPCK OSOC active time OPCK OSOC float delay time OPCK OMOD delay time OPCK OMOD active time OPCK OMOD float delay time OPCK OEOP delay time OPCK OEOP active time OPCK OEOP float delay time OPCK OERR delay time OPCK OERR active time OPCK OERR float delay time OPCK OVAL delay time OPCK OVAL active time OPCK OVAL float delay time OPCK OCLAV delay time OPCK OCLAV active time OPCK OCLAV float delay time tDOPROPK2 tAOPROPK2 tFOPROPK2 tDOSOOPK2 tAOSOOPK2 tFOSOOPK2 tDOMOOPK2 tAOMOOPK2 tFOMOOPK2 tDOEOOPK2 tAOEOOPK2 tFOEOOPK2 tDOEROPK2 tAOEROPK2 tFOEROPK2 tDOVAOPK2 tAOVAOPK2 tFOVAOPK2 tDOCAOPK2 tAOCAOPK2 tFOCAOPK2 Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Symbol tSOENOPK2 tHOENOPK2 tSOADOPK2 tHOADOPK2 tDODAOPK2 tAODAOPK2 tFODAOPK2 Load capacitance: Load capacitance: Load capacitance: Conditions MIN. TYP. MAX. Unit
Data Sheet S17097EJ2V0DS
PD98442
POS-PHY Level3 mode (IFM[1:0] 11), output interface
Parameter OENB setup time OPCK OENB hold time from OPCK OPCK ODATA[31:0] delay time OPCK OPRTY delay time OPCK OSOC delay time OPCK OMOD delay time OPCK OEOP delay time OPCK OERR delay time OPCK OVAL delay time OPCK OCLAV delay time OPCK delay time Symbol tSOENOPK3 tHOENOPK3 tDODAOPK3 tDOPROPK3 tDOSOOPK3 tDOMOOPK3 tDOEOOPK3 tDOEROPK3 tDOVAOPK3 tDOCAOPK3 tDOSXOPK3 Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Conditions MIN. TYP. MAX. Unit
Data Sheet S17097EJ2V0DS
PD98442
OPCK (Input) RFCLK tSOADOPK2/3 OADDR (Input) RADR tAOVAOPK2 OVAL (Output) RVAL tDOCAOPK2/3 tAOCAOPK2 tFOCAOPK2 tHOADOPK2/3 tFOVAOPK2 tDOVAOPK2/3
OCLAV (Output) PRPA
tSOENOPK2/3 tHOENOPK2/3 OENB (Input) RENB tDOSXOPK (Output) tDOSOOPK2/3 tAOSOOPK2 OSOC (Output) RSOP tAOEOOPK2 OEOP (Output) REOP tAOMOOPK2 OMOD (Output) RMOD tAOEROPK2 OERR (Output) RERR tAODAOPK2 ODATA (Output) RDAT tAOPROPK2 OPRTY (Output) RPRTY tDOPROPK2/3 tFOPROPK2 tDODAOPK2/3 tFODAOPK2 tFOMOOPK2 tDOMOOPK tFOEOOPK2 tDOEOOPK tFOSOOPK2
tFOEROPK2
tDOEROPK
Remark OVAL, OCLAV, OSOC, OEOP, OMOD, OERR, ODATA, OPRTY function tri-state signals Level2 mode, two-state signals Level3 mode.
Data Sheet S17097EJ2V0DS
PD98442
2.5.5 interface Read cycle timing
Parameter ADDR setup time DSB[RDB] ADDR hold time from DSB[RDB] setup time DSB[RDB] hold time from DSB[RDB] RWB[WRB] setup time DSB[RDB] RWB[WRB] hold time from DSB[RDB] DSB[RDB] ACKB[RDYB] output delay time DSB[RDB] ACKB[RDYB] active time DSB[RDB] ACKB[RDYB] float time DSB[RDB] DATA output delay time tDRDYRDB tFRDYRDB tVDTRDB Load capacitance: Load capacitance: tREFCLK ACKB[RDYB] valid DATA output time DATA float time from DSB[RDB] DSB[RDB] DSB[RDB] minimum interval tFDTRDB tDSINT tREFCLK tDDTRDB Symbol tSADRDB tHADRDB tSCSRDB tHCSRDB tSWRRDB tHWRRDB tVRDYRDB Load capacitance: Conditions MIN. TYP. MAX. Unit
Note
tREFCLK
Note MAX. value tDRDYRDB varies depending whether extended access function used (depending L[n]CMDRJ register value). When used (both L0CMDRJ L1CMDRJ 1Fh): tDRDYRDB (MAX.) tREFCLK tIOPCK tDRDYRDB (MAX.) tREFCLK tIOPCK Remarks Before deasserting DSB[RDB] that been asserted once, detect that ACKB[RDYB] been asserted. tREFCLK duration cycle (1/fREFCLK) reference clock. When used least either L0CMDRJ L1CMDRJ other than 1Fh):
Data Sheet S17097EJ2V0DS
PD98442
BUSM mode
ADDR[10:0] (Input) tSCSRDB (Input) tSWRRDB RWB/WRB (Input) tDSINT DSB/RDB (Input) tVRDYRDB tDRDYRDB tVDTRDV DATA[7:0] (Output) Hi-Z Invalid tDDTRDB tFDTRDB Hi-Z tHWRRDB tHCSRDB tSADRDB tHADRDB
ACKB/RDYB (Output)
Hi-Z
tFRDYRDB
Hi-Z
BUSM mode
tSADRDB ADDR[10:0] (Input) tSCSRDB (Input) tSWRRDB RWB/WRB (Input) tDSINT DSB/RDB (Input) tVRDYRDB ACKB/RDYB (Output) Hi-Z tARDYRDB tVDTRDB DATA[7:0] (Output) Hi-Z tDDTRDB tFDTRDB Hi-Z tFRDYRDB Hi-Z tHWRRDB tHCSRDB tHADRDB
Invalid
Data Sheet S17097EJ2V0DS
PD98442
Write cycle timing
Parameter ADDR setup time DSB[RDB] ADDR hold time from DSB[RDB] setup time DSB[RDB] hold time from DSB[RDB] RWB[RDB] setup time DSB[WRB] RWB[RDB] hold time from DSB[WRB] DSB[WRB] low-pulse width DSB[WRB] ACKB [RDYB] output delay time DSB[WRB] ACKB [RDYB] active time DSB[RDB] ACKB[RDYB] float time DATA setup time DSB[WRB] DATA hold time from DSB[WRB] Symbol tSADWR tHADWR tSCSWR tHCSWR tSRDWR tHRDWR tWLWR tVRDYWR tDRDYWR tFRDYWR tSDAWR tHDAWR Conditions Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Load capacitance: Note Note MIN. tREFCLK tIOPCK Note TYP. MAX. Unit
DSB[WRB] DSB[WRB] minimum tDSINT interval
Notes
MAX. value tDRDYWR varies depending whether extended access function used (depending L[n]CMDRJ register value). When used (both L0CMDRJ L1CMDRJ 1Fh): tDRDYWR (MAX.) tREFCLK tIOPCK When used least either L0CMDRJ L1CMDRJ other than 1Fh): tDRDYWR (MAX.) tREFCLK tIOPCK
restriction write access PD98442, RESTRICTION.
Remarks Before deasserting DSB[WRB] that been asserted once, detect that ACKB[RDYB] been asserted. tREFCLK duration cycle (1/fREFCLK) reference clock.
Data Sheet S17097EJ2V0DS
PD98442
BUSM mode
tSADWR ADDR[10:0] (Input) tSCSWR (Input) tSRDWR RWB/WRB (Input) tWLWR tDRDYWR DSB/RDB (Input) tVRDYWR ACKB/RDYB (Output) Hi-Z tFRDYWR Hi-Z tDSINT tHRDWR tHCSWR tHADWR
tSDAWR DATA[7:0] (Input)
tHDAWR
BUMS mode
tSADWR ADDR[10:0] (Input) tSCSWR (Input) tWLWR RWB/WRB (Input) tSRDWR DSB/RDB (Input) tDRDYWR tVRDYWR ACKB/RDYB (Output) Hi-Z tFRDYRDB Hi-Z tHRDWR tDSINT tHCSWR tHADWR
tSDAWR DATA[7:0] (Input)
tHDAWR
Data Sheet S17097EJ2V0DS
PD98442
2.5.6 Alarm output
Parameter ALM[15:0] output high-pulse width Symbol tWPALM Conditions Reference clock frequency: MHz, load capacitance: Reference clock frequency: MHz, load capacitance: ALM[15:0] output recovery clock (RCVRLCK[n]) period tRCVCK Reference clock frequency: Reference clock frequency: MIN. TYP. MAX. Unit
Remarks recovery clock (RCVRLCK[n]) output from setting RALM[n] register. outputs recovery clock serial line divided synchronization clock ALM[15:0] output signal changes depending type output alarm RALM[n] register. output pulse shortest when decode error set. period recovery clock RCVRLCK[n] corresponding serial line output.
tRCVCK RCVRCLK[n] (Output) tWPALM ALM[3:0] (Output)
2.5.7 General-purpose input port
Parameter Reference clock frequency EXIN input high-pulse width Symbol fREFCLK tWPEXIN Conditions RFCKTTL, RFCKPLT, RFCKPLC Load capacitance: MIN. tREFCLK TYP. MAX. Unit
Remark µPD98442 samples EXIN[2:0] input with reference clock.
RFCKTTL, RFCKPLT, RFCKPLC EXIN[2:0] (Input)
tWPEXIN
Data Sheet S17097EJ2V0DS
PD98442
2.5.8 Others
Parameter PCKO period Symbol tPCKO Conditions When CKSEL When CKSEL MIN. TYP. MAX. Unit
Remark PCKO clock output changes reference clock clock generated transmission depending value CKSEL CKOE register. output also stopped PCKOE register.
tPCKO
PCKO (Output)
2.5.9 JTAG interface
Parameter cycle high-level width low-level width Symbol tCYJK tWHJK tWLJK Load capacitance: Load capacitance: Conditions MIN. tCYJK TYP. MAX. Unit
JDO/ouput output delay time tDDOJK JDO/ouput float output delay tFDOJK time setup time hold time from JDI/input setup time JDI/input hold time from JRSTB assert time tSMSJK tHMSJK tSDIJK tHDIJK tWLJRST
tCYJK tWHJK tWLJK
VDD2/2
Data Sheet S17097EJ2V0DS
PD98442
(Input) tSMSJK (Input) tSDIJK JDI/input (Input) tDDOJK JDO/output (Output) Hi-Z tDDOJK tFDOJK Hi-Z tHDIJK tHMSJK
tWLJRST JRSTB (nput)
Data Sheet S17097EJ2V0DS
PD98442
CONNECTION POWER SUPPLY GROUND PINS SERIAL INTERFACE
high-speed block serial interface µPD98442 LVDS driver, PLL/CDR circuit, bias generation circuit that susceptible noise. Therefore, layout power supply ground pins must designed that affected noise much possible. power supply ground pins serial interface µPD98442 classified into four types blocks which power supplied, shown Table 3-1. Figure shows example connecting power supply ground pins. Table 3-1. Power Supply Pins Serial Interface
VDT0, VDT1, VDT2 GDT0, GDT1, GDT2 VAT0, VAT1 GAT0, GAT1 VQT0, VQT1, VDT2, VQT3 GQT0, GQT1, GDT2, GQT3 VDR0, VDR1, VDR2, VDR3, VDR4, VDR5, VDR6 GDR0, GDR1, GDR2, GDR3, GDR4, GDR5, GDR6 VAR0, VAR1 GAR0, GAR1 1.8-V reception analog power supply/GND Power Supplied 1.8-V transmission LVDS block power supply/GND 1.8-V transmission analog power supply/GND 1.8-V transmission LVDS driver power supply/GND 1.8-V reception LVDS block power supply/GND
Data Sheet S17097EJ2V0DS
PD98442
Figure 3-1. Example Connecting Serial Interface Power Supply Pins
Power source (1.8 GND_18
Transmission highspeed block VDT0 VDT2 Transmission LVDS block GDT0 GDT2 VAT0 VAT1
µPD98442
VDD_18
IREFVT
Transmission analog block
GAT0 GAT1 VQT0 VDQ3
GQT0 GQT3
Transmission LVDS driver
Reception high-speed block VDR0 VDR6 Reception LVDS block
GDR0 GDR6
VAR0 VAR1 IREFVR
GAR0 GAR1
Reception analog block
Remark (including resistance component (rated current (Place many capacitors possible board.)
Data Sheet S17097EJ2V0DS
PD98442
RESTRICTION Illegal Data Driving After Register Write
When write operation performed PD98442 internal register interface, PD98442 illegally drives data signals DATA[7:0] certain period after (WRB) signal deasserted. result, another signal conflict with DATA[7:0] signal. PD98442 starts illegal driving DATA[7:0] after rise (WRB) signal write access, regardless input status signal. This operation does occur upon read access. PD98442 drives DATA[7:0] illegally timing shown below.
Parameter Delay from (WRB) start illegal drive Period illegal driving When extended access function used When extended access function used Symbol tREFCLK tREFCLK tIOPCK tREFCLK tIOPCK Time
tREFCLK Equivalent clock cycle input reference clock (1/fREFCLK) tIOPCK Equivalent clock cycle clock with lowest frequency among clocks input IPCK OPCK. period varies depending extended access function (set L0CMDRJ L1CMDRJ registers). extended access function used when both L0CMDRJ L1CMDRJ 1Fh. extended access function used when either L0CMDRJ L1CMDRJ value other than 1Fh. Figure 4-1. DATA[7:0] Illegal Driving Period (1/2) BUSM0 mode
ADDR[9:0] RWB/WRB
DSB/RDB ACKB/RDYB DATA[7:0] DATA
Period illegal driving
Data Sheet S17097EJ2V0DS
PD98442
Figure 4-1. DATA[7:0] Illegal Driving Period (2/2) BUSM1 mode
ADDR[9:0] RWB/WRB
DSB/RDB ACKB/RDYB DATA[7:0] DATA
Period illegal driving
Implement workarounds shown below system avoid conflict between DATA[7:0] another signal. When writing PD98442 register, complete outputting data DATA[7:0] after hold time (WRB) MIN.) satisfied before period elapsed. When writing PD98442 register, execute next access unless period from (WRB) write cycle elapsed.
Figure 4-2. Avoiding Conflict (Example BUSM0 Mode)
ADDR[9:0] execute next access during illegal driving period. RWB/WRB DSB/RDB ACKB/RDYB DATA[7:0]
DATA
Illegal driving period
Outputting write data complete before illegal driving starts.
Remark This data sheet shows only restrictions related characteristics. restrictions function described user's manual. Also PD98442 User's Manual (S17098E).
Data Sheet S17097EJ2V0DS
PD98442
PACKAGE DRAWING
304-PIN PLASTIC FBGA (19x19)
INDEX MARK
(UNIT:mm) ITEM DIMENSIONS 19.00±0.10 19.00±0.10 0.20 0.80 1.48±0.10 0.35±0.06 1.13 0.50+0.05 -0.10 0.08 0.10 0.20 1.10 1.10 P304F1-80-HN2
Data Sheet S17097EJ2V0DS
PD98442
RECOMMENDED SOLDERING CONDITIONS
µPD98442 should soldered mounted under following recommended conditions. soldering methods conditions other than those recommended below, contact Electronics sales representative. technical information, following website. Semiconductor Device Mounting Technology Manual
Table 6-1. Recommended Soldering Conditions Surface-Mount Type µPD98442F1-HN2-A: 304-pin fine-pitch FBGA
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: Time: seconds MAX. (210 more), Number times: MAX., Number days: 7Note (After that, prebaking necessary hours.) Symbol IR60-107-3
Note number days after pack opened. storage conditions MAX.
Data Sheet S17097EJ2V0DS
PD98442
NOTES CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM INPUT Waveform distortion input noise reflected wave cause malfunction. input CMOS device stays area between (MAX) (MIN) noise, etc., device malfunction. Take care prevent chattering noise from entering device when input level fixed, also transition period when input level passes through area between (MAX) (MIN). HANDLING UNUSED INPUT PINS Unconnected CMOS device inputs cause malfunction. input unconnected, possible that internal input level generated noise, etc., causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected resistor there possibility that will output pin. handling related unused pins must judged separately each device according related specifications governing device. PRECAUTION AGAINST strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work benches floors should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with mounted semiconductor devices. STATUS BEFORE INITIALIZATION Power-on does necessarily define initial status device. Immediately after power source turned devices with reset functions have been initialized. Hence, power-on does guarantee output levels, settings contents registers. device initialized until reset signal received. reset operation must executed immediately after power-on devices with reset functions. POWER ON/OFF SEQUENCE case device that uses different power supplies internal operation external interface, rule, switch external power supply after switching internal power supply. When switching power supply off, rule, switch external power supply then internal power supply. reverse power on/off sequences result application overvoltage internal elements device, causing malfunction degradation internal elements passage abnormal current. correct power on/off sequence must judged separately each device according related specifications governing device. INPUT SIGNAL DURING POWER STATE input signals pull-up power supply while device powered. current injection that results from input such signal pull-up power supply cause malfunction abnormal current that passes device this time cause degradation internal elements. Input signals during power state must judged separately each device according related specifications governing device.
Data Sheet S17097EJ2V0DS
PD98442
Regional Information
Some information contained this document vary from country country. Before using Electronics product your application, pIease contact Electronics office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country. [GLOBAL SUPPORT]
Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782
Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65030
Sucursal
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318
Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-558-3737
Madrid, Spain Tel: 091-504
Succursale
France Tel: 01-30-67
Filiale Italiana
Electronics Shanghai Ltd.
Shanghai, P.R. China Tel: 021-5888-5400
Milano, Italy Tel: 02-66
Branch Netherlands
Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377
Eindhoven, Netherlands Tel: 040-244
Tyskland Filial
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311
Taeby, Sweden Tel: 08-63
United Kingdom Branch
Milton Keynes, Tel: 01908-691-133
J04.1
Data Sheet S17097EJ2V0DS
PD98442
POS-PHY trademark PMC-Sierra, Inc.
information this document current September, 2004. information subject change without notice. actual design-in, refer latest publications Electronics data sheets data books, etc., most up-to-date specifications Electronics products. products and/or types available every country. Please check with Electronics sales representative availability additional information. part this document copied reproduced form means without prior written consent Electronics. Electronics assumes responsibility errors that appear this document. Electronics does assume liability infringement patents, copyrights other intellectual property rights third parties arising from Electronics products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Electronics others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Electronics assumes responsibility losses incurred customers third parties arising from these circuits, software information. While Electronics endeavors enhance quality, reliability safety Electronics products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects Electronics products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment anti-failure features. Electronics products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only Electronics products developed based customerdesignated "quality assurance program" specific application. recommended applications Electronics product depend quality grade, indicated below. Customers must check quality grade each Electronics product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade Electronics products "Standard" unless otherwise expressly specified Electronics data sheets data books, etc. customers wish Electronics products applications intended Electronics, they must contact Electronics sales representative advance determine Electronics' willingness support given application. (Note) "NEC Electronics" used this statement means Electronics Corporation also includes majority-owned subsidiaries. "NEC Electronics products" means product developed manufactured Electronics defined above).
11-1

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