RM7000 Application Note RM7000 64-bit MIPS Instruction Architectu
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Design Notes
RM7000 Application Note
RM7000 64-bit MIPS Instruction Architecture with 48/64-entry memory management unit, double precision floating point unit, 64-bit multiplexed address data (which capable operating MHz). Also included chip 128KB secondary cache support external tertiary cache, thus RM7000 additional pins support external cache. maximum on-chip clock rate MHz.
Packaging
RM7000 packaged 304-ball SBGA package supplied Amkor/Anam (www.amkor.com), largest packaging company Asia. 304-ball SBGA package moisture sensitivity shipped tray. thermal data 304-pin package given table below. data there expressed degrees Celsius.
Theta(J-A) 13.1 Theta(J-C) 0.72 1.08
prudent make heat sink recommendations. amount heat your application will produce will differ from anyone else's, thus what works customer work you. starting point your search heat sink could series Wakefield Engineering (www.wakefield.com). These heat sinks mechanical dimensions (27.9mm 27.9mm) 31mm 31mm 304-SBGA package. Other vendors heat sinks AAVID (www.aavid.com) Thermalloy (www.thermalloy.com). However, compatible part Wakefield's series found either site. determining your application will require heat sink, following three formulas will use. first formula infix notation):
Theta[SA] (((Temp[J] Temp[A]) Pwr[D]) (Theta[JC] Theta[CS]))
This formula calculates amount heat sink will need keep temperature below, maximum temperature with given ambient temperature. Theta[SA] this value less required keep temperature from exceeding QED's recommended maximum temperature. Thus, higher number less heat sink will need. second formula infix notation):
Theta[JA] Theta[JC] Theta[CS] Theta[SA].
This formula tells that amount resistance heat transfer from junction ambient simply following, thermal resistance from case (Theta[JC]), thermal resistance from case heat sink (Theta[CS]), thermal resistance from heat sink ambient (Theta[SA]). third formula infix notation):
PowerDissipated ((Temp[J] Temp[A]) Theta[JA]).
This formula tells amount power that dissipated with present heat spreader.
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Design Notes RM7000 Microprocessor example selecting heat sink forced air, maximum power values RM7000 frequency internal frequency MHz. MHz, VccIO, worst case Watts. MHz, VccInt, worst case Watts. Thus, total power Watts. First examine what know. maximum temperate package degree Celsius. this maximum package temperature, will degrees warmer. However, degrees Celsius junction temperature, Temp[J]. ambient temperature, Temp[A], just select degrees Celsius. From package data know that thermal resistance between case between 0.72 1.08. worst value 1.08, best 0.72. This function surface area case surface area. hold power constant vary interface area, then clearly larger would offer least resistance heat conduction. From this assumption chose thermal resistance between case, Theta[JC]. connect heat sink component, usually heat sink compound (grease) thermal tape. Wakefield give value their DeltaPad(tm) degree Celsius watt. This likely mounting method thermal resistance between case heat sink Theta[CS] 0.5. RM7000 data sheets know that maximum power 250/100 watts (typical power about half this). This amount power must dissipate. Wakefield data book this referred here referred Pwr[D]. Calculating size heat sink need, which thermal resistance between heat sink free air, Theta[SA], get:
Theta[SA] (((Temp[J] Temp[A]) Pwr[D]) (Theta[JC] Theta[CS])) Theta[SA] 0.5)) Theta[SA] 3.65 degree Celsius watt.
From chart given with Wakefield series, which will have obtain your own, using labeling along right side, determine that satisfy calculated 3.65 rating four version various flow. 0.25" high heat sink will need over forced airflow. 0.35" high heat sink will need about forced airflow. 0.45" high heat sink will need about forced airflow. 0.6" high heat sink will need about forced airflow. Again keep mind this example worst case from RM7000 data sheet. Your requirement less. above example solves worst case, where heat sink forced required. your power requirement much less, then need forced even heat sink. forced Theta[JA] RM7000 package 13.1. With Temp[MAX] selected Temp[A] then third formula above yields maximum power dissipation, without heat sink flow, approximately watts (3.82 13.1).
VccInt
RM7000 requires separate 2.5-volt supply internal core logic. specific amount current required will vary your operating frequency, will into specific design here. general, will need regulator derive Volts. your board already volts from some other source skip this section. When need supply 2.5-volt power more than just CPU, then your best choice switching buck regulator. Vendors these switching regulators have ample application notes implementing circuitry their devices.
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Design Notes RM7000 Microprocessor When supplying 2.5-volt power only RM7000, linear regulator your best choice. There three such regulators that have seen use. first that comes mind Micrel MIC28502. This device takes volts pins outputs volts with being ground, being adjust pin. This part requires couple caps couple resistors breadboarded minutes. second part with very similar footprint Unitrode UC385T-ADJ. difference between this part Micrel part that UC385 bias voltage regulators logic. This logic requires bias that least volts greater than Vout. Vout volts, Vbias least volts. This means that that UC385T tied 5-volt source. saving grace having both volts volts this regulator that gives some very good noise margins. similar part from Linear Technology LT1584. third part that familiar with LT1085CT from Linear Technology. This ubiquitous 3-pin regulator. requires volts adjust circuitry between pluses this device that ones like available from multiple vendors. negatives using such part that, volts, regulator shunt volt across itself. This means regulator will dissipate much 2.5-volt power CPU.
VccP
Phase Lock Loops tend susceptible noise when operated lower frequencies. keep noise PLL, there pass filter circuit given appendix RM5200 Family User Manual power pins. resistor value from ohms will suffice. Place smallest value capacitor closes CPU. power chip Phase Lock Loop applied across VccP VssP pins. RM7000, requires volts, which same VccInt. Land Pattern support RM5270, RM5271, RM7000 devices should have resistor layout such that power applied VccP from either VccIO VccInt supply.
System Interface
RM5200 system interface very simple relative many others. does only types transfers; Block Reads, Block Writes, Non-block reads, Non-block writes independent transfers under external request. Many designs independent transfers, thus, there generally only types transfers across system interface. Block reads writes always transfers full 32-byte cache line. 32-bit RM5230 RM5231 block transfer takes words word being bytes 32-bits). Non-block double word loads stores broken into word transactions. does arbitration; essentially single master bus. only time master when released external agent system ASIC during read cycle response external request. system interface made three buses; multiplexed address data called SysAD bus, parity called SysADC bus, command called SysCMD bus. RM5230 RM5231 SysAD 32-bits wide. Even byte parity addresses data that appear SysAD carried SysADC bus. type transfers being initiated address cycle types data during data cycle indicated 9-bit SysCMD bus. system interface control pins. RdRdy* WrRdy* pins driven external agent system ASIC control rate which issues reads write cycles, respectively. Since RM5200 pendent bus, that only transaction taking place moment time, then circuit designers tend RdRdy* low. These only times external agent system ASIC accept read when performing read. ValidOut* signal driven inform external agent that placed valid address data SysAD bus, valid command SysCMD bus, along with even parity SysADC bus. ValidIn* signal driven external agent inform that external agent placed valid data SysAD appropriate response data type SysCMD bus. When system does implement external cache, external agent does have drive SysADC with even parity. Instead tell generate parity data driving SySCMD4 high during data cycles. Release* driven inform external agent that mastership bus. Thus Release* gets asserted both during address cycle read following CPU's acceptance external request.
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Design Notes RM7000 Microprocessor sixth control external request pin, ExtRqst*. external agent asserts when wants independent transfer across system interface. Once external agent mastership system interface buses whatever wants long does drive ValidIn* low. Once sees ValidIn* low, assumes external agent returning data during read cycle returning system interface following release system interface external request. Another interest system interface SysClock. Everything occurs rising edge SysClock. reads accept read data fast external agent provide writes there write protocols control write behavior. older R4000 compatible mode says that will address more often than once every SysClock cycles. non-block writes this means that back-to-back word write will contain unused (idle) cycles. pipeline mode does away with unused cycles. allows writes take place fast provide them. Write Reissue mode improvement pipeline mode allow higher SysClock frequencies. higher SysClock frequencies, external agent able de-assert WrRdy* fast enough halt following write. Thus, under pipeline mode, external agent able accept following write, even block write; otherwise, data will lost. Under Write Reissue mode, WrRdy* asserted during issue cycle, write ignore, since will re-issue initialization interface made ModeIn, ModeClock, BigEndian pins. RM5200 CPUs uses serial configuration mode stream number idle cycle (wait states) between data cycles block write, strength it's drive pins, write protocol, allow system designer pass information firmware. ModeClock divide SysClock pin's clock signal used clock data external serial EEPROM CPLD. ModeIn input serial mode stream. serial EEPROM such Xilinx XC1700E used, however most designs implement simple state machine CPLD. BigEndian should tied endianness serial mode stream. Pulling this high forces into endian mode. Reset*, ColdReset*, VccOK pins discussed Section RM5200 Family User Manual. Essentially, whenever ColdReset* asserted, serial mode data re-loaded. warm reset when only Reset* asserted. During warm reset serial mode data re-loaded. VccOK generated power supply system tell okay start configuration cycle. RM523x supports JTAG Boundary Scan test mode. JTAG BSDL files available QED's site (www.qedinc.com). RM523x does support JTAG chip debugging. JTAG pins JTMS, JTCK, JTDO, JTDI used they left disconnected, since there appropriate pull-ups chip these pins. pull these pins low! RM523x interrupt pins (Int[0:5]*) non-maskable interrupt (NMI*). These pins should presented RM523x logic device with input logic device pulled-up keep random noise these pins. These pins must also meet setup hold timing given data sheets. remaining pins RM7000 304-SBGA package connected used power ground. system interface made three buses; multiplexed address data called SysAD bus, parity called SysADC bus, command called SysCmd bus. RM7000 SysAD 64-bits wide. Even byte parity addresses data that appear SysAD carried SysADC bus. type transfers being initiated address cycle types data during data cycle indicated 9-bit SysCmd bus. system interface control pins. RdRdy* WrRdy* pins driven external agent system ASIC control rate which issues reads write cycles, respectively. Since RM7000 pendent bus, that only transaction taking place moment time, then circuit designers tend RdRdy* low. This only time external agent system ASIC accept read when performing read. ValidOut* signal driven inform external agent that placed valid address data SysAD bus, valid command SysCMD bus, along with even parity SysADC bus. ValidIn* signal driven external agent inform that external agent placed valid data SysAD appropriate response data type SysCMD bus. When system does implement external cache, external agent
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Design Notes RM7000 Microprocessor does have drive SysADC with even parity. Instead tell generate parity data driving SySCMD4 high during data cycles. Release* driven inform external agent that mastership bus. Thus Release* gets asserted both during address cycle read following CPU's acceptance external request. sixth control external request pin, ExtRqst*. external agent asserts when wants independent transfer across system interface. Once external agent mastership system interface buses whatever wants long does drive ValidIn* low. Once sees ValidIn* low, assumes external agent returning data during read cycle returning system interface following release system interface external request. Another interest system interface SysClock. Everything occurs rising edge SysClock. reads accept read data fast external agent provide writes there write protocols control write behavior. older R4000 compatible mode says that will address more often than once every SysClock cycles. non-block writes this means that back-to-back word write will contain unused (idle) cycles. pipeline mode does away with unused cycles. allows writes take place fast provide them. Write Reissue mode improvement pipeline mode allow higher SysClock frequencies. higher SysClock frequencies, external agent able de-assert WrRdy* fast enough halt following write. Thus, under pipeline mode, external agent able accept following write, even block write; otherwise, data will lost. Under Write Reissue mode, WrRdy* asserted during issue cycle, write ignore, since will re-issue CPUs uses configuration mode bits select number idle cycle (wait states) between data cycles block write, select strength it's drive pins, select write protocol, allow system designer pass information firmware. RM7000 also supports multiple-outstanding-reads out-of-order returns data. This allows RM7000 maximize stall while waiting data long pipeline still execute. 304-pin RM7000 package, connected, used SysAD bus, used carry commands, used support even parity, used power (VccIO), used Internal Power (VccInt), used ground (Vss), used configuration, used initialization used supply power Phase Lock Loop. operations system interface address data traveling across 64-pin SysAD bus, commands data type information traveling 9-pin SysCmd bus, with even parity SysADC bus. SysADC pins supported external agent, then external agent must drive SysCMD4* high while supplying data. This forces check parity system interface, instead generate parity received data. Also, this case, SysADC pins should tied high. SysCmd these parity pin, which always driven ignored input. This pin, SysCmdP, should tied low. signals ValidIn*, ValidOut*, RdRdy*, WrRdy*, Release*, ExtRqst* control pins system interface. ValidOut* driven RM7000 when there valid address valid data SysAD valid command data type information SysCmd bus. ValidIn* driven external agent when placed valid data SysAD valid data type information SysCmd bus. pins RdRdy* WrRdy* driven external agent signal that capable performing read write, respectively. external agent wishes make transfer across system interface device other than RM7000, signals give asserting ExtRqst*. signals that given pulsing Release* cycle. Note that ExtRqst* priority over system interface reads writes. During independent transfer, external agent MUST ValidIn* until ready give bus. give bus, external agent drives "External Request Release NULL" code SysCmd asserts ValidIn*. initialization interface made ModeIn, ModeClock, BigEndian pins. CPUs developed uses serial mode stream configure CPU. ModeClock divide SysClock pins clock signal used clock data external serial EEPROM CPLD. ModeIn input serial mode stream. type
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Design Notes RM7000 Microprocessor serial EEPROM used equivalent Xilinx XC1700E devices. Most designs implement simple state machine CPLD. BigEndian should tied endianness serial mode stream. However, endianness forced endian tying this high. Reset*, ColdReset*, VccOk pins discussed Section RM7000 User Manual. Essentially, whenever ColdReset* asserted, serial mode data re-loaded. warm reset when only Reset* asserted. During warm reset serial mode data re-loaded. VccOk generated power supply system tell okay start configuration cycle. RM7000 supports JTAG Boundary Scan test mode. JTAG BSDL files available QED's site (www.qedinc.com). RM7000 does support JTAG chip debug. JTAG pins used they left disconnected, since there appropriate pull-ups chip these pins. pull these pins low! RM7000 interrupt pins (Int[9:0]*) non-maskable interrupt (NMI*). These pins should presented RM7000 logic device with input logic device pulled-up keep random noise these pins. These pins must also meet setup hold timing given data sheets. power supplies needed RM7000. input/output pins (VccIO) requires Volts while internal core logic (VccInt) requires volts. 2.5-volt power derived from 3.3-volt supply using dropout linear regulator such Micrel MIC29302 Unitrode UC385T. VccInt pins typically requires little less that current MHz. This will less on-chip frequency lowered. VccIO pins also requires less than current, will require even less less than load implemented system interface. RM7000 requires volt power on-chip Phase Lock Loop (PLL). This power should filtered RM7000. circuitry recommends given Section "Clock Interface", RM7000 User Manual. smallest closest
Resources
find up-to-date books subject high-speed design, start with site (www.ipc.org). international standards organization design, fabrication, assembly. manuals that they publish that useful IPC-D-317B IPC-2141. They also have link another site, where select your PCBs stack-up then site will calculate impedance you. There also free Gerber viewer download. site also link Barnes Noble bookstore. They list several books Controlled Impedance Circuit design (the other name high-speed circuit design). However, author familiar with books listed there cannot comment their usefulness. book subject that author familiar with publish 1993 written Howard Johnson Martin Graham. very good book MIPS architecture "See MIPS Run" Dominic Sweetman. founder Algorthmics (www.algor.co.uk). book results years spent answering customer's questions about MIPS architecture. Other resources that should aware IBIS models from QED. These used with "Signal Integrity Software" determine signal quality your design. IBIS models free available from QED. Signal Integrity Software available from several vendors. known author HyperLynx (www.hyperlynx.com) Applied Simulation Technology (www.apsimtech.com). With such tools your chances obtaining working high-speed design first time much improved. those designers doing their ASIC, unencrypted Verilog Functional Models available. These released free charge under Intellectual Property Non-Disclosure. your sales person paperwork started.
Observation
First foremost; "DON'T FORGET CAPS". Questionable layouts still work with enough capacitors good layouts fail because shortage capacitors. good Technical Note selecting bypass capacitors obtained from Micron Technology site. Technical Note that want TN-00-06.
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Design Notes RM7000 Microprocessor clocks, clock tree structure keep trace runs equal lengths that rising edges arrive their designations same time.
Rules Thumb Layout
Ground return loops
most important thing design keeping noise down ground power planes. make cuts into ground power planes, signal trace across cut. return current signal flows directly under trace. putting reference plane underneath signal trace force return current take different path back transmitter, thus introducing noise. have other choice, then your reduce noise putting several ceramic capacitors across trace crossing.
Crosstalk analysis
Crosstalk worst problem encounter. short, keep trace runs short apart possible. longer traces parallel each other, greater chance introducing noise into other.
Trace current capacity
traces smaller, their resistance goes Since load that want drive capacitive this resistance, effect same pass filter. rise time your signal will become longer, causing bandwidth reduced.
Trace stub lengths
Since objective keep noise signal, T-routing. point-to-point trace routing. This will keep trace stubs lengths minimum. Trace stubs causes noise signal.
Rules Thumb Fabrication
Dialog
First formost talk board fabricator that going fabricate your PCB. They have possible done high speed fabrication someone else have learned from experience that they pass you. They also answer your questions about what they capable doing. fabricator have equipment limitation, have design your within those limitations. Also sometimes they direct less expensive alternative that aware
Price
High Speed Fabrication cheap. receive very quote, make sure fabricator knows what required. very wary anyone offering exceptionally price. Make sure that getting quality material. Most fabricators FR-4, there many levels quality, thus suitability, high-speed usage. lower quality FR-4 will have higher moisture absorption lower ratio fiber epoxy, which will raise PCBs coefficient permeability.
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Design Notes RM7000 Microprocessor
This document may, wholly partially, subject change without notice. Quantum Effect Devices, Inc. reserves right make changes products specifications time without notice, order improve design performance supply best possible product. rights reserved. permitted reproduce duplicate, form, whole part this document without QED's permission. will held responsible damage user property that result from accidents, misuse, other causes arising during operation user's unit. LIFE SUPPORT POLICY: QED's products designed, intended, authorized components intended surgical implant into body, other applications intended support sustain life, other application which failure product could create situation where personal injury death occur. Should customer purchase products such unintended unauthorized application, customer shall indemnify hold officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that negligent regarding design manufacture part. does assume responsibility circuitry described other than circuitry embodied product. company makes representations that circuitry described herein free from patent infringement other rights third parties, which result from use. license granted implication otherwise under patent, patent rights, other rights, QED. logo RISCMark trademarks Quantum Effect Devices, Inc. MIPS registered trademark MIPS Technologies, Inc. other trademarks respective property trademark holders.
Laurin McLaurin RM7000-AN1151110002
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