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High Speed Standard Clock Generator With Frequency Synthesizer RE


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M66239FP
High Speed Standard Clock Generator With Frequency Synthesizer
REJ03E0002-0100 Rev.1.00 2005
M66239FP high speed synchronizing clock generator with frequency synthesizer which fabricated high performance silicon gate CMOS process technology. able output clock sync with external trigger. features excellent synchronizing precision (sync accuracy: jitter) over wide range frequency band. Also, frequency synthesizer function which able modulate input frequency resister setting before normal operation. Frequency modulation resolution high accuracy 0.01%. order process Y/M/C/K printing signal processing chip, M66239FP integrate fore synchronizing clock generator macro with frequency synthesizer function. Also, this part various applications frequency synthesizer LSI.
Features
Power supply voltage: Single Frequency band: Synchronizing precision (jitter): ±1.5 Output clock type Sync clock output (CKO) Sync clock output inverted (CKOB) One-shot pulse output (PULSE) Continuous clock output (CLKO: asynchronous trigger) Trigger edge: Polarity (positive/negative) selectable Output clock phase control: step resolution clock period) Frequency synthesizer type Offset type modulation Triangle type modulation Polygon type modulation Frequency modulation resolution: 0.01% Output clock center frequency modulation: 0.01% step/Maximum ±2.55% Output clock peak frequency modulation: 0.01% step/Maximum ±2.55% Output clock modulation period: resister setting Output clock modulation start position: resister setting Output clock disable function: Disable CKOB PULSE control Integrated synchronizing clock generator macro with frequency synthesizer function
Application
Digital color copier/Digital color laser beam printer
Rev.1.00 2005 page
M66239FP
Block Diagram
SCLK1/SENABLE1/SDATA1 MCLK1 TR1/MODE1
Serial input register
Frequency modulation circuit
Sync clock generator
CLKO1 CKO1 CKOB1 PULSE1
SCLK2/SENABLE2/SDATA2 MCLK2 TR2/MODE2
Serial input register
Frequency modulation circuit
Sync clock generator
CLKO2 CKO2 CKOB2 PULSE2
SCLK3/SENABLE3/SDATA3 MCLK3 TR3/MODE3
Serial input register
Frequency modulation circuit
Sync clock generator
CLKO3 CKO3 CKOB3 PULSE3
SCLK4/SENABLE4/SDATA4 MCLK4 TR4/MODE4
Serial input register
Frequency modulation circuit
Sync clock generator
CLKO4 CKO4 CKOB4 PULSE4
Rev.1.00 2005 page
M66239FP
Configuration
1st-line 4th-line
TESTP1 TESTN1 DACVCC DACGND RESET1 TEST<0> TEST<1> PLLVCC PLLGND PLLVCC PLLGND AVCC AGND MODE1 MCLK1 DVCC DGND DGND DVCC MCLK2 MODE2 AGND AVCC PLLGND PLLVCC PLLGND PLLVCC TEST<2> TEST<3> RESET2 DACGND DACVCC TESTN2 TESTP2
SCLK1 SENABLE1 SDATAIN1 SDATAOUT1 DACGND DACVCC CKO1 AGND AVCC CKOB1 PULSE1 DGND DVCC CLKO1 FSET1<2> FSET1<1> FSET1<0> FSET4<0> FSET4<1> FSET4<2> CLKO4 DVCC DGND PULSE4 CKOB4 AVCC AGND CKO4 DACVCC DACGND SDATAOUT4 SDATAIN4 SENABLE4 SCLK4
TESTP4 TESTN4 DACVCC DACGND RESET4 TEST<7> TEST<6> PLLVCC PLLGND PLLVCC PLLGND AVCC AGND MODE4 MCLK4 DVCC DGND DGND DVCC MCLK3 MODE3 AGND AVCC PLLGND PLLVCC PLLGND PLLVCC TEST<5> TEST<4> RESET3 DACGND DACVCC TESTN3 TESTP3
M66239FP XXXXXX
Rev.1.00 2005 page
SCLK2 SENABLE2 SDATAIN2 SDATAOUT2 DACGND DACVCC CKO2 AGND AVCC CKOB2 PULSE2 DGND DVCC CLKO2 FSET2<2> FSET2<1> FSET2<0> FSET3<0> FSET3<1> FSET3<2> CLKO3 DVCC DGND PULSE3 CKOB3 AVCC AGND CKO3 DACVCC DACGND SDATAOUT3 SDATAIN3 SENABLE3 SCLK3
2nd-line Package 144P6Q (Top view)
3rd-line
M66239FP
Name MCLK SCLK SENABLE SDATAIN RESET FSET<2:0> MODE CLKO CKOB PULSE SDATAOUT Input clock. Serial resister clock input. Serial resister enable input. level: disable, level: enable Serial resister data input. System reset input. When "L", system reset function. Reset function initialize resister data default settings. Frequency range settings correspond MCLK frequency. Trigger edge polarity (positive/negative) select. level: negative edge mode, level: positive edge mode Trigger input clock outputs. Continuous clock output. CLKO asynchronous clock output trigger. Sync. clock output. Synchronized with trigger signal. Sync. clock output. Synchronized with trigger signal. CKOB inverted clock CKO. Sync. clock output. Synchronized with trigger signal. PULSE one-shot pulse synchronized with CKO. Serial resister data output. Output enable control. level: CKOB PULSE will disabled. level: clock outputs will enabled. Test control input. "L". Test control input. open. Digital block GND. Analog block GND. block GND. converter GND. Function
TEST<7:0> TESTP<4:1> TESTN<4:1> DVCC DGND AVCC AGND
Rev.1.00 2005 page
M66239FP
Whole Block Diagram
CLKO1 CKO1 CKOB1 PULSE1 CLKO2 CKO2 CKOB2 PULSE2 CLKO3 CKO3 CKOB3 PULSE3 CLKO4 CKO4 CKOB4 PULSE4
MCLK1
Y-line channel
MCLK2
M-line channel
MCLK3
C-line channel
MCLK4
K-line channel
Unit Channel Block Diagram
Frequency modulation circuit
CLKO
MCLK
Clock generator
FSET<2:0>
Frequency control Sync clock generator
CKOB
SENABLE SDATAIN SCLK SDATAOUT RESET Serial input register PULSE TEST mode control
TEST<7:0>
MODE
Rev.1.00 2005 page
M66239FP
Function Summary
Sync Clock Generation Function M66239FP standard clock generator function, able output clock sync with external trigger features excellent synchronizing precision (sync accuracy: jitter) over wide range frequency band. Sync clock output timing determined trigger input signal edge. Trigger edge polarity (positive/negative) selectable MODE input. Time-lag between trigger input signal edge sync clock output equals clock input signal pulse width M66239FP internal delay. Variation this ±1.5ns, ensuring excellent synchronizing accuracy. There three types outputs: synchronous clock output (CKO), synchronous clock inverted output (CKOB), one-shot pulse output (PULSE). Synchronous clock output same frequency clock input signal MCLK. Synchronous clock inverted output CKOB inverted signal sync clock CKO. PULSE one-shot pulse output which almost equal cycles. three sync outputs suspended when trigger input signal level when MODE "H", level when MODE level. During these period, PULSE stay level, CKOB stay level. Also, start phase sync. clocks controlled steps Clock Period). steps resolution controlled serial resister setting. M66239FP integrate four synchronizing clock generator macro with frequency synthesizer function.
Frequency Modulation Function M66239FP able modulate sync. clock frequency. Frequency modulation profile controlled serial resister. Serial resister controlled serial input clock (SCLK), serial input enable (SENABLE) serial input data (SDATAIN). When SENABLE level, SDATAIN able write serial input resister SCLK. SDATAIN composed address distinction resister data. After write operation completed, able confirm resister status using read operation serial input resister. Resister setting follows. (10) (11) Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) 3rd.pole position (3rdPole) 4th.pole position (4thPole) 1st.Pole frequency (f1stPole) 3rd.Pole frequency (f3rdPole) Resister Resister Resister Resister Resister Resister Resister Resister Resister Resister Resister
There four operation modes, center frequency offset type modulation (mode1), triangle type modulation (mode2 polygon type modulation (mode4).
Rev.1.00 2005 page
M66239FP
Sync. Clock Generation Operation Timing
Trigger Mode (Negative edge operation: MODE "H")
1/fIN MCLK tw(TR) tsp(CKO) tsp(CKO) CKOB tss(CKO) PULSE tss(PULSE) tw(PULSE)
tss(CKO)
Figure Trigger Mode
Trigger Mode (Positive edge operation: MODE "L")
1/fIN MCLK tw(TR) tsp(CKO) tsp(CKO) CKOB tss(CKO) tss(CKO)
PULSE tss(PULSE) tw(PULSE)
Figure Trigger Mode Notes: (CKO, CKOB PULSE) equals input clock width Value refers internal delay M66239FP. Under environment where temperature change, value kept constant approximately. Dispersion under such conditions defined (synchronizing precision: jitter). Outputs (CKO, CKOB PULSE) unknown until twice trigger pulse input reaches after power-on. Internal trigger signal generated EXOR MODE signal.
Rev.1.00 2005 page
M66239FP
Sync. Clock Phase Timing
M66239FP able control phase sync clock outputs (CKO, CKOB, PULSE) each step. clock period) This phase shift control serial input resister Also, edge phase position) sync clock outputs shifted, edge phase position) sync clock outputs either shifted position resister position, after edge phase position) sync clock outputs shift resister settings. CLKO output this phase shift function because CLKO asynchronous clock output trigger.
MCLK CKOB PULSE CLKO
Phase shift Phase shift Phase shift Phase shift
Phase shift Phase shift Phase shift Phase shift
each step Notes: edge phase sync clock output shifted. edge phase sync clock output either shifted position resistor position, edge phase sync clock output shift resistor settings. step resolution, less than synchronizing precision (jitter) able realize such high step resolution. guarantee value which taken into account jitter noise.
tss(CKO)
Figure Sync. Clock Phase Timing
Rev.1.00 2005 page
M66239FP
Frequency Modulation Operation Timing
Function Mode Mode frequency offset type modulation. Output clock frequency keep Fcenter-freqency. Frequency modulation serial input resister. Operation mode Frequency modulation start position (Tstart) Output center frequency (fcenter)
MCLK Output clock frequency Fpeak+ Fcenter
Resister Resister Resister
Tstart
Fpeak- Modulation start Note: Until next input, output clock frequency keep "Fcenter".
Figure Operation Timing Mode
Rev.1.00 2005 page
M66239FP Function Mode Mode triangle modulation type following. Frequency modulation serial input resister. Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) Resister Resister Resister Resister Resister Resister Resister
MCLK Output clock frequency Fpeak+ Tspace1 Fcenter Tspace2 Fpeak- Modulation start Pole Pole Modulation Tspace6
Tstart Trate
Notes: Each Pole position (cycle number) defined Tstart position. Until next input, output clock frequency keep "Fcenter".
Figure Operation Timing Mode
Rev.1.00 2005 page
M66239FP Function Mode Mode triangle modulation type following. Frequency modulation serial input resister. Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) Resister Resister Resister Resister Resister Resister Resister
MCLK Output clock frequency Fpeak+ Fcenter
Tstart Trate
Fpeak-
Tspace1 Modulation start Pole
Tspace2 Pole
Tspace6 Modulation
Notes: Each Pole position (cycle number) defined Tstart position. Until next input, output clock frequency keep "Fcenter".
Figure Operation Timing Mode
Rev.1.00 2005 page
M66239FP Function Mode Mode polygon modulation type following. Frequency modulation serial input resister. (10) (11) Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) 3rd.pole position (3rdPole) 4th.pole position (4thPole) 1st.Pole frequency (f1stPole) 3rd.Pole frequency (f3rdPole) Resister Resister Resister Resister Resister Resister Resister Resister Resister Resister Resister
MCLK Output clock frequency Fpeak+ F3rdpole Fcenter F1stpole Fpeak- Tspace1 Tspace2 Tspace3 Tspace4 Tspace5
Tstart Trate
Modulation start Pole
Pole Pole
Pole
Modulation
Notes: Each Pole position (cycle number) defined Tstart position. Until next input, output clock frequency keep "Fcenter". F3rdpole Fpeak+ must higher frequency than Fcenter. F1stpole Fpeak- must lower frequency than Fcenter.
Figure Operation Timing Mode
Rev.1.00 2005 page
M66239FP Function Mode (cont.) Mode polygon modulation type following. Frequency modulation serial input resister. (10) (11) Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) 3rd.pole position (3rdPole) 4th.pole position (4thPole) 1st.Pole frequency (f1stPole) 3rd.Pole frequency (f3rdPole) Resister Resister Resister Resister Resister Resister Resister Resister Resister Resister Resister
MCLK Output clock frequency Fpeak+ F1stpole Fcenter F3rdpole Fpeak- Tspace1 Tspace2 Tspace3 Tspace4 Tspace5
Tstart Trate
Modulation start Pole
Pole Pole
Pole
Modulation
Notes: Each Pole position (cycle number) defined Tstart position. Until next input, output clock frequency keep "Fcenter". F1stpole Fpeak+ must higher frequency than Fcenter. F3rdpole Fpeak- must lower frequency than Fcenter.
Figure Operation Timing Mode
Rev.1.00 2005 page
M66239FP
CLKO Operation Timing
CLKO output continuation clock output that frequency modulation worked like asynchronous relation with operation timing specified operation mode figure below other operation mode same. Also, because CLKO continuation clock output before synchronous clock generation circuit, phase relation during channel guaranteed.
MCLK CLKO Output clock frequency Fpeak+ F3rdpole Fcenter F1stpole Fpeak- Tspace1 Tspace2 Tspace3 Tspace4 Tspace5
Tstart Trate
Modulation start Output clock frequency Fpeak+ F3rdpole Fcenter F1stpole Fpeak- Pole Tstart
Pole Pole Trate
Pole
Modulation
Tspace1 Tspace2
Tspace3
Tspace4
Tspace5
Modulation start Pole
Pole Pole
Pole
Modulation
Figure (upper) CLKO (lower)
Rev.1.00 2005 page
M66239FP
Frequency Modulation Resister Setting (Write Operation)
Write Operation Frequency modulation serial input resister. Serial input resister controlled serial input clock (SCLK), serial input enable (SENABLE) serial input data (SDATAIN). When SENABLE level, SDATAIN written serial input resister SCLK. SDATAIN composed address distinction data resister data. After SENABLE change "H", more than dummy SLCK cycle needed.
SENABLE SCLK SDATAIN cycles dummy input
4bit address
16bit data
write operation, cycles continuously.
Figure Frequency Modulation Resister Setting (Write Operation)
Rev.1.00 2005 page
M66239FP
Frequency Modulation Resister
Resister Name Resister Resister Resister Resister Address Function Operation mode Modulation period Modulation start position Center frequency
Setting Range
Default Value
Number
0000000000000001 0000000000000100 0000010111011100 1111111111111111 0000000001100100 0000001111111111 0000000000000000 0000000111111111
0000000000000001(1 dec)
Mode1 when
Unit 1LSB
0010000000000000(8192 dec) MCLK cycle 0000000100000000(256 dec) 0000000100000000(256 dec) MCLK cycle MCLK frequency
-2.55% when min. value +2.55% when max. value
when Modulate side more than Modulate side less than
±2.55% when
Resister
Peak frequency
0000000000011110 0000000011111111
±0.30% when min. value ±2.55% when max. value
0000000011111111(255 dec)
MCLK frequency
1st-pole position Resister 2nd-pole position Resister 3rd-pole position Resister 4th-pole position Resister 1st-pole frequency (Mode Resister 3rd-pole frequency (Mode Resister Modulation resolution
Resister
0000000111110100 1001111111111111 0000000111110100 1001111111111111 0000000111110100 1001111111111111 0000000111110100 1001111111111111 0000000000000000 0000000111111111
0000011001100110(1638 dec) MCLK cycle 0000110011001100(3276 dec) MCLK cycle 0001001100110010(4914 dec) MCLK cycle 0001100110011000(6552 dec) MCLK cycle 0000000010000000(128 dec)
-1.28% when
MCLK frequency
-2.55% when min. value +2.55% when max. value
0000000000000000 0000000111111111
-2.55% when min. value +2.55% when max. value
0000000110000000(384 dec)
+1.28% when
MCLK frequency
0000000000000000 0000000000000001
±0.01% mode when min. ±0.005% mode when max.
0000000000000000(0 dec)
0.01% mode when
Resister Output phase control
0000000000000000 0000000000000111
Delay when min. Delay 7T/8 when max.
0000000000000000(0 dec)
Delay when
(Clock cycle)
Notes: following value resister operation mode "0000000000000001" operation mode "0000000000000010" operation mode "0000000000000011" operation mode "0000000000000100" Resister must change. Above table intend setting available value resister, practical limits described page Resister phase control sync clock output. default value above resister use, write operation resister must done. Resister refer following. Pole Tspace1 Pole Tspace1 Tspace2 Pole Tspace1 Tspace2 Tspace3 Pole Tspace1 Tspace2 Tspace3 Tspace4
Rev.1.00 2005 page
M66239FP
Frequency Modulation Resister Setting (Read Operation)
Read Operation After write operation completed, confirm resister status using read operation serial input resister. When SENABLE level, SDATAIN written serial input resister SCLK. SDATAIN composed address distinction data. After SENABLE change "H", more than dummy SLCK cycle needed.
SENABLE
SCLK SDATAIN cycles dummy input
4bit address write operation, cycles continuously. SDATAOUT 16bit data
Figure Frequency Modulation Resister Setting (Read Operation)
Rev.1.00 2005 page
M66239FP
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage Storage temperature Symbol Tstg Ratings -0.3 +4.6 -0.3 Vcc+0.3 -0.3 Vcc+0.3 +150
Unit
Conditions
Power dissipation 2500 30°C/W, 50°C Note: should less than 30°C/W, Tjmax should less than 125°C. When 30°C/W Tjmax 125°C, Ta(max) will 50°C. needs over layers, over size, over occupied ratio (average value each layer) roughly. Please contact sales division when design layout.
Recommended Operating Conditions
Item Supply voltage Supply voltage Input voltage Output voltage Operating temperature Symbol Topr 3.15 3.46 Unit Conditions
Characteristics
+50°C, 3.15 3.46V,
Item input voltage input voltage output voltage output voltage Supply current (static) Supply current (active) Symbol input current input current Input capacitance Unit fMCLK MHz, fSCLK MHz, fMCLK MHz, fSCLK MHz, fMCLK MHz, fSCLK MHz, fMCLK MHz, fSCLK MHz, Test Conditions
Note: direction current flowing circuit specified positive. sign)
Rev.1.00 2005 page
M66239FP
Timing Requirements
+50°C, 3.15 3.46V,
Item MCLK frequency MCLK SCLK clock duty input pulse width MCLK SCLK input rising time MCLK SCLK input falling time SDATA, SENABLE set-up time SDATA, SENABLE hold time SCLK frequency Internal lock time RESET pulse width Symbol fMCLK fDUTY tw(TR) fSCLK Tplllock tw(RESET) Unit Test Conditions
Switching Characteristics
+50°C, 3.15 3.46V,
Item Synchronizing precision (jitter) Sync. clock output start time Sync. clock CKOB output start time One-shot pulse output start time Sync clock output stop time Sync. clock CKOB output stop time One-shot pulse width Sync. clock output duty Symbol tss(CKO) tss(CKOB) tss(PULSE) tsp(CKO) tsp(CKOB) tw(PULSE) foDUTY(CKO) tp-10 ±1.5 tLp+50 tLp+50 tp+10 Unit Test Conditions
Sync. clock CKOB output duty foDUTY(CKOB) Notes: 1/fIN, (100 fDUTY)/100 Switching test waveform Input pulse level MCLK: Vcc, Input clock rising time: Input clock falling time: Criteria Voltage MCLK: Vcc/2, Sync. clock: Vcc/2
Rev.1.00 2005 page
M66239FP
Frequency Modulation Characteristics
+50°C, 3.15 3.46V,
Item Frequency modulation start position Frequency modulation period Center frequency Center frequency resolution Peak frequency side) Peak frequency side) Peak frequency resolution 1st.pole position 2nd.pole position 3rd.pole position 4th.pole position cycle between 1stPole Tstart cycle between 2ndPole 1stPole cycle between 3rdPole 2ndPole cycle between 4thPole 3rdPole cycle between modulation end-4thPole cycle between modulation end-2ndPole case mode mode 1st.Pole frequency case page 1st.Pole frequency case page 3rd.Pole frequency case page 3rd.Pole frequency case page Symbol Tstart Trate Fcenter Fstep1 Fpeak+ Fpeak- Fstep2 1stPole 2ndPole 3rdPole 4thPole Tspace1 Tspace2 Tspace3 Tspace4 Tspace5 Tspace6 F1stpole F3rdpole 1500 0.01 +0.3 -0.3 0.01
Tstart+500 1stPole+500 2ndPole+500 3rdPole+500
8192
1023 65535 ±2.55 +2.55 -2.55 40959 40959 40959 40959
-Fpeak+0.1 +Fpeak-0.1 +Fpeak-0.1 -Fpeak+0.1
Unit
Cycle Cycle
Test Conditions
Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle
Fcenter-0.1 Fcenter+0.1 Fcenter+0.1 Fcenter-0.1
Notes: Regarding Fpeak+/-, F1stpole, F3rdpole higher frequency than Fcenter specified positive sign), lower frequency than Fcenter specified negative sign). above limitations Fcenter, Fstep1, Fpeak+/-, Fstep2, F1stpole, F3rdpole, 1stPole, 2ndPole, 3rdPole, 4thPole setting available vale. Actual output clock affected jitter, above limitations guarantee value which taken into account jitter noise. Minimum specification modulation period 1500 cycles, operation mode needs over 2500 cycles.
Frequency Range Setting Input Clock
FEST<2:0> pins need correspond following table. Table Frequency Range Setting Input Clock
FSET<2> FSET<1> FSET<0>
Input Clock Frequency (MHz)
Notes: MCLK frequency change under operating, should need start power procedure again. FSET<2:0> setting changed, reset function needed again. reset operation, serial resisters default settings, should serial resister again.
Rev.1.00 2005 page
M66239FP
After Power-On Procedure
After power-on, M66239FP status unknown. Following procedure must done. power-on After input clock frequency stable, FSET[2:0]. Reset pulse input. Input more than MCLK 1000 clock cycle from FSET setting completed RESET level. Serial resister set. After input MCLK clock till lockup time (Tplllock), input twice pulse. Input more than cycle MCLK clocks between 1st. 2nd. After that, sync clock will outputted from M66239FP.
More than 1000 cycles
MCLK
Input clock frequency stable tw(RESET) Tplllock
RESET
FSET Serial resister
FSET<2:0> (refer page
Serial resister (refer page More than cycles Setting completed
CKO/CKOB/PULSE
Note: case change resister after complete above power procedure, resister value reflects after least more twice pulse input. when changing register center frequency purpose changed, locked time must wait. Also,there problem even trigger signal entered before lock after changing register When changing register except register need wait locked time PLL.
Figure After Power-On Procedure
Rev.1.00 2005 page
M66239FP
Input Clock Change Sequence
When changing frequency input clock, being inside each range frequency range which specified page change FSET unnecessary lock sometimes comes when frequency changed even inside each range frequency range. When frequency input clock changes each range frequency range comes lock condition, adds that takes time locking once again. stable output clock, after passing lock time frequency input clock after phase change, enter signal. output clock which stable after entry gotten signal. About change frequency which exceeds frequency range which specified page purpose FSET[2:0] changed, sequence power must done.
MCLK
over Clock change Clock stable
sequence when changing entry frequency each range frequency range
Figure Input Clock Change Sequence
Rev.1.00 2005 page
M66239FP
Package Dimensions
JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A FP-144L FP-144LV MASS[Typ.] 1.2g
NOTE) DIMENSIONS "*1" "*2" INCLUDE MOLD FLASH. DIMENSION "*3" DOES INCLUDE TRIM OFFSET.
Reference Symbol
Dimension Millimeters 19.9 19.9 20.0 20.0 21.8 21.8 22.0 22.0 22.2 22.2 0.05 0.17 0.22 0.20 0.09 0.145 0.125 0.08 0.10 1.25 1.25 0.35 0.65 0.20 0.15 0.27 20.1 20.1
Terminal cross section
Index mark
Detail
Rev.1.00 2005 page
Sales Strategic Planning Div.
Keep safety first your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Renesas Technology Corp. puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Renesas Technology Corp. product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Renesas Technology Corp. third party. Renesas Technology Corp. assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Renesas Technology Corp. without notice product improvements other reasons. therefore recommended that customers contact Renesas Technology Corp. authorized Renesas Technology Corp. product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Renesas Technology Corp. assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Renesas Technology Corp. various means, including Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). When using information contained these materials, including product data, diagrams, charts, programs, algorithms, please sure evaluate information total system before making final decision applicability information products. Renesas Technology Corp. assumes responsibility damage, liability other loss resulting from information contained herein. Renesas Technology Corp. semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Renesas Technology Corp. authorized Renesas Technology Corp. product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corp. necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corp. further details these materials products contained therein.
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