PCM1721 Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABL
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PCM1721
Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE
FEATURES
ACCEPTS 16-, 20-, 24-BIT INPUT DATA COMPLETE STEREO DAC: Includes Digital Filter Output DYNAMIC RANGE: 94dB MULTIPLE SAMPLING FREQUENCIES: 16kHz, 22.05kHz, 24kHz 32kHz, 44.1kHz, 48kHz 64kHz, 88.2kHz, 96kHz PROGRAMMABLE CIRCUIT: 256fS/384fS from 27MHz Master Clock NORMAL DATA INPUT FORMATS SELECTABLE FUNCTIONS: Soft Mute Digital Attenuator (256 Steps) Digital De-emphasis OUTPUT MODE: Left, Right, Mono, Mute
DESCRIPTION
PCM1721 complete cost stereo audio digital-to-analog converter (DAC) with phase-locked loop (PLL) circuit included. derives either 256fS 384fS system clock from external 27MHz reference frequency. contains 3rd-order modulator, digital interpolation filter, analog output amplifier. PCM1721 accept 16-, 20-, 24-bit input data either normal formats. digital filter performs interpolation function includes selectable features such soft mute, digital attenuation digital de-emphasis. programmed sampling standard digital audio frequencies well one-half double sampling frequencies. PCM1721 ideal applications which combine compressed audio video data such DVD, DVDROM, set-top boxes MPEG sound cards.
BCKIN LRCIN Serial Input Oversampling Digital Filter with Function Controller
Multi-level Delta-Sigma Modulator
Low-pass Filter
VOUTL
Multi-level Delta-Sigma Modulator Low-pass Filter VOUTR
Mode Control
ZERO BPZ-Cont. 256fS/384fS Open Drain
RSTB Clock/OSC Manager Power Supply
SCKI
MCKI
SCKO
PGND AGND DGND
International Airport Industrial Park Mailing Address: 11400, Tucson, 85734 Street Address: 6730 Tucson Blvd., Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1996 Burr-Brown Corporation
PDS-1319A
PCM1721
Printed U.S.A. August, 1996
SPECIFICATIONS
specifications +25°C, +VCC +VDD +5V, 44.1kHz, 16-bit input data, SYSCLK 384fS, unless otherwise noted. PCM1721 PARAMETER RESOLUTION DATA FORMAT Audio Data Format Data Length Sampling Frequency (fS) Standard One-half Double CONDITIONS Standard/I2S 16/20/24 Selectable 44.1 22.05 88.2 256fS/384fS 27MHz 27MHz 27MHz, 15pF ±250 UNITS Bits
PERFORMANCE Master Clock Input Frequency Generated Sysclk Frequency Generated Sysclk Jitter Generated Sysclk Transient(1) Generated Sysclk Duty Cycle DIGITAL INPUT/OUTPUT LOGIC LEVEL DYNAMIC PERFORMANCE(2) THD+N (0dB) THD+N -60dB Dynamic Range (EIAJ Method) Signal-to-Noise Ratio(3) Channel Separation ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-emphasis Error INTERNAL ANALOG FILTER -3dB Bandwidth Passband Response POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: TEMPERATURE RANGE Operation Storage
44.1kHz 96kHz 44.1kHz 96kHz 44.1kHz 96kHz 44.1kHz 96kHz 44.1kHz
±1.0 ±1.0 0.62 VCC/2
Vp-p
±5.0 ±5.0
VOUT VCC/2 Full Scale (-0dB) Load
0.445 0.555 ±0.17 11.125/fS -0.2 -0.16 +100 +0.55
20kHz 44.1kHz 96kHz
NOTES: Sysclk transient maximum frequency lock time when frequency changed. Dynamic performance specs tested with 20kHz pass filter THD+N specs tested with 30kHz LPF, 400Hz HPF, Average-Mode. tested Infinite Zero Detection off.
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
PCM1721
CONFIGURATION
VIEW SSOP
ASSIGNMENTS
NAME MCKI SCKO SCKI RSTB ZERO TYPE FUNCTION Master Clock Input. System Clock Out. This output 256fS 384fS system clock generated internal PLL. Power Supply (+5V) System Clock (256fS 384fS) Input. Reserved factory use, connect. Latch serial control data Clock serial control data Data serial control Reset Input. When this low, digital filters modulators held reset. Zero Data Flag. This when input data continuously zero more than cycles BCKIN. Right Channel Analog Output Analog Ground Analog Power Supply (+5V) Left Channel Analog Output Common analog output amplifiers. clock clocking audio data. Serial audio data input Left/Right Word Clock. Frequency equal Test pin, must tied "LOW". Reserved factory use, connect. Analog Power Supply (+5V) Digital Ground Ground Connection
MCKI SCKO SCKI RSTB
PGND DGND TEST LRCIN BCKIN VOUTL
VOUTR AGND VOUTL BCKIN LRCIN TEST DGND PGND
ZERO VOUTR AGND
PACKAGE INFORMATION
PRODUCT PCM1721 PACKAGE 24-Pin SSOP PACKAGE DRAWING NUMBER(1)
NOTE: detailed drawing dimension table, please data sheet, Appendix Burr-Brown Data Book.
These pins include internal pull-up resistors.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage +6.5V +VCC +VDD Difference ±0.1V Input Logic Voltage -0.3V (VDD 0.3V) Power Dissipation 530mW Operating Temperature Range +70°C Storage Temperature -55°C +125°C Lead Temperature (soldering, +260°C Thermal Resistance, +70°C/W
PCM1721
TYPICAL PERFORMANCE CURVES
+25°C, =+5V, 44.1kHz, 16-bit input data, 384fS, unless otherwise noted. Measurement bandwidth 20kHz.
DYNAMIC PERFORMANCE
THD+N TEMPERATURE 44.1kHz
DYNAMIC RANGE TEMPERATURE 44.1kHz
Dynamic Range (dB)
5.5V 4.5V 5.0V
THD+N (dB)
4.5V 5.5V
5.0V
5.0V 5.5V
Temperature (°C)
Temperature (°C)
THD+N TEMPERATURE 96kHz 4.5V
DYNAMIC RANGE TEMPERATURE 96kHz
Dynamic Range (dB)
5.0V
4.5V
THD+N (dB)
5.0V
5.5V
5.5V
Temperature (°C)
Temperature (°C)
TEMPERATURE 96kHz
TEMPERATURE 44.1kHz
4.5V 5.5V
5.0V
(dB)
(dB)
5.0V
5.5V
4.5V Temperature (°C)
Temperature (°C)
PCM1721
TYPICAL PERFORMANCE CURVES
DYNAMIC PERFORMANCE
THD+N
(CONT)
+25°C, =+5V, 44.1kHz, 16-bit input data, 384fS, unless otherwise noted. Measurement bandwidth 20kHz.
DYNAMIC RANGE
THD+N (dB)
(kHz) 384fS 256fS
Dynamic Range (dB)
256fS
384fS
(kHz)
(dB)
256fS
(mA)
384fS
(kHz)
(kHz)
PCM1721
TYPICAL PERFORMANCE CURVES
+25°C, +5V, 44.1kHz, fSYS 384fS, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
PASSBAND RIPPLE CHARACTERISTIC
-0.2
-0.4
-0.6
-0.8
-100 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS Frequency (Hz)
0.1134fS 0.2268fS Frequency (Hz) 0.3402fS 0.4535fS
DE-EMPHASIS FREQUENCY RESPONSE (3kHz) Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) Frequency (Hz) -0.2 -0.4 -0.6
Level (dB)
DE-EMPHASIS ERROR (3kHz) -0.2 -0.4 -0.6 3628 7256 Frequency (Hz) DE-EMPHASIS ERROR (44.1kHz) -0.2 -0.4 -0.6 4999.8375 9999.675 Frequency (Hz) DE-EMPHASIS ERROR (48kHz)
Error (dB) Error (dB) Error (dB)
Level (dB)
10884
14512
Level (dB)
14999.5125
19999.35
5442
10884 Frequency (Hz)
16326
21768
PCM1721
TYPICAL CONNECTION DIAGRAM Figure illustrates typical connection diagram PCM1721 MPEG2 application. 27MHz master video clock (fM) drives MCKI (pin PCM1721. programmable system clock generated PCM1721 PLL, with SCKO used drive MPEG2 decoder's system clock input. standard audio signals (data, clock, word clock) generated decoder from PCM1721's system clock, providing synchonization audio video signals.
CIRCUIT PCM1721 programmable internal circuit, shown Figure designed accept 27MHz master clock generate internal system clocks required operate digital filter modulator, either 256fS 384fS. will directly track variations master clock's frequency, jitter system clock specified 250ps maximum. Figure illustrates timing requirements 27MHz master clock.
Analog SERO Audio Decoder SCKO LRCKO SYSCKI 256fS/384fS BCKIN LRCIN SCKO SCKI PCM1721 ZERO Master 27MHz VOUTR VOUTL 10µF Post Analog Mute Analog Post Analog Mute PGND DGND
Analog
SCR(1)
MCKIN TEST
RSTB
STRB SCKO System Controller
AGND NOTE: SCR: System Clock Reference PCR: Program Clock Reference
Analog
FIGURE External Master Clock Input.
Sampling Frequency Selection 256fS/384fS Selection
Section System Clock Input
Frequency Selection
Counter Phase Detector Loop Filter Counter
System Clock Input Section
27MHz Master Clock Input
Generated System Clock
FIGURE Block Diagram.
1/27MHz 1/256fS 1/384fS 2.0V 0.8V
13ns (min) 13ns (min)
FIGURE MCKI, SCKI Input Timing.
PCM1721
1/fS L_ch LRCIN (pin BCKIN (pin AUDIO DATA WORD 16-BIT (pin R_ch
AUDIO DATA WORD 20-BIT (pin
AUDIO DATA WORD 24-BIT (pin
FIGURE "Normal" Data Input Timing.
1/fS LRCIN (pin BCKIN (pin AUDIO DATA WORD 16-BIT (pin L_ch R_ch
AUDIO DATA WORD 20-BIT (pin
AUDIO DATA WORD 24-BIT (pin
FIGURE "I2S" Data Input Timing.
tMLS tMCH tMCY tMCL tMLL 1.4V tMLH 1.4V
tMDS tMDH
1.4V
Pulse Cycle Time Pulse Width Pulse Width HIGH Set-up Time Hold Time Level Time Set-up Time Hold Time
tMCY tMCL tMCH tMDS tMDH tMLL tMLS tMLH
100ns (min) 50ns (min) 50ns (min) 30ns (min) 30ns (min) 30ns 1SYSCLK (min) 30ns (min) 30ns (min)
FIGURE Serial Interface Timing.
PCM1721
Sampling Frequencies-LRCIN (kHz) Half Standard Sampling Freq Standard Sampling Freq Double Standard Sampling Freq 22.05 44.1 88.2
TABLE Sampling Frequencies.
HALF STANDARD SAMPLING FREQUENCY 256fS (kHz) INTERNAL SYSTEM CLOCK (MHz) 4.096 5.6448 6.144 6.144 8.4672 9.216 8.192 11.2896 12.288 12.288 16.934 18.432 16.384 22.5792 24.576 24.576 33.8688 36.864 384fS (kHz)
PCM1721's internal programmed nine different sampling frequencies (LRCIN), shown Table internal sampling clocks generated various programmed frequencies shown Table Because finite limitations PLL's counters, errors associated with specific frequencies shown.
DOUBLE STANDARD SAMPLING FREQUENCY 256fS (kHz) 384fS (kHz) FREQ ERROR
STANDARD SAMPLING FREQUENCY 256fS (kHz) 384fS (kHz)
4.0982
22.05 5.64543
22.05
44.1
44.1
88.2
88.2
0.0537 0.0112
6.13634 6.13634 8.46604 9.21426 8.18849 11.29087 12.2946 12.2946 16.93215 18.42851 16.37699 22.58174 24.5892 24.5892 33.8643 36.85702
-0.1247 -0.1247 -0.0137 -0.0189 -0.0428 0.0112 0.0537 0.0537 -0.0133 -0.0189 -0.0428 0.0112 0.0537 0.0537 -0.0133 -0.0189
TABLE Sampling Frequencies Internal System Clock.
FUNCTION Input Audio Data Format Selection Normal Format Format Input Audio Data Selection 16/20/24 Bits Input LRCIN Polarity Selection Lch/Rch High/Low Lch/Rch Low/High De-emphasis Control Soft Mute Control Attenuation Control Lch, Individually Lch, Common Infinite Zero Detection Circuit Control Operation Enable (OPE) Sample Rate Selection Internal System Clock Selection 256fS 384fS Double Sampling Rate Selection Standard Sampling Rate-44.1/48/32kHz Double Sampling Rate-88.2/96/32kHz Half Sampling Rate-22.05/24/16kHz Sampling Frequency 44.1kHz Group 48kHz Group 32kHz Group Analog Output Mode Mono, Mute DEFAULT MODE Normal Format
SPECIAL FUNCTIONS PCM1721 includes several special functions, including digital attenuation, digital de-emphasis, soft mute, data format selection input word resolution. These functions controlled using three-wire interface. (pin used program data, (pin used clock program data, (pin used latch program data. Table lists selectable special functions.
Bits Lch/Rch High/Low Lch, Individually Fixed Enabled
384fS
Standard Sampling Rate
44.1kHz
Stereo
TABLE III. Selectable Functions.
PCM1721
MAPPING PROGRAM REGISTERS
MODE0 MODE1 MODE2 MODE3 DSR1 DSR0
PROGRAM REGISTER MAPPING PCM1721's special functions controlled using four program registers which bits long. These registers loaded using After data bits clocked used latch data appropriate register. Table shows complete mapping four registers Figure illustrates serial interface timing.
REGISTER NAME Register NAME (7:0) (1:0) (7:0) (1:0) (1:0) (3:0) (1:0) (1:0) (1:0) (1:0)
ATTENUATION DATA LOAD CONTROL, (LDL) used simultaneously analog outputs Rch. output level controlled AL[0:7] attenuation data when this When output level controlled remains previous attenuation level. Register equivalent function LDL. When output level left right channel simultaneously controlled. attenuation level given (y/256) (dB), where when when user-determined step number, integer value between 255. Example:
DESCRIPTION Attenuation Data Attenuation Data Load Control Register Address Reserved Attentuation Data Attenuation Data Load Control Register Address Reserved Left Right DACs Soft Mute Control De-emphasis Control Left Right DACs Operation Control Input Audio Data Select Output Mode Select Register Address Reserved Audio Data Format Select Polarity LRCIN (pin Select Attenuator Control System Clock Select Double Sampling Rate Select Sampling Rate Select Infinite Zero Detection Circuit Control Register Address Reserved
Register
Register
Register
068dB
-48.16dB
TABLE Internal Register Mapping. REGISTER
REGISTER
Register used control left channel attenuation. Bits (AL0 AL7) used determine attenuation level. level attenuation given log10 (ATT_DATA/255)]
Register used control right channel attenuation. Register bits (AR0 AR7) control level attenuation.
PCM1721
REGISTER
MUTE
Bits (PL0:3) used control output format. output PCM1721 programmed different states, shown Table VIII.
OUTPUT MUTE MUTE MUTE MUTE R)/2 R)/2 R)/2 R)/2 OUTPUT MUTE R)/2 MUTE R)/2 MUTE R)/2 MUTE R)/2 MONO STEREO REVERSE NOTE MUTE
Register used control soft mute, de-emphasis, operation enable, input resolution, output format. used soft mute: "HIGH" level will cause output muted (this ramped down digital domain, "click" audible). used control de-emphasis. "LOW" level disables de-emphasis, while "HIGH" level enables de-emphasis. (OPE) used operational control. Table illustrates features controlled OPE.
DATA INPUT Zero Other Zero Other OUTPUT Forced BPZ(1) Forced BPZ(1) Controlled Normal SOFTWARE MODE INPUT Enabled Enabled Enabled Enabled
TABLE Operation Enable (OPE) Function. controls operation DAC: when "LOW", will convert non-zero input data. input data continuously zero cycles BCKIN, output will forced zero only "HIGH". When "HIGH", output will forced bipolar zero, irrespective input data.
DATA INPUT Zero Other Zero Other OUTPUT Forced BPZ(1) Normal Zero(2) Normal
TABLE VIII. Programmable Output Format. REGISTER
DSR1 DSR0
Register used control input data format polarity, attenuation channel control, system clock frequency, sampling frequency infinite zero detection. Bits (I2S) (LRP) used control input data format. "LOW" sets format "Normal" (MSB-first, right-justified Japanese format) "HIGH" sets format (Philips serial data protocol). (LRP) used select polarity LRCIN (sample rate clock). When "LOW", left channel data assumed when LRCIN "HIGH" phase right channel data assumed when LRCIN "LOW" phase. When "HIGH", polarity assumption reversed. (ATC) used controlling attenuator. When "HIGH", attenuation data loaded program Register used both left right channels. When "LOW", attenuation data each register applied separately left right channels. (SYS) system clock selection. When "LOW", system clock frequency 384fS. When "HIGH", system clock frequency 256fS. Bits (DSR0) (DSR1) used control multiples sampling rate:
DSR1 DSR0 Normal Double One-half Reserved Multiple 32/44.1/48kHz 64/88.2/96kHz 16/22.05/24kHz Defined
TABLE Infinite Zero Detection (IZD) Function.
SOFTWARE MODE INPUT Enabled Enabled Disabled Disabled
DATA INPUT RSTB "HIGH" RSTB "LOW" Zero Other Zero Other
OUTPUT Controlled Controlled Forced BPZ(1) Forced BPZ(1)
TABLE VII. Reset (RSTB) Function.
NOTE: disconnected from output amplifier. connected output amplifier.
Bits (IW0) (IW1) used determine input word resolution. PCM1721 input word resolutions bits:
(IW1) (IW0) Input Resolution 16-bit Data Word 20-bit Data Word 24-bit Data Word Reserved
PCM1721
Bits (SF0) (SF1) used select sampling frequency:
Sampling Frequency 44.1kHz group 48kHz group 32kHz group Reserved 22.05/44.1/88.2kHz 24/48/96kHz 16/32/64kHz Defined
used control infinite zero detection function (IZD).
When "LOW", zero detect circuit off. Under this condition, automatic muting will occur input continuously zero. When "HIGH", zero detect feature enabled. input data continuously zero cycles BCKIN, output will immediately forced bipolar zero state (VCC/2). zero detection feature used avoid noise which occur when input When output forced bipolar zero, there audible click. PCM1721 allows zero detect feature disabled user implement external muting circuit.
(pin (pin (pin
FIGURE Serial Interface Timing.
tMLS tMCH tMCY tMCL tMLL
tMLH 1.4V
1.4V
tMDS tMDH
1.4V
Pulse Cycle Time Pulse Width Pulse Width HIGH Set-up Time Hold Time Level Time Set-up Time Hold Time
tMCY tMCL tMCH tMDS tMDH tMLL tMLS tMLH
100ns (min) 50ns (min) 50ns (min) 30ns (min) 30ns (min) 30ns 1SYSCLK (min) 30ns (min) 30ns (min)
FIGURE Program Register Input Timing.
PCM1721
APPLICATION CONSIDERATIONS
DELAY TIME There finite delay time delta-sigma converters. converters, this commonly referred latency. delta-sigma converter, delay time determined order number filter stage, chosen sampling rate. following equation expresses delay time PCM1721: 11.125 1/fS 44.1kHz, 11.125/44.1kHz 251.4µs Applications using data from disc tape source, such audio, CD-Interactive, Video DAT, Minidisc, etc., generally affected delay time. some professional applications such broadcast audio studios, important total delay time less than 2ms. OUTPUT FILTERING testing purposes dynamic tests done PCM1721 using 20kHz pass filter. This filter limits measured bandwidth THD+N, etc. 20kHz. Failure such filter will result higher THD+N lower Dynamic Range readings than found specifications. pass filter removes band noise. Although audible, affect dynamic specification numbers. performance internal pass filter from 24kHz shown Figure higher frequency rolloff filter shown Figure user's application PCM1721 driving wideband amplifier, recommended external pass filter. simple 3rdorder filter shown Figure some applications, passive filter 2nd-order filter adequate.
INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale)
-0.5
-1.0 Frequency (Hz)
FIGURE Pass Filter Frequency Response.
INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz)
100k
Frequency (Hz)
FIGURE Pass Filter Wideband Frequency Response.
GAIN FREQUENCY Gain 1500pF VSIN -270
680pF
100pF
Phase
-180
Frequency (Hz) 100k
-360
FIGURE 3rd-Order LPF.
Phase
OPA604
Gain (dB)
PCM1721
2.6V VCC/VDD 2.2V 1.8V Reset Reset Removal Internal Reset 1024 system XTI) clocks Clock
FIGURE Internal Power-On Reset Timing.
RSTB tRST(1)
Reset Reset Removal
Internal Reset 1024 system (XTI) clocks Clock NOTE: tRST 20ns
FIGURE RSTB-Pin Reset Timing. Reset PCM1721 both internal power-on reset circuit RSTB (pin which accepts external forced reset RSTB LOW. internal power reset, initialize (reset) done automatically power >2.2V (typ). During internal reset LOW, output invalid analog outputs forced VCC/2. Figure illustrates timing internal power reset. PCM1721 accepts external forced reset when RSTB During RSTB output invalid analog outputs forced VCC/2 after internal initialize (1024 system clocks count after RSTB Figure illustrates timing RSTB reset. supplies used without common connection, delta between supplies during ramp-up time must less than 0.6V. application circuit avoid power-on latch-up condition shown Figure
Digital Power Supply
Analog Power Supply
DGND
AGND
POWER SUPPLY CONNECTIONS
PCM1721 three power supply connections: digital (VDD), analog (VCC), (VCP). Each connection also separate ground return pin. acceptable common power supply three power pins. separate
FIGURE Latch-up Prevention Circuit.
BYPASSING POWER SUPPLIES power supplies should bypassed close possible unit. Refer Figure optimal values bypass capacitors. also recommended include 0.1µF ceramic capacitor parallel with 10µF tantalum capacitor.
PCM1721
18-Bit
5-level Quantizer 48fS (384fS) 64fS (256fS)
FIGURE 5-Level Modulator Block Diagram.
THEORY OPERATION
delta-sigma section PCM1721 based 5-level amplitude quantizer 3rd-order noise shaper. This section converts oversampled input data 5-level deltasigma format. block diagram 5-level delta-sigma modulator shown Figure This 5-level delta-sigma modulator advantage stability clock jitter sensitivity over typical one-bit level) delta-sigma modulator. combined oversampling rate delta-sigma modulator internal interpolation filter 48fS 384fS system clock, 64fS 256fS system clock. theoretical quantization noise performance 5-level delta-sigma modulator shown Figure
Gain (-dB)
ORDER MODULATOR -100 -120 -140 -160 Frequency (kHz)
FIGURE Quantization Noise Spectrum.
PCM1721
AC-3 APPLICATION CIRCUIT typical application PCM1721 AC-3 channel audio decoding playback. This circuit uses PCM1721 develop audio system clock from 27MHz video clock, with SCKO used drive AC-3 decoder PCM1720 units, non-PLL version PCM1721.
10µF SCKO AC-3 Audio Decoder LRCKO SERO_0 SERO_1 SERO_2 SYSCKI BCKIN LRCIN SCKI PCM1720 VOUTR ZERO RSTB AGND STRB SCKO 10µF Three-wire (Serial I/O) BCKIN LRCIN SCKI PCM1720 VOUTR ZERO RSTB AGND 3.3µF 10µF Post Pass Filter Analog Mute Analog Mute Control 10µF DGND VOUTL Post Pass Filter Analog Mute Analog Analog 3.3µF Analog Mute Control 10µF DGND VOUTL Post Pass Filter Analog Mute Analog
Analog
Post Pass Filter
Analog Mute
Analog
Post Pass Filter
Analog Mute
Analog
Analog
Analog
PGND DGND Master Clock Generator BCKIN LRCIN SCKO SCKI MCKI PCM1721
VOUTL
10µF
VOUTR
Post Pass Filter
Analog Mute
Analog
Reset
RSTB AGND 3.3µF Analog ZERO Mute Control
FIGURE Connection Diagram 6-Channel AC-3 Application.
PCM1721
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